A data pre-fetching method and device supporting multiple memory access modes

Abstract

The present invention discloses a data prefetching method and device supporting multiple memory access modes. The method of the present invention includes: when it is detected that an instruction with a program counter PC value of P1 issues an access to a memory address A in a cache, while using a bit vector to issue a prefetch, using the most recently updated best offset D to issue an offset prefetch to the page to which the memory address A belongs as a supplementary means for the bit vector to issue a prefetch; using access information to update the bit vector information, and at the same time evaluating the offset accessed in the most recent period of time in each spatial region to update the best offset D according to preset conditions. The present invention simultaneously issues prefetches using the best offset and the bit vector corresponding to the spatial region, which can not only obtain better performance benefits for programs with space-intensive memory access characteristics, but also obtain better performance benefits for programs that often present a stride access mode, and can effectively improve the cache hit rate.

Description

Technical Field

[0001] The present invention belongs to the computer micro-architecture and storage component design technology in the field of microprocessor design, and specifically relates to a data pre-fetching method and device supporting multiple memory access modes. Background Art

[0002] The era of big data has arrived. For many big data applications, long off-chip DRAM access is a well-known performance bottleneck. Due to the speed mismatch between the processor and the off-chip DRAM, the processor can easily stall for hundreds of cycles each time it accesses DRAM, resulting in huge performance losses.

[0003] Cache hierarchies can improve program performance for data references with good temporal and spatial locality, but in some big data applications, there is still high data reference latency due to high cache miss rates.

[0004] Data prefetching is a well-researched technology that can improve the hit rate of cache access. It identifies the specific access pattern of the program to the memory and fetches the cache line where the required data is located to the appropriate cache level before accessing the cache data, thereby reducing the cache miss rate and data reference latency. Current prefetchers can only identify one memory access pattern and often perform poorly in programs with different memory access patterns. Therefore, they can only bring limited performance improvements. If multiple hardware prefetchers are combined together, although they can identify multiple different memory access patterns and obtain good performance benefits, they will bring great hardware overhead. For example, in some programs with space-intensive memory access characteristics, by using bit vectors to record the access information of cache lines in the spatial region, issuing prefetches based on the bit vectors corresponding to the spatial region in the future can obtain relatively good performance benefits; on the contrary, in some programs that often present stride access patterns, issuing prefetches by using bit vectors to record the access status of cache lines in the spatial region cannot obtain higher performance benefits. Summary of the invention

[0005] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a data prefetching method and device supporting multiple memory access modes are provided. When using a bit vector to record the access status of cache lines in a spatial area, the present invention simultaneously evaluates the optimal offset of the most recent memory access behavior, and uses the bit vector corresponding to the optimal offset and the spatial area to issue a prefetch. Not only can better performance benefits be obtained for programs with space-intensive memory access characteristics, but also better performance benefits can be obtained for programs that often present stride access patterns, which can effectively improve the cache hit rate.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A data prefetching method supporting multiple memory access modes, comprising:

[0008] 1) Detect the access of the instruction to the cache. When it is detected that the instruction with the program counter PC value P1 issues an access to the memory address A in the cache, jump to the next step;

[0009] 2) While using the bit vector for recording the access information of the cache line in the spatial region R1 to which the memory address A belongs to issue a prefetch, use the most recently updated best offset D to issue an offset prefetch to the page to which the memory address A belongs as a supplementary means for issuing prefetches using the bit vector; and use an instruction with a program counter PC value of P1 to issue access information to the memory address A in the cache, update the bit vector information for recording the access information of the cache line in the spatial region, and evaluate the offset accessed in the recent period of time in each spatial region to update the best offset D according to preset conditions.

[0010] Optionally, it is recorded that the memory address A belongs to the K1th cache line of physical page J, and in step 2), using the most recently updated optimal offset D to issue an offset prefetch to the page to which the memory address A belongs includes: determining whether the K1+Dth cache line belongs to physical page J, and if it is located in physical page J, then issuing a prefetch for the K1+Dth cache line of physical page J; it is recorded that the memory address A belongs to the L1th cache line of spatial region R1, and in step 2), using a bit vector for recording access information of cache lines in spatial region R1 to which the memory address A belongs to issue a prefetch includes: for each bit set to 1 in the bit vector for recording access information of cache lines in spatial region R1 to which the memory address A belongs, prefetching the corresponding cache line in spatial region R1, wherein each bit set to 1 in the bit vector indicates that the bit has been accessed within the recent period of time.

[0011] Optionally, in step 2), the bit vector information for recording the access information of the cache line in the spatial region is updated, and the offset accessed in the recent period of time in each spatial region is evaluated to update the optimal offset D according to the preset conditions, including:

[0012] 2.1) Use the spatial region R1 to index a preset accumulation table, where the accumulation table is used to record the trigger access instruction PC and the offset within the spatial region for triggering access to the spatial region, as well as the bit vector corresponding to the spatial region R1 in the most recent period of time; if a matching item is indexed, jump to the next step; otherwise, jump to step 2.6);

[0013] 2.2) For each offset F in the spatial region set to 1 in the bit vector of the matching item record, the difference F-L1 is calculated respectively. If the difference F-L1 has a corresponding offset d in the preset offset score list, then the score corresponding to the offset d in the offset score list is increased by 1. The offset score list is used to record the scores corresponding to the preset multiple offsets;

[0014] 2.3) In the accumulation table, set the L1th bit vector corresponding to the spatial region R1 in the most recent period to 1;

[0015] 2.4) Increment the execution count counter by 1;

[0016] 2.5) Determine whether the count value of the conditional execution times counter is greater than or equal to the first set value or whether there is an offset in the offset score list with a score greater than the second set value. If the condition is met, select the offset d with the highest score in the offset score list to update the optimal offset D, clear the scores of all offsets in the offset score list, and clear the conditional execution times counter; jump to step 1);

[0017] 2.6) Use the spatial region R1 to index a preset filter table, where the filter table is used to record the trigger access instruction PC for triggering access to the spatial region and the offset within the spatial region; if a matching item is indexed, jump to the next step; otherwise, jump to step 2.9);

[0018] 2.7) For the trigger access instruction whose program counter PC value is P2 and offset is L2, the difference between L2 and L1 is calculated. If the difference between L2 and L1 has a corresponding offset d in the preset offset score list, the score corresponding to the offset d in the offset score list is increased by 1;

[0019] 2.8) evict the indexed matching item from the filter table, allocate a new item to the space region R1 in the accumulator table, record the corresponding program counter PC value P2 and offset L2 corresponding to the evicted trigger access instruction, and set the L1 and L2 positions in the allocated new item to 1 and the other positions to 0; if a valid item in the accumulator table is evicted due to the allocation of a new item to the space region R1 in the accumulator table, then record the evicted valid item in a preset pattern history table, which is used to record the bit vector transferred from the accumulator table; jump to step 2.5);

[0020] 2.9) Determine that this access is a triggered access to the spatial region R1, record the information of the triggered access in the filter table, and then use the program counter PC value P1 of the current access instruction and the cache line L1 to index the pattern history table. If a match is found in the pattern history table, and based on the bit that has been set to 1 in the bit vector corresponding to the match in the pattern history table, issue a prefetch for the corresponding cache line of the spatial region R1; jump to step 2.1).

[0021] Optionally, recording the evicted valid item into a preset pattern history table in step 2.8) includes: allocating a new item for the evicted valid item record in the pattern history table, and recording the program counter PC value, offset and bit vector of the instruction corresponding to the evicted valid item record through the allocated new item.

[0022] Optionally, in step 2.9), recording the information that triggers the access in the filter table includes: allocating a new item to the spatial region R1 in the filter table, and recording the information that triggers the access through the allocated new item, including recording the program counter PC value P1 of the instruction that triggers the access and the cache line L1 in the accessed spatial region.

[0023] Optionally, in step 2.9), when a prefetch is issued for the corresponding cache line of the spatial region R1 according to the bit that has been set to 1 in the bit vector corresponding to the matching item in the pattern history table, if the bit that has been set to 1 in the bit vector corresponding to the matching item in the pattern history table is 1, a prefetch is issued for a corresponding cache line of the spatial region R1; if multiple bits have been set to 1 in the bit vector corresponding to the matching item in the pattern history table, prefetches are issued for multiple corresponding cache lines of the spatial region R1.

[0024] Optionally, the fields of each table entry of the filter table include a total of four fields, namely, a space area, a content, a valid bit and an LRU bit, wherein the space area field is used to record the address of the space area, the content field is used to record the program counter PC value of the trigger access instruction corresponding to the space area and the offset of the space area, the valid bit field is used to indicate the valid state of the table entry, and the LRU bit field is used to record the LRU replacement strategy of this table;

[0025] The fields of each entry in the accumulation table include a total of four fields, namely, a space area, content, a valid bit, and an LRU bit, wherein the space area field is used to record the address of the space area, the content field is used to record the program counter PC value of the trigger access instruction corresponding to the space area, the offset of the space area, and the bit vector, the valid bit field is used to indicate the valid state of the entry, and the LRU bit field is used to record the LRU replacement strategy of this table;

[0026] The fields of each table entry in the mode history table include four fields, namely content, bit vector, valid bit and LRU bit, wherein the content field is used to record the program counter PC value of the trigger access instruction corresponding to the space area and the offset of the space area, the bit vector is used to record the corresponding bit vector, the valid bit field is used to indicate the valid state of the table entry, and the LRU bit field is used to record the LRU replacement strategy of this table; each table entry in the offset score list includes two fields, namely offset and score, and the offsets are 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 27, 30, a total of 18 fixed offsets.

[0027] In addition, the present invention also provides a data pre-fetching device supporting multiple memory access modes, including a control unit, an execution count counter and a plurality of storage tables, wherein the storage tables include:

[0028] The filter table is indexed by the region number of the space region and is used to record the trigger access instruction PC and the offset within the space region for triggering access to the space region;

[0029] The accumulation table is indexed by the region number of the space region and is used to record the PC of the trigger access instruction and the offset within the space region for triggering access to the space region, as well as the bit vector of the space region in the recent period;

[0030] The pattern history table uses the instruction PC that triggers the access and the offset index in the spatial region to record the bit vector transferred from the accumulation table;

[0031] An offset score list, used to record different offsets and their respective scores;

[0032] The control unit is connected to the execution times counter and a plurality of storage tables respectively, and the control unit is programmed or configured to execute the steps of the data pre-fetching method supporting multiple memory access modes.

[0033] In addition, the present invention also provides a microprocessor, which includes a cache and a prefetch unit for prefetching data into the cache, and the prefetch unit is programmed or configured to execute the steps of the data prefetching method supporting multiple memory access modes.

[0034] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is used to be executed by a microprocessor to implement the steps of the data prefetching method supporting multiple memory access modes.

[0035] Compared with the prior art, the present invention mainly has the following advantages: the present invention can not only record the access information of the cache lines in each spatial region through the bit vector, and use these bit vectors to issue prefetches for the cache lines in the spatial region when accessing similar spatial regions in the future, but also can evaluate the optimal offset of the memory access behavior in the recent period when recording the access information of the cache lines in each spatial region through the bit vector, and use the optimal offset to issue prefetches when the access to the cache is detected next. The present invention can enable the prefetcher to not only evaluate the optimal offset of the recent memory access behavior while using the bit vector to record the access information of the cache lines in the spatial region, but also use the optimal offset and the bit vector corresponding to the spatial region to issue prefetches without adding too much hardware overhead, thereby solving the problem of too low prefetch coverage in some programs that present a frequent stride access pattern when using the information recorded by the bit vector alone to issue prefetches. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Schematic diagram of the basic flow of the method of the embodiment of the present invention.

[0037] Figure 2 The following are detailed steps for pre-fetching and recording information in an embodiment of the present invention.

[0038] Figure 3 This is a processing flow after detecting that a cache line is evicted from the cache in an embodiment of the present invention.

[0039] Figure 4 It is a field structure diagram of the filter table in an embodiment of the present invention.

[0040] Figure 5 It is a field structure diagram of the accumulation table in an embodiment of the present invention.

[0041] Figure 6 4 is a field structure diagram of the mode history table in an embodiment of the present invention.

[0042] Figure 7 This is a field structure diagram of the offset score list in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] like Figure 1 As shown, the data prefetching method supporting multiple memory access modes in this embodiment includes:

[0044] 1) Detect the access of the instruction to the cache. When it is detected that the instruction with the program counter PC value P1 issues an access to the memory address A in the cache, jump to the next step;

[0045] 2) While using the bit vector for recording the access information of the cache line in the spatial region R1 to which the memory address A belongs to issue a prefetch, use the most recently updated best offset D to issue an offset prefetch to the page to which the memory address A belongs as a supplementary means for issuing prefetches using the bit vector; and use an instruction with a program counter PC value of P1 to issue access information to the memory address A in the cache, update the bit vector information for recording the access information of the cache line in the spatial region, and evaluate the offset accessed in the recent period of time in each spatial region to update the best offset D according to preset conditions.

[0046] The data prefetching method of this embodiment uses a bit vector to record the access status of cache lines in a spatial region and simultaneously evaluates the optimal offset of the most recent memory access behavior, and uses the bit vector corresponding to the optimal offset and the spatial region to issue a prefetch. Not only can better performance benefits be obtained for programs with space-intensive memory access characteristics, but also for programs that often present stride access patterns. Good performance benefits can also be obtained, which can effectively improve the cache hit rate.

[0047] In this embodiment, it is recorded that the memory address A belongs to the K1th cache line of the physical page J. In step 2), the most recently updated optimal offset D is used to issue an offset prefetch to the page to which the memory address A belongs, including: determining whether the K1+Dth cache line belongs to the physical page J. If it is located in the physical page J, a prefetch is issued for the K1+Dth cache line of the physical page J; it is recorded that the memory address A belongs to the L1th cache line of the spatial region R1. In step 2), the bit vector used to record the access information of the cache line in the spatial region R1 to which the memory address A belongs is used to issue a prefetch, including: for each bit set to 1 in the bit vector used to record the access information of the cache line in the spatial region R1 to which the memory address A belongs, a corresponding cache line in the spatial region R1 is prefetched, wherein each bit set to 1 in the bit vector indicates that the bit has been accessed in the recent period of time.

[0048] In step 2), based on the memory access information of this time, while using the bit vector to record the memory access information of the spatial region, the offset accessed in the recent period of time in each spatial region is evaluated to update the optimal offset D according to the preset conditions. The part of using the bit vector to record the memory access information of the spatial region is to calculate which cache line of which spatial region the address of this memory access belongs to. For example, if the memory address A accessed this time belongs to the L1th cache line of the spatial region R1, then the L1th position of the bit vector recording the memory access information of the spatial region R1 is set to 1, indicating that the L1th cache line has been accessed. The offset is evaluated by calculating the difference between the cache line currently accessed and the cache line previously accessed in the spatial region, and scoring the offset that appears. For example, the memory address A accessed this time belongs to the L1th cache line of the spatial region R1. Through the bit vector of the spatial region R1, it is known that the L2th cache line of the spatial region R1 has been previously accessed, so the score of the offset L1-L2 is increased by 1. When the preset conditions are met, the offset with the highest score is used as the optimal offset D. Among them, the preset condition can be selected as required that the number of updates exceeds a set value or the offset with the highest score exceeds a set value.

[0049] See also Figure 2 As an optional implementation, in step 2), the bit vector information for recording the access information of the cache line in the spatial region is updated, and the offset accessed in the recent period of time in each spatial region is evaluated to update the optimal offset D according to the preset conditions, including:

[0050] 2.1) Use the spatial region R1 to index a preset accumulation table, where the accumulation table is used to record the trigger access instruction PC and the offset within the spatial region for triggering access to the spatial region, as well as the bit vector corresponding to the spatial region R1 in the most recent period of time; if a matching item is indexed, jump to the next step; otherwise, jump to step 2.6);

[0051] 2.2) For each offset F in the spatial region set to 1 in the bit vector of the matching item record, the difference F-L1 is calculated respectively. If the difference F-L1 has a corresponding offset d in the preset offset score list, then the score corresponding to the offset d in the offset score list is increased by 1. The offset score list is used to record the scores (number of occurrences) corresponding to the preset multiple offsets;

[0052] 2.3) In the accumulation table, set the L1th bit vector corresponding to the spatial region R1 in the most recent period to 1;

[0053] 2.4) Increment the execution count counter by 1; in this embodiment, the execution count counter is named test_round, referred to as the test_round counter, and the test_round counter is initialized to 0 in advance;

[0054] 2.5) Determine whether the count value of the conditional execution times counter is greater than or equal to the first set value or whether there is an offset in the offset score list with a score greater than the second set value. If the condition is met, select the offset d with the highest score in the offset score list to update the optimal offset D, clear the scores of all offsets in the offset score list, and clear the conditional execution times counter; jump to step 1); the first set value and the second set value can be set according to actual needs. For example, as a preferred implementation, the first set value in this embodiment is 512 and the second set value is 32; if the count value of the execution times counter is greater than or equal to 512, or there is an offset with a score greater than 32, then the offset with the highest score at this time is used as the optimal offset D;

[0055] 2.6) Use the spatial region R1 to index a preset filter table, where the filter table is used to record the trigger access instruction PC for triggering access to the spatial region and the offset within the spatial region; if a matching item is indexed, jump to the next step; otherwise, jump to step 2.9);

[0056] 2.7) For the trigger access instruction whose program counter PC value is P2 and offset is L2, the difference between L2 and L1 is calculated. If the difference between L2 and L1 has a corresponding offset d in the preset offset score list, the score corresponding to the offset d in the offset score list is increased by 1;

[0057] 2.8) The indexed matching item is evicted from the filter table, a new item is allocated to the space region R1 in the accumulation table, the corresponding program counter PC value P2 and offset L2 corresponding to the evicted triggering access instruction are recorded, and the L1 and L2 positions in the allocated new item are set to 1 and the other positions are set to 0; see Figure 2 If a valid entry in the accumulation table is evicted due to the allocation of a new entry to the spatial region R1 in the accumulation table, the evicted valid entry is recorded in a preset pattern history table, where the pattern history table is used to record the bit vector transferred from the accumulation table; jump to step 2.5);

[0058] 2.9) Determine that this access is a triggered access to the spatial region R1, record the information of the triggered access in the filter table, and then use the program counter PC value P1 of the current access instruction and the cache line L1 to index the pattern history table. If a match is found in the pattern history table, and according to the bits that have been set to 1 in the bit vector corresponding to the match in the pattern history table, a prefetch is issued for the corresponding cache line of the spatial region R1 (for example, the bit vector of the match in the pattern history table is 00001111 0000000000000000 00000000, because the 4th, 5th, 6th, and 7th bits in the bit vector are all 1, and the other bits are all 0, so a prefetch is issued for the 4th, 5th, 6th, and 7th cache lines of the spatial region R1); jump to step 2.1).

[0059] Based on the methods recorded in the above steps 2.1) to 2.9), from the perspective of hardware resource utilization, all the proposed hardware structures have been fully utilized, especially the accumulation table, which is not only used to record the bit vector corresponding to the spatial region, but also used to generate the optimal offset of the recent memory access pattern, achieving dual purpose of one table. From the perspective of prefetch coverage, the proposed design has a higher prefetch coverage than the prefetch using the bit vector corresponding to the spatial region or the optimal offset alone, and can achieve the highest prefetch coverage of the two methods in most applications.

[0060] See also Figure 3 , whenever it is detected that a cache line is replaced out of the cache, the spatial region where the cache line is located is used to index the accumulator table. If there is a matching item in the accumulator table, it is evicted from the accumulator table, and the trigger access information and bit vector recorded by it are transferred to the pattern history table. When it is detected that cache line E is replaced out of the cache, the spatial region R3 to which cache line E belongs is used to index the accumulator table. If there is a matching item in the accumulator table, the matching item is evicted, and the information is transferred to the pattern history table. For example, the trigger access instruction PC P4, offset L4 recorded by the evicted item, bit vector 00001111 11111111111111111 11111111, then a new item is allocated to instruction PC P4 and offset L4 in the pattern history table, and the bit vector 00001111 111111111 111111111 111111111. Then continue to detect whether a cache line is replaced out of the cache. In step 2.8) of this embodiment, recording the evicted valid item into the preset pattern history table includes: allocating a new item for the evicted valid item record in the pattern history table, and recording the program counter PC value, offset and bit vector of the instruction corresponding to the evicted valid item record through the allocated new item.

[0061] In this embodiment, recording the information that triggers access in the filter table in step 2.9) includes: allocating a new item to the spatial region R1 in the filter table, and recording the information that triggers access through the allocated new items, including recording the program counter PC value P1 of the triggering access instruction and the cache line L1 in the accessed spatial region.

[0062] In this embodiment, in step 2.9), when a prefetch is issued for the corresponding cache line of the spatial region R1 according to the bit that has been set to 1 in the bit vector corresponding to the matching item in the pattern history table, if the bit that has been set to 1 in the bit vector corresponding to the matching item in the pattern history table is 1, a prefetch is issued for one corresponding cache line of the spatial region R1; if multiple bits have been set to 1 in the bit vector corresponding to the matching item in the pattern history table, prefetches are issued for multiple corresponding cache lines of the spatial region R1.

[0063] like Figure 4 As shown, the fields of each entry of the filter table in this embodiment include a space area, content, valid bit and LRU (least recently used) bit, a total of four fields, wherein the space area field is used to record the address of the space area, the content field is used to record the program counter PC value of the trigger access instruction corresponding to the space area and the offset of the space area, the valid bit field is used to indicate the valid state of the table entry, and the LRU bit field is used to record the LRU (least recently used) replacement strategy of this table. The filter table in this embodiment is 16-way group associative, with a total of 128 items, and will be updated using the LRU (least recently used) replacement strategy. Since it is a known method to update the table using the LRU (least recently used) replacement strategy, it is described in detail here.

[0064] like Figure 5 As shown, the fields of each table entry of the accumulation table in this embodiment include four fields, namely, space area, content, valid bit and LRU bit. The space area field is used to record the address of the space area, the content field is used to record the program counter PC value of the trigger access instruction corresponding to the space area, the offset of the space area and the bit vector, the valid bit field is used to indicate the valid state of the table entry, and the LRU bit field is used to record the LRU replacement strategy of this table; the accumulation table in this embodiment is 16-way set associative, with a total of 128 items, and will be updated using the LRU (least recently used) replacement strategy.

[0065] like Figure 6As shown, the fields of each table entry of the pattern history table in this embodiment include four fields, namely content, bit vector, valid bit and LRU bit. The content field is used to record the program counter PC value of the trigger access instruction corresponding to the space area and the offset of the space area, the bit vector is used to record the corresponding bit vector, the valid bit field is used to indicate the valid state of the table entry, and the LRU bit field is used to record the LRU replacement strategy of this table; the pattern history table in this embodiment is 16-way set associative, with a total of 8192 items, and will be updated using the LRU (least recently used) replacement strategy.

[0066] like Figure 7 As shown, each entry in the offset score list in this embodiment includes two fields: offset and score. Our offset prefetching mode does not consider cross-page prefetching, so the selection of the offset in the table depends on the size of the memory page. Given that the page size in most computing systems is 64 cache lines, the optional offset range is -63 to +63. According to experience, negative values, large values, and offsets with prime factors greater than 5 cannot achieve sufficient benefits, so 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 27, and 30 are selected to use a total of 18 fixed offsets.

[0067] In summary, the method of this embodiment solves the problem that when only one prefetching method of bit vector is used, the prefetching coverage is insufficient, and when multiple prefetching methods are used, a large amount of hardware overhead is caused. At present, most hardware prefetchers can only detect one memory access mode and issue a prefetch, or use multiple different hardware storage tables to detect multiple different memory access modes and issue a prefetch, but the latter requires the use of additional storage tables, which brings a large amount of additional hardware storage overhead. The method of this embodiment proposes a data prefetching method that supports multiple memory access modes. When recording the bit vector of the spatial region, it can use the storage table that records the bit vector of the spatial region to evaluate the optimal offset of the memory access mode in the most recent period, and can simultaneously use the optimal offset and the bit vector of the spatial region to issue a prefetch, thereby adding additional prefetch modes without adding additional storage tables.

[0068] In addition, this embodiment also provides a data prefetching device supporting multiple memory access modes, including a control unit, an execution count counter and a plurality of storage tables, wherein the storage tables include:

[0069] The filter table is indexed by the region number of the space region and is used to record the trigger access instruction PC and the offset within the space region for triggering access to the space region;

[0070] The accumulation table is indexed by the region number of the space region and is used to record the PC of the trigger access instruction and the offset within the space region for triggering access to the space region, as well as the bit vector of the space region in the recent period;

[0071] The pattern history table uses the instruction PC that triggers the access and the offset index in the spatial region to record the bit vector transferred from the accumulation table;

[0072] An offset score list, used to record different offsets and their respective scores;

[0073] The control unit is connected to the execution times counter and the plurality of storage tables respectively, and the control unit is programmed or configured to execute the steps of the aforementioned data pre-fetching method supporting a plurality of memory access modes.

[0074] In addition, this embodiment also provides a microprocessor, which includes a cache and a prefetch unit for prefetching data into the cache, and the prefetch unit is programmed or configured to execute the steps of the aforementioned data prefetching method that supports multiple memory access modes.

[0075] In addition, this embodiment also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is used to be executed by a microprocessor to implement the steps of the aforementioned data prefetching method supporting multiple memory access modes.

[0076] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 A process or multiple processes and / or boxes Figure 1These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0077] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A data prefetching method supporting multiple memory access modes, characterized in that: include: 1) Detect the access of the instruction to the cache. When it is detected that the instruction with the program counter PC value P1 issues an access to the memory address A in the cache, jump to the next step; 2) While using the bit vector for recording the access information of the cache line in the spatial region R1 to which the memory address A belongs to issue a prefetch, use the most recently updated best offset D to issue an offset prefetch to the page to which the memory address A belongs as a supplementary means for the bit vector to issue a prefetch; use the instruction with the program counter PC value P1 to issue the access information of the memory address A in the cache, update the bit vector information for recording the access information of the cache line in the spatial region, and evaluate the offset accessed in the recent period of time in each spatial region to update the best offset D according to the preset conditions; In step 2), the bit vector information for recording the access information of the cache line in the spatial region is updated, and the offset accessed in the recent period of time in each spatial region is evaluated to update the optimal offset D according to the preset conditions, including: 2.1) Use the spatial region R1 to index a preset accumulation table, which is used to record the trigger access instruction PC and the offset within the spatial region for triggering access to the spatial region, as well as the bit vector corresponding to the spatial region R1 in the recent period of time; if a matching item is indexed, jump to the next step; otherwise, jump to step 2.6); 2.2) For each offset F in the spatial region set to 1 in the bit vector of the matching item record, the difference F-L1 is calculated respectively. If the difference F-L1 has a corresponding offset d in the preset offset score list, then the score corresponding to the offset d in the offset score list is increased by 1. The offset score list is used to record the scores corresponding to the preset multiple offsets; 2.3) In the accumulation table, set the L1th bit vector corresponding to the spatial region R1 in the most recent period to 1; 2.4) Increment the execution count counter by 1; 2.5) Determine whether the count value of the conditional execution times counter is greater than or equal to the first set value or whether there is an offset in the offset score list with a score greater than the second set value. If the condition is met, select the offset d with the highest score in the offset score list to update the optimal offset D, clear the scores of all offsets in the offset score list, and clear the conditional execution times counter; jump to step 1); 2.6) Use the spatial region R1 to index a preset filter table, where the filter table is used to record the trigger access instruction PC and the offset within the spatial region for triggering access to the spatial region; if a matching item is indexed, jump to the next step; otherwise, jump to step 2.9); 2.7) For the trigger access instruction with the program counter PC value P2 and offset L2 corresponding to the index to the matching item, calculate the difference between L2 and L1. If the difference between L2 and L1 has a corresponding offset d in the preset offset score list, then increase the score corresponding to offset d in the offset score list by 1; 2.8) The indexed matching item is evicted from the filter table, a new item is allocated to the space region R1 in the accumulation table, the corresponding program counter PC value P2 and offset L2 corresponding to the evicted triggering access instruction are recorded, and the L1 and L2 positions in the allocated new item are set to 1 and the other positions are set to 0; if a valid item in the accumulation table is evicted due to the allocation of a new item to the space region R1 in the accumulation table, the evicted valid item is recorded in a preset pattern history table, and the pattern history table is used to record the bit vector transferred from the accumulation table; jump to step 2.5); 2.9) Determine that this access is a triggered access to the spatial region R1, record the information of the triggered access in the filter table, and then use the program counter PC value P1 of the current access instruction and the cache line L1 to index the pattern history table. If a match is found in the pattern history table, and according to the bit that has been set to 1 in the bit vector corresponding to the match in the pattern history table, issue a prefetch for the corresponding cache line of the spatial region R1; jump to step 2.1).

2. The data prefetching method supporting multiple memory access modes according to claim 1, characterized in that: Note that memory address A belongs to the K1th cache line of physical page J. In step 2), using the most recently updated best offset D to issue an offset prefetch to the page to which memory address A belongs includes: determining whether the K1+Dth cache line belongs to physical page J. If it is located in physical page J, then issuing a prefetch for the K1+Dth cache line of physical page J. Note that memory address A belongs to the L1th cache line of spatial region R1. In step 2), using a bit vector for recording access information of cache lines in spatial region R1 to which memory address A belongs, issuing a prefetch includes: for each bit set to 1 in the bit vector for recording access information of cache lines in spatial region R1 to which memory address A belongs, prefetching the corresponding cache line in spatial region R1, wherein each bit set to 1 in the bit vector indicates that the bit has been accessed in the recent period of time.

3. The data prefetching method supporting multiple memory access modes according to claim 1, characterized in that: In step 2.8), recording the evicted valid item into the preset pattern history table includes: allocating a new item for the evicted valid item record in the pattern history table, and recording the program counter PC value, offset and bit vector of the instruction corresponding to the evicted valid item record through the allocated new item.

4. The data prefetching method supporting multiple memory access modes according to claim 1, characterized in that: In step 2.9), recording the information that triggers the access in the filter table includes: allocating a new item to the space region R1 in the filter table, and recording the information that triggers the access through the allocated new items, including recording the program counter PC value P1 of the instruction that triggers the access and the cache line L1 in the accessed space region.

5. The data prefetching method supporting multiple memory access modes according to claim 1, characterized in that: In step 2.9), when a prefetch is issued for the corresponding cache line of the spatial region R1 according to the bit that has been set to 1 in the bit vector corresponding to the matching item in the pattern history table, if the bit that has been set to 1 in the bit vector corresponding to the matching item in the pattern history table is 1, a prefetch is issued for a corresponding cache line of the spatial region R1; if the bit that has been set to 1 in the bit vector corresponding to the matching item in the pattern history table is multiple bits, a prefetch is issued for multiple corresponding cache lines of the spatial region R1.

6. The data pre-fetching method supporting multiple memory access modes according to claim 1, characterized in that: The fields of each entry of the filter table include a total of four fields: space area, content, valid bit and LRU bit, wherein the space area field is used to record the address of the space area, the content field is used to record the program counter PC value of the trigger access instruction corresponding to the space area and the offset of the space area, the valid bit field is used to indicate the valid state of the entry, and the LRU bit field is used to record the LRU replacement strategy of this table; The fields of each entry in the accumulation table include a total of four fields, namely, a space area, content, a valid bit, and an LRU bit, wherein the space area field is used to record the address of the space area, the content field is used to record the program counter PC value of the trigger access instruction corresponding to the space area, the offset of the space area, and the bit vector, the valid bit field is used to indicate the valid state of the entry, and the LRU bit field is used to record the LRU replacement strategy of this table; The fields of each table entry in the mode history table include four fields, namely content, bit vector, valid bit and LRU bit, wherein the content field is used to record the program counter PC value of the trigger access instruction corresponding to the space area and the offset of the space area, the bit vector is used to record the corresponding bit vector, the valid bit field is used to indicate the valid state of the table entry, and the LRU bit field is used to record the LRU replacement strategy of this table; each table entry in the offset score list includes two fields, namely offset and score, and the offsets are 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 27, 30, a total of 18 fixed offsets.

7. A data pre-fetching device supporting multiple memory access modes, characterized in that: It includes a control unit, an execution times counter and a plurality of storage tables, wherein the storage tables include: The filter table is indexed by the region number of the space region and is used to record the trigger access instruction PC and the offset within the space region for triggering access to the space region; The accumulation table is indexed by the region number of the space region and is used to record the PC of the trigger access instruction and the offset within the space region for triggering access to the space region, as well as the bit vector of the space region in the recent period; The pattern history table uses the instruction PC that triggers the access and the offset index in the spatial region to record the bit vector transferred from the accumulation table; An offset score list, used to record different offsets and their respective scores; The control unit is connected to the execution times counter and the plurality of storage tables respectively, and the control unit is programmed or configured to execute the steps of the data prefetching method supporting multiple memory access modes as claimed in any one of claims 1 to 6.

8. A microprocessor comprising a cache and a prefetch unit for prefetching data into the cache, characterized in that: The pre-fetch unit is programmed or configured to execute the steps of the data pre-fetch method supporting multiple memory access modes as claimed in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored therein, characterized in that: The computer program is used to be executed by a microprocessor to implement the steps of the data prefetching method supporting multiple memory access modes as described in any one of claims 1 to 6.

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