A DMA data transfer method and device

Abstract

The present application is applicable to the field of computer technology, and provides a DMA data transfer method and device, the data transfer method is applied to a DMA controller, including: obtaining a read instruction set, the read instruction set including first configuration information, the first configuration information including first discrete address information and first continuous address information; according to the first configuration information in the read instruction set, transferring data within a discrete address range corresponding to the first discrete address information to a continuous address range corresponding to the first continuous address information. The embodiment of the present application controls the DMA data transfer operation through an instruction set, and during the DMA data transfer process, the normal operation of the CPU will not be affected by the generation of a DMA interrupt.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and in particular, relates to a direct memory access (DMA) data transfer method and device. Background Art

[0002] DMA transfer refers to copying data from one address space to another address space. DMA transfer plays an important role in high-performance embedded system algorithms and networks. In the prior art, DMA can only move data from a certain address area to another address area. For example, data in the address range [a,b] can be moved to the address range [h,j], where "the address range [a,b]" can be understood as the space between position a and position b in the memory.

[0003] However, when data in multiple discrete address ranges need to be moved to a continuous address range, multiple DMA transfer operations need to be initiated. For example, when data in the address ranges [a1,b1], [a2,b2], and [a3,b3] are moved sequentially to the address range [h,j], DMA needs to initiate three transfer operations. Similarly, if data in the address range [a,b] need to be moved sequentially to three discrete address ranges [h1,j1], [h2,j2], and [h3,j3], DMA also needs to initiate three transfer operations.

[0004] It can be seen that in the related art, when there is a need for data transfer, DMA needs to perform multiple operations to complete the transfer of all data, which will frequently generate DMA interrupts, affecting the central processing unit (CPU) or other coprocessors to assist the CPU in completing the processing work that it cannot perform or performs inefficiently or ineffectively. Summary of the invention

[0005] In view of this, an embodiment of the present application provides a DMA data transfer method and device, which can solve one or more technical problems in the related technology.

[0006] In a first aspect, an embodiment of the present application provides a DMA data transfer method, which is applied to a DMA controller. The DMA data transfer method includes: obtaining a read instruction set, the read instruction set includes first configuration information, the first configuration information includes first discrete address information and first continuous address information; according to the first configuration information in the read instruction set, transferring data within a discrete address range corresponding to the first discrete address information to a continuous address range corresponding to the first continuous address information.

[0007] In the second aspect, an embodiment of the present application provides a DMA data transfer method, which is applied to a DMA controller. The DMA data transfer method includes: obtaining a write instruction set, the write instruction set includes second configuration information, the second configuration information includes second discrete address information and second continuous address information; according to the second configuration information in the write instruction set, transferring data within a continuous address range corresponding to the second continuous address information to a discrete address range corresponding to each of the second discrete address information.

[0008] In a third aspect, an embodiment of the present application provides a DMA data transfer device, which is configured in a DMA controller and includes: a first acquisition module, used to obtain a read instruction set, the read instruction set includes first configuration information, the first configuration information includes first discrete address information and first continuous address information; a data reading module, used to transfer data within a discrete address range corresponding to the first discrete address information to a continuous address range corresponding to the first continuous address information according to the first configuration information in the read instruction set.

[0009] In a fourth aspect, an embodiment of the present application provides a DMA data transfer device, which is configured in a DMA controller, and includes: a second acquisition module, used to obtain a write instruction set, the write instruction set includes second configuration information, the second configuration information includes second discrete address information and second continuous address information; a data write module, used to transfer the data in the continuous address range corresponding to the second continuous address information to the discrete address range corresponding to each of the second discrete address information according to the second configuration information in the write instruction set.

[0010] In a fifth aspect, an embodiment of the present application provides a coprocessor, wherein the coprocessor is coupled to a DMA controller, or the DMA controller is coupled and integrated in the coprocessor, and the DMA controller includes the DMA data transfer device described in the third aspect, and / or the DMA data transfer device described in the fourth aspect.

[0011] In a sixth aspect, an embodiment of the present application provides an electronic device, comprising a memory, a coprocessor, and a computer program stored in the memory and executable on the coprocessor, wherein when the coprocessor executes the computer program, the coprocessor implements the DMA data transfer method as described in any embodiment of the first aspect, and / or implements the DMA data transfer method as described in any embodiment of the second aspect.

[0012] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer storage medium stores a computer program, and when the computer program is executed by a coprocessor, the DMA data transfer method as described in any embodiment of the first aspect is implemented, and / or the DMA data transfer method as described in any embodiment of the second aspect is implemented.

[0013] In the eighth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the DMA data transfer method as described in any embodiment of the first aspect, and / or implement the DMA data transfer method as described in any embodiment of the second aspect.

[0014] The embodiment of the present application controls the DMA data transfer operation through an instruction set, thereby realizing the transfer of data within a discrete address range to a continuous address range, or the transfer of data within a continuous address range to each discrete address range, so that the normal operation of the CPU will not be affected by the generation of DMA interrupts during the DMA data transfer process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 This is a schematic diagram of an implementation flow of a DMA data transfer method provided in one embodiment of the present application;

[0017] Figure 2 It is a structural diagram of a read instruction set provided by an embodiment of the present application;

[0018] Figure 3 This is a schematic diagram of the meaning of configuration information provided by an embodiment of the present application;

[0019] Figure 4 This is a schematic diagram of the meaning of configuration information provided by an embodiment of the present application;

[0020] Figure 5 is a schematic diagram of an image and its sub-images provided by an embodiment of the present application;

[0021] Figure 6 This is a schematic diagram of the meaning of configuration information in an image processing application scenario provided by an embodiment of the present application;

[0022] Figure 7This is a schematic diagram of an implementation flow of a DMA data transfer method provided in one embodiment of the present application;

[0023] Figure 8 It is a structural diagram of a write instruction set provided by an embodiment of the present application;

[0024] Fig. 9 This is a process diagram of a DMA data transfer method provided by an embodiment of the present application;

[0025] Fig.10 is a schematic diagram of an image processing application scenario provided by an embodiment of the present application;

[0026] Fig.11 This is a schematic diagram of the meaning of configuration information in an image processing application scenario provided by an embodiment of the present application;

[0027] Fig.12 It is a structural schematic diagram of a DMA data transfer device provided by an embodiment of the present application;

[0028] Fig.13 It is a structural schematic diagram of a DMA data transfer device provided by an embodiment of the present application;

[0029] Fig.14 It is a structural schematic diagram of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0030] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0031] The term "and / or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0032] "One embodiment" or "some embodiments" described in the specification of this application means that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the sentences "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0033] In addition, in the description of the present application, "plurality" means two or more. The terms "first" and "second" are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0034] It should also be understood that, unless otherwise clearly specified or limited, the term "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] The DMA data handling of the embodiment of the present application is divided into two parts. One is the DMA data handling based on the read instruction set, which mainly realizes the movement of each data in certain discrete addresses to a continuous address range. The other is the DMA data handling based on the write instruction set, which mainly realizes the movement of data in a continuous address range to each discrete address area. Therefore, the data handling based on the write instruction set can be regarded as the reverse process of the data handling based on the read instruction set. In addition, the DMA data handling based on the read instruction set has a locking function.

[0036] It should be noted that the DMA data transfer method provided in the present application can be executed by a DMA controller, and the DMA controller can be coupled to or integrated into the coprocessor; if the DMA controller can be coupled to or integrated into the coprocessor, the DMA data transfer method is executed under the control of the coprocessor, and there is no restriction here.

[0037] Figure 1 This is a flowchart of a DMA data transfer method based on a read instruction set provided in an embodiment of the present application. The method may include steps S110 to S120.

[0038] S110, obtaining a read instruction set.

[0039] The read instruction set includes configuration information, and the configuration information includes discrete address information and continuous address information. The discrete address information includes one or more, and the discrete address information is the source address information; the continuous address information is the target address information, and the data in one or more source addresses is moved to a target address.

[0040] As a possible implementation manner, configuration information is determined according to user operations and / or system settings, and a read instruction set is generated according to the configuration information.

[0041] In some embodiments, the discrete address information in the read instruction set includes the starting offset address of the source memory, the address space size of a single discrete address, the address distance between two adjacent discrete addresses of the same data source, the number of discrete addresses of the same data source, the address distance between two adjacent discrete addresses of different data sources, and the number of data sources, etc.; the continuous address information includes the starting offset address information of the destination memory, etc.

[0042] S120, according to the configuration information in the read instruction set, move the data in the discrete address range corresponding to the discrete address information to the continuous address range corresponding to the continuous address information.

[0043] In some embodiments, Figure 2 The structure diagram of the read instruction set is shown in FIG. Figure 2 As shown, the read instruction set has a total of 256 bits. The configuration information included in the read instruction set is shown in Table 1 below.

[0044] Table 1

[0045]

[0046]

[0047] The specific meanings of sector_length, L1_sector_gap, L1_sector_num, L2_sector_gap, and L2_sector_num in the configuration information shown in Table 1 can be found in Figure 3 and Figure 4 As shown. Figure 3 and Figure 4As shown, assuming that the discrete address where the data in the source memory is located is a large interval A, then A can be divided into multiple small intervals, for example, into five small intervals a1, a2, a3, a4, and a5, where a1, a3, and a5 areas are areas where data needs to be read and the address space sizes of the three are equal, and a2 and a4 areas are areas where data does not need to be read and the address space sizes of the two are equal; the total number of small intervals a1, a3, and a5 is L2_sector_num, and the address space size of a2 and a4 is L2_sector_gap. Further, assuming that the gray areas in the figure are of the same size and the data in the areas need to be moved, and the blank areas are of the same size but the data in the areas do not need to be moved, then the address space size of the gray areas is sector_length, the address space size of the blank areas is L1_sector_gap, and the number of gray areas in each small interval a1, a3, and a5 is L1_sector_num. Based on the above configuration information, an address scheduling can be established inside the DMA. After moving the data in a gray area address space, it will automatically jump to the next gray area address space to move the data until all the gray area data in the source memory is moved to the destination memory, that is, the data of each discrete address is moved to a continuous address range, such as Figure 3 and Figure 4 Through these configuration information, DMA can move data in multiple discrete address ranges to a continuous address range at one time.

[0048] The following uses image data as an example to describe in detail the DMA data transfer method provided in the embodiment of the present application.

[0049] In the process of image processing, there are often many images to be processed. Generally, the memory will store the images according to the arrangement order of the images to be processed, such as Figure 5 As shown, the memory stores the first image first, then the second image, and then the third image in the order of the images to be processed, until all images are stored. It should be noted that when storing images, the image data of a single image is stored in sequence row by row.

[0050] However, in the image processing process, in order to consider the cost of hardware resources, a single image that is too large in size is split into multiple small images, namely sub-images, for processing. Figure 5 As shown. A single image can be considered as consisting of many sub-images, such as A0, B0, A1, B1, A2, B2, A3, and B3. Each time the image is processed, all sub-images with the same position and size are taken out for processing, for example Figure 5As shown, sub-images A0, A1, A2, and A3 are first taken out for parallel processing. After sub-images A0, A1, A2, and A3 are processed, sub-images B0, B1, B2, and B3 are taken out for processing. The same operation is repeated until all sub-images are processed in sequence, and the processing of all images is completed. In the above process of taking sub-images for processing, the data of the sub-images needs to be moved to the corresponding coprocessor for processing. However, if the conventional DMA data transfer method is used, it is necessary to move A0 first, then A1, then A2, then A3, then B0, and then B1, until all sub-images are moved. It can be seen that the conventional method will cause DMA to generate an interrupt signal to the CPU every time a sub-image is moved, so that the CPU frequently generates interrupt signals, affecting its normal operation.

[0051] Based on the above problems, an embodiment of the present application provides a DMA data transfer method based on a read instruction set, which first determines the configuration information through user operation and / or system settings, then generates a read instruction set according to the configuration information, and then uses the read instruction set to complete data transfer to ensure the normal operation of the CPU.

[0052] In one embodiment, Figure 6 As shown, sector_length can be set to the image width of the sub-image, L1_sector_gap can be set to the distance from the end of the first row to the beginning of the second row in two adjacent rows of the sub-image, L1_sector_num is the image height of the sub-image, and L2_sector_num is the total number of all images. ( Figure 6 L2_sector_num is 4). Combined with Figure 5 and Figure 6 As shown, assuming Figure 6 The last pixel of sub-image A0 in the first image is C, and the first pixel of sub-image A1 in the second image is D. The address distance between these two pixels is recorded as |CD|, then L2_sector_gap = |CD|-L1_sector_gap, where L2_sector_gap is the address distance between the two images, that is, the length of the data that does not need to be read.

[0053] Further, according to the configuration information obtained above, Figure 2 The structure shown generates a read instruction set, and uses the read instruction to move the four sub-images A0, A1, A2, and A3 from the four images at discrete addresses to a continuous address range. After the data is moved, the DMA controller directly notifies the coprocessor for subsequent processing. According to the above configuration, the sub-images after all images are split can be moved to the coprocessor in sequence through the read instruction set, avoiding frequent interrupt signals that affect the CPU.

[0054] In some embodiments of the present application, the DMA based on the read instruction set also has a locking function, that is, the address space between the configuration information lock_bn_begin (i.e., the starting position of executing the locking function) and lock_bn_end (i.e., the end position of executing the locking function) in the instruction set is locked. Once the space is locked, the DMA controller cannot move data into the address space. If the next read instruction set is configured to move data into the locked space at this time, the DMA movement will stop until the space is unlocked, and the unlocking is controlled by the coprocessor. The general locking and unlocking scenario is caused by the fact that the data in the address space has not been used up by the coprocessor or needs to be used by the coprocessor later. Locking can prevent the data in the address space from being overwritten, or reduce the number of repeated reading sub-images. When the data in the address space does not need to be used by the coprocessor anymore, the coprocessor needs to send an unlock signal to the DMA controller. After receiving the unlock signal, the DMA controller will unlock the address space, so that data can be moved into the address space.

[0055] The embodiment of the present application also provides a DMA data transfer method based on a write instruction set. It should be noted that the DMA data transfer method based on a write instruction set can be understood as the inverse operation of the DMA data transfer based on a read instruction set, which transfers data in a continuous address range to each discrete address range.

[0056] In one embodiment, Figure 7 As shown, the DMA data transfer method based on the write instruction set may include steps S210 to S220.

[0057] S210, obtaining a write instruction set.

[0058] The write instruction set includes configuration information, which includes at least discrete address information and continuous address information. The continuous address information is the source address information; the discrete address information includes one or more discrete address information, which is the target address information. The data in a source address is moved to one or more discrete target addresses.

[0059] As a possible implementation manner, configuration information is determined according to user operations and / or system settings, and a write instruction set is generated according to the configuration information.

[0060] In some embodiments, the continuous address information of the write instruction set includes the starting offset address information of the source memory, etc.; the discrete address information includes the starting offset address of the destination memory, the address space size of a single discrete address, the address distance between two adjacent discrete addresses of the same data source, the number of discrete addresses of the same data source, the address distance between two adjacent discrete addresses of different data sources, and the number of data sources, etc.

[0061] S220, according to the configuration information in the write instruction set, move the data in the continuous address range corresponding to the continuous address information to the discrete address range corresponding to each discrete address information.

[0062] In some embodiments, Figure 8 The structure diagram of the write instruction set is shown in FIG. Figure 8 As shown, the write instruction set has a total of 256 bits. The configuration information included in the write instruction set is shown in Table 2 below.

[0063] Table 2

[0064]

[0065]

[0066] The specific meanings of sector_length, L1_sector_gap, L1_sector_num, L2_sector_gap, and L2_sector_num in the configuration information shown in Table 2 are the same as those in Table 1, and can also be seen in Table 2. Figure 3 and Figure 4 It will not be described here in detail, please refer to the above.

[0067] DMA data transfer based on the write instruction set can be seen as follows Fig. 9 The operations shown, such as Fig. 9 As shown, DMA data transfer based on the write instruction set can complete the reading of continuous data and write it into one or more discrete address ranges. Through the configuration information in the write instruction set, DMA can transfer data in a continuous address range to multiple discrete address ranges at one time.

[0068] The following continues the above Figures 5 and 6 The embodiment of the image data shown in FIG. 1 applies the DMA data transfer method to image processing. In the image processing process, continue to refer to Figure 5 and Figure 6 As shown, to split a large single image into multiple small sub-images for processing, it is necessary to move out the sub-images A0, A1, A2, and A3 of the same size in the same position of all images, that is, to move the data in the discrete address space to the continuous address space, such as Fig.10As shown, when the coprocessor completes the processing, that is, the data of sub-images A0, A1, A2, and A3 are processed into A'0, A'1, A'2, and A'3, then the processed data needs to be moved out. After each sub-image is processed, it needs to be written to the corresponding position, that is, the data in the continuous address is moved to the discrete address space. The above operation can be completed by using the DMA data transfer method based on the write instruction set provided in the embodiment of the present application. At this time, the information such as sector_length, L1_sector_gap, L1_sector_num, L2_sector_gap, and L2_sector_num configured in the write instruction set is the corresponding related information on the final output image, such as Fig.11 Specifically, Fig.11 As shown, sector_length can be set to the image width of the sub-image, L1_sector_gap can be set to the distance from the end of the first row to the beginning of the second row in two adjacent rows of the sub-image, L1_sector_num is the image height of the sub-image, and L2_sector_num is the total number of images ( Fig.11 4). Assume Fig.11 The last pixel of sub-image A'0 in the first image is C', and the first pixel of sub-image A'1 in the second image is D'. The address distance between these two pixels is denoted as |C'D'|, then L2_sector_gap = |C'D'| - L1_sector_gap.

[0069] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0070] An embodiment of the present application also provides a DMA data transfer device, which is configured in a DMA controller. For details not described in detail in the DMA data transfer device, please refer to the relevant description of the aforementioned method embodiment, which will not be repeated here.

[0071] See also Fig.12 , Fig.12 Schematic diagram of a DMA data transfer device provided by an embodiment of the present application. Fig.12 As shown, the DMA data transport device includes: a first acquisition module 1210 and a data reading module 1220.

[0072] The first acquisition module 1210 is used to acquire a read instruction set.

[0073] The data reading module 1220 is used to move the data in the discrete address range corresponding to the discrete address information to the continuous address range corresponding to the continuous address information according to the configuration information in the read instruction set.

[0074] See also Fig.13 , Fig.13 Schematic diagram of a DMA data transfer device provided by an embodiment of the present application. Fig.13 As shown, the DMA data transport device includes: a second acquisition module 1310 and a data writing module 1320.

[0075] The second acquisition module 1310 is used to acquire a write instruction set.

[0076] The data writing module 1320 is used to move the data in the continuous address range corresponding to the continuous address information to the discrete address range corresponding to each discrete address information according to the configuration information in the write instruction set.

[0077] An embodiment of the present application further provides a DMA controller, the DMA controller includes the aforementioned Fig.12 The DMA data transfer device of the embodiment shown, and / or the aforementioned Fig.13 The DMA data transfer device of the illustrated embodiment.

[0078] An embodiment of the present application further provides a coprocessor, wherein the coprocessor is integrated with the aforementioned DMA controller, or the coprocessor is coupled with the aforementioned DMA controller.

[0079] An embodiment of the present application also provides an electronic device. Fig.14 As shown, the electronic device may include one or more coprocessors 1400 ( Fig.14 Only one is shown in the figure), a memory 1410 and a computer program 1420 stored in the memory 1410 and executable on one or more coprocessors 1400, for example, a DMA data transfer program. When one or more coprocessors 1400 execute the computer program 1420, the aforementioned Figure 1 The DMA data transfer method of the embodiment shown, and / or the aforementioned Figure 7 Alternatively, one or more coprocessors 1400 may implement the aforementioned steps when executing computer program 1420. Fig.12 The DMA data transfer device of the embodiment shown, and / or the aforementioned Fig.13 The functions of each module / unit in the DMA data handling device embodiment of the illustrated embodiment are not limited here.

[0080] Exemplarily, the computer program 1420 may be divided into one or more modules / units, one or more modules / units are stored in the memory 1410, and are executed by the coprocessor 1400 to complete the present application. One or more modules / units may be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program 1420 in the processing unit.

[0081] For example, the computer program 1420 can be divided into the following modules. The specific functions of each module are as follows:

[0082] A first acquisition module, used for acquiring a read instruction set;

[0083] The data reading module is used to move the data in the discrete address range corresponding to the discrete address information to the continuous address range corresponding to the continuous address information according to the configuration information in the read instruction set.

[0084] and / or,

[0085] A second acquisition module is used to acquire a write instruction set;

[0086] The data writing module is used to move the data in the continuous address range corresponding to the continuous address information to the discrete address range corresponding to each discrete address information according to the configuration information in the write instruction set.

[0087] Those skilled in the art will understand that Fig.14 The electronic device is merely an example of an electronic device and does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, the electronic device may also include input and output devices, network access devices, buses, etc.

[0088] In one embodiment, the so-called coprocessor 1400 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0089] In one embodiment, the memory 1410 may be an internal storage unit of an electronic device, such as a hard disk or memory of the electronic device. The memory 1410 may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device. Further, the memory 1410 may also include both an internal storage unit of the electronic device and an external storage device. The memory 1410 is used to store computer programs and other programs and data required by the electronic device. The memory 1410 may also be used to temporarily store data that has been output or is to be output.

[0090] An embodiment of the present application also provides another preferred embodiment of an electronic device. In this embodiment, the electronic device includes one or more coprocessors. The one or more coprocessors are used to execute the following program modules stored in the memory:

[0091] A first acquisition module, used for acquiring a read instruction set;

[0092] The data reading module is used to move the data in the discrete address range corresponding to the discrete address information to the continuous address range corresponding to the continuous address information according to the configuration information in the read instruction set.

[0093] and / or,

[0094] A second acquisition module is used to acquire a write instruction set;

[0095] The data writing module is used to move the data in the continuous address range corresponding to the continuous address information to the discrete address range corresponding to each discrete address information according to the configuration information in the write instruction set.

[0096] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0097] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the aforementioned Figure 1 The DMA data transfer method of the embodiment shown, and / or the aforementioned Figure 7 The DMA data transfer method of the illustrated embodiment.

[0098] An embodiment of the present application provides a computer program product, when the computer program product is run on an electronic device, the electronic device can implement the above Figure 1 The DMA data transfer method of the embodiment shown, and / or the aforementioned Figure 7 The DMA data transfer method of the illustrated embodiment.

[0099] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0100] According to different design requirements, the implementation of the first acquisition module, the data reading module, the second acquisition module, and the data writing module can be hardware, firmware, software (i.e., computer program) or a combination of the above three. In terms of hardware, the first acquisition module, the data reading module, the second acquisition module, and the data writing module can be a logic circuit implemented on an integrated circuit. The related functions of the first acquisition module, the data reading module, the second acquisition module, and the data writing module can be implemented as hardware using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the first acquisition module, the data reading module, the second acquisition module, and the data writing module can be implemented in various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASIC), digital signal processors (DSP), field programmable gate arrays (FPGA) and / or other processing units. In terms of software and / or firmware, the related functions of the above-mentioned first acquisition module, data reading module, second acquisition module, and data writing module, etc. can be implemented as a computer program. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form, etc. The computer program code can be recorded / stored in a computer-readable medium. The computer-readable medium may include: any entity or device that can carry computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), RAM, electric carrier signal, telecommunication signal and software distribution medium, etc. The central processing unit (CPU), controller, microcontroller or microprocessor can read and execute the computer program code from the computer-readable medium, thereby realizing the related functions of the above-mentioned first acquisition module, data reading module, second acquisition module, and data writing module, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electric carrier signals and telecommunication signals.

[0101] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A DMA data transfer method, applied to a DMA controller, characterized in that: The data of multiple sub-images in multiple images are transferred from a discrete address space to a continuous address space, and the DMA data transfer method includes: Acquire a read instruction set, the read instruction set including first configuration information, the first configuration information including first discrete address information and first continuous address information; wherein the first discrete address information includes a starting offset address of a source memory, an address space size of a single discrete address, an address distance between two adjacent discrete addresses of the same data source, the number of discrete addresses of the same data source, an address distance between two adjacent discrete addresses of different data sources, and the number of data sources; the first continuous address information includes a starting offset address information of a destination memory; According to the first configuration information in the read instruction set, move the data in the discrete address range corresponding to the first discrete address information to the continuous address range corresponding to the first continuous address information; The address space size of the single discrete address is the image width of the sub-image, the address distance between two adjacent discrete addresses of the same data source is the distance from the end of the first row to the beginning of the second row in two adjacent rows of the sub-image, the number of discrete addresses of the same data source is the image height of the sub-image, the address distance between two adjacent discrete addresses of different data sources is the address distance between the last pixel of the previous sub-image and the first pixel of the next sub-image in two adjacent sub-images, and the number of data sources is the number of sub-images; The discrete addresses where the data in the source memory are located are a large interval, and the large interval is divided into multiple small intervals, including areas where data needs to be read and areas where data does not need to be read, and the address space sizes of the areas where data needs to be read are equal and the address space sizes of the areas where data does not need to be read are equal; Based on the above configuration information, an address scheduling is established inside the DMA, and after the data in the address space of an area where data needs to be read is moved, it automatically jumps to the address space of the next area where data needs to be read to move data, until the data of all areas where data needs to be read in the source memory are moved to the destination memory, that is, the data of each discrete address is moved to a continuous address range; The first configuration information enables DMA to move data in multiple discrete address ranges into one continuous address range at one time.

2. The DMA data transfer method according to claim 1, wherein: The first configuration information also includes indication information of whether to execute the locking function.

3. The DMA data transfer method according to claim 1, wherein: The first configuration information also includes the starting and ending positions for executing the locking function. The DMA data transfer method further includes: when it is determined that the indication information of whether to execute the locking function in the first configuration information is to execute the locking function, locking the address space between the start and end positions of executing the locking function.

4. The DMA data transfer method according to claim 3, wherein: The locking of the address space between the starting position and the ending position of executing the locking function includes: stopping the transfer of data into the address space between the starting position and the ending position of executing the locking function until the address space is unlocked.

5. The DMA data transfer method according to any one of claims 1 to 4, characterized in that: The DMA data transfer method for moving multiple sub-images in multiple images from data in continuous addresses to data in discrete address spaces includes: Acquire a write instruction set, the write instruction set including second configuration information, the second configuration information including second discrete address information and second continuous address information; wherein: the second continuous address information includes the starting offset address information of the source memory; the second discrete address information includes the starting offset address of the destination memory, the address space size of a single discrete address, the address distance between two adjacent discrete addresses of the same data source, the number of discrete addresses of the same data source, the address distance between two adjacent discrete addresses of different data sources, and the number of data sources; According to the second configuration information in the write instruction set, move the data in the continuous address range corresponding to the second continuous address information to the discrete address range corresponding to each of the second discrete address information; Through the second configuration information, DMA can move data in a continuous address range to multiple discrete address ranges at one time.

6. A DMA data transfer device, configured in a DMA controller, characterized in that: The DMA data transfer device transfers data of multiple sub-images in multiple images from a discrete address space to a continuous address space, wherein the DMA data transfer device comprises: A first acquisition module is used to acquire a read instruction set, wherein the read instruction set includes first configuration information, and the first configuration information includes first discrete address information and first continuous address information; wherein: the first discrete address information includes a starting offset address of a source memory, an address space size of a single discrete address, an address distance between two adjacent discrete addresses of the same data source, the number of discrete addresses of the same data source, the address distance between two adjacent discrete addresses of different data sources, and the number of data sources; the first continuous address information includes a starting offset address information of a destination memory; a data reading module, configured to move data within a discrete address range corresponding to the first discrete address information to a continuous address range corresponding to the first continuous address information according to the first configuration information in the read instruction set; The address space size of the single discrete address is the image width of the sub-image, the address distance between two adjacent discrete addresses of the same data source is the distance from the end of the first row to the beginning of the second row in two adjacent rows of the sub-image, the number of discrete addresses of the same data source is the image height of the sub-image, the address distance between two adjacent discrete addresses of different data sources is the address distance between the last pixel of the previous sub-image and the first pixel of the next sub-image in two adjacent sub-images, and the number of data sources is the number of sub-images; The discrete addresses where the data in the source memory are located are a large interval, and the large interval is divided into multiple small intervals, including areas where data needs to be read and areas where data does not need to be read, and the address space sizes of the areas where data needs to be read are equal and the address space sizes of the areas where data does not need to be read are equal; Based on the above configuration information, an address scheduling is established inside the DMA, and after the data in the address space of an area where data needs to be read is moved, it automatically jumps to the address space of the next area where data needs to be read to move data, until the data of all areas where data needs to be read in the source memory are moved to the destination memory, that is, the data of each discrete address is moved to a continuous address range; The first configuration information enables DMA to move data in multiple discrete address ranges into one continuous address range at one time.

7. A DMA data transfer device as claimed in claim 6, characterized in that: The DMA data transfer device moves data of multiple sub-images in multiple images from continuous addresses to discrete address spaces, and the DMA data transfer device includes: A second acquisition module is used to acquire a write instruction set, wherein the write instruction set includes second configuration information, and the second configuration information includes second discrete address information and second continuous address information; wherein: the second continuous address information includes the starting offset address information of the source memory; the second discrete address information includes the starting offset address of the destination memory, the address space size of a single discrete address, the address distance between two adjacent discrete addresses of the same data source, the number of discrete addresses of the same data source, the address distance between two adjacent discrete addresses of different data sources, and the number of data sources; a data writing module, configured to move data in a continuous address range corresponding to the second continuous address information to discrete address ranges corresponding to each of the second discrete address information according to the second configuration information in the write instruction set; Through the second configuration information, DMA can move data in a continuous address range to multiple discrete address ranges at one time.

8. A coprocessor, characterized in that: The coprocessor is coupled to a DMA controller, or the DMA controller is coupled and integrated in the coprocessor, and the DMA controller includes the DMA data transfer device as described in any one of claims 6-7.

9. An electronic device, characterized in that: The invention comprises a memory, a coprocessor and a computer program stored in the memory and executable on the coprocessor, wherein the coprocessor implements the DMA data transfer method according to any one of claims 1 to 5 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by the coprocessor, the DMA data transfer method according to any one of claims 1 to 5 is implemented.

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