Simulation Method, Device and Storage Medium of Reconfigurable Processor System

Abstract

The present invention discloses a simulation method, device, and storage medium for a reconfigurable processor system. Among them, for the simulation method of the reconfigurable processor system, the reconfigurable processor includes a reconfigurable processor and external devices, and it includes: determining a simulation mode according to input parameters of a user, where the simulation mode includes a normal mode and a fast mode; in the case where the simulation mode is the fast mode, determining a simulation duration according to the input parameters; and performing simulation on the reconfigurable processor according to clock synchronization points preset in modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to address-based interfaces within the reconfigurable processor system.

Description

Technical Field

[0001] The present invention relates to the technical field of reconfigurable processors, and in particular, to a simulation method, apparatus, and storage medium for a reconfigurable processor system. Background Art

[0002] Reconfigurable processors usually require a cycle-accurate simulator to simulate their functions. This is because if a node has multiple input edges, that is, it depends on multiple data inputs, then the multiple data inputs must arrive at the node at the same time, otherwise data stalls will occur, reducing the computing efficiency. Therefore, it is necessary to model the number of computational clock cycles of the processing unit on the simulator, so as to use the compilation stage or hardware mechanism to ensure the alignment between multiple data inputs of the node. Reconfigurable processors are usually used as coprocessors of the central processing unit (CPU), so the complete system often includes a central processing unit and peripheral devices. If cycle-accurate modeling is performed on the entire system, two problems will arise: large development workload and long execution time.

[0003] In view of the technical problem in the above-mentioned prior art that the existing simulation method of reconfigurable processors needs to perform cycle-accurate modeling on all system modules, resulting in a large development workload and a long execution time, no effective solution has been proposed yet. Summary of the Invention

[0004] Embodiments of the present disclosure provide a simulation method, apparatus, and storage medium for a reconfigurable processor system, so as to at least solve the technical problem in the prior art that the existing simulation method of reconfigurable processors needs to perform cycle-accurate modeling on all system modules, resulting in a large development workload and a long execution time.

[0005] According to one aspect of the embodiments of the present disclosure, a simulation method for a reconfigurable processor system is provided. The reconfigurable processor includes a reconfigurable processor and external devices, and the method includes: determining a simulation mode according to input parameters of a user, where the simulation mode includes a normal mode and a fast mode; in the case where the simulation mode is the fast mode, determining a simulation duration according to the input parameters; and simulating the reconfigurable processor according to clock synchronization points preset in modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to address-based interfaces within the reconfigurable processor system.

[0006] According to another aspect of the embodiments of the present disclosure, a storage medium is further provided. The storage medium includes a stored program, where, when the program runs, the method described in any one of the above is executed by a processor.

[0007] According to another aspect of the embodiments of the present disclosure, there is also provided a simulation device for a reconfigurable processor system. The reconfigurable processor includes a reconfigurable processor and external devices, and the simulation device includes: a first determination module for determining a simulation mode according to input parameters of a user, where the simulation mode includes a normal mode and a fast mode; a second determination module for determining a simulation duration according to the input parameters when the simulation mode is the fast mode; and a first simulation module for simulating the reconfigurable processor according to clock synchronization points preset in modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to an address-based interface within the reconfigurable processor system.

[0008] According to another aspect of the embodiments of the present disclosure, there is also provided a simulation device for a reconfigurable processor system. The reconfigurable processor includes a reconfigurable processor and external devices, and the simulation device includes: a processor; and a memory connected to the processor for providing instructions for the processor to perform the following processing steps: determining a simulation mode according to input parameters of a user, where the simulation mode includes a normal mode and a fast mode; determining a simulation duration according to the input parameters when the simulation mode is the fast mode; and simulating the reconfigurable processor according to clock synchronization points preset in modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to an address-based interface within the reconfigurable processor system.

[0009] In the embodiments of the present disclosure, the synchronization accuracy is controlled by operating parameters to meet different simulation requirements of users. While accurately modeling the clocks of key modules, other modules can be modeled with lower precision to ensure the correctness of mutual operations, thereby reducing the workload of developing a system simulator and increasing the simulation speed. Furthermore, it solves the technical problems in the prior art that the existing simulation methods for reconfigurable processors require accurate clock modeling for all system modules, resulting in a large development workload and a long execution time. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present invention. The schematic embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation to the present disclosure. In the drawings:

[0011] Figure 1 is a hardware structure block diagram of a computing device for implementing the method according to Embodiment 1 of the present disclosure;

[0012] Figure 2A and Figure 2B is a schematic diagram of a reconfigurable processor system according to Embodiment 1 of the present disclosure;

[0013] Figure 3It is a schematic flowchart of a simulation method for a reconfigurable processor system according to the first aspect of Embodiment 1 of the present disclosure;

[0014] Figure 4A It is a schematic diagram of the simulation process of a reconfigurable processor system in the fast mode according to Embodiment 1 of the present disclosure;

[0015] Figure 4B It is a schematic diagram of the execution process of a reconfigurable processor system including one processing unit array in the fast mode according to Embodiment 1 of the present disclosure;

[0016] Figure 5A It is a schematic diagram of the simulation process of a reconfigurable processor system in the normal mode according to Embodiment 1 of the present disclosure;

[0017] Figure 5B It is a schematic diagram of the execution process of a reconfigurable processor system including one processing unit array in the normal mode according to Embodiment 1 of the present disclosure;

[0018] Figure 6 It is a schematic diagram of the execution process of a reconfigurable processor system including two processing unit arrays in the fast mode according to Embodiment 1 of the present disclosure;

[0019] Figure 7 It is a schematic diagram of the execution process of a reconfigurable processor system including two processing unit arrays in the normal mode according to Embodiment 1 of the present disclosure;

[0020] Figure 8 It is a schematic diagram of a simulation device for a reconfigurable processor system according to Embodiment 2 of the present disclosure; and

[0021] Figure 9 It is a schematic diagram of a simulation device for a reconfigurable processor system according to Embodiment 3 of the present disclosure. Detailed implementation manners

[0022] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0023] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present disclosure are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0024] Embodiment 1

[0025] According to this embodiment, an embodiment of a simulation method for a reconfigurable processor system is also provided. It should be noted that the steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer-executable instructions. And although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0026] The method embodiment provided in this embodiment can be executed in a mobile terminal, a computer terminal, a server or a similar computing device. Figure 1 The hardware structure block diagram of a computing device for implementing the simulation method of a reconfigurable processor system is shown. As Figure 1 shown, the computing device may include one or more processors (the processor may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory for storing data, and a transmission device for communication functions. In addition, it may further include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the I / O interface), a network interface, a power supply and / or a camera. Those of ordinary skill in the art can understand that Figure 1 the structure shown is only schematic and does not limit the structure of the above-mentioned electronic device. For example, the computing device may further include more or fewer components than Figure 1 shown, or have a different configuration from Figure 1 shown.

[0027] It should be noted that one or more of the above-mentioned processors and / or other data processing circuits can generally be referred to as "data processing circuits" herein. The data processing circuit can be embodied in software, hardware, firmware, or any combination thereof, in whole or in part. In addition, the data processing circuit can be a single independent processing module, or be incorporated in whole or in part into any one of other elements in the computing device. As involved in the embodiments of the present disclosure, the data processing circuit is a kind of processor control (such as the selection of a variable resistance terminal path connected to an interface).

[0028] The memory can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the simulation method of the reconfigurable processor system in the embodiments of the present disclosure. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, implements the simulation method of the reconfigurable processor system of the above application program. The memory can include high-speed random access memory, and can also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories. In some instances, the memory can further include a memory remotely set relative to the processor, and these remote memories can be connected to the computing device through a network. Examples of the above network include but are not limited to the Internet, intranet, local area network, mobile communication network, and combinations thereof.

[0029] The transmission device is used to receive or send data via a network. Specific examples of the above network can include a wireless network provided by a communication provider of the computing device. In one instance, the transmission device includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station and thus communicate with the Internet. In one instance, the transmission device can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0030] The display can be, for example, a touch-screen liquid crystal display (LCD), which enables a user to interact with the user interface of the computing device.

[0031] It should be noted here that in some alternative embodiments, the above Figure 1 shown computing device can include hardware elements (including circuits), software elements (including computer code stored on a computer-readable medium), or a combination of both hardware elements and software elements. It should be pointed out that Figure 1 is only an example of a specific specific instance, and is intended to show the types of components that can exist in the above computing device.

[0032] Figure 2AIt is a schematic diagram of the reconfigurable processor system according to this embodiment. As shown in Figure 2, a basic reconfigurable processor system includes two major modules: a central processor and a reconfigurable processor. The reconfigurable processor further includes a data import / export unit and an array of computing units. Data is usually stored in external storage. The reconfigurable processor uses the data import / export unit to read the data into on-chip storage, processes it through the array of computing units, writes it into on-chip storage, and writes it back to external storage through the data import / export unit. The central processor controls its execution process by writing to the status register of the reconfigurable processor and obtains its execution status by reading the status register. Figure 2B It is another schematic diagram of the reconfigurable processor system according to this embodiment, Figure 2B which shows a reconfigurable processor system including two arrays of processing units. The processing method is similar to that of a reconfigurable processing system including one array of processing units.

[0033] Under the above operating environment, according to the first aspect of this embodiment, a simulation method for a reconfigurable processor system is provided. Figure 3 It shows a schematic flowchart of the method. Referring to Figure 3 as shown, the method includes:

[0034] S302: Determine the simulation mode according to the input parameters of the user, where the simulation mode includes a normal mode and a fast mode;

[0035] S304: When the simulation mode is the fast mode, determine the simulation duration according to the input parameters; and

[0036] S306: Simulate the reconfigurable processor according to the clock synchronization points preset in the modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to the address-based interfaces within the reconfigurable processor system.

[0037] As described in the background art, reconfigurable processors usually require cycle-accurate simulators to simulate their functions. This is because if a node has multiple input edges, that is, it depends on multiple data inputs, then the multiple data inputs must arrive at the node at the same time; otherwise, data stalls will occur, reducing the computing efficiency. Therefore, it is necessary to model the number of computing clock cycles of the processing units on the simulator, so as to ensure the alignment between multiple data inputs of the node by using the compilation stage or hardware mechanism. Reconfigurable processors usually serve as coprocessors of the central processing unit (CPU). Therefore, the complete system often includes a central processor and peripheral devices. If cycle-accurate modeling is performed on the entire system, two problems will arise: large development workload and long execution time.

[0038] In view of this, an embodiment of the present application provides a simulation method for a reconfigurable processor system. First, the system simulator can determine a simulation mode according to the input parameters of the user, where the simulation mode includes a normal mode and a fast mode.

[0039] Specifically, developers can preset program parameters so that the simulation of the reconfigurable processor system with variable precision can be achieved through parameter setting. Thus, through the input parameters of the user, it can be determined whether the user selects the normal mode or the fast mode to perform the simulation of the reconfigurable processor system.

[0040] Furthermore, when the simulation mode is the fast mode, the system simulator can determine the simulation duration according to the input parameters. Then, the system simulator performs the simulation of the reconfigurable processor according to the clock synchronization points preset in the modules of the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to the address-based interfaces in the reconfigurable processor system.

[0041] Specifically, referring to Figure 2A and Figure 2B as shown, different modules in the reconfigurable processor system can be modeled with different precisions, so that while accurately modeling the clocks of key modules, other modules can be modeled with lower precision to ensure the correctness of mutual operations, thereby reducing the workload of system simulator development and improving the simulation speed. The simulation of the reconfigurable processor system is performed based on the simulation duration obtained from the parameters and the clock synchronization points in the fast mode.

[0042] Thus, through the above method, the synchronization precision is controlled by the operating parameters to meet different simulation requirements of users. And while accurately modeling the clocks of key modules, other modules can be modeled with lower precision to ensure the correctness of mutual operations, thereby reducing the workload of system simulator development and improving the simulation speed. Furthermore, the technical problems in the prior art that the existing simulation method of the reconfigurable processor needs to accurately model the clocks of all system modules, resulting in a large development workload and a long execution time, are solved.

[0043] In addition, each clock-accurate module in the system defines its own clock. Since the system simulator maintains a global clock, it is necessary to synchronize the module internal clock and the global clock at appropriate moments, and these moments are the clock synchronization points.

[0044] Optionally, the reconfigurable processor includes an array of processing units and a data import / export unit, and the external device includes an external storage and a central processing unit. The array of processing units is connected to the central processing unit through a reconfigurable processor status register; the array of processing units is connected to the data import / export unit through on-chip storage of the reconfigurable processor; the data import / export unit is connected to the external storage, and the reconfigurable processor status register and the on-chip storage of the reconfigurable processor are address-based interfaces.

[0045] Specifically, referring to Figure 2A and Figure 2B As shown, the reconfigurable processor is connected to the external device through the reconfigurable processor status register and the on-chip storage of the reconfigurable processor as an interface, and the reconfigurable processor status register and the on-chip storage of the reconfigurable processor implement a synchronization mechanism based on addresses. Thus, through the interface design of the above reconfigurable processor system, the address-based inter-module synchronization mechanism of this solution can be implemented. Based on this mechanism, interoperability between different-precision simulator modules can be achieved. The prerequisite for the simulator to use this synchronization mechanism is that the modules with different precisions in the system are only coupled through the status of address mapping.

[0046] Optionally, according to the preset clock synchronization points and simulation duration of the reconfigurable processor, the operation of simulating the reconfigurable processor includes: determining whether the current simulation time is less than the simulation duration. When the current simulation time is less than the simulation duration, the central processing unit simulates the execution of one machine cycle and determines whether the central processing unit reaches the preset clock synchronization point. When the central processing unit does not reach the clock synchronization point, the central processing unit simulates the execution of one machine cycle; when the central processing unit reaches the clock synchronization point, the data import / export unit simulates the execution of one machine cycle and determines whether the data import / export unit reaches the clock synchronization point. When the data import / export unit does not reach the clock synchronization point, the data import / export unit simulates the execution of one machine cycle; when the data import / export unit reaches the clock synchronization point, the array of processing units simulates the execution of one machine cycle; and when the simulation of one machine cycle by the array of processing units ends, the simulation time is incremented by 1, and it is determined whether the simulation time is less than the simulation duration. When the simulation time is not less than the simulation duration, the simulation of the reconfigurable processor ends.

[0047] Specifically, referring to Figure 4A and Figure 4BAs shown, after the simulation starts, the central processing unit executes one cycle, and then determines whether the module has reached a pre-set clock synchronization point. When the clock synchronization point has not been reached, the central processing unit continues to process one machine cycle until the pre-set clock synchronization point is reached. Then, the next module's data import / export unit executes a machine cycle, and then determines whether the data import / export unit has reached the clock synchronization point. If the clock synchronization point is reached, the execution of the next module is carried out. Finally, the processing unit array is simulated for one clock cycle, one loop ends, the simulation time is incremented by 1, and then it is determined whether the simulation duration has been reached, so as to determine whether the simulation is completed.

[0048] In addition, the reconfigurable processor system not only includes Figure 2A and Figure 2B the modules shown in, when other modules are included, the simulation is also carried out in the above manner.

[0049] Optionally, the method further includes: when the simulation mode is the normal mode, simulating the reconfigurable processor according to the simulation duration. Thus, this application allows the synchronization accuracy to be controlled by operating parameters, so as to meet different simulation requirements.

[0050] Optionally, when the simulation mode is the normal mode, the operation of simulating the reconfigurable processor according to the simulation duration includes: determining whether the current simulation time is less than the simulation duration. When the current simulation time is less than the simulation duration, the central processing unit simulates and executes one machine cycle; after the central processing unit simulates and executes one machine cycle, the data import / export unit simulates and executes one machine cycle; after the data import / export unit simulates and executes one machine cycle, the processing unit array simulates and executes one machine cycle; and after the processing unit array simulates and executes one machine cycle, the simulation time is incremented by 1, and it is determined whether the simulation time is less than the simulation duration. When the simulation time is not less than the simulation duration, the simulation of the reconfigurable processor ends.

[0051] Specifically, referring to Figure 5A and Figure 5B shown, when the user selects to run in the normal mode through parameters, the simulation starts in the normal mode, that is, clock accuracy modeling is carried out for all modules in the reconfigurable processor system. The central processing unit, the data import / export unit, and the processing unit array respectively simulate and execute one machine cycle, the simulation time is incremented by 1, and then the simulation time is compared with the simulation duration. When it is not less than the simulation duration, the simulation ends.

[0052] Optionally, it further includes: performing clock accuracy modeling on the processing unit array through a clock accuracy model; performing functional-level modeling on the central processing unit through a functional model; and performing functional-level modeling on the data import / export unit through a functional model.

[0053] Specifically, there are two options for adding clock synchronization points to the clock accurate model:

[0054] a. If there is only a single clock accurate module in the system, or there are multiple clock accurate modules and the modules work simultaneously, the system clock can be aligned with the clock inside the clock accurate module;

[0055] b. If there are multiple clock accurate modules in the system but they work alternately, clock synchronization points can be used to separate them when the modules access addresses coupled to the outside.

[0056] The system simulator adds clock synchronization points to the central processing unit module and the data import / export unit:

[0057] a) Two types of clock synchronization points are added to the central processing unit module, and one of them can be selected during operation. The first one has relatively higher accuracy, but the execution speed of the simulator is also slower:

[0058] i. Perform clock synchronization after each instruction ends: that is, assume that each instruction consumes one clock cycle;

[0059] ii. Perform clock synchronization after reading and writing the status register of the reconfigurable processor.

[0060] The system simulator adds two types of clock synchronization points to the data import / export module, and one of them can be selected during operation. The first one has relatively higher accuracy, but the execution speed of the simulator is also slower:

[0061] i. Perform clock synchronization every 16 bytes of data written, that is, transfer 16 bytes of data per clock cycle;

[0062] ii. Perform clock synchronization after a data transfer command ends.

[0063] The system simulator adds a clock synchronization point to the processing unit array. Since only the processing unit array in this system is modeled with clock accuracy, the system clock is aligned with this module.

[0064] Thus, through the above methods, clock accurate modeling is performed on the processing unit array, and functional-level modeling is performed on the central processing unit and the data import / export unit, so that modeling in the fast mode can be achieved, the correctness of mutual operations can be ensured, the workload of system simulator development can be reduced, and the simulation speed can be increased.

[0065] In addition, the specific implementation of this embodiment is as follows:

[0066] 1. Model each module in the system with different accuracies according to system simulation requirements. Typical accuracies include the clock accurate model, functional model, etc.

[0067] 2. Maintain a global system clock in the system simulator.

[0068] 3. Add clock synchronization points for low-precision models: Since modules with low-precision modeling often do not have clock information, it is necessary to add clock synchronization points. At these clock synchronization points, the clocks of modules with different precision modeling will be aligned. Depending on different simulation precision requirements, the positions of inserting clock synchronization points in low-precision models are optional. If more clock synchronization points are inserted, the number of clock alignments will be more, but it may also result in more development effort and a decrease in simulation speed. The requirement of this mechanism for clock synchronization points is that if two operations of a model both access (read or write) an address coupled with other modules, then these two operations need to be separated by a clock synchronization point.

[0069] 4. There are two options for adding clock synchronization points to clock-precise models:

[0070] a) If there is only a single clock-precise module in the system, or there are multiple clock-precise modules and the modules work simultaneously, then the system clock can be aligned with the clocks inside the clock-precise modules;

[0071] b) If there are multiple clock-precise modules in the system but they work alternately, then when the modules access addresses coupled with the outside, they can be separated by clock synchronization points.

[0072] Specifically, for multiple clock-precise modules working alternately, the simulation calculation amount can be reduced by setting synchronization points. Taking two modules A and B as an example: A works first and B works later. After A works, it needs to interact with the system, and the interaction method is usually to read and write an address that can be accessed by both A and the system. When setting a clock synchronization point during the access, only module A is activated before reaching the synchronization point, instead of synchronizing with the system clock at each clock, thus saving a large amount of simulation overhead for activating other modules.

[0073] 5. When the system clock advances one clock cycle:

[0074] a) For modules with clock-precise modeling,

[0075] i. If the system clock is synchronized with the module, then execute the operations that need to be executed in this clock cycle in the module;

[0076] ii. If the system clock is not synchronized with the module, then the module executes until the clock synchronization point.

[0077] b) For modules with non-clock-precise modeling, then execute the operations between the clock synchronization points of the module. It should be noted that the effectiveness of the synchronization point can be controlled according to the runtime parameters of the system simulator, so as to achieve different simulation precision requirements.

[0078] In addition, in a reconfigurable processor, it is usually only necessary to accurately model the clock of the processing unit array. This module is only coupled to other modules through the reconfigurable processor status register and on-chip storage, so it meets the requirements of the synchronization mechanism of the present invention. According to the synchronization mechanism proposed in the present invention, the system simulator is designed as follows:

[0079] 1. In the Figure 2A system, the present invention accurately models the clock of the processing unit array and functionally models the central processing unit and the data import / export unit;

[0080] 2. Add clock synchronization points for the central processing unit module and the data import / export unit:

[0081] a) Add two types of clock synchronization points in the central processing unit module, and one of them can be selected during operation. The first one has relatively high accuracy, but the simulator execution speed is also slower.

[0082] i. Perform clock synchronization after each instruction ends: that is, assume that each instruction consumes one clock cycle;

[0083] ii. Perform clock synchronization after reading and writing the status register of the reconfigurable processor.

[0084] b) Add two types of clock synchronization points for the data import / export module, and one of them can be selected during operation. The first one has relatively high accuracy, but the simulator execution speed is also slower.

[0085] i. Perform clock synchronization every 16 bytes of data written, that is, 16 bytes of data are transferred per clock cycle;

[0086] ii. Perform clock synchronization after a data transfer command ends.

[0087] 3. Add a clock synchronization point for the processing unit array. Since only the processing unit array is accurately modeled for the clock in this system, the system clock is aligned with this module.

[0088] 4. Define two execution modes for the system simulator, fast mode and normal speed mode. In fast mode, both the central processing unit and the data import / export unit adopt relatively high-precision synchronization methods, while in normal speed mode, both adopt lower-precision methods. When the system clock advances,

[0089] a) The processing unit array executes operations on a single clock;

[0090] b) If the normal speed mode is selected, both the central processing unit and the import / export unit use the first synchronization point, and their execution is as Figure 4B shown. In the figure, the module marked with E is the module that actually executes valid operations.

[0091] i. The central processing unit executes an instruction;

[0092] ii. If the data import / export unit is in the process of executing a command, it transfers 16 bytes of data.

[0093] c) If the fast mode is selected, both the central processing unit and the import / export unit use the second synchronization point, and its execution Figure 5B as shown

[0094] i. The central processing unit executes multiple instructions until it accesses the status register of the reconfigurable processor;

[0095] ii. If the data import / export unit receives a data transfer command, it completes the execution of the command.

[0096] It can be seen that in the normal speed mode, each instruction on the central processing unit requires one machine cycle, and the data transfer command is divided into multiple machine cycles according to the data volume. Although the array does not start computing during these machine cycles, the change of the clock will cause a large number of status updates in the processing unit array. This modeling method can synchronize the status updates of the processor and the data import / export unit at the system level, but the computational workload is large. Especially when starting the operating system, a large number of system clock changes will cause the system to consume a long simulation time.

[0097] For system simulation, most of the time, such frequent and unnecessary status synchronization, or recording the status updates of the processor and the data import / export unit, is not required. Therefore, the fast mode can be used. In the fast mode, the instructions and data transfer commands on the central processing unit that do not affect the outside are completed within one machine cycle, thus avoiding the simulation computational workload required to update the status of a large number of units in the processing unit array.

[0098] In addition, there are two processing unit arrays in the system, as Figure 2B shown, and its data processing flow is similar to that of Embodiment 1, which will not be elaborated here. Assuming that Processing Unit Array 1 and Processing Unit Array 2 work alternately, the simulator is designed as follows:

[0099] 1. In the above system, the present invention accurately models the clocks of Processing Unit Arrays 1 and 2, and functionally models the central processing unit and the data import / export unit.

[0100] 2. Add clock synchronization points to the central processing unit module and the data import / export unit, and the adding method is the same as that of Embodiment 1.

[0101] 3. Add clock synchronization points to the processing unit array:

[0102] a) When the clock in the processing unit array module advances, a system clock synchronization is performed, that is, the clock in the module is aligned with the system clock;

[0103] b) When the processing unit array completes a full calculation task, a system clock synchronization is performed.

[0104] 4. When the system clock advances:

[0105] a) The behavior of the central processing unit module and the data import / export module is the same as that in Mode 1.

[0106] b) The behavior of the processing unit array is as follows:

[0107] i. If the normal speed mode is selected, the first synchronization point is utilized, and the execution method is as Figure 6 shown.

[0108] ii. If the fast mode is selected, the second synchronization point is utilized, and the execution method is as Figure 7 shown.

[0109] Among them, Figure 6 and Figure 7 due to the picture height limitation, the effective array execution computation amount in the fast mode does not increase proportionally. It can be seen that by decoupling the clock of the clock precision module from the system clock, the additional computation amount caused by the unenabled module is further reduced.

[0110] In addition, as shown in Figure 1 According to the second aspect of this embodiment, a storage medium is provided. The storage medium includes a stored program, wherein, when the program runs, the method described in any one of the above is executed by a processor.

[0111] Thus, according to this embodiment, the synchronization precision is controlled by operating parameters to meet different simulation requirements of users. While accurately modeling the clocks of key modules, other modules can be modeled with lower precision to ensure the correctness of mutual operations, thereby reducing the workload of system simulator development and increasing the simulation speed. Furthermore, the technical problem in the prior art that the existing simulation method of the reconfigurable processor requires accurate clock modeling for all system modules, resulting in a large development workload and a long execution time, is solved.

[0112] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0113] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc), and includes several instructions for causing a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0114] Embodiment 2

[0115] Figure 8 Fig. shows a simulation device 800 of a reconfigurable processor system according to the present embodiment. This device 800 corresponds to the method described in the first aspect of Embodiment 1. Refer to Figure 8 As shown, the device 800 includes: a first determination module 810 for determining a simulation mode according to input parameters of a user, where the simulation mode includes a normal mode and a fast mode; a second determination module 820 for determining a simulation duration according to the input parameters when the simulation mode is the fast mode; and a first simulation module 830 for simulating the reconfigurable processor according to clock synchronization points preset in modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to address-based interfaces within the reconfigurable processor system.

[0116] Optionally, the reconfigurable processor includes a processing unit array and a data import / export unit, the external device includes an external storage and a central processor, where the processing unit array is connected to the central processor through a reconfigurable processor status register; the processing unit array is connected to the data import / export unit through a reconfigurable processor on-chip storage; the data import / export unit is connected to the external storage, where the reconfigurable processor status register and the reconfigurable processor on-chip storage are address-based interfaces.

[0117] Optionally, the first simulation module 830 includes: a first execution sub-module, configured to determine whether the current simulation time is less than the simulation duration. If the current simulation time is less than the simulation duration, the central processing unit (CPU) simulates the execution of one machine cycle and determines whether the CPU reaches a pre-set clock synchronization point. If the CPU does not reach the clock synchronization point, the CPU simulates the execution of one machine cycle; a second execution sub-module, configured to, if the CPU reaches the clock synchronization point, the data import / export unit simulates the execution of one machine cycle and determines whether the data import / export unit reaches the clock synchronization point. If the data import / export unit does not reach the clock synchronization point, the data import / export unit simulates the execution of one machine cycle; a third execution sub-module, configured to, if the data import / export unit reaches the clock synchronization point, the processing unit array simulates the execution of one machine cycle; and a first end sub-module, configured to, when the processing unit array finishes simulating the execution of one machine cycle, increment the simulation time by 1, determine whether the simulation time is less than the simulation duration, and if the simulation time is not less than the simulation duration, end the simulation of the reconfigurable processor.

[0118] Optionally, the apparatus 800 further includes: a second simulation module, configured to simulate the reconfigurable processor according to the simulation duration when the simulation mode is the normal mode.

[0119] Optionally, the second simulation module includes: a fourth execution sub-module, configured to determine whether the current simulation time is less than the simulation duration. If the current simulation time is less than the simulation duration, the CPU simulates the execution of one machine cycle; a fifth execution sub-module, configured to, when the CPU finishes simulating the execution of one machine cycle, the data import / export unit simulates the execution of one machine cycle; a sixth execution sub-module, configured to, when the data import / export unit finishes simulating the execution of one machine cycle, the processing unit array simulates the execution of one machine cycle; and a second end sub-module, configured to, when the processing unit array finishes simulating the execution of one machine cycle, increment the simulation time by 1, determine whether the simulation time is less than the simulation duration, and if the simulation time is not less than the simulation duration, end the simulation of the reconfigurable processor.

[0120] Optionally, the apparatus 800 further includes: a first modeling module, configured to perform clock-accurate modeling on the processing unit array through a clock-accurate model; a second modeling module, configured to perform functional-level modeling on the CPU through a functional model; and a third modeling module, configured to perform functional-level modeling on the data import / export unit through a functional model.

[0121] Therefore, according to this embodiment, the synchronization accuracy is controlled by operating parameters to meet different simulation requirements of users. While accurately modeling the clocks of key modules, other modules can be modeled with lower precision to ensure the correctness of mutual operations, thereby reducing the workload of developing the system simulator and increasing the simulation speed. Furthermore, it solves the technical problems in the prior art that the existing simulation method of reconfigurable processors requires accurate clock modeling for all system modules, resulting in a large development workload and a long execution time.

[0122] Embodiment 3

[0123] Figure 9 Fig. 9 shows a simulation device 900 of a reconfigurable processor system according to Embodiment 9 described herein. The device 900 corresponds to the method according to the first aspect of Embodiment 1. Refer to Figure 9 As shown, the device 900 includes: a processor 910; and a memory 920, connected to the processor 910, for providing instructions for the processor 910 to process the following steps: determining a simulation mode according to user input parameters, where the simulation mode includes a normal mode and a fast mode; in the case where the simulation mode is the fast mode, determining a simulation duration according to the input parameters; and simulating the reconfigurable processor according to clock synchronization points preset in the modules of the reconfigurable processor system and the simulation duration, where the clock synchronization points are set based on the address-based interfaces in the reconfigurable processor system.

[0124] Optionally, the reconfigurable processor includes a processing unit array and a data import / export unit, the external device includes an external storage and a central processing unit, where the processing unit array is connected to the central processing unit through a reconfigurable processor status register; the processing unit array is connected to the data import / export unit through a reconfigurable processor on-chip storage; the data import / export unit is connected to the external storage, where the reconfigurable processor status register and the reconfigurable processor on-chip storage are address-based interfaces.

[0125] Optionally, the operation of simulating the reconfigurable processor according to the preset clock synchronization point and simulation duration of the reconfigurable processor includes: determining whether the current simulation time is less than the simulation duration. If the current simulation time is less than the simulation duration, the central processing unit (CPU) simulates the execution of one machine cycle and determines whether the CPU reaches the preset clock synchronization point. If the CPU does not reach the clock synchronization point, the CPU simulates the execution of one machine cycle; if the CPU reaches the clock synchronization point, the data import / export unit simulates the execution of one machine cycle and determines whether the data import / export unit reaches the clock synchronization point. If the data import / export unit does not reach the clock synchronization point, the data import / export unit simulates the execution of one machine cycle; if the data import / export unit reaches the clock synchronization point, the processing unit array simulates the execution of one machine cycle; and after the processing unit array simulates the execution of one machine cycle, the simulation time is incremented by 1, and it is determined whether the simulation time is less than the simulation duration. If the simulation time is not less than the simulation duration, the simulation of the reconfigurable processor ends.

[0126] Optionally, the memory 920 is further configured to provide instructions for the processor 910 to process the following processing steps: in the case where the simulation mode is the normal mode, simulating the reconfigurable processor according to the simulation duration.

[0127] Optionally, in the case where the simulation mode is the normal mode, the operation of simulating the reconfigurable processor according to the simulation duration includes: determining whether the current simulation time is less than the simulation duration. If the current simulation time is less than the simulation duration, the central processing unit (CPU) simulates the execution of one machine cycle; after the CPU simulates the execution of one machine cycle, the data import / export unit simulates the execution of one machine cycle; after the data import / export unit simulates the execution of one machine cycle, the processing unit array simulates the execution of one machine cycle; and after the processing unit array simulates the execution of one machine cycle, the simulation time is incremented by 1, and it is determined whether the simulation time is less than the simulation duration. If the simulation time is not less than the simulation duration, the simulation of the reconfigurable processor ends.

[0128] Optionally, the memory 920 is further configured to provide instructions for the processor 910 to process the following processing steps: performing clock-accurate modeling on the processing unit array through a clock accurate model; performing functional-level modeling on the central processing unit through a functional model; and performing functional-level modeling on the data import / export unit through a functional model.

[0129] Therefore, according to this embodiment, the synchronization accuracy is controlled by operating parameters to meet different simulation requirements of users. While accurately modeling the clocks of key modules, lower-precision modeling can be used for other modules to ensure the correctness of mutual operations, thereby reducing the workload of system simulator development and improving the simulation speed. Furthermore, it solves the technical problems in the prior art that the existing simulation methods for reconfigurable processors require accurate clock modeling for all system modules, resulting in a large development workload and a long execution time.

[0130] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments.

[0131] In the above embodiments of the present invention, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0132] In the several embodiments provided by the present invention, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the units or modules can be in an electrical or other form.

[0133] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0134] In addition, the functional units in each embodiment of the present invention can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0135] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs that can store program codes.

[0136] The foregoing are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A simulation method for a reconfigurable processor system, the reconfigurable processor including a reconfigurable processor and external devices, characterized in that, Including: Determine a simulation mode according to input parameters of a user, where the simulation mode includes a normal mode and a fast mode; When the simulation mode is the fast mode, determine a simulation duration according to the input parameters; And Perform simulation on the reconfigurable processor according to clock synchronization points preset in modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to address-based interfaces within the reconfigurable processor system; The reconfigurable processor includes an array of processing units and a data import / export unit, and the external device includes an external storage and a central processor, where The array of processing units is connected to the central processor through a reconfigurable processor status register; The array of processing units is connected to the data import / export unit through on-chip storage of the reconfigurable processor; and The data import / export unit is connected to the external storage, where the reconfigurable processor status register and the on-chip storage of the reconfigurable processor are the address-based interfaces; The operation of performing simulation on the reconfigurable processor according to the clock synchronization points preset for the reconfigurable processor and the simulation duration includes: Judge whether the current simulation time is less than the simulation duration. When the current simulation time is less than the simulation duration, the central processor simulates and executes one machine cycle, and judge whether the central processor reaches the preset clock synchronization point. When the central processor does not reach the clock synchronization point, the central processor simulates and executes one machine cycle; When the central processor reaches the clock synchronization point, the data import / export unit simulates and executes one machine cycle, and judge whether the data import / export unit reaches the clock synchronization point. When the data import / export unit does not reach the clock synchronization point, the data import / export unit simulates and executes one machine cycle; When the data import / export unit reaches the clock synchronization point, the array of processing units simulates and executes one machine cycle; and When the simulation of one machine cycle by the array of processing units ends, the simulation time is incremented by 1, and judge whether the simulation time is less than the simulation duration. When the simulation time is not less than the simulation duration, the simulation of the reconfigurable processor ends.

2. The method according to claim 1, characterized in that, Further including: When the simulation mode is the normal mode, perform simulation on the reconfigurable processor according to the simulation duration.

3. The method according to claim 2, wherein When the simulation mode is the normal mode, the operation of performing simulation on the reconfigurable processor according to the simulation duration includes: Judge whether the current simulation time is less than the simulation duration. When the current simulation time is less than the simulation duration, the central processor simulates and executes one machine cycle; When the simulation of one machine cycle by the central processor ends, the data import / export unit simulates and executes one machine cycle; When the simulation of one machine cycle by the data import / export unit ends, the array of processing units simulates and executes one machine cycle; and When the simulation execution of the processing unit array ends one machine cycle, the simulation time is incremented by 1, and it is determined whether the simulation time is less than the simulation duration. When the simulation time is not less than the simulation duration, the simulation of the reconfigurable processor ends.

4. The method according to claim 1, wherein It further includes: Performing clock-accurate modeling on the processing unit array through a clock-accurate model; Performing functional-level modeling on the central processing unit through a functional model; And Performing functional-level modeling on the data import / export unit through the functional model.

5. A storage medium, characterized in that, The storage medium includes a stored program, wherein when the program runs, the method according to any one of claims 1 to 4 is executed by a processor.

6. A simulation device for a reconfigurable processor system, the reconfigurable processor including a reconfigurable processor and external devices, characterized in that It includes: A first determination module for determining a simulation mode according to user input parameters, where the simulation mode includes a normal mode and a fast mode; A second determination module for determining the simulation duration according to the input parameters when the simulation mode is the fast mode; And A first simulation module for simulating the reconfigurable processor according to the clock synchronization points preset in the modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to the address-based interfaces within the reconfigurable processor system; The reconfigurable processor includes a processing unit array and a data import / export unit, and the external device includes an external storage and a central processing unit, where The processing unit array is connected to the central processing unit through a reconfigurable processor status register; The processing unit array is connected to the data import / export unit through on-chip storage of the reconfigurable processor; and The data import / export unit is connected to the external storage, where the reconfigurable processor status register and the on-chip storage of the reconfigurable processor are the address-based interfaces; The first simulation module includes: A first execution sub-module for determining whether the current simulation time is less than the simulation duration. When the current simulation time is less than the simulation duration, the central processing unit simulates the execution of one machine cycle and determines whether the central processing unit reaches the preset clock synchronization point. When the central processing unit does not reach the clock synchronization point, the central processing unit simulates the execution of one machine cycle; A second execution sub-module for, when the central processing unit reaches the clock synchronization point, the data import / export unit simulates the execution of one machine cycle and determines whether the data import / export unit reaches the clock synchronization point. When the data import / export unit does not reach the clock synchronization point, the data import / export unit simulates the execution of one machine cycle; A third execution sub-module for, when the data import / export unit reaches the clock synchronization point, the processing unit array simulates the execution of one machine cycle; and A first end sub-module, which is used for the simulation execution of the processing unit array to end a machine cycle, increment the simulation time by 1, and determine whether the simulation time is less than the simulation duration. If the simulation time is not less than the simulation duration, the simulation of the reconfigurable processor ends.

7. A simulation device for a reconfigurable processor system, the reconfigurable processor including a reconfigurable processor and external devices, characterized in that, Including: A processor; And A memory, connected to the processor, and used to provide instructions for the processor to process the following processing steps: Determine the simulation mode according to the input parameters of the user, where the simulation mode includes a normal mode and a fast mode; If the simulation mode is the fast mode, determine the simulation duration according to the input parameters; And Simulate the reconfigurable processor according to the clock synchronization points preset in the modules within the reconfigurable processor system and the simulation duration, where the clock synchronization points are set according to the address-based interfaces within the reconfigurable processor system; The reconfigurable processor includes a processing unit array and a data import / export unit, and the external device includes an external storage and a central processor, where The processing unit array is connected to the central processor through a reconfigurable processor status register; The processing unit array is connected to the data import / export unit through a reconfigurable processor on-chip storage; and The data import / export unit is connected to the external storage, where the reconfigurable processor status register and the reconfigurable processor on-chip storage are the address-based interfaces; The operation of simulating the reconfigurable processor according to the clock synchronization points preset in the reconfigurable processor and the simulation duration includes: Determine whether the current simulation time is less than the simulation duration. If the current simulation time is less than the simulation duration, the central processor simulates and executes a machine cycle, and determine whether the central processor reaches the preset clock synchronization point. If the central processor does not reach the clock synchronization point, the central processor simulates and executes a machine cycle; If the central processor reaches the clock synchronization point, the data import / export unit simulates and executes a machine cycle, and determine whether the data import / export unit reaches the clock synchronization point. If the data import / export unit does not reach the clock synchronization point, the data import / export unit simulates and executes a machine cycle; If the data import / export unit reaches the clock synchronization point, the processing unit array simulates and executes a machine cycle; and When the simulation execution of a machine cycle by the processing unit array ends, the simulation time is incremented by 1, and it is determined whether the simulation time is less than the simulation duration. If the simulation time is not less than the simulation duration, the simulation of the reconfigurable processor ends.

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