A convolution process simplified method, device, equipment and storage medium

Abstract

The present invention discloses a method, device, equipment and storage medium for simplifying a convolution process. The present invention obtains a convolution kernel matrix and a matrix to be operated, decomposes the convolution kernel matrix, obtains the difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix, performs a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and performs a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result. Differential processing is performed on the first convolution result and the second convolution result to obtain a true convolution result, which is equivalent to adding a second convolution on the basis of the original number of convolutions, which is beneficial to reducing the number of convolutions; at the same time, there is no need to double the hardware resources, which is beneficial to saving hardware resources, manufacturing costs and occupied area. The present invention can be widely applied to the technical fields of a method, device, equipment and storage medium for simplifying a convolution process.

Description

Technical Field

[0001] The present invention relates to the field of neural network hardware accelerators, and in particular to a method, device, equipment and storage medium for simplifying a convolution process. Background Art

[0002] Existing hardware acceleration for convolution requires preserving the sign of matrix elements during calculations. Therefore, to perform signed matrix multiplication, the signed numbers in the matrix are typically classified into non-negative and negative numbers. Convolution operations on these two types of numbers are then performed in two separate hardware systems, and the two results are combined in a push-pull system to produce the final result. However, this approach doubles the hardware resources and the number of convolutions, resulting in additional manufacturing costs and footprint. This approach significantly reduces system integration, necessitating a solution. Summary of the Invention

[0003] In view of this, in order to solve at least one of the above technical problems, the purpose of the present invention is to provide a simplified method, device, equipment and storage medium for the convolution process, thereby reducing the number of convolutions, saving hardware resources and manufacturing costs.

[0004] The technical solution adopted in the embodiment of the present invention is:

[0005] A simplified method for the convolution process, comprising:

[0006] Obtaining a convolution kernel matrix and a matrix to be operated; wherein the elements to be operated on the matrix to be operated are non-negative;

[0007] Decomposing the convolution kernel matrix to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix;

[0008] Performing a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and performing a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result;

[0009] Differential processing is performed based on the first convolution result and the second convolution result to obtain a true convolution result.

[0010] Furthermore, the convolution kernel matrix includes a plurality of convolution kernel elements, and the second decomposition matrix includes a plurality of identical second decomposition elements; the decomposition processing of the convolution kernel matrix to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix includes:

[0011] Calculating the absolute value of each of the convolution kernel elements and determining the maximum absolute value;

[0012] Determine a constant value of the second decomposition element according to the maximum absolute value; the constant value is greater than or equal to the maximum absolute value;

[0013] The convolution kernel matrix is decomposed according to the constant value to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix.

[0014] Furthermore, the second decomposition matrix includes a plurality of identical second decomposition elements; and the decomposition processing of the convolution kernel matrix to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix includes:

[0015] When the convolution kernel matrix is obtained through normalization processing, determining the value of the second decomposition element to be 1;

[0016] The convolution kernel matrix is decomposed according to the second decomposition element having a value of 1 to obtain a difference between a non-negative first decomposition matrix and a non-negative all-one matrix.

[0017] Further, performing differential processing on the first convolution result and the second convolution result to obtain a true convolution result includes:

[0018] Calculate the difference between the first convolution result and the second convolution result to obtain a true convolution result.

[0019] Further, performing a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and performing a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result, includes:

[0020] The first decomposition matrix, the matrix to be operated, and the second decomposition matrix are input into a matrix multiplication accelerator, wherein the matrix multiplication accelerator includes a single memristor array; the single memristor array is used to perform a first convolution based on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and to perform a second convolution based on the second decomposition matrix and the matrix to be operated to obtain a second convolution result.

[0021] Furthermore, the matrix multiplication accelerator further includes a peripheral circuit, and performing differential processing on the first convolution result and the second convolution result to obtain a true convolution result includes:

[0022] The first convolution result and the second convolution result output by the single memristor array are received through the peripheral circuit, and the difference between the first convolution result and the second convolution result is calculated through the peripheral circuit to obtain a true convolution result.

[0023] An embodiment of the present invention further provides a device for simplifying the convolution process, including:

[0024] An acquisition module is used to acquire a convolution kernel matrix and a matrix to be operated; the elements to be operated in the matrix to be operated are non-negative;

[0025] A decomposition module, configured to decompose the convolution kernel matrix to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix;

[0026] A matrix multiplication accelerator is used to perform a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and to perform a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result; and to perform differential processing on the first convolution result and the second convolution result to obtain a true convolution result.

[0027] Furthermore, the matrix multiplication accelerator includes a single memristor array and a peripheral circuit connected to the single memristor array; the single memristor array is used to perform a first convolution based on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and to perform a second convolution based on the second decomposition matrix and the matrix to be operated to obtain a second convolution result; the peripheral circuit is used to perform differential processing based on the first convolution result and the second convolution result to obtain a true convolution result.

[0028] An embodiment of the present invention also provides an electronic device, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the method.

[0029] An embodiment of the present invention also provides a computer-readable storage medium, in which at least one instruction, at least one program, a code set or an instruction set is stored. The at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the method.

[0030] The beneficial effects of the present invention are: by obtaining a convolution kernel matrix and a matrix to be operated, decomposing the convolution kernel matrix to obtain the difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix, performing a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and performing a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result, performing differential processing on the first convolution result and the second convolution result to obtain a true convolution result, which is equivalent to adding a second convolution on the basis of the original number of convolutions, which is beneficial to reducing the number of convolutions; at the same time, there is no need to double the hardware resources, which is beneficial to saving hardware resources, manufacturing costs and occupied area. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the steps of the simplified method of the convolution process of the present invention;

[0032] Figure 2 Schematic diagram of a matrix multiplication accelerator according to a specific embodiment of the present invention;

[0033] Figure 3 Schematic diagram of the convolution process according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0035] The terms "first," "second," "third," and "fourth," etc., in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, rather than to describe a specific order. In addition, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0036] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] like Figure 1 As shown, an embodiment of the present invention provides a simplified method for the convolution process, including steps S100-S400:

[0038] S100: Obtain a convolution kernel matrix and a matrix to be operated.

[0039] In the embodiment of the present invention, when performing convolution, the convolution layer may have several different convolution kernels (or called convolution kernel matrices) K i, i = 1, 2, ..., n, where n is the number of different convolution kernels (convolution kernel matrices) in the convolution layer. Optionally, each convolution kernel matrix includes a number of convolution kernel elements, and the matrix to be operated on has a number of elements to be operated on. The matrix to be operated on M is usually the original information matrix containing the image or speech in the input layer, or is usually the result matrix obtained after the nonlinear operation of the previous layer in the hidden layer. Therefore, the elements to be operated on in the matrix to be operated on M are all non-negative.

[0040] S200 , decomposing the convolution kernel matrix to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix.

[0041] In the embodiment of the present invention, a number of elements in the first decomposition matrix are recorded as first decomposition elements, and a number of elements in the second decomposition matrix are recorded as second decomposition elements.

[0042] Optionally, step S200 may include step S210 or S220:

[0043] S210. When the convolution kernel matrix is obtained through normalization, the value of the second decomposition element is determined to be 1; the convolution kernel matrix is decomposed according to the second decomposition element with a value of 1 to obtain the difference between the non-negative first decomposition matrix and the non-negative all-one matrix.

[0044] In the embodiment of the present invention, the convolution kernel matrix may be a matrix that has been normalized in advance, and the convolution kernel matrix K i The convolution kernel elements in the range [-1, 1] can be determined. At this time, the value of the second decomposition element can be determined to be 1, that is, the second decomposition matrix is determined to be a full 1 matrix. At this time, the convolution kernel matrix K is calculated based on the second decomposition element with a value of 1. i Decomposition processing, the specific formula is:

[0045] K i =K′ i -1=K′ i -K′0

[0046] Among them, K i is the convolution kernel matrix, K′ i is the non-negative first decomposition matrix, 1, and K′0 is the second decomposition matrix (all-1 matrix).

[0047] S220. Calculate the absolute value of each convolution kernel element and determine the maximum absolute value; determine the constant value of the second decomposition element based on the maximum absolute value; decompose the convolution kernel matrix based on the constant value to obtain the difference between the non-negative first decomposition matrix and the non-negative second decomposition matrix.

[0048] Optionally, when the convolution kernel matrix has not been normalized, the absolute value of each convolution kernel element is calculated and the maximum absolute value is determined. For example, the maximum absolute value is X1. The constant value X2 of the second decomposition element is determined according to the maximum absolute value (X2 ≥ X1). That is, the second decomposition matrix is determined to be a matrix of all X2. At this time, the convolution kernel matrix K is normalized according to the constant value X2. i Decomposition processing, the specific formula is:

[0049] K i =K″ i -X2=K″ i -K″0

[0050] Among them, K i is a non-negative first decomposition matrix, and K″0 is a second decomposition matrix. It should be noted that in the embodiment of the present invention, the convolution kernel matrix is taken as an example as a matrix that has been normalized in advance, that is, K i =K′ i -1=K′ i -K′0 is used as an example for description and is not specifically limited in other embodiments.

[0051] S300: Perform a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and perform a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result.

[0052] Optionally, in the embodiment of the present invention, the convolution process is processed by a matrix multiplication accelerator of neural network hardware as an example for explanation. Other means may be used in other embodiments without specific limitation.

[0053] In the embodiment of the present invention, Figure 2 As shown, the matrix multiplication accelerator includes a single memristor array 201 (only part of it is shown) and a peripheral circuit 202 (only part of it is shown) connected to the output end of the single memristor array; x and y represent elements at corresponding positions (x, y) in the input matrix. In this embodiment of the present invention, the first decomposition matrix, the matrix to be operated, and the second decomposition matrix are input into the matrix multiplication accelerator, specifically, input into the input end of the single memristor array 201, so that the single memristor array 201 performs a first convolution based on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and performs a second convolution based on the second decomposition matrix and the matrix to be operated to obtain a second convolution result.

[0054] Specifically, the calculation formula is:

[0055] K i *M=(K′ i -K′0)*M=K′ i *MR′0=R′ i -R′0

[0056] Among them, * is convolution, K i is the convolution kernel matrix, K′ i is the first decomposition matrix, K′0 is the second decomposition matrix (all 1 matrix), M is the matrix to be operated, R′ i K′ i *M represents the first convolution result, and R′0 is K′0*M, which represents the second convolution result.

[0057] It should be noted that if Figure 3 As shown, the signed convolution kernel matrix is decomposed and convolved, which is equivalent to the original n first decomposition matrices K′ i (Compared with the original convolution kernel matrix K i The number of convolution operations is the same as that of the first convolution operation. A second separation matrix K′0 is added on the basis of the first convolution operation, so only n+1 convolution operations are needed to obtain the first convolution result and the second convolution result, realizing the conversion of the signed matrix convolution calculation into the unsigned matrix convolution. Among them, K′ i *M performs a total of n convolutions (first convolution), and K′0*M performs one convolution (second convolution). The original push-pull structure in the prior art first decomposes each convolution kernel matrix into two parts, non-negative and negative, and performs convolution separately, which actually performs 2n convolution operations. Therefore, this solution can greatly reduce the number of convolutions, saving hardware resources, energy consumption, manufacturing costs and occupied area for convolution operations. In addition, the method of the embodiment of the present invention is applicable to the decomposition operation of matrices of two dimensions, three dimensions and more. Figure 2 The calculation of a two-dimensional matrix is used as an example for explanation and does not constitute a limitation; this solution retains the wavelength division multiplexing design, greatly improving the system parallelism while reducing the complexity of the system.

[0058] S400: Perform differential processing on the first convolution result and the second convolution result to obtain a true convolution result.

[0059] Optionally, the difference between the first convolution result and the second convolution result is calculated to obtain the true convolution result R i , specifically:

[0060] R i =R′ i -R′0

[0061] Among them, R′ i is the first convolution result, and R′0 is the second convolution result.

[0062] It should be noted that differential processing can be performed by the peripheral circuit 202 of the matrix multiplication accelerator. Specifically, the first convolution result and the second convolution result output by the single memristor array 201 are received by the peripheral circuit 202, and the difference between the first convolution result and the second convolution result is calculated by the peripheral circuit 202 to obtain the true convolution result.

[0063] It should be noted that during the calculation process of the matrix multiplication accelerator, R′0, as the convolution result of the all-one matrix K′0, is calculated first. It can be stored in a capacitor sequence provided in the peripheral circuit 202 or stored in the digital memory of the peripheral circuit 202 after passing through the digital-to-analog conversion module of the peripheral circuit 202, so that the differential module of the peripheral circuit 202 can perform differential processing based on the first convolution result and the second convolution result. At the same time, since only n+1 convolution operations are required, only a single memristor array 201 is required. Based on the original single memristor array 201, targeted modifications are made to the peripheral circuit 202, and the hardware circuit is optimized for the final required differential module. When the convolution scale is large enough, using this algorithm can achieve the theoretical minimum physical computation amount, thereby greatly improving the overall integration of the system and reducing hardware redundancy.

[0064] like Figure 2 As shown, in the existing solution, an additional memristor array 203 (only a portion is shown) and an additional peripheral circuit 204 are required to perform matrix convolution of the negative part. For example, the existing convolution process is recorded as C=A×B, and the existing convolution process can be expressed as:

[0065]

[0066] C + =A + ×B,G - =A - ×B

[0067] C=(A + -A - )×B=C + -C -

[0068] Among them, A is the convolution kernel matrix, A + A is a matrix of the same size as A and contains only the non-negative elements of A. - is a matrix of the same size as A and containing only negative elements in A, B is the matrix to be operated, C + The convolution result of the matrix with non-negative elements, C - is the convolution result of the matrix with negative elements, and C is the final convolution result. It can be seen that by using such a decomposition, the multiplication of the signed matrix A is converted into two unsigned matrices A+ and A - In order to perform matrix multiplication (a memristor array can usually only perform unsigned number multiplication), the original matrix A is actually divided into two, and the two are input into the single memristor array 201 and the additional memristor array 203 respectively. After two convolution multiplications, the results are merged. The additional memristor array 203 is required to perform another n convolutions, for a total of 2n convolutions. The number of convolutions and hardware resources are greatly increased. The solution of the embodiment of the present invention overcomes the above shortcomings and does not require the addition of additional hardware resources to increase costs and occupied area.

[0069] An embodiment of the present invention further provides a device for simplifying the convolution process, including:

[0070] An acquisition module is used to obtain a convolution kernel matrix and a matrix to be operated; the elements to be operated in the matrix to be operated are non-negative;

[0071] A decomposition module, configured to decompose the convolution kernel matrix to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix;

[0072] The matrix multiplication accelerator is used to perform a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and to perform a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result; and to perform differential processing on the first convolution result and the second convolution result to obtain a true convolution result.

[0073] Optionally, the matrix multiplication accelerator includes a single memristor array 201 and a peripheral circuit 202 connected to the single memristor array 201; the single memristor array 201 is used to perform a first convolution based on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and to perform a second convolution based on the second decomposition matrix and the matrix to be operated to obtain a second convolution result; the peripheral circuit 202 is used to perform differential processing based on the first convolution result and the second convolution result to obtain a true convolution result.

[0074] The contents of the above method embodiments are all applicable to the present device embodiments. The functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0075] An embodiment of the present invention further provides an electronic device, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, code set, or instruction set, and the at least one instruction, at least one program, code set, or instruction set is loaded and executed by the processor to implement the method for simplifying the convolution process of the aforementioned embodiment. The electronic device of the embodiment of the present invention includes, but is not limited to, any intelligent terminal such as a mobile phone, tablet computer, computer, or vehicle-mounted computer.

[0076] The contents of the above method embodiments are all applicable to the present device embodiments. The functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0077] An embodiment of the present invention also provides a computer-readable storage medium, which stores at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by a processor to implement the simplified method of the convolution process of the aforementioned embodiment.

[0078] An embodiment of the present invention further provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the simplified convolution process method of the aforementioned embodiment.

[0079] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0080] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0081] In the several embodiments provided herein, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or omitting or disabling certain features. Furthermore, the coupling or direct coupling or communication connection shown or discussed between each other may be through interfaces, or indirect coupling or communication connection between devices or units, which may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the objectives of the present embodiments according to actual needs. Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in either hardware or software functional units.

[0082] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store programs.

[0083] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for simplifying the convolution process, characterized in that: include: Get the convolution kernel matrix and the matrix to be operated; The elements to be operated on the matrix to be operated on are non-negative; Decomposing the convolution kernel matrix to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix; Inputting the first decomposed matrix, the matrix to be operated, and the second decomposed matrix into a matrix multiplication accelerator, wherein the matrix multiplication accelerator includes a single memristor array; The single memristor array is used to perform a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and to perform a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result; Performing differential processing on the first convolution result and the second convolution result to obtain a true convolution result; The convolution kernel matrix includes a plurality of convolution kernel elements, and the second decomposition matrix includes a plurality of identical second decomposition elements; the decomposition processing of the convolution kernel matrix to obtain the difference between the non-negative first decomposition matrix and the non-negative second decomposition matrix includes: Calculating the absolute value of each of the convolution kernel elements and determining the maximum absolute value; Determine a constant value of the second decomposition element according to the maximum absolute value; the constant value is greater than or equal to the maximum absolute value; Decomposing the convolution kernel matrix according to the constant value to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix; or, When the convolution kernel matrix is obtained through normalization processing, determining the value of the second decomposition element to be 1; The convolution kernel matrix is decomposed according to the second decomposition element having a value of 1 to obtain a difference between a non-negative first decomposition matrix and a non-negative all-one matrix.

2. The method for simplifying the convolution process according to claim 1, characterized in that: The performing differential processing on the first convolution result and the second convolution result to obtain a true convolution result includes: Calculate the difference between the first convolution result and the second convolution result to obtain a true convolution result.

3. The method for simplifying the convolution process according to claim 1, characterized in that: The matrix multiplication accelerator further includes a peripheral circuit, and performing differential processing on the first convolution result and the second convolution result to obtain a true convolution result includes: The first convolution result and the second convolution result output by the single memristor array are received through the peripheral circuit, and the difference between the first convolution result and the second convolution result is calculated through the peripheral circuit to obtain a true convolution result.

4. A simplified device for the convolution process, characterized in that: include: Acquisition module, used to obtain the convolution kernel matrix and the matrix to be operated; The elements to be operated on the matrix to be operated on are non-negative; A decomposition module, configured to decompose the convolution kernel matrix to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix; a matrix multiplication accelerator, configured to perform a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and perform a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result; and perform differential processing on the first convolution result and the second convolution result to obtain a true convolution result; The matrix multiplication accelerator includes a single memristor array, and the single memristor array is used to perform a first convolution on the first decomposition matrix and the matrix to be operated to obtain a first convolution result, and to perform a second convolution on the second decomposition matrix and the matrix to be operated to obtain a second convolution result; The convolution kernel matrix includes a plurality of convolution kernel elements, and the second decomposition matrix includes a plurality of identical second decomposition elements; the decomposition processing of the convolution kernel matrix to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix includes: Calculating the absolute value of each of the convolution kernel elements and determining the maximum absolute value; Determine a constant value of the second decomposition element according to the maximum absolute value; the constant value is greater than or equal to the maximum absolute value; Decomposing the convolution kernel matrix according to the constant value to obtain a difference between a non-negative first decomposition matrix and a non-negative second decomposition matrix; or, When the convolution kernel matrix is obtained through normalization processing, determining the value of the second decomposition element to be 1; The convolution kernel matrix is decomposed according to the second decomposition element having a value of 1 to obtain a difference between a non-negative first decomposition matrix and a non-negative all-one matrix.

5. The device for simplifying the convolution process according to claim 4, characterized in that: The matrix multiplication accelerator includes a peripheral circuit connected to the single memristor array; the peripheral circuit is used to perform differential processing based on the first convolution result and the second convolution result to obtain a true convolution result.

6. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the method according to any one of claims 1 to 3.

7. A computer-readable storage medium, characterized in that The storage medium stores at least one instruction, at least one program, a code set, or an instruction set, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the method according to any one of claims 1 to 3.

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