Display panel motherboard, display panel motherboard testing method and display panel

Abstract

The embodiment of the present application discloses a display panel motherboard, a test method for the display panel motherboard, and a display panel. The display panel motherboard includes a display area and a test area, the display area includes a plurality of display panel bodies arranged in parallel, and a signal input terminal is arranged on the display panel body; a test circuit is formed in the test area, and the test circuit includes a first signal terminal and a control circuit, and a signal channel is formed between the first signal terminal and the signal input terminal of each display panel body, so that the first signal terminal controls the display of the corresponding display panel body after receiving the first control signal; the control circuit is connected to the signal channel between the first signal terminal and the plurality of signal input terminals to control the signal channel between the first signal terminal and the signal input terminals of at least part of the display panel body to be turned on or off. The present application controls at least part of the signal channel to be turned on or off by the control circuit, so that the range of defective products can be reduced during the test process, thereby improving the test efficiency.

Description

Technical Field

[0001] The present application relates to the display field, and in particular to a display panel motherboard, a test method for a display panel motherboard, and a display panel. Background Art

[0002] With the development of display technology, display panels are increasingly used in wearable, car-mounted, mobile phone, tablet, computer and TV products. Before the display panel is connected to the driving circuit and put into use, its performance needs to be tested to detect defective products and avoid defective products from flowing into the subsequent process and causing material loss. At present, the display panel motherboard is usually made first. Each display panel motherboard includes a plurality of display panel bodies distributed in an array and tested at the same time. Since the signal lines of the display panel bodies in the same column are connected together, when one of the display panel bodies has a poor display, the entire column of display panel bodies will have a poor display. It is impossible to determine the specific location of the defective product. In the subsequent process, the display panel motherboard needs to be cut into independent single display panel bodies for testing and differentiation, which leads to low test efficiency. Summary of the invention

[0003] The embodiments of the present application provide a display panel motherboard, a test method for a display panel motherboard, and a display panel, which can solve the problem of low test efficiency of existing display panel motherboards.

[0004] An embodiment of the present application provides a display panel motherboard, comprising:

[0005] A display area, the display area comprising a plurality of display panel bodies arranged in parallel, the display panel bodies being provided with signal input terminals;

[0006] A test area is formed with a test circuit, which includes a first signal terminal and a control circuit; a signal channel is formed between the first signal terminal and the signal input terminal of each display panel body, so that the first signal terminal controls the display of the corresponding display panel body after receiving the first control signal; the control circuit is connected to the signal channel between the first signal terminal and multiple signal input terminals to control the signal channel between the first signal terminal and the signal input terminals of at least some of the display panel bodies to be turned on or off.

[0007] Optionally, in some embodiments of the present application, the control circuit includes a control switch connected to the signal channel, and a second signal end electrically connected to the control switch, and the second signal end is used to control the corresponding control switch to be turned on or off after receiving a second control signal.

[0008] Optionally, in some embodiments of the present application, the control circuit includes a plurality of connecting lines, one end of the plurality of connecting lines is connected to the first signal end, and the other ends of the plurality of connecting lines are connected one-to-one with the signal input ends of the plurality of display panel bodies to form a signal channel between the first signal end and the signal input ends of each of the display panel bodies; and the control switch is connected to at least some of the connecting lines.

[0009] Optionally, in some embodiments of the present application, the number of the control switches is equal to the number of the display panel bodies, and each of the connecting lines is connected to the control switch.

[0010] Optionally, in some embodiments of the present application, the control circuit includes a main line connected to the first signal terminal, and a plurality of connection nodes are arranged on the main line; the control circuit also includes a plurality of branch lines, one ends of the plurality of branch lines are connected one-to-one with the plurality of connection nodes, and the other ends of the plurality of branch lines are connected one-to-one with the signal input terminals of the plurality of display panel bodies to form a signal channel between the first signal terminal and the signal input terminals of each of the display panel bodies; the control switch is connected to the main line between at least some adjacent two of the connection nodes.

[0011] Optionally, in some embodiments of the present application, the number of the control switches is equal to the number of the display panel bodies, the control switch is connected to the main line between any two adjacent connection nodes, and the control switch is connected to the main line between any one of the connection nodes and the first signal end.

[0012] Optionally, in some embodiments of the present application, the control circuit includes a plurality of the second signal terminals and a plurality of the control switches, the number of the second signal terminals is equal to the number of the control switches, and the second signal terminals are electrically connected to the control switches in a one-to-one correspondence.

[0013] Optionally, in some embodiments of the present application, the test circuit also includes a third signal terminal, and the third signal terminal is electrically connected to the signal input terminal of any one of the display panel bodies, so that the third signal terminal controls the display of the corresponding display panel body after receiving a third control signal.

[0014] Accordingly, an embodiment of the present application further provides a method for testing a display panel motherboard, wherein the display panel motherboard is any one of the display panel motherboards described above, and the method comprises:

[0015] Providing a display panel motherboard;

[0016] Input a first control signal through the first signal terminal of the display panel motherboard, and control the signal channel between the first signal terminal and the signal input terminals of the plurality of display panel bodies on the display panel motherboard to be connected through the control circuit on the display panel motherboard, so that the plurality of display panel bodies display;

[0017] Determining whether any of the plurality of display panel bodies has display abnormality;

[0018] If a display panel body among the plurality of display panel bodies has display abnormality, the control circuit controls the signal channel between the first signal end and the signal input end of some of the display panel bodies to be disconnected, so that the corresponding display panel body is turned off;

[0019] It is determined whether any of the remaining display panel bodies has display abnormality.

[0020] Accordingly, an embodiment of the present application further provides a display panel, the display panel comprising:

[0021] The display panel body is provided with a signal input terminal;

[0022] A test section, provided with a test signal terminal, the test section comprising a test circuit connected between the test signal terminal and the signal input terminal;

[0023] A circuit board is arranged on the testing part, and the circuit board is electrically connected to the signal input terminal of the display panel body.

[0024] Optionally, in some embodiments of the present application, the test circuit includes a signal line, one end of the signal line is connected to the test signal terminal, and the other end of the signal line is connected to the signal input terminal of the display panel body to form a signal channel between the test signal terminal and the signal input terminal.

[0025] Optionally, in some embodiments of the present application, the test circuit also includes a control switch connected to the signal line, and a signal control terminal is also provided on the test unit, the signal control terminal is electrically connected to the control switch, and the signal control terminal is used to control the control switch to be turned on or off after receiving a control signal.

[0026] In the embodiment of the present application, the display panel motherboard includes a display area and a test area, the display area includes a plurality of display panel bodies arranged in parallel, and a signal input terminal is arranged on the display panel body; a test circuit is formed in the test area, and the test circuit includes a first signal terminal and a control circuit, and a signal channel is formed between the first signal terminal and the signal input terminal of each display panel body, so that the first signal terminal controls the display of the corresponding display panel body after receiving the first control signal; the control circuit is connected to the signal channel between the first signal terminal and the plurality of signal input terminals to control the signal channel between the first signal terminal and the signal input terminals of at least part of the display panel body to be turned on or off. The present application sets a control circuit in the test circuit on the display panel motherboard, so that when the display panel motherboard is tested, the control circuit can be used to control at least part of the signal channel to be turned on or off according to the display situation of the display area, thereby reducing the range of defective products in the display area, thereby reducing the amount of subsequent inspections and improving the test efficiency of the display panel motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a structural schematic diagram of a display panel motherboard provided in an embodiment of the present application;

[0029] Figure 2 is a schematic structural diagram of another display panel motherboard provided in an embodiment of the present application;

[0030] Figure 3 is a schematic structural diagram of another display panel motherboard provided in an embodiment of the present application;

[0031] Figure 4 is a schematic structural diagram of another display panel motherboard provided in an embodiment of the present application;

[0032] Figure 5 is a schematic structural diagram of another display panel motherboard provided in an embodiment of the present application;

[0033] Figure 6 is a schematic structural diagram of another display panel motherboard provided in an embodiment of the present application;

[0034] Figure 7 is a schematic structural diagram of another display panel motherboard provided in an embodiment of the present application;

[0035] Figure 8is a schematic structural diagram of another display panel motherboard provided in an embodiment of the present application;

[0036] Fig. 9 It is a flow chart of a method for testing a display panel motherboard provided in an embodiment of the present application;

[0037] Fig.10 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0038] Fig.11 It is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.

[0039] Description of reference numerals:

[0040]

[0041] DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0043] The embodiments of the present application provide a display panel motherboard, a display panel motherboard testing method and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0044] First, the embodiment of the present application provides a display panel motherboard. Figure 1 and Figure 2 As shown, the display panel motherboard 100 includes a display area 110, and the display area 110 includes a plurality of display panel bodies 111 arranged in parallel. A signal input terminal 112 is provided on the display panel body 111, and the display of the corresponding display panel body 111 can be controlled by inputting a control signal at the signal input terminal 112.

[0045] Among them, after the display panel motherboard 100 is manufactured, the display panel motherboard 100 needs to be tested to determine whether there is a display panel body 111 with poor display in the display area 110, so as to avoid defective products in multiple display panel bodies 111 from flowing into subsequent processes or being put into use, thereby causing material waste.

[0046] At the same time, when manufacturing the display panel motherboard 100, in order to improve the manufacturing efficiency, the signal lines of the display panel bodies 111 in the same column are directly connected together, so that when the display panel body 111 template is tested, the display panel bodies 111 in the same column will affect each other, that is, when one display panel body 111 displays abnormally, the entire column of display panel bodies 111 will show abnormalities, so that the location of the defective product cannot be determined. In the subsequent manufacturing process, the display panel motherboard 100 needs to be cut into independent single display panel bodies 111 and then checked one by one, resulting in low testing efficiency.

[0047] In the embodiment of the present application, the display panel motherboard 100 further includes a test area 120, in which a test circuit is formed for detecting whether the multiple display panel bodies 111 of the display area 110 can display normally. The test circuit includes a first signal terminal 121, and a signal channel is formed between the first signal terminal 121 and the signal input terminal 112 of each display panel body 111, so that the first signal terminal 121 controls the corresponding display panel body 111 to display after receiving the first control signal.

[0048] That is to say, the first signal terminal 121 simultaneously forms a signal channel with the signal input terminals 112 of multiple display panel bodies 111. When the corresponding signal channel is turned on, the display of the corresponding display panel body 111 can be controlled by inputting the first control signal at the first signal terminal 121, and whether it is a defective product can be determined based on the display status of the corresponding display panel body 111.

[0049] The test circuit also includes a control circuit 122, which is connected to a signal channel between the first signal terminal 121 and the plurality of signal input terminals 112 to control the conduction or disconnection of the signal channel between the first signal terminal 121 and at least part of the signal input terminals 112 of the display panel main body 111. By regulating the conduction and disconnection of the signal channel corresponding to the part of the display panel main body 111 by the control circuit 122, the display conditions of the display panel main body 111 in different ranges can be tested, so as to narrow the range of defective products in the plurality of display panel main bodies 111 and improve the test efficiency of the display panel motherboard 100.

[0050] The embodiment of the present application sets a control circuit 122 in the test circuit on the display panel motherboard 100, and connects the control circuit 122 to the signal channel between the first signal terminal 121 and the multiple signal input terminals 112. When the display panel motherboard 100 is tested, the control circuit 122 can regulate the conduction and disconnection of the signal channels corresponding to some display panel bodies 111 according to the display conditions of the display area 110, thereby narrowing the range of defective products in the display area 110, thereby reducing the subsequent inspection amount and improving the testing efficiency of the display panel motherboard 100.

[0051] Optionally, the control circuit 122 includes a control switch 1222 connected to the signal channel, and a second signal terminal 1221 electrically connected to the control switch 1222, and the second signal terminal 1221 is used to control the corresponding control switch 1222 to be turned on or off after receiving the second control signal. By setting the control switch 1222 on the signal channel, the turning on or off of the control switch 1222 is used to control the turning on or off of the corresponding signal channel, thereby adjusting the test range of the display area 110.

[0052] Among them, the conduction or disconnection of the control switch 1222 is controlled by the second control signal received on the second signal terminal 1221, that is, the conduction or disconnection of the signal channel between the first signal terminal 121 and the signal input terminal 112 of the display panel body 111 can be simultaneously controlled by the first control signal received by the first signal terminal 121 and the second control signal received by the second signal terminal 1221. By adjusting the setting position and connection method of the control switch 1222, the signal channels corresponding to different display panel bodies 111 can be controlled separately, thereby further narrowing the range of defective products in the display area 110.

[0053] Optional, such as Figure 1 As shown, the control circuit 122 includes a plurality of connecting lines 1223, one end of the plurality of connecting lines 1223 is connected to the first signal terminal 121, and the other end of the plurality of connecting lines 1223 is connected one-to-one with the signal input terminals 112 of the plurality of display panel bodies 111 to form a signal channel between the first signal terminal 121 and the signal input terminal 112 of each display panel body 111, that is, the plurality of connecting lines 1223 are connected in parallel with each other, that is, the signal channels between the first signal terminal 121 and the signal input terminal 112 of each display panel body 111 are connected in parallel with each other.

[0054] At least some of the connecting lines 1223 are connected to control switches 1222. Since the connecting lines 1223 are connected in parallel, the control switches 1222 connected to the corresponding connecting lines 1223 are also connected in parallel. By regulating the second control signal received at the second signal terminal 1221 connected to the corresponding control switch 1222, the connection and disconnection of the connecting line 1223 can be individually controlled. This circuit design method enables the connection or disconnection of the signal channel between the signal input terminal 112 of the display panel body 111 and the first signal terminal 121 corresponding to the connecting line 1223 connected to the control switch 1222 to be individually controlled, so that the range of the display area 110 corresponding to the test is more accurate.

[0055] Optionally, the number of control switches 1222 is equal to the number of display panel bodies 111, and each connection line 1223 is connected with a control switch 1222, that is, the conduction or disconnection of the signal channel between the signal input terminal 112 and the first signal terminal 121 of each display panel body 111 can be controlled by the conduction or disconnection of the corresponding control switch 1222. During the test process of the display panel motherboard 100, by controlling the conduction of a single control switch 1222, the display condition of a single display panel body 111 can be tested, thereby determining the specific location of defective products in multiple display panel bodies 111, without the need for subsequent cutting and separate testing processes, thereby greatly improving the test efficiency of the display panel motherboard 100.

[0056] It should be noted that the control switch 1222 includes a control end, a first connection end and a second connection end, and the second signal end 1221 is connected to the control end, and the conduction or disconnection of the first connection end and the second connection end is controlled by the second control signal received by the second signal end 1221. The first connection ends of multiple control switches 1222 are connected together with the first signal end 121, and the second connection ends of multiple control switches 1222 are connected one-to-one with the signal input ends 112 of multiple display panel bodies 111, so that the parallel connection of multiple control switches 1222 can be realized, thereby realizing the mutual parallel connection of signal channels between the first signal end 121 and the signal input ends 112 of each display panel body 111.

[0057] Optional, such as Figure 2 and Figure 3As shown, the control circuit 122 includes a main line 1224 connected to the first signal terminal 121, and a plurality of connection nodes 1225 are provided on the main line 1224, so that other lines can be electrically connected to the first signal terminal 121 through the corresponding connection nodes 1225. The control circuit 122 also includes a plurality of branch lines 1226, one end of the plurality of branch lines 1226 is connected to the plurality of connection nodes 1225 in a one-to-one correspondence, and the other end of the plurality of branch lines 1226 is connected to the signal input terminals 112 of the plurality of display panel bodies 111 in a one-to-one correspondence, so as to form a signal channel between the first signal terminal 121 and the signal input terminals 112 of each display panel body 111.

[0058] That is to say, the positions of the signal channels corresponding to the main lines 1224 between the first signal terminal 121 and the signal input terminals 112 of each display panel body 111 partially overlap, so that a constraint relationship exists between the signal channels, that is, when the connection node 1225 closer to the first signal terminal 121 is in a disconnected state from the first signal terminal 121, the connection node 1225 farther from the first signal terminal 121 is also in a disconnected state from the first signal terminal 121.

[0059] Among them, a control switch 1222 is connected to the main line 1224 between at least some of the adjacent two connection nodes 1225. By adjusting the position of the control switch 1222 between each connection node 1225, it is possible to implement regional testing of multiple display panel bodies 111 to determine the regional range where defective products in the display panel body 111 are located.

[0060] Optionally, the number of control switches 1222 is equal to the number of display panel bodies 111, and a control switch 1222 is connected to the main line 1224 between any two adjacent connection nodes 1225, and a control switch 1222 is connected to the main line 1224 between any connection node 1225 and the first signal terminal 121, that is, a control switch 1222 is provided on the signal channel between the signal input terminal 112 of each display panel body 111 and the first signal terminal 121, and multiple control switches 1222 are connected in series.

[0061] By connecting the plurality of control switches 1222 in series, it is possible to implement regional testing of the plurality of display panel bodies 111, so as to determine the region range where defective products are located in the display panel bodies 111. In addition, compared with connecting the plurality of control switches 1222 in parallel, this connection mode can reduce the number of signal lines between the signal input terminals 112 and the first signal terminals 121 of the plurality of display panel bodies 111, and at the same time, reduce the region range where defective products are located in the plurality of display panel bodies 111.

[0062] It should be noted that multiple control switches 1222 are connected in series, which means that the control ends of the multiple control switches 1222 are respectively electrically connected to the corresponding second signal ends 1221, and the first connection ends and the second connection ends of the multiple control switches 1222 are alternately connected, that is, the conduction or disconnection between the first connection end and the second connection end of each control switch 1222 is controlled by the second control signal received by the corresponding second signal end 1221, but the conduction or disconnection of the signal channel between the signal input end 112 of each display panel body 111 and the first signal end 121 is mutually restricted. Only when the signal channels corresponding to the control switches 1222 closer to the first signal end 121 are all in the on state, the signal channels corresponding to the control switches 1222 farther from the first signal end 121 can be in the on state.

[0063] Optionally, in the embodiment of the present application, the control circuit 122 includes a plurality of second signal terminals 1221 and a plurality of control switches 1222, the number of the second signal terminals 1221 is equal to the number of the control switches 1222, and the second signal terminals 1221 are electrically connected to the control switches 1222 in a one-to-one correspondence, that is, the on or off of each control switch 1222 can be individually controlled by the second control signal received on the corresponding second signal terminal 1221. This design makes the control of the plurality of control switches 1222 more independent, which is conducive to the mutual coordination between different control switches 1222, thereby helping to determine the area range where defective products are located in the plurality of display panel bodies 111.

[0064] Among them, the specific testing methods corresponding to different switch settings and connection modes will be described in detail in subsequent embodiments and will not be repeated here.

[0065] Optionally, a plurality of display panel bodies 111 are arranged in parallel along the first direction X, and in the first direction X, the first signal terminal 121 and the second signal terminal 1221 are located on the same side of the display area 110. The first signal terminal 121 and the second signal terminal 1221 are both used to connect to a test device, and arranging the first signal terminal 121 and the second signal terminal 1221 on the same side of the display area 110 facilitates the connection between the display panel motherboard 100 and the test device.

[0066] In some embodiments, the plurality of second signal terminals 1221 are distributed on opposite sides of the display area 110 . This structural design facilitates the connection design between the second signal terminals 1221 and the control switches 1222 , thereby reducing signal routing between the control switches 1222 and the corresponding second signal terminals 1221 .

[0067] Optional, such as Figures 4 to 7As shown, the test circuit also includes a third signal terminal 123, and the third signal terminal 123 is electrically connected to the signal input terminal 112 of any one of the display panel bodies 111, so that the third signal terminal 123 controls the display of the corresponding display panel body 111 after receiving the third control signal. By adding the third signal terminal 123 and directly connecting the third signal terminal 123 to the signal input terminal 112 of one of the display panel bodies 111, the display panel body 111 can be directly tested, so that the multiple display panel bodies 111 are divided into two parts, and the area where defective products are located in the multiple display panel bodies 111 can be further narrowed by inputting the first control signal and the third control signal at the first signal terminal 121 and the third signal terminal 123 at the same time or separately.

[0068] In some embodiments, Figure 4 and Figure 6 As shown, in the first direction X, the first signal terminal 121 and the third signal terminal 123 are located on opposite sides of the display area 110, the first signal terminal 121 is electrically connected to the signal input terminal 112 of the adjacent display panel body 111 in the display area 110, and the third signal terminal 123 is electrically connected to the signal input terminal 112 of the adjacent display panel body 111 in the display area 110, that is, the first signal terminal 121 and the third signal terminal 123 are both directly electrically connected to the signal input terminal 112 of the corresponding adjacent display panel body 111.

[0069] This connection method enables the display panel bodies 111 located on opposite sides of the display area 110 in the first direction X to be directly tested, and then other areas are tested according to the test results to determine the area range where defective products are located. In addition, this connection method can also simplify the signal routing between the third signal terminal 123 and the corresponding display panel body 111, reducing the difficulty of manufacturing.

[0070] In other embodiments, Figure 5 and Figure 7 As shown, in the first direction X, the first signal terminal 121 and the third signal terminal 123 are located on the same side of the display area 110. This structural design enables the connection terminals on the display panel motherboard 100 for connecting to the test equipment to be located in the same area of ​​the display panel motherboard 100, thereby facilitating the connection between the display panel motherboard 100 and the test equipment.

[0071] Optional, such as Figure 8 As shown, the display panel motherboard 100 includes multiple display areas 110 and multiple test areas 120. The multiple display areas 110 and the multiple test areas 120 are arranged in a one-to-one correspondence, that is, each test area 120 is used to test the corresponding display area 110, so as to determine the range of defective products in each display area 110 on the display panel motherboard 100.

[0072] Among them, multiple display areas 110 are arranged in parallel along the second direction Y, and the second direction Y forms an angle with the first direction X. In some embodiments, the first direction X is perpendicular to the second direction Y, that is, the multiple display panel bodies 111 on the display panel motherboard 100 are distributed in an array, and the test area 120 is located between two adjacent display areas 110. This distribution method makes the display panel motherboard 100 as a whole regularly arranged, and can also improve the utilization rate of the display panel motherboard 100.

[0073] Secondly, an embodiment of the present application also provides a testing method for a display panel motherboard, wherein the tested display panel motherboard is the display panel motherboard in the above embodiment, which includes all the technical features in the above embodiment and therefore has all the beneficial effects in the above embodiment, which will not be described one by one here.

[0074] like Fig. 9 As shown, the test method of the display panel motherboard mainly includes the following steps:

[0075] S100 , providing a display panel motherboard 100 .

[0076] The display panel motherboard 100 includes a display area 110 and a test area 120. The display area 110 includes a plurality of display panel bodies 111 arranged in parallel, and a signal input terminal 112 is provided on the display panel body 111. A test circuit is formed in the test area 120, and the test circuit includes a first signal terminal 121 and a control circuit 122. A signal channel is formed between the first signal terminal 121 and the signal input terminal 112 of each display panel body 111, so that the first signal terminal 121 controls the display of the corresponding display panel body 111 after receiving the first control signal. The control circuit 122 is connected to the signal channel between the first signal terminal 121 and the plurality of signal input terminals 112 to control the conduction or disconnection of the signal channel between the first signal terminal 121 and the signal input terminals 112 of at least some of the display panel bodies 111.

[0077] S200, input a first control signal through the first signal terminal 121 of the display panel motherboard 100, and control the signal channel between the first signal terminal 121 and the signal input terminal 112 of the multiple display panel bodies 111 on the display panel motherboard 100 through the control circuit 122 on the display panel motherboard 100 to enable the multiple display panel bodies 111 to display.

[0078] The first signal terminal 121 is used for inputting the first control signal, and the control circuit 122 is used for controlling the conduction or disconnection of the signal channel between the first signal terminal 121 and the signal input terminal 112 of each display panel body 111. When testing the display panel motherboard 100, by inputting the first control signal to the first signal terminal 121 and controlling the conduction of each signal channel through the control circuit 122, the first control signal received by the first signal terminal 121 is transmitted to each display panel body 111 through the signal input terminal 112, so that the multiple display panel bodies 111 display under the drive of the received control signal.

[0079] It should be noted that, in addition to the control signal received on the signal input terminal 112, other control signals are also input to the display panel body 111 to ensure that the display panel body 111 can display normally. Among them, the signal input terminal 112 can be connected to the scan signal line or the data signal line in the display panel body 111. When the signal input terminal 112 is connected to the scan signal line of the display panel body 111, the data signal line of the display panel body 111 will simultaneously input another control signal. When the signal input terminal 112 is connected to the data signal line of the display panel body 111, the scan signal line of the display panel body 111 will also simultaneously input another control signal, so that the display panel body 111 is driven by the control signals on the scan signal line and the data signal line to display.

[0080] S300 , determining whether any display panel body 111 among the plurality of display panel bodies 111 has display abnormality.

[0081] After all the signal channels between the first signal terminal 121 on the display panel motherboard 100 and the signal input terminal 112 of each display panel body 111 are turned on, it is determined whether there is display abnormality in the multiple display panel bodies 111 according to the display status of the display area 110 of the display panel motherboard 100, so as to determine whether there are defective products in the multiple display panel bodies 111.

[0082] It should be noted that when part of the display area 110 is not bright, part of the display area has bright lines or is displayed randomly, it is determined that there is a display abnormality in the multiple display panel bodies 111. When making the determination, the multiple display panel bodies 111 of the display area 110 are judged as a whole. If an abnormality is found, the area range where the defective product is located is further tested and checked.

[0083] S400 , if a display panel body 111 among the plurality of display panel bodies 111 has display abnormality, the control circuit 122 controls the signal channel between the first signal terminal 121 and the signal input terminal 112 of some display panel bodies 111 to be disconnected, so that the corresponding display panel body 111 is turned off.

[0084] When the signal channels between the first signal terminal 121 and the signal input terminals 112 of each display panel body 111 are all connected, and a display panel body 111 among the plurality of display panel bodies 111 has abnormal display, it indicates that there are defective products among the plurality of display panel bodies 111. The control circuit 122 controls the signal channels between the first signal terminal 121 and the signal input terminals 112 of some display panel bodies 111 to be disconnected, so that the corresponding display panel bodies 111 of the part are turned off, so as to test the display panel bodies 111 of the other parts, and at the same time, it is also possible to indirectly determine whether there are defective products among the turned-off display panel bodies 111.

[0085] S500 , determining whether any of the remaining display panel bodies 111 has display abnormality.

[0086] After closing part of the display panel main body 111, the signal channel between the signal input terminal 112 and the first signal terminal 121 of the remaining display panel main body 111 is kept connected to determine whether there is any display abnormality in the remaining display panel main body 111. If the remaining display panel main body 111 displays no abnormality, it means that there is no defective product in the remaining display panel main body 111, and there is a defective product in the closed display panel main body 111; if there is any display abnormality in the remaining display panel main body 111, it means that there is a defective product in the remaining display panel main body 111, and it is necessary to continue to close part of the display panel main body 111 or adjust the range of the closed display panel main body 111 to continue to narrow the range of defective products in the display panel main body 111.

[0087] It should be noted that the specific test method varies with the different control circuits 122 , and the test method will be described below using several specific connection methods.

[0088] In some embodiments, Figure 1As shown, taking three display panel bodies 111 as an example, the three display panel bodies 111 are respectively connected to three control switches 1222 in one-to-one correspondence, the three control switches 1222 are connected in parallel and electrically connected to the first signal terminal 121, and each control switch 1222 is respectively connected to a second signal terminal 1221 to achieve individual control of the on or off of each control switch 1222. The direction indicated by the first direction X arrow is the first display panel body 111, the second display panel body 111 and the third display panel body 111, and the corresponding connections are the first control switch 1222, the second control switch 1222 and the third control switch 1222.

[0089] When testing the display panel motherboard 100, first input the first control signal at the first signal terminal 121, and input the second control signal at the second signal terminal 1221 to turn on all three control switches 1222; then determine whether the three display panel bodies 111 as a whole display abnormality; when the three display panel bodies 111 as a whole display normal, it means that the three display panel bodies 111 are normal.

[0090] When the three display panel bodies 111 display abnormally as a whole, the first and second display panel bodies 111 are closed, the third display panel body 111 is opened, and the third display panel body 111 is judged to be normal or abnormal according to the display condition of the third display panel body 111; then the first and third display panel bodies 111 are closed, the second display panel body 111 is opened, and the second display panel body 111 is judged to be normal or abnormal according to the display condition of the second display panel body 111; then the second and third display panel bodies 111 are closed, the first display panel body 111 is opened, and the first display panel body 111 is judged to be normal or abnormal according to the display condition of the first display panel body 111, thereby determining normal products and defective products among the three display panel bodies 111.

[0091] In other embodiments, Figure 2 As shown, the three display panel bodies 111 are respectively connected to the three control switches 1222 in one-to-one correspondence, the three control switches 1222 are connected in series and electrically connected to the first signal terminal 121, and each control switch 1222 is respectively connected to a second signal terminal 1221 to achieve individual control of the on or off of each control switch 1222. The direction indicated by the first direction X arrow is the first display panel body 111, the second display panel body 111 and the third display panel body 111, and the corresponding connections are the first control switch 1222, the second control switch 1222 and the third control switch 1222.

[0092] When testing the display panel motherboard 100, first input the first control signal at the first signal terminal 121, and input the second control signal at the second signal terminal 1221 to turn on all three control switches 1222; then determine whether the three display panel bodies 111 as a whole display abnormality; when the three display panel bodies 111 as a whole display normal, it means that the three display panel bodies 111 are normal.

[0093] When the overall display of the three display panel bodies 111 is abnormal, the third control switch 1222 is closed, and the first and second control switches 1222 are opened; if the display is normal, it means that the first and second display panel bodies 111 are normal, and the third display panel body 111 is abnormal; if the display is abnormal, the third and second control switches 1222 are closed, and the first control switch 1222 is opened; if the display is normal, it means that the first display panel body 111 is normal, and the second display panel body 111 is abnormal; if the display is abnormal, it means that the first display panel body 111 is abnormal, and the second and third display panel bodies 111 cannot be determined, and subsequent separate inspections are required to determine whether they are abnormal.

[0094] It should be noted that if Figure 3 As shown, the first display panel body 111 can also be directly connected to the first signal terminal 121, that is, the first control switch 1222 is not provided, and only the second and third control switches 1222 are provided. When the first control signal is input to the first signal terminal 121 and the second and third control switches 1222 are closed, the first display panel body 111 can be judged to be normal or abnormal according to the display condition of the first display panel body 111. In addition, only when the first display panel body 111 displays normally, can the second and third display panel bodies 111 be judged.

[0095] In some other embodiments, Figure 4 and Figure 5 As shown, in Figure 2 A third signal terminal 123 is added on the basis of the embodiment shown, and the third signal terminal 123 is directly connected to the signal input terminal 112 of the third display panel body 111. When testing the display panel motherboard 100, a first control signal is input to the first signal terminal 121, a third control signal is input to the third signal terminal 123, and the third control switch 1222 is turned off, and the first and second control switches 1222 are turned on, so that the normality or abnormality of the third display panel body 111 can be directly determined.

[0096] If the first and second display panel bodies 111 display normally as a whole, it means that both are normal; if the first and second display panel bodies 111 display abnormally as a whole, close the third and second control switches 1222 and open the first control switch 1222; if the display is normal, it means that the first display panel body 111 is normal and the second display panel body 111 is abnormal; if the display is abnormal, it means that the first display panel body 111 is abnormal and the second display panel body 111 cannot be determined, and needs to be checked separately later to determine whether it is abnormal.

[0097] It should be noted that if Figure 6 and Figure 7 As shown, the first display panel body 111 can also be directly connected to the first signal terminal 121, that is, the first control switch 1222 is not provided, and only the second and third control switches 1222 are provided. When the first control signal is input to the first signal terminal 121, the third control signal is input to the third signal terminal 123, and the second and third control switches 1222 are closed, the first and third display panel bodies 111 can be directly judged to be normal or abnormal according to the display conditions of the first and third display panel bodies 111. When at least one of them is displayed normally, the second display panel body 111 is further judged according to the conduction or disconnection of the second and third control switches 1222.

[0098] Finally, the embodiment of the present application also provides a display panel, such as Fig.10 and Fig.11 As shown, the display panel 200 includes a display panel body 111, and a signal input terminal 112 is provided on the display panel body 111 for receiving a control signal transmitted to the display panel body 111. The display panel body 111 serves as the main display part of the display panel 200. By adjusting the display mode of the display panel body 111, different display requirements of the display panel 200 can be achieved.

[0099] The display panel 200 includes a test section 210, on which a test signal terminal 211 is provided, and the test section 210 includes a test circuit connected between the test signal terminal 211 and the signal input terminal 112. The test signal terminal 211 is used to receive a test signal, and the test signal is transmitted to the signal input terminal 112 through the test circuit, and then transmitted to the inside of the display panel body 111 to control the display of the display panel body 111. The display of the display panel body 111 can be used to determine whether the display panel body 111 is a qualified product or a defective product, so as to avoid defective products from flowing into subsequent processes or being put into use, thereby causing material waste.

[0100] The display panel 200 includes a circuit board 220, which is disposed on the test unit 210 and is electrically connected to the signal input terminal 112 of the display panel body 111 to control the display of the display panel body 111. By adjusting the circuit control mode on the circuit board 220, different display requirements of the display panel 200 can be achieved.

[0101] It should be noted that during the manufacturing process of the display panel 200, the display panel body 111 can be inspected through the test circuit on the test unit 210, and after the display panel body 111 is determined to be a qualified product, the circuit board 220 is connected to the test unit 210 to avoid waste of materials due to the display panel body 111 being a defective product.

[0102] The display panel body 111 and the test unit 210 in the embodiment of the present application can be formed by cutting the display panel motherboard 100 in the above embodiment. If the display panel body 111 is determined to be a qualified product when the display panel motherboard 100 is tested, the display panel body 111 can directly enter the next process; if the display panel body 111 is determined to be a defective product or the display condition of the display panel body 111 cannot be determined when the display panel motherboard 100 is tested, the display panel body 111 can be supplemented with a test circuit on the test unit 210 after cutting to prevent defective products from flowing into subsequent processes or being put into use, thereby causing material waste.

[0103] In some embodiments, when manufacturing the display panel 200, the display panel body 111 and the test unit 210 can be directly manufactured first, and then the display panel body 111 is tested through the test circuit on the test unit 210. If the test is qualified, the display panel body 111 will flow into the subsequent process, and the circuit board 220 will be connected to the test unit 210 and connected to the signal input terminal 112 of the display panel body 111 to form the display panel 200.

[0104] Optional, such as Fig.10 As shown, the test circuit includes a signal line 213, one end of the signal line 213 is connected to the test signal terminal 211, and the other end of the signal line 213 is connected to the signal input terminal 112 of the display panel body 111, so as to form a signal channel between the test signal terminal 211 and the signal input terminal 112. That is, the test signal terminal 211 and the signal input terminal 112 are directly connected through the signal line 213. This setting method makes it possible to judge whether the display panel body 111 is a qualified product or a defective product according to the display condition of the display panel body 111 as long as a control signal is input to the test signal terminal 211, and the test method is simple and convenient.

[0105] In some embodiments, Fig.11As shown, the test circuit also includes a control switch 1222 connected to the signal line 213. The test unit 210 is provided with a signal control terminal 212, which is electrically connected to the control switch 1222. The signal control terminal 212 is used to control the control switch 1222 to be turned on or off after receiving a control signal. That is, when testing the display panel body 111, it is necessary to input a control signal at the signal control terminal 212 and the test signal terminal 211 at the same time, so that the control switch 1222 is turned on, and the control signal can be smoothly transmitted to the display panel body 111, so as to realize the determination of the display status of the display panel body 111.

[0106] This arrangement allows the display panel body 111 to flow into the next process and form the display panel 200. Then, the control switch 1222 can be disconnected by inputting a signal at the signal control terminal 212, thereby disconnecting the signal line 213. At this time, if the display of the display panel body 111 is controlled by the circuit board 220, the control signal on the circuit board 220 can be prevented from affecting the display effect of the display panel 200 due to being transmitted on the signal line 213 at the same time.

[0107] It should be noted that the display panel 200 includes a thin film transistor layer, the thin film transistor layer includes a first thin film transistor, the first thin film transistor is located in the display panel body 111, and the first thin film transistor includes a metal layer. When the test circuit of the test unit 210 only includes a signal line 213, the signal line 213 can be provided at the same layer as the metal layer of the first thin film transistor to simplify the manufacturing process of the display panel 200.

[0108] When the test circuit also includes a control switch 1222, the control switch 1222 includes a second thin film transistor, and the second thin film transistor is arranged in the same layer as each film layer in the first thin film transistor, that is, in the process of manufacturing the display panel 200, the first thin film transistor in the display panel main body 111 and the second thin film transistor in the test part 210 are formed at the same time, so as to further simplify the manufacturing process of the display panel 200 and reduce the production cost.

[0109] The above is a detailed introduction to a display panel motherboard, a testing method for a display panel motherboard and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel motherboard, characterized in that: include: A display area, the display area comprising a plurality of display panel bodies arranged in parallel, the display panel bodies being provided with signal input terminals; A test area is formed with a test circuit, the test circuit includes a first signal terminal and a control circuit; a signal channel is formed between the first signal terminal and the signal input terminal of each display panel body, so that the first signal terminal controls the display of the corresponding display panel body after receiving a first control signal; the control circuit is connected to the signal channel between the first signal terminal and multiple signal input terminals to control the signal channel between the first signal terminal and at least part of the signal input terminals of the display panel body to be turned on or off, the control circuit includes multiple control switches connected to the signal channel, and multiple second signal terminals electrically connected to the multiple control switches, each of the control switches is connected between the first signal terminal and the corresponding signal input terminal, each of the second signal terminals is used to control the corresponding control switch to be turned on or off after receiving a second control signal, and multiple control switches are connected in series.

2. The display panel motherboard according to claim 1, characterized in that: The control circuit includes a plurality of connecting lines, one end of the plurality of connecting lines is connected to the first signal end, and the other end of the plurality of connecting lines is connected one-to-one with the signal input ends of the plurality of display panel bodies to form a signal channel between the first signal end and the signal input ends of each of the display panel bodies; the control switch is connected to at least some of the connecting lines.

3. The display panel motherboard according to claim 2, characterized in that: The number of the control switches is equal to the number of the display panel bodies, and each of the connecting lines is connected with the control switch.

4. The display panel motherboard according to claim 1, characterized in that: The control circuit includes a main line connected to the first signal terminal, and a plurality of connection nodes are arranged on the main line; the control circuit also includes a plurality of branch lines, one ends of the plurality of branch lines are connected to the plurality of connection nodes one-to-one, and the other ends of the plurality of branch lines are connected to the signal input terminals of the plurality of display panel bodies one-to-one to form a signal channel between the first signal terminal and the signal input terminals of each of the display panel bodies; the control switch is connected to the main line between at least some of the adjacent two connection nodes.

5. The display panel motherboard according to claim 4, characterized in that: The number of the control switches is equal to the number of the display panel bodies, the control switch is connected to the main line between any two adjacent connection nodes, and the control switch is connected to the main line between any one of the connection nodes and the first signal end.

6. The display panel motherboard according to claim 1, characterized in that: The control circuit includes a plurality of the second signal terminals and a plurality of the control switches, the number of the second signal terminals is equal to the number of the control switches, and the second signal terminals are electrically connected to the control switches in a one-to-one correspondence.

7. The display panel motherboard according to claim 1, characterized in that: The test circuit further includes a third signal terminal, and the third signal terminal is electrically connected to a signal input terminal of any one of the display panel bodies, so that the third signal terminal controls the display of the corresponding display panel body after receiving a third control signal.

8. A method for testing a display panel motherboard, characterized in that: The display panel motherboard is the display panel motherboard according to any one of claims 1 to 7, and the method comprises: A display panel motherboard is provided, wherein the control circuit comprises a plurality of control switches connected to the signal channel, and a plurality of second signal terminals electrically connected to the plurality of control switches, each of the control switches is connected between the first signal terminal and the corresponding signal input terminal, each of the second signal terminals is used to control the corresponding control switch to be turned on or off after receiving a second control signal, and the plurality of control switches are connected in series; Input a first control signal through the first signal terminal of the display panel motherboard, and control the signal channel between the first signal terminal and the signal input terminals of the plurality of display panel bodies on the display panel motherboard to be connected through the control circuit on the display panel motherboard, so that the plurality of display panel bodies display; Determining whether any of the plurality of display panel bodies has display abnormality; If a display panel body among the plurality of display panel bodies has display abnormality, the control circuit controls the signal channel between the first signal end and the signal input end of some of the display panel bodies to be disconnected, so that the corresponding display panel body is turned off; It is determined whether any of the remaining display panel bodies has display abnormality.

9. A display panel obtained by cutting the display panel motherboard according to any one of claims 1 to 7, characterized in that: include: The display panel body is provided with a signal input terminal; A test section, provided with a test signal terminal, the test section comprising a test circuit connected between the test signal terminal and the signal input terminal; A circuit board is arranged on the testing part, and the circuit board is electrically connected to the signal input terminal of the display panel body.

10. The display panel according to claim 9, characterized in that: The test circuit includes a signal line, one end of which is connected to the test signal end, and the other end of which is connected to the signal input end of the display panel body to form a signal channel between the test signal end and the signal input end.

11. The display panel according to claim 10, characterized in that: The test circuit also includes a control switch connected to the signal line. The test unit is also provided with a signal control terminal, which is electrically connected to the control switch. The signal control terminal is used to control the control switch to be turned on or off after receiving a control signal.

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