Data output device and semiconductor device including the same

Abstract

A semiconductor device includes a memory controller and a data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output device configured to output read data from the memory cell array by sensing a logic level of the read data during a low period of a first clock, which is an inverted signal of a divided clock of the clock signal, and a low period of a second clock having a set phase delay amount from the divided clock.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0003121, filed on January 11, 2021, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Various embodiments can relate generally to semiconductor devices, and more particularly, to a semiconductor device and a semiconductor device including a data output device. BACKGROUND

[0004] As demand for high-speed semiconductor systems increases, research has been conducted on high-speed operation of semiconductor devices constituting the semiconductor systems and high-speed data transmission and reception between the semiconductor devices.

[0005] To improve the operation speed of a semiconductor device, the semiconductor device operates in synchronization with a clock signal applied from the outside of the semiconductor device.

[0006] As the speed of the clock signal increases, the operation speed of the semiconductor device can be improved. However, as the frequency of the clock signal increases, it is difficult to accurately synchronize the semiconductor device with the clock signal. SUMMARY

[0007] In one embodiment of the disclosure, a semiconductor device can include a memory controller and a data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output device configured to output read data from the memory cell array by sensing a logic level of the read data during a low period of a first clock and a low period of a second clock, the first clock being an inverted phase signal of a divided clock of the clock signal, the second clock having a set phase delay amount from the divided clock.

[0008] In one embodiment of the disclosure, a data output device can include a clock generation circuit configured to generate a plurality of divided clocks having different phases from each other in response to a clock signal provided from an external device, a trigger circuit configured to receive read data from a memory cell array and output a driving signal according to a logic level of the read data during a low period of a first clock and a low period of a second clock, the first clock being an inverted phase signal of each of the plurality of divided clocks, the second clock being delayed from the divided clock by a set phase delay amount, and a data output driver configured to generate output data by driving the read data according to a logic level of the driving signal. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other aspects, features, and advantages of the subject matter of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a diagram illustrating a configuration of a semiconductor device according to one embodiment of the present disclosure;

[0011] Figure 2 is a diagram illustrating a configuration of a semiconductor memory device according to one embodiment of the present disclosure;

[0012] Figure 3 is a diagram illustrating a configuration of a data output device according to an embodiment of the present disclosure;

[0013] Figure 4 is a diagram illustrating a configuration of a trigger circuit according to an embodiment of the present disclosure;

[0014] Figure 5 is a diagram illustrating a configuration of a latch circuit according to one embodiment of the present disclosure;

[0015] Figure 6 is a timing chart illustrating an operation of a data output device according to one embodiment of the present disclosure; and

[0016] Figure 7 is a timing chart illustrating data sensing timing according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Various embodiments of the present teachings are described in reference to cross-sectional and / or plan view illustrations of idealized embodiments of the present teachings. However, those of ordinary skill in the art will recognize that the embodiments of the present teachings can vary from the shapes of the illustrations. The embodiments of the present teachings should not be construed as limited to the particular shapes of the illustrations. While the present teachings are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in order to elucidate the principles of the present teachings and the practical application thereof. It should be understood by those skilled in the art that the present teachings are not limited to the illustrated embodiments but can vary from the illustrated embodiments without departing from the spirit of the present teachings.

[0018] Various embodiments of the present teachings are described in reference to cross-sectional and / or plan view illustrations of idealized embodiments of the present teachings. However, those of ordinary skill in the art will recognize that the embodiments of the present teachings can vary from the shapes of the illustrations. The embodiments of the present teachings should not be construed as limited to the particular shapes of the illustrations. While the present teachings are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in order to elucidate the principles of the present teachings and the practical application thereof. It should be understood by those skilled in the art that the present teachings are not limited to the illustrated embodiments but can vary from the illustrated embodiments without departing from the spirit of the present teachings.

[0019] Figure 1 is a diagram illustrating a configuration of a semiconductor device according to one embodiment of the present disclosure;

[0020] Reference Figure 1According to one embodiment, the semiconductor device 10 may include a memory controller 101, an input / output (I / O) interface 102, a data storage 103, and a buffer memory 104.

[0021] The memory controller 101 can be configured to decode instructions applied from an external device (host device) via the I / O interface 102, and control data input from the data storage 103 and the buffer memory 104, as well as data output to the data storage 103 and the buffer memory 104, based on the decoding result. For example, the memory controller 101 can control the data to be programmed into the data storage 103 in response to a write request from an external device. The memory controller 101 can provide the data stored in the data storage 103 to the host device in response to a read request from an external device.

[0022] The memory controller 101 may include a controller configured to control the data storage 103 and a controller configured to control the buffer memory 104.

[0023] The data storage 103 can operate synchronously with a clock signal provided from the memory controller 101, and can store or output stored data according to the control of the memory controller 101. The data storage 103 can be constructed from volatile or non-volatile memory devices. In one embodiment, the data storage 103 can be implemented using a memory device selected from various non-volatile memory devices, such as electrically erasable programmable read-only memory (EEPROM), NAND flash memory, NOR flash memory, phase-change random access memory (PRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), and spin torque transfer magnetic random access memory (STTRAM). In one embodiment, the data storage 103 can be implemented using a memory device selected from volatile memory devices, such as dynamic random access memory (DRAM), mobile DRAM, and static random access memory (SRAM).

[0024] Data storage 103 may include multiple semiconductor memory (MEM) devices 20-1, 20-2, ..., and 20-M, which are composed of multiple dies, multiple chips, or multiple packages. In one embodiment, 'M' may be an integer greater than 2.

[0025] The buffer memory 104 can be used as a space configured to temporarily store data when the semiconductor device 10 performs a series of operations (such as writing or reading data) in conjunction with an external device. Figure 1The diagram shows that the buffer memory 104 is located outside the memory controller 101, but the buffer memory 104 may be included inside the memory controller 101.

[0026] The buffer memory 104 can be controlled by a buffer memory controller (e.g., a buffer manager (not shown) set in the memory controller 101).

[0027] The buffer memory 104 may include volatile memory devices such as DRAM, mobile DRAM, and SRAM.

[0028] I / O interface 102 can provide a physical connection between memory controller 101 and external devices (host devices), enabling memory controller 101 to receive control signals for data I / O from external devices and exchange data with them. I / O interface 102 may include one of various standard interface protocols, such as Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Embedded MMC (eMMC) protocol, PCMCIA protocol, Parallel Advanced Technology Attachment (PATA) protocol, Serial Advanced Technology Attachment (SATA) protocol, Small Computer System Interface (SCSI) protocol, Serial Attached SCSI (SAS) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Universal Flash Memory (UFS) protocol, Enhanced Small Disk Interface (ESDI) protocol, and Electronic Integrated Drive (IDE) protocol.

[0029] The semiconductor device 10 can be used as an auxiliary storage device or external storage device for a host device in which the semiconductor device 10 is installed. The semiconductor device 10 may include a solid-state drive (SSD), a USB memory, a secure digital card (SD), a mini secure digital card (mSD), a micro secure digital card (microSD), a secure digital high-capacity card (SDHC), a memory stick card, a smart media card (SM), an MMC card, an eMMC card, a compact flash memory (CF) card, etc.

[0030] Figure 2 This is a diagram illustrating the configuration of a semiconductor memory device according to one embodiment. Figure 2 The diagram illustrates a flash memory device as an example of a semiconductor memory device.

[0031] refer to Figure 2The semiconductor memory device 20 may include a memory cell array 210, a row decoder 220, a data read / write circuit 230, a column decoder 240, a voltage generator 250, and control logic 260. The control logic 260 may be implemented in hardware, software, or a combination of both. For example, the control logic 260 may be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0032] The memory cell array 210 may include memory cells MC, which are disposed in the intersection region of word lines WL1 to WLm and bit lines BL1 to BLn. In one embodiment, 'm' may be an integer greater than one, and 'n' may be an integer greater than one.

[0033] The memory cell array 210 may include a three-dimensional (3D) memory array. The 3D memory array may extend perpendicularly to a flat surface of a semiconductor substrate and may have a structure comprising NAND strings in which at least one memory cell is vertically positioned above another memory cell. However, the 3D memory array is not limited to this structure. More generally, any memory array having both vertical and horizontal dimensions and high integration density can be used as a 3D memory array.

[0034] The row decoder 220 can be coupled to the memory cell array 210 via word lines WL1 to WLm. The row decoder 220 can operate under the control of control logic 260. The row decoder 220 can decode addresses provided from external devices (not shown). The row decoder 220 can select and drive word lines WL1 to WLm based on the decoding result. For example, the row decoder 220 can provide word line voltages from voltage generator 250 to word lines WL1 to WLm.

[0035] Data read / write circuitry 230 can be coupled to memory cell array 210 via bit lines BL1 to BLn. Data read / write circuitry 230 may include read / write circuits RW1 to RWn corresponding to bit lines BL1 to BLn, respectively. Data read / write circuitry 230 can operate under the control of control logic 260. Depending on the operating mode, data read / write circuitry 230 can operate as a write driver or a sense amplifier. For example, in a write operation, data read / write circuitry 230 can operate as a write driver to store data provided from an external device into memory cell array 210. In another example, in a read operation, data read / write circuitry 230 can operate as a sense amplifier to read data from memory cell array 210.

[0036] Data read / write circuit 230 may include the data output device to be described (seeFigure 3 (of 100).

[0037] The column decoder 240 can operate under the control of the control logic 260. The column decoder 240 can decode addresses provided from external devices. Based on the decoding result, the column decoder 240 can couple the data I / O lines (or data I / O buffers) to the read / write circuits RW1 to RWn of the data read / write circuit 230, which correspond to bit lines BL1 to BLn, respectively.

[0038] Voltage generator 250 can generate voltages to be used in the operation of semiconductor memory device 20. The voltage generated by voltage generator 250 can be applied to the memory cells MC of memory cell array 210. For example, a programming voltage generated during a programming operation can be applied to the word line of the memory cell on which a programming operation is to be performed. In another example, an erase voltage generated during an erase operation can be applied to the well region of the memory cell on which an erase operation is to be performed. In yet another example, a read voltage generated during a read operation can be applied to the word line of the memory cell on which a read operation is to be performed.

[0039] Control logic 260 can control the overall operation of semiconductor memory device 20 based on control signals provided from external devices. For example, control logic 260 can control read operations, write operations, and erase operations of semiconductor memory device 20.

[0040] Figure 3 This is a diagram illustrating the configuration of a data output device according to one embodiment.

[0041] refer to Figure 3 According to one embodiment, the data output device 100 may include a clock generation circuit 1100, a trigger circuit 1200, and a data output driver 1300.

[0042] The clock generation circuit 1100 can generate multiple frequency-divided clocks ICLK, QCLK, IBCLK, and QBCLK with different phases from each other in response to an external clock signal CLK. The external clock signal CLK can be a switching signal input from outside the semiconductor memory device 20 (e.g., memory controller 101).

[0043] Multiple frequency-divided clocks ICLK, QCLK, IBCLK, and QBCLK may include, but are not limited to, a first frequency-divided clock ICLK, a second frequency-divided clock QCLK, a third frequency-divided clock IBCLK, and a fourth frequency-divided clock QBCLK, and the number of frequency-divided clocks may vary depending on the implementation of the clock generation circuit 1100.

[0044] The frequency-divided clocks ICLK, QCLK, IBCLK, and QBCLK generated in the clock generation circuit 1100 can have a frequency twice as low as the external clock signal CLK and can have a phase difference of 90 degrees.

[0045] The clock generation circuit 1100 may include a frequency divider circuit, which may include a phase-locked loop (PLL), a delay-locked loop (DLL), etc.

[0046] The trigger circuit 1200 can receive, for example, multi-bit data DATA<1:n> transmitted via global I / O lines (not shown), and can output drive signals DRV synchronously with the first to fourth frequency divider clocks ICLK, QCLK, IBCLK and QBCLK according to the logic level of the data DATA<1:n>.

[0047] The data output driver 1300 can generate output data DOUT according to the logic level of the drive signal DRV, and can provide the output data DOUT to an external device (e.g., memory controller 101) through I / O pads (not shown). In one embodiment, the data output driver 1300 can be configured to generate output data DOUT by driving data read according to the logic level of the drive signal DRV.

[0048] Specifically, the trigger circuit 1200 according to this technology can be configured to sense the logic level of data DATA<1:n> during the time period when the low-level period of the first clock and the low-level period of the second clock overlap, by setting the inverted signal of each of the first to fourth divided clocks ICLK, QCLK, IBCLK, and QBCLK as the first clock and setting a signal with a set phase delay for each divided clock as the second clock. Here, the set phase delay can be [360 degrees / number of divided clocks]. For example, when the clock generation circuit 1100 divides the external clock signal CLK into four clocks, the phase difference between the first clock and the second clock can be 90 degrees. For example, when the clock generation circuit 1100 divides the external clock signal CLK into X clocks, the phase difference between the X divided clocks is equal. In one embodiment, X is an integer greater than or equal to 2.

[0049] In one embodiment, the trigger circuit 1200 can use the inverted signal of the first divided clock ICLK as the first clock CLK_INV, and use a signal with a phase delay of 90 degrees from the first divided clock ICLK (e.g., the second divided clock QCLK) as the second clock CLK90 to drive the first data DATA. <1> Similarly, the trigger circuit 1200 can use the inverted signal of the second divided clock QCLK as the first clock CLK_INV, and use a signal with a phase delay of 90 degrees from the second divided clock QCLK (e.g., the third divided clock IBCLK) as the second clock CLK90 to drive the second data DATA. <2> The trigger circuit 1200 can use the inverted signal of the third divided clock IBCLK as the first clock CLK_INV, and use a signal with a phase delay of 90 degrees from the third divided clock IBCLK (e.g., the fourth divided clock QBCLK) as the second clock CLK90 to drive the third data DATA. <3> The trigger circuit 1200 can use the inverted signal of the fourth divided clock QBCLK as the first clock CLK_INV, and use a signal with a phase delay of 90 degrees from the fourth divided clock QBCLK (e.g., the first divided clock ICLK) as the second clock CLK90 to drive the fourth data DATA. <4> .

[0050] Since the logic level of data DATA<1:n> is sensed during the time period when the low level period of the first clock, which is the inverted signal of the frequency divider clock, coincides with the low level period of the second clock, which has a set phase delay for the frequency divider clock, the sensing timing can be advanced compared to sensing the data during the high level period of the frequency divider clock.

[0051] The timing margin used to invert the frequency divider clock can prevent or reduce the overlap of sensing periods of continuously input data.

[0052] Figure 4 This is a diagram illustrating the configuration of a trigger circuit according to one embodiment.

[0053] refer to Figure 4 According to one embodiment, the trigger circuit 1200 may include a latch 1210 and a register 1220.

[0054] The latch 1210 may include multiple latching circuits 1211, 1212, 1213, and 1214, which are configured to: use the inverted signal of each of the divided clocks ICLK, QCLK, IBCLK, and QBCLK as a first clock, and use a signal having a set phase delay to the divided clocks as a second clock, sensing data DATA during the time period when the low-level period of the first clock coincides with the low-level period of the second clock. <1> DATA <2> DATA <3> and DATA <4> The logic level.

[0055] The first latch circuit 1211 can sense the first data DATA by using the inverted signal of the first divided clock ICLK as the first clock CLK_INV and using a signal with a phase delay of 90 degrees from the first divided clock ICLK (e.g., the second divided clock QCLK) as the second clock CLK90. <1> This is used to output the first data point RD1 that is rising and the first data point FD1 that is falling.

[0056] The second latch circuit 1212 can sense the second data DATA by using the inverted signal of the second divided clock QCLK as the first clock CLK_INV and using a signal with a phase delay of 90 degrees from the second divided clock QCLK (e.g., the third divided clock IBCLK) as the second clock CLK90. <2> This is used to output the second data RD2 (rising) and the second data FD2 (falling).

[0057] The third latch circuit 1213 can sense the third data DATA by using the inverted signal of the third divided clock IBCLK as the first clock CLK_INV and using a signal with a phase delay of 90 degrees from the third divided clock IBCLK (e.g., the fourth divided clock QBCLK) as the second clock CLK90. <3> This is used to output the rising third data RD3 and the falling third data FD3.

[0058] The fourth latch circuit 1214 can sense the fourth data DATA by using the inverted signal of the fourth divided clock QBCLK as the first clock CLK_INV and using a signal with a phase delay of 90 degrees from the fourth divided clock QBCLK (e.g., the first divided clock ICLK) as the second clock CLK90. <4> This is used to output the fourth data point that is rising, RD4, and the fourth data point that is falling, FD4.

[0059] Register 1220 can output a drive signal DRV based on the logic levels of rising data RD1 to RD4 and falling data FD1 to FD4 sensed by latch 1210. In one embodiment, the drive signal DRV may include a rising drive signal RDRV and a falling drive signal FDRV. Register 1220 may include a first register 1221 and a second register 1222, the first register 1221 being configured to output a rising drive signal RDRV by driving rising data RD1 to RD4, and the second register 1222 being configured to output a falling drive signal FDRV by driving falling data FD1 to FD4.

[0060] Figure 5 This is a diagram illustrating the configuration of a latch circuit according to one embodiment.

[0061] Figure 5 The diagram illustrates a latch circuit 121A according to one embodiment, and Figure 4 The first to fourth latch circuits 1211 to 1214 shown in the figure can have the same configuration as latch circuit 121A.

[0062] refer to Figure 5 The latch circuit 121A may include a sensor 131, a charging circuit 133, and an output device 135.

[0063] Using the inverted signal of the frequency divider clock DCLK as the first clock CLK_INV, and using a signal with a set phase delay for the frequency divider clock DCLK as the second clock CLK90, during the time period when the low level period of the first clock CLK_INV coincides with the low level period of the second clock CLK90, the sensor 131 can sense the logic levels of data IN and INB, and apply a signal corresponding to the sensed logic level to the first output node NODE1 and the second output node NODE2, and can sense the signals applied to the first output node NODE1 and the second output node NODE2, and output the sensed signals as latch signals LAT2 and LAT2B.

[0064] The charging circuit 133 can charge or discharge the potential of the first output node NODE1 and the second output node NODE2 of the sensor 131 in response to the first clock CLK_INV and the second clock CLK90.

[0065] Output 135 can output rising data RD and falling data FD in response to latch signals LAT2 and LAT2B.

[0066] In one embodiment, sensor 131 may include: a first P-type transistor P10 configured to provide a power supply voltage VCCI in response to a first clock CLK_INV; a second P-type transistor P11 and a third P-type transistor P12 configured to provide a sensing voltage in response to a second clock CLK90; and a fourth P-type transistor P13 and a fifth P-type transistor P14 configured to apply a sensing voltage to output nodes NODE1 and NODE2 according to the logic levels of data IN and INB.

[0067] Sensor 131 may further include a first latch 1311 and a second latch 1313. The first latch 1311 can generate a first latch signal LAT2 by inverting and driving first sensing data (e.g., the potential of the first output node NODE1) applied to the first output node NODE1. In one embodiment, the first sensing data applied to the first output node NODE1 can be inverted and then driven using a ground voltage VSS and a power supply voltage VCCI.

[0068] The second latch 1313 can generate a second latch signal LAT2B by driving second sense data (e.g., the potential of the second output node NODE2) applied to the second output node NODE2. In one embodiment, the second sense data applied to the second output node NODE2 can be inverted and then driven by a ground voltage VSS and a power supply voltage VCCI.

[0069] In one embodiment, the charging circuit 133 may include a first N-type transistor to a seventh N-type transistor N10 to N16, the first N-type transistor to the seventh N-type transistor N10 to N16 being configured to maintain or discharge the potential of output nodes NODE1 and NODE2 in response to a first clock CLK_INV and a second clock CLK90.

[0070] While the sensor 131 senses data IN and INB during the period when the low level of the first clock CLK_INV coincides with the low level of the second clock CLK90, the charging circuit 133 can maintain the potential of the output nodes NODE1 and NODE2. When the latch signals LAT2 and LAT2B generated in the sensor 131 are transmitted to the output device 135, the output nodes NODE1 and NODE2 can be discharged by the charging circuit 133.

[0071] In one embodiment, the output device 135 may include a first output device 1351 and a second output device 1353, the first output device 1351 being configured to output rising data RD in response to a first latch signal LAT2 and a second latch signal LAT2B, and the second output device 1353 being configured to output falling data FD in response to the first latch signal LAT2 and the second latch signal LAT2B received from the sensor 131.

[0072] because Figure 4 The first to fourth latch circuits 1211 to 1214 shown in the figure have the same characteristics as... Figure 5 The latch circuit 121A shown in the figure has the same configuration, so the first data to the fourth data DATA can be sensed sequentially by the first latch circuit to the fourth latch circuit 1211 to 1214. <1> DATA <2> DATA <3> and DATA <4> .

[0073] Figure 6 This is a timing diagram illustrating the operation of a data output device according to one embodiment.

[0074] like Figure 6 As shown, during the period when the low level of the first clock CLK_INV coincides with the low level of the second divided clock QCLK, the first latch circuit 1211 can sense the first data D1. During this coincidence period, the low level of the first clock CLK_INV and the low level of the second clock CLK90 can coincide. The first clock CLK_INV is the inverted signal ICLK_INV of the first divided clock ICLK, and the second clock CLK90 is the second divided clock QCLK with a phase delay of 90 degrees from the first divided clock ICLK. In one embodiment, D1 to D16 can be the first data DATA respectively. <1> Data up to number 16 <16> .

[0075] like Figure 6 As shown, during the period when the low level of the first clock CLK_INV coincides with the low level of the third divided clock IBCLK, the second latch circuit 1212 can sense the second data D2. During this coincidence period, the low level of the first clock CLK_INV and the low level of the second clock CLK90 can coincide. The first clock CLK_INV is the inverted signal QCLK_INV of the second divided clock QCLK, and the second clock CLK90 is the third divided clock IBCLK with a phase delay of 90 degrees from the second divided clock QCLK.

[0076] like Figure 6As shown, during the period when the low level of the first clock CLK_INV coincides with the low level of the fourth divided clock QBCLK, the third latch circuit 1213 can sense the third data D3. During this coincidence period, the low level of the first clock CLK_INV and the low level of the second clock CLK90 can coincide. The first clock CLK_INV is the inverted signal IBCLK_INV of the third divided clock IBCLK, and the second clock CLK90 is the fourth divided clock QBCLK with a phase delay of 90 degrees from the third divided clock IBCLK.

[0077] like Figure 6 As shown, during the period when the low level of the first clock CLK_INV coincides with the low level of the first divided clock ICLK, the fourth latch circuit 1214 can sense the fourth data D4. During this coincidence period, the low level of the first clock CLK_INV and the low level of the second clock CLK90 can coincide. The first clock CLK_INV is the inverted signal QBCLK_INV of the fourth divided clock QBCLK, and the second clock CLK90 is the first divided clock ICLK with a phase delay of 90 degrees from the fourth divided clock QBCLK.

[0078] Compared to sensing data during the high-level periods of each of the divided clocks ICLK, QCLK, IBCLK, and QBCLK without inverting the divided clocks ICLK, QCLK, IBCLK, and QBCLK, and during the high-level periods of each divided clock with a 90-degree phase delay, the data sensing timing can be advanced.

[0079] Because a timing margin corresponding to the inversion time ΔT of each of the divided clocks ICLK, QCLK, IBCLK and QBCLK in latch circuits 1211 to 1214 is generated, the sensing periods of the continuously input data D1 to D16 can be prevented from overlapping or the overlap can be mitigated.

[0080] Figure 7 This is a timing diagram illustrating data sensing timing according to one embodiment.

[0081] refer to Figure 7 Data can be sensed during the sensing period OPCLK_P, which is set from the first timing T1, which coincides with the low level of the first clock DCLK_INV, which is inverted by the frequency divider clock DCLK, and the low level of the second clock CLK90, which has a phase delay of 90 degrees from the frequency divider clock DCLK.

[0082] Therefore, since the sensing timing is advanced from the second timing T2 to the first timing T1 compared to the sensing data during the sensing period OPCLK_N, which is set from the high-level period of the divided clock DCLK and the high-level period of the second clock CLK90 with a phase delay of 90 degrees from the divided clock DCLK, the data output speed can be improved.

[0083] Furthermore, due to the timing margin ΔT corresponding to the time used to generate the first clock CLK_INV by inverting the divided clock DCLK, conflicts between continuously sensed data can be prevented or mitigated.

[0084] The embodiments described above in this disclosure are intended to illustrate the embodiments and not to limit the embodiments. Various alternatives and equivalents are possible. The embodiments are not limited to those described herein. The embodiments are also not limited to any particular type of semiconductor device. In view of this disclosure, other additions, reductions, or modifications are apparent and are intended to fall within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: Memory controller; as well as Data storage is configured to input and output data synchronously with a clock signal provided from the memory controller. The data storage mentioned therein includes: Memory cell array; as well as A data output device is configured to output read data from the memory cell array by sensing the logic level of read data during a period when the low level period of a first clock coincides with the low level period of a second clock, wherein the first clock is the inverted signal of a frequency-divided clock of the clock signal, and the second clock has a set phase delay from the frequency-divided clock.

2. The semiconductor device according to claim 1, wherein the data output device comprises: A clock generation circuit is configured to generate multiple frequency-divided clocks with different phases from each other in response to the clock signal; The trigger circuit is configured to receive the read data and output a drive signal synchronously with the first clock and the second clock according to the logic level of the read data. as well as A data output driver is configured to generate output data by driving the read data according to the logic level of the drive signal.

3. The semiconductor device of claim 2, wherein the frequency divider clock has a lower frequency than the clock signal.

4. The semiconductor device of claim 2, wherein the phase difference between the frequency divider clocks is set to 360 degrees per frequency divider clock.

5. The semiconductor device of claim 2, wherein the clock generation circuit is configured to: generate a first frequency-divided clock having a frequency lower than the clock signal, a second frequency-divided clock delaying the first frequency-divided clock by the predetermined phase delay, a third frequency-divided clock delaying the second frequency-divided clock by the predetermined phase delay, and a fourth frequency-divided clock delaying the third frequency-divided clock by the predetermined phase delay.

6. The semiconductor device of claim 5, wherein the trigger circuit comprises: The first latch circuit is configured to sense the first read data synchronously with the inverted signal of the first divided clock and the second divided clock. The second latch circuit is configured to sense the second read data synchronously with the inverted signal of the second divided clock and the third divided clock. The third latch circuit is configured to sense the third read data synchronously with the inverted signal of the third frequency divider clock and the fourth frequency divider clock. as well as The fourth latch circuit is configured to sense the fourth read data synchronously with the inverted signal of the fourth divided clock and the first divided clock.

7. The semiconductor device of claim 2, wherein the trigger circuit comprises: The sensor is configured to: sense the logic level of the read data during the low-level period of the first clock and the low-level period of the second clock that coincides with the low-level period of the first clock, apply a first latch signal corresponding to the logic level of the read data to a first output node, and apply a second latch signal corresponding to the logic level of the read data to a second output node; The charging circuit is configured to maintain or discharge the potential of the first output node and the potential of the second output node in response to the first clock and the second clock. as well as The output is configured to output rising data and falling data in response to the first latch signal and the second latch signal.

8. The semiconductor device of claim 7, wherein the drive signal comprises a rising drive signal and a falling drive signal, and The trigger circuit further includes: A first register is configured to output the rising drive signal in response to the rising data; as well as The second register is configured to output the drop drive signal in response to the drop data.

9. A data output device, comprising: The clock generation circuit is configured to generate multiple frequency-divided clocks with different phases from each other in response to a clock signal provided from an external device. The trigger circuit is configured to receive read data from the memory cell array and, during the overlap of a low-level period of a first clock and a low-level period of a second clock, output a drive signal according to the logic level of the read data, wherein the first clock is the inverted signal of each of the plurality of frequency-divided clocks, and the second clock is delayed by a set phase delay from the frequency-divided clocks. as well as A data output driver is configured to generate output data by driving the read data according to the logic level of the drive signal.

10. The data output device according to claim 9, wherein each of the frequency divider clocks has a frequency lower than the clock signal.

11. The data output device according to claim 9, wherein the phase difference between the frequency division clocks is set to 360 degrees / number of frequency division clocks.

12. The data output device of claim 9, wherein the clock generation circuit is configured to: generate a first frequency-divided clock having a frequency lower than the clock signal, a second frequency-divided clock delaying the first frequency-divided clock by the set phase delay, a third frequency-divided clock delaying the second frequency-divided clock by the set phase delay, and a fourth frequency-divided clock delaying the third frequency-divided clock by the set phase delay.

13. The data output device according to claim 12, wherein the trigger circuit comprises: The latch is configured to output a latch signal by sensing the logic level of the read data during the low-level period of the first clock and the low-level period of the second clock that coincides with the low-level period of the first clock for each of the first to fourth divided clocks. as well as The register is configured to output the drive signal according to the logic level of the latch signal.

14. The data output device according to claim 13, wherein the latch comprises: The first latch circuit is configured to sense the first read data synchronously with the inverted signal of the first divided clock and the second divided clock. The second latch circuit is configured to sense the second read data synchronously with the inverted signal of the second divided clock and the third divided clock. The third latch circuit is configured to sense the third read data synchronously with the inverted signal of the third frequency divider clock and the fourth frequency divider clock. as well as The fourth latch circuit is configured to sense the fourth read data synchronously with the inverted signal of the fourth divided clock and the first divided clock.

15. The data output device according to claim 9, wherein the trigger circuit comprises: The sensor is configured to apply a latch signal generated by sensing the logic level of the read data to the output node during the low-level period of the first clock and the low-level period of the second clock that coincides with the low-level period of the first clock. The charging circuit is configured to maintain or discharge the potential of the output node in response to the first clock and the second clock. as well as The output device is configured to output the drive signal in response to the latch signal.

16. The data output device of claim 15, wherein the sensor includes a first latch and a second latch, the first latch being configured to apply a first latch signal corresponding to the logic level of the read data to a first output node, and the second latch being configured to apply a second latch signal corresponding to the logic level of the read data to a second output node, and The output is configured to output rising data and falling data in response to the first latch signal and the second latch signal.

17. The data output device according to claim 16, wherein the drive signal includes a rising drive signal and a falling drive signal, and The trigger circuit further includes: A first register is configured to output the rising drive signal in response to the rising data; as well as The second register is configured to output the drop drive signal in response to the drop data.

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