A method of manufacturing an interconnect structure and a memory device
By using a polysilicon layer as a protective layer during the interconnect structure manufacturing process, the problem of bit line defects in memory cells was solved, the stability and yield of memory devices were improved, and the integrity protection of the metal line structure was achieved.
Patent Information
- Application Number
- CN202011561498.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-12-25
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2040-12-25
AI Technical Summary
In the manufacturing process of the interconnect structure between the memory cell and the peripheral circuit, existing technologies have many defects in the bit lines of the memory cell and its outer parts, which leads to a decrease in the yield and unstable performance of memory devices.
During the fabrication of interconnect structures, a protective layer is formed on a polysilicon layer, which serves as a hard mask to prevent damage to the underlying metal line structure. This includes etching after ion implantation to form two layers of protection, ensuring the integrity of the metal line structure.
This improves the stability and yield of memory devices, avoids damage to the metal wire structure and its protective layer, and ensures the reliability of the interconnect structure.
Smart Images
Figure CN114758982B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for manufacturing interconnect structures and memory devices. Background Technology
[0002] In existing technologies, polysilicon plugs are formed on the contact portions of memory cells, and then the connection structure between the memory cells and surrounding circuits is formed. The fabrication process of this connection structure typically employs techniques such as dry etching, deposition, and cleaning.
[0003] However, after manufacturing the interconnect structure between the memory cell and the peripheral circuit using existing processes, it was found that there were many defects in the bit lines of the memory cell and its outer parts, which ultimately led to a decrease in the yield and unstable performance of the memory device. Summary of the Invention
[0004] This application provides a method for manufacturing an interconnect structure and a memory device. During the manufacturing process of the interconnect structure, a polysilicon layer can be used to protect the underlying metal line structure, preventing damage and thus improving the stability of the device.
[0005] Firstly, this application provides the following technical solution through an embodiment of the application:
[0006] A method for manufacturing an interconnect structure, comprising:
[0007] A first contact hole is formed above a first active region; wherein the first contact hole is located between metal lines; a polysilicon layer is formed above the first active region and a second active region; wherein the polysilicon layer fills the first contact hole; a second contact hole is formed above the second active region; ion implantation is performed into the second active region within the second contact hole; the polysilicon layer is etched, and a contact plug is formed within the first contact hole; a metal layer is formed above the first active region and the second active region; wherein the metal layer fills the first contact hole and the second contact hole, and forms a connection.
[0008] Optionally, forming a first contact hole between the metal lines above the first active region includes:
[0009] A first mask is formed over the first active region and the second active region; etching is performed over the first active region to form a first contact hole; the first mask is removed.
[0010] Optionally, forming a second contact hole above the second active region includes:
[0011] A second mask is formed on the polysilicon layer; the polysilicon layer above the second active region is etched to form the second contact hole.
[0012] Optionally, the ion implantation into the second active region within the second contact hole includes:
[0013] N+ type ion implantation is performed on the second active region within the second contact hole.
[0014] Optionally, the ion implantation into the second active region within the second contact hole includes:
[0015] P+ type ion implantation is performed on the second active region within the second contact hole.
[0016] Optionally, etching the polysilicon layer and forming a contact plug within the first contact hole includes:
[0017] A third mask is formed inside the second contact hole; the polysilicon layer is etched to form a contact plug inside the first contact hole.
[0018] Optionally, the first active region is the active region of the storage cell region, and the second active region is the active region of the peripheral circuit region.
[0019] Optionally, the metal line is a bit line.
[0020] Optionally, the metal layer is characterized by being tungsten metal.
[0021] Secondly, through one embodiment of this application, the following technical solution is provided:
[0022] A storage device comprising an interconnect structure manufactured using any of the methods described in the first aspect above.
[0023] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:
[0024] 1. Compared with the prior art, the embodiments of the present invention effectively utilize the polysilicon layer in the interconnect structure manufacturing process. The polysilicon layer is etched in the final step before the metal layer deposition, i.e., etching after ion implantation. This allows multiple deposition, etching, and cleaning processes during interconnect structure manufacturing to be performed on the polysilicon layer, without damaging the metal line structure and its protective layer beneath the polysilicon layer, thus improving the stability of the manufactured semiconductor device.
[0025] 2. In this embodiment of the invention, two protective layers, a patterned mask and a polysilicon layer, can be formed during ion implantation, further avoiding damage to the metal line structure and its protective layer, and improving the stability of the manufactured semiconductor device. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figures 1 to 5 This is a schematic cross-sectional view of a semiconductor device manufactured using a conventional process according to an embodiment of the present invention.
[0028] Figures 6 to 12 This is a cross-sectional schematic diagram of a semiconductor device manufactured using the interconnect structure manufacturing method provided by the present invention. Detailed Implementation
[0029] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0030] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0031] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0032] In the existing technology, taking the manufacturing process of memory devices as an example, the process for manufacturing the interconnect structure between active regions is as follows:
[0033] After forming a hard mask 111 above the active region 101 of the memory cell area, dry etching is used to form the contact hole 121 and the contact portion of the active region 101, such as... Figure 1 As shown. Polysilicon is deposited above the active region 101 of the memory cell area, then a mask is formed again and dry etching is performed to form polysilicon contact plugs 122 between the bit lines, as shown. Figure 2As shown. The overlay mask is removed, and a spin-on-hard mask (SOH) pattern is applied. Then, photolithography is performed to form contact holes 123 and contact portions above the active area 102 in the peripheral circuit area, as shown. Figure 3 As shown. Then the coated SOH was removed, and N+ type mask deposition and N-type ion implantation were performed, as well as P+ type mask deposition and P-type ion implantation, respectively, as shown. Figure 4 As shown. Finally, a cleaning process and deposition of conductive metal 124 are performed, as follows. Figure 5 As shown. The memory devices produced by this fabrication process have low reliability and certain defects. Analysis revealed that the multiple cleaning, deposition, and ion implantation processes in the above-mentioned process damage the metal line structure 103 above the active region 101 of the memory cell area, and the contact plugs 122 formed between the metal line structures 103 have structural defects, ultimately leading to a decrease in the reliability of the memory device. Based on the above findings, this invention further optimizes the process and proposes a method for manufacturing interconnect structures to improve or solve these problems.
[0034] The method for manufacturing an interconnect structure provided in this embodiment can be applied to the fabrication of semiconductor devices, including but not limited to DRAM (Dynamic Random Access Memory) devices and flash memory devices. The method in this embodiment can be used in the fabrication of any similar interconnect structure, and is particularly suitable for protecting the metal lines on the active region while forming the interconnect structure. In this embodiment, the metal lines are mainly described using bit line 201 as an example.
[0035] For details, please refer to Figure 6 A semiconductor substrate, such as a Si or SiO2 substrate, is provided. An active region is formed on the substrate. The active region is divided into two parts: a first active region 210 and a second active region 220. Specifically, the first active region 210 can be the active region of a memory cell region 21, and the second active region 220 can be the active region of a peripheral circuit region 22. Bit lines 201 and a protective layer 203 structure outside the bit lines 201 are formed above the active regions through etching and deposition processes. The protective layer 203 can extend above the second active region 220, and a SiN layer can be deposited as the protective layer 203. A dielectric layer 205 is then deposited to fill the area. Further, a first mask 231 is formed on the semiconductor substrate and the dielectric layer 205 above the active regions. This first mask 231 can be a hard mask pattern. Then, the dielectric layer 205 between the bit lines 201 is etched until it contacts the active regions, forming first contact holes 211, such as... Figure 7As shown, the etching method can be dry etching. Next, the first mask 231 is removed, and a polysilicon layer 212 is formed over the protective layer 203 on the active region, inside the contact holes, and over the bit lines 201 for protective coverage. Figure 8 As shown.
[0036] Furthermore, unlike existing technologies, in this embodiment of the invention, a second mask 232 is first formed on the polysilicon layer 212, such as a spin-coated hard mask (SOH). Figure 9 As shown; then, a second contact hole 221 is formed above the second active region 220 until it contacts the second active region 220. At this time, the polysilicon layer 212 is not etched first, allowing the polysilicon layer 212 to provide protection in subsequent processes. Next, please refer to... Figure 10 Ion implantation is performed on the contact portion of the second active region 220. First, the mask used during the first ion implantation is covered, and N+ ions are implanted into the second active region 220 in the first region at the bottom of the second contact hole 221. The mask is then removed. Next, the mask used during the second ion implantation is covered, and P+ ions are implanted into the second active region 220 in the second region at the bottom of the second contact hole 221. After ion implantation is completed, the mask covering the polysilicon layer 212 is removed. The first region and the second region are different regions at the bottom of the second contact hole 221.
[0037] In the preceding processes, such as cleaning, mask deposition, and ion implantation, bit line 201 and its protective layer 203 are both located under the polysilicon layer 212. This effectively protects bit line 201 and protective layer 203, effectively using the polysilicon layer 212 as a hard mask. Especially during ion implantation, it can form a double-layer protection, preventing damage or loss of bit line 201 and protective layer 203, ensuring the integrity of the first contact hole 211 structure between bit lines 201, and guaranteeing device performance stability.
[0038] Next, a third mask 233, such as an SOH layer, is deposited in the second contact hole 221 to protect the active region below the second contact hole 221 after ion implantation. Then, the polysilicon layer 212 is etched, removing all polysilicon layers 212 outside the first contact hole 211 and etching away a portion of the polysilicon within the first contact hole 211, forming a contact plug 213 at the bottom of the first contact hole 211. Figure 11 As shown. The contact plug 213 can isolate the first active region 210. Finally, the third mask 233 in the second contact hole 221 is removed, and conductive metal is deposited in the contact plug 213, the protective layer 203, and the second contact hole 221. The metal layer 214 can then connect the second active region 220 below the contact plug 213 and the second contact hole 221, completing the fabrication of the interconnect structure, as shown. Figure 12 As shown.
[0039] In summary, the embodiments of the present invention can achieve the following effects:
[0040] Compared to existing technologies, this invention effectively utilizes the polysilicon layer 212 in the interconnect structure manufacturing process. The polysilicon layer 212 is etched in the final step before the metal deposition layer 214, i.e., after ion implantation. This ensures that multiple deposition, etching, and cleaning processes during interconnect structure manufacturing are performed on the polysilicon layer 212, preventing damage to the bit lines 201 and protective layer 203 beneath the polysilicon layer 212. Furthermore, during ion implantation, a double protective layer of pattern mask and polysilicon layer 212 is formed, further preventing damage to the bit lines 201 and their protective layer 203.
[0041] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0042] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0043] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A method for manufacturing an interconnect structure, characterized in that, include: A first contact hole is formed above the first active region; wherein the first contact hole is located between the metal lines; A polysilicon layer is formed above the first active region and the second active region; wherein the polysilicon layer fills the first contact hole; A second contact hole is formed above the second active region; Ion implantation is performed into the second active region within the second contact hole; The polysilicon layer is etched, and a contact plug is formed in the first contact hole; A metal layer is formed above the first active region and the second active region; wherein the metal layer fills the first contact hole and the second contact hole and forms a connection.
2. The method as described in claim 1, characterized in that, The formation of the first contact hole between the metal lines above the first active region includes: A first mask is formed above the first active region and the second active region; Etching is performed above the first active region to form a first contact hole; Remove the first mask.
3. The method as described in claim 1, characterized in that, A second contact hole is formed above the second active region, including: A second mask is formed on the polysilicon layer; The polysilicon layer above the second active region is etched to form the second contact hole.
4. The method as described in claim 1, characterized in that, The step of ion implantation into the second active region within the second contact hole includes: N+ type ion implantation is performed on the second active region within the second contact hole.
5. The method as described in claim 1, characterized in that, The step of ion implantation into the second active region within the second contact hole includes: P+ type ion implantation is performed on the second active region within the second contact hole.
6. The method as described in claim 1, characterized in that, The etching of the polysilicon layer and the formation of a contact plug within the first contact hole includes: A third mask is formed within the second contact hole; The polysilicon layer is etched to form a contact plug within the first contact hole.
7. The method as described in claim 1, characterized in that, The first active region is the active region of the memory cell region, and the second active region is the active region of the peripheral circuit region.
8. The method as described in claim 1, characterized in that, The metal wire is a bit line.
9. The method as described in claim 1, characterized in that, The metal layer is tungsten.
10. A storage device, characterized in that, This includes interconnect structures manufactured using any of the methods described in claims 1-9.
Citation Information
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