Light detection device

Abstract

The present disclosure relates to a light detection device, including: a semiconductor substrate, the semiconductor substrate including a floating diffusion node; and a wiring layer, the wiring layer including: a first wiring, the first wiring connected to the floating diffusion node; a first hollow area; and a second hollow area, wherein the first hollow area, the first wiring and the second hollow area are arranged in sequence in a specific direction.

Description

[0001] This application is a divisional application of patent application No. 201680015741.4, filed on March 17, 2016, with the invention name “Solid-state image capture element and electronic device”. Technical Field

[0002] The present disclosure relates to a solid-state image capturing element and an electronic device, and more particularly to a solid-state image capturing element and an electronic device capable of reducing capacitance by using a hollow area. Background Art

[0003] In complementary metal oxide semiconductor (CMOS) image sensors, as pixel miniaturization continues, the aperture area of ​​the photodiode decreases, reducing sensitivity. Furthermore, the size of the pixel transistors decreases, and random noise worsens. As a result, the signal-to-noise ratio (S / N) decreases, and image quality deteriorates.

[0004] Therefore, it has been proposed to improve the signal-to-noise ratio by reducing the parasitic capacitance of the floating diffusion (FD) and improving the charge-to-voltage conversion efficiency.

[0005] The parasitic capacitance of the FD includes the diffusion capacitance of the FD, the capacitance connected to the gate electrode of the amplifier transistor via the FD wiring, the capacitance of the FD wiring, and any other capacitance. The diffusion capacitance of the FD can be reduced by lowering the concentration of N-type impurities in the FD. However, in this case, there is a concern about contact failure.

[0006] The capacitance of the gate electrode of the amplifier transistor can be reduced by reducing the size of the amplifier transistor. However, when the size of the amplifier transistor is reduced, random noise is further deteriorated.

[0007] Furthermore, the capacitance of the FD wiring can be reduced to some extent by designing the wiring layout. However, because the FD needs to be connected to the amplifier transistor, this wiring layout is limited by the shared pixel system. Therefore, reducing the capacitance of the FD wiring by designing the wiring layout is difficult.

[0008] Therefore, a method of reducing the capacitance of the FD wiring by changing the entire periphery of the wiring layer to a low dielectric constant film (for example, refer to PTL 1) has been proposed.

[0009] [Citation List]

[0010] [Patent Document]

[0011] [PTL 1]

[0012] JP 2009-231501A Summary of the Invention

[0013] [Technical Issues]

[0014] As a method of reducing capacitance, a method different from the method described in PTL 1 is desired.

[0015] The present disclosure has been made in consideration of such a situation, and makes it possible to reduce capacitance by using the hollow area.

[0016] [Solution to the problem]

[0017] A solid-state image capturing element according to an aspect of the present disclosure is a solid-state image capturing element in which at least a portion of a region between an FD wiring connected to a floating diffusion and wirings other than the FD wiring is a hollow region.

[0018] An electronic device according to one aspect of the present disclosure corresponds to the solid-state image capturing element of the one aspect of the present disclosure.

[0019] According to one aspect of the present disclosure, at least a portion of a region between an FD wiring connected to a floating diffusion node and wirings other than the FD wiring is a hollow region.

[0020] [Beneficial effects of the present invention]

[0021] According to one aspect of the present disclosure, capacitance can be reduced. Further, according to one aspect of the present disclosure, capacitance can be reduced using the hollow region.

[0022] The advantageous effects described in the present disclosure are not necessarily limited and may be any effects described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] [ Figure 1 ]

[0024] Figure 1 2 is a schematic diagram showing a configuration example of a CMOS image sensor as a solid-state image capturing element according to the first embodiment of the present disclosure.

[0025] [ Figure 2 ]

[0026] Figure 2 To show that Figure 1 Schematic diagram of an example of a circuit configuration of one pixel among pixels two-dimensionally arranged in a pixel area.

[0027] [ Figure 3 ]

[0028] Figure 3 is a schematic diagram showing a first structural example of a CMOS image sensor.

[0029] [ Figure 4]

[0030] Figure 4 FIG2 is a schematic diagram showing a second structural example of a CMOS image sensor.

[0031] [ Figure 5 ]

[0032] Figure 5 is a schematic diagram showing a third structural example of the CMOS image sensor.

[0033] [ Figure 6 ]

[0034] Figure 6 is a diagram showing a fourth structural example of a CMOS image sensor.

[0035] [ Figure 7 ]

[0036] Figure 7 is a schematic diagram showing a circuit configuration example of a pixel of a CMOS image sensor according to a second embodiment of the present disclosure.

[0037] [ Figure 8 ]

[0038] Figure 8 1 and 2 are views showing an example of the layout of each portion of a CMOS image sensor according to the third embodiment.

[0039] [ Figure 9 ]

[0040] Figure 9 From the wiring layer side Figure 8 A plan view of a first structural example of a pixel area in FIG.

[0041] [ Figure 10 ]

[0042] Figure 10 Including along Figure 9 The cross-sectional view cut along A-A' Figure 9 A cross-sectional view obtained by cutting along line BB'.

[0043] [ Figure 11 ]

[0044] Figure 11 For the purpose of illustrating the manufacturing Figure 9 and Figure 10 Schematic diagram of the method for a semiconductor substrate.

[0045] [ Figure 12 ]

[0046] Figure 12 For the purpose of illustrating the manufacturing Figure 9 and Figure 10 Schematic diagram of the method for a semiconductor substrate.

[0047] [ Figure 13 ]

[0048] Figure 13 For the purpose of illustrating the manufacturing Figure 9 and Figure 10 Schematic diagram of the method for a semiconductor substrate.

[0049] [ Figure 14 ]

[0050] Figure 14 For the purpose of illustrating the manufacturing Figure 9 and Figure 10 Schematic diagram of the method for a semiconductor substrate.

[0051] [ Figure 15 ]

[0052] Figure 15 For the Figure 9 A-A' cut Figure 8 A cross-sectional view of a second structural example of the pixel area in FIG.

[0053] [ Figure 16 ]

[0054] Figure 16 For the purpose of illustrating the manufacturing Figure 15 Schematic diagram of the method for a semiconductor substrate.

[0055] [ Figure 17 ]

[0056] Figure 17 For the purpose of illustrating the manufacturing Figure 15 Schematic diagram of the method for a semiconductor substrate.

[0057] [ Figure 18 ]

[0058] Figure 18 For the purpose of illustrating the manufacturing Figure 15 Schematic diagram of the method for a semiconductor substrate.

[0059] [ Figure 19 ]

[0060] Figure 19 For the purpose of illustrating the manufacturing Figure 15 Schematic diagram of the method for a semiconductor substrate.

[0061] [ Figure 20 ]

[0062] Figure 20 For the Figure 9 A-A' cut Figure 8A cross-sectional view of another second structure example of the pixel area.

[0063] [ Figure 21 ]

[0064] Figure 21 For the Figure 9 A-A' cut Figure 8 A cross-sectional view of a third structural example of the pixel area in FIG.

[0065] [ Figure 22 ]

[0066] Figure 22 For the purpose of illustrating the manufacturing Figure 21 Schematic diagram of the method for a semiconductor substrate.

[0067] [ Figure 23 ]

[0068] Figure 23 For the purpose of illustrating the manufacturing Figure 21 Schematic diagram of the method for a semiconductor substrate.

[0069] [ Figure 24 ]

[0070] Figure 24 Schematic diagram showing another structural example of the hollow region between the FD wiring and the semiconductor substrate.

[0071] [ Figure 25 ]

[0072] Figure 25 For the purpose of illustrating the manufacturing Figure 8 Schematic diagram of the first approach in a CMOS image sensor.

[0073] [ Figure 26 ]

[0074] Figure 26 For the purpose of illustrating the manufacturing Figure 8 Schematic diagram of the first approach in a CMOS image sensor.

[0075] [ Figure 27 ]

[0076] Figure 27 For the purpose of illustrating the manufacturing Figure 8 Schematic diagram of the first approach in a CMOS image sensor.

[0077] [ Figure 28 ]

[0078] Figure 28 For the purpose of illustrating the manufacturing Figure 8 Schematic diagram of the second method of the CMOS image sensor.

[0079] [ Figure 29 ]

[0080] Figure 29 For the purpose of illustrating the manufacturing Figure 8 Schematic diagram of the second method of the CMOS image sensor.

[0081] [ Figure 30 ]

[0082] Figure 30 For the purpose of illustrating the manufacturing Figure 8 Schematic diagram of the second method of the CMOS image sensor.

[0083] [ Figure 31 ]

[0084] Figure 31 For the purpose of illustrating the manufacturing Figure 8 Schematic diagram of the second method of the CMOS image sensor.

[0085] [ Figure 32 ]

[0086] Figure 32 Schematic diagram showing other structural examples of the hollow region around a through silicon via (TSV).

[0087] [ Figure 33 ]

[0088] Figure 33 is a plan view for explaining the arrangement of hollow regions of a CMOS image sensor according to a fourth embodiment.

[0089] [ Figure 34 ]

[0090] Figure 34 To show Figure 33 Schematic diagram of examples of other shapes of the hollow area around the FD wiring.

[0091] [ Figure 35 ]

[0092] Figure 35 FIG2 is a plan view showing an example of the shape of a hollow region formed around a TSV.

[0093] [ Figure 36 ]

[0094] Figure 36 : is a block diagram showing a configuration example of an image capturing device as an electronic device according to the present disclosure.

[0095] [ Figure 37 ]

[0096] Figure 37FIG2 is a schematic diagram showing an example of using the above-mentioned CMOS image sensor. DETAILED DESCRIPTION

[0097] Hereinafter, a mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described. The description will be made in the following order.

[0098] 1. First embodiment: CMOS image sensor ( Figures 1 to 6 )

[0099] 2. Second embodiment: CMOS image sensor ( Figure 7 )

[0100] 3. Third embodiment: CMOS image sensor ( Figures 8 to 32 )

[0101] 4. Fourth embodiment: CMOS image sensor ( Figures 33 to 35 )

[0102] 5. Fifth embodiment: electronic device ( Figure 36 )

[0103] 6. Examples of CMOS image sensors used ( Figure 37 )

[0104] <First embodiment>

[0105] (Configuration Example of CMOS Image Sensor According to First Embodiment)

[0106] Figure 1 2 is a schematic diagram showing a configuration example of a CMOS image sensor as a solid-state image capturing element according to the first embodiment of the present disclosure.

[0107] The CMOS image sensor 50 includes a pixel area 51, a pixel drive line 52, a vertical signal line 53, a vertical drive unit 54, a column processor 55, a horizontal drive unit 56, a system controller 57, a signal processor 58, and a memory unit 59, all of which are formed on a semiconductor substrate (chip) (such as a silicon substrate) not shown.

[0108] The pixel region 51 of the CMOS image sensor 50 includes pixels arranged two-dimensionally in an array shape. Each pixel has a photoelectric conversion element that generates an amount of charge corresponding to the amount of incident light. These charges are accumulated within the photoelectric conversion element, allowing the CMOS image sensor 50 to capture an image. Furthermore, in the pixel region 51, pixel drive lines 52 are formed for each row of pixels arranged in an array shape, and vertical signal lines 53 are formed for each column.

[0109] The vertical drive unit 54 includes a shift register, an address decoder, or any other unit, and drives each pixel of the pixel area 51 in units of rows. One end of the pixel drive line 52 is connected to an output terminal (not shown) corresponding to each row of the vertical drive unit 54. Although the detailed configuration of the vertical drive unit 54 is not shown, the vertical drive unit 54 has two scanning systems: a readout scanning system and a sweep scanning system.

[0110] The readout scanning system sequentially selects each row to read pixel signals from each pixel in row units and outputs the selected signals from the output terminals connected to the pixel drive lines 52 of the selected rows. In this arrangement, the pixels of the rows selected by the readout scanning system are read as pixel signals, which are electrical signals of the charge accumulated in the photoelectric conversion elements. The readout scanning system supplies the pixel signals to the vertical signal lines 53.

[0111] The cleanup scanning system turns on a reset signal output from the output terminal of the pixel drive line 52 connected to each row to clear (reset) unnecessary charge from the photoelectric conversion element. By scanning the cleanup scanning system, a so-called electronic shutter operation is sequentially performed for each row. In this case, the electronic shutter operation discards the charge of the photoelectric conversion element and starts a new exposure (starting to accumulate charge).

[0112] The column processor 55 includes a signal processing circuit for each column of the pixel area 51. Each signal processing circuit of the column processor 55 performs signal processing such as analog / digital (A / D) conversion processing on the pixel signal output from each pixel of the selected row through the vertical signal line 53. After this signal processing, the column processor 55 temporarily stores these pixel signals.

[0113] The horizontal driving unit 56 includes a shift register, an address decoder, or any other unit, and sequentially selects the signal processing circuits of the column processor 55. Based on the selective scanning of the horizontal driving unit 56, the pixel signals processed by each signal processing circuit of the column processor 55 are sequentially output to the signal processor 58.

[0114] The system controller 57 includes a timing generator or any other unit that generates various timing signals. Based on the timing signals generated by the timing generator, the system controller 57 controls the vertical driving unit 54, the column processor 55, and the horizontal driving unit 56.

[0115] The signal processor 58 performs various signal processing on the pixel signal output from the column processor 55. At this time, when necessary, the signal processor 58 stores the intermediate result of the signal processing in the memory unit 59 and refers to the memory unit 59 when necessary. After the signal processing, the signal processor 58 outputs the pixel signal.

[0116] The memory unit 59 includes a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0117] (Circuit Configuration Example of Pixel)

[0118] Figure 2 To show that Figure 1 Schematic diagram of an example of a circuit configuration of one pixel among pixels two-dimensionally arranged in a pixel area.

[0119] The pixel 90 has a photodiode 91 as a photoelectric conversion element, a transfer transistor 92 , an FD 93 , a reset transistor 94 , an amplifying transistor 95 , and a selection transistor 96 .

[0120] The photodiode 91 generates electric charge according to the amount of light received, and accumulates the electric charge. The anode terminal of the photodiode 91 is grounded, and has a cathode terminal connected to the FD 93 via the transfer transistor 92.

[0121] The gate terminal of the transfer transistor 92 is connected to one of the pixel drive lines 52 formed for the pixel 90 for supplying a transfer signal. When turned on by the transfer signal, the transfer transistor 92 reads out the charge generated by the photodiode 91 and transfers the charge to the FD 93.

[0122] The FD 93 holds the charge read from the photodiode 91. The gate terminal of the reset transistor 94 is connected to one of the pixel drive lines 52 formed for the pixel 90, and is used to supply a reset signal. When turned on by the reset signal, the reset transistor 94 discharges the charge accumulated in the FD 93 to the power supply 97 of the potential VDD, and resets the potential of the FD 93.

[0123] A gate terminal of the amplification transistor 95 is connected to the FD 93 , and the amplification transistor 95 outputs a pixel signal corresponding to the potential of the FD 93 by using a power supply 97 .

[0124] The gate terminal of the selection transistor 96 is connected to a line of the pixel drive line 52 formed for the pixel 90 for supplying a selection signal. When turned on by the selection signal, the selection transistor 96 supplies the pixel signal output from the amplifier transistor 95 to the vertical signal line 53. Figure 1 Column processor 55 in.

[0125] The FD 93 can be shared among a plurality of pixels 90 .

[0126] (First Structure Example of CMOS Image Sensor)

[0127] Figure 3 2 is a schematic diagram showing a first structural example of the CMOS image sensor 50 .

[0128] like Figure 3 As shown in FIG, the CMOS image sensor 50 includes a wiring layer 112 stacked on a semiconductor substrate 111 such as a silicon substrate. The wiring layer 112 includes, for example, five wiring layers 121 to 125.

[0129] On the semiconductor substrate 111, a photodiode 91, an FD 93, a power supply 97, etc. are formed. Between the photodiode 91 and the FD 93, a transfer transistor 92 is formed on the semiconductor substrate 111. An amplifier transistor 95 is connected to the power supply 97. Further, in the wiring layer 124, a vertical signal line 53 is formed.

[0130] The amplifier transistor 95 is connected to the FD wiring 132 formed in the wiring layer 122 via a through-hole 131 formed in the wiring layer 121. At the same time, the FD 93 is connected to the FD wiring 132 via a through-hole 131 formed in the wiring layer 121. With this arrangement, the amplifier transistor 95 is connected to the FD 93 via the through-hole 131 and the FD wiring 132.

[0131] The power supply 97 is connected to the wiring 133 formed in the wiring layer 122 through the through hole 131 formed in the wiring layer 121. The transfer transistor 92 is connected to the TRG wiring 134 formed in the wiring layer 122 through the through hole 131 formed in the wiring layer 121.

[0132] In the areas where wiring is not formed in the wiring layers 121 to 125, a wiring interlayer film 130 such as a SiO film is formed. Figure 3 In the example shown in FIG. 1 , the area around the FD wiring 132 (this area includes the entire area between the FD wiring 132 and the adjacent wiring 133 and between the FD wiring 132 and the adjacent TRG wiring 134, which are formed in the wiring layer 122 other than the FD wiring 132) is a hollow area 135. The FD wiring 132 and the hollow area 135 are in contact with each other.

[0133] When the interlayer wiring film 130 is a SiO film, the dielectric constant of the hollow region (air) 135 is 1 / 4 times that of the interlayer wiring film 130. Therefore, by forming the hollow region 135, the capacitance of the FD wiring 132 is reduced to approximately 1 / 4 of the capacitance of the FD wiring 132 in the case where the hollow region 135 is formed.

[0134] Furthermore, since the wiring interlayer film 130 is formed in the region other than the hollow region 135 in the wiring layer 122 , the mechanical strength is higher than in a case where the wiring interlayer film 130 is not formed in the entire wiring layer 122 .

[0135] (Second Structure Example of CMOS Image Sensor)

[0136] Figure 4 2 is a schematic diagram showing a second structural example of the CMOS image sensor 50 .

[0137] exist Figure 4 In the configuration shown, Figure 3 Components that are identical to those in the drawings are marked with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0138] Figure 4 The structure of the CMOS image sensor 50 is similar to Figure 3 The difference in the structure is that hollow areas 201 to 206 are formed instead of the hollow area 135.

[0139] exist Figure 4 In the example, hollow areas 201 to 206 are formed in the area around the FD wiring 132 (including the entire area between the FD wiring 132 and the wiring 133 and between the FD wiring 132 and the TRG wiring 134) so ​​as not to contact the FD wiring 132, the wiring 133 and the TRG wiring 134.

[0140] (Third Structure Example of CMOS Image Sensor)

[0141] Figure 5 2 is a diagram showing a third structural example of the CMOS image sensor 50 .

[0142] exist Figure 5 In the configuration shown, Figure 3 Components that are identical to those in the drawings are marked with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0143] Figure 5 The structure of the CMOS image sensor 50 is similar to Figure 3 The difference in the structure is that a hollow area 221 is formed instead of the hollow area 135.

[0144] exist Figure 5 In the example, the area around the FD wiring 132 (including only the area between the FD wiring 132 and the wiring 133 , excluding the entire area between the FD wiring 132 and the wiring 133 and between the FD wiring and the TRG wiring 134 ) is the hollow area 221 .

[0145] That is, because the FD wiring 132 processes analog signals, it is less resistant to noise than wiring that processes digital signals, such as the vertical signal line 53. Therefore, it is desirable to reduce the capacitance between the wiring 133, which becomes a noise source due to its connection to the power supply 97, and the wiring 132. However, in some cases, it is better to maintain the capacitance between the TRG wiring 134 and the FD wiring 132.

[0146] Therefore, in Figure 5 In the example shown in FIG, the area around the FD wiring (including only the area between the FD wiring 132 and the adjacent wiring 133 and the area between the FD wiring 132 and the adjacent TRG wiring 134) is set as the hollow area 221. In other words, of the area between the FD wiring 132 and the adjacent wiring 133 and the area between the FD wiring 132 and the adjacent TRG wiring 134, the area other than the area between the FD wiring 132 and the TRG wiring 134 becomes the hollow area 221.

[0147] As a result, the propagation of noise through the capacitance between the FD wiring 132 and the wiring 133 that becomes a noise source can be suppressed. Furthermore, the capacitance between the TRG wiring 134 and the FD wiring 132 can be maintained.

[0148] like Figure 5 As shown in , the hollow region 221 may be in contact with the FD wiring 132 and the wiring 133 , or may not be in contact with the FD wiring 132 and the wiring 133 .

[0149] (Fourth Configuration Example of CMOS Image Sensor)

[0150] Figure 6 2 is a diagram showing a fourth structural example of the CMOS image sensor 50 .

[0151] exist Figure 6 In the configuration shown in Figure 3 Components that are identical to those in the drawings are marked with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0152] Figure 6 The structure of the CMOS image sensor 50 is similar to Figure 3 The structure in FIG. 1 is different in that in addition to the hollow area 135 , a hollow area 241 is also formed.

[0153] exist Figure 6 In the example, the entire area around the vertical signal line 53 is the hollow area 241.

[0154] That is, when the number of vertical signal lines 53 is large, high-speed driving can be performed, but the wiring density increases, and the capacitance of the vertical signal lines 53 increases. As a result, the response deteriorates, the variation of the pixel signal increases, and the image quality of the captured image deteriorates. Therefore, in Figure 6 In the example of FIG, the entire area around the vertical signal line 53 serves as the hollow area 241. With this arrangement, the capacitance of the vertical signal line 53 can be reduced. As a result, the image quality of the captured image can be improved by suppressing the change of the pixel signal during high-speed driving.

[0155] exist Figure 6 In the example, although the entire area around the vertical signal line 53 is the hollow area 241, only a portion of the area around the vertical signal line 53 may be the hollow area 241. Further, the hollow areas 201 to 206 or the hollow area 221 may be formed instead of the hollow area 135.

[0156] Furthermore, if Figure 6 As shown in , the hollow area 241 may or may not be in contact with the wiring adjacent to the vertical signal line 53 .

[0157] As described above, in the CMOS image sensor 50, at least a portion of the region between the FD wiring 132 and the wiring 133, and between the FD wiring 132 and the TRG wiring 134, is the hollow region 135 (201 to 206, or 221). Therefore, the capacitance of the FD wiring 132 can be reduced, and the charge-voltage conversion efficiency can be improved without changing the wiring layout.

[0158] Further, since there is no need to change the wiring layout, any system can be used as a system for sharing the pixels of the CMOS image sensor 50 .

[0159] In the regions of the wiring layers 121 to 125 , unlike the wirings and the hollow region 135 ( 201 to 206 , 221 , and / or 241 ), a low dielectric constant film may be formed instead of the wiring interlayer film 130 .

[0160] <Second embodiment>

[0161] (Circuit Configuration Example of Pixel of CMOS Image Sensor According to Second Embodiment)

[0162] The configuration of the CMOS image sensor as a solid-state image capturing element according to the second embodiment of the present disclosure is the same as that of the second embodiment except for the circuit configuration of each pixel two-dimensionally arranged in the pixel area 51 and the operation of the sweep scanning system. Figure 1 The configuration of the CMOS image sensor shown in FIG is the same. Therefore, below, only the circuit configuration of each pixel and the operation of the clear scanning system will be described. Figure 1The reference numerals in describe configuration elements different from those of pixels of a CMOS image sensor.

[0163] Figure 7 is a schematic diagram showing a circuit configuration example of a pixel of a CMOS image sensor according to a second embodiment of the present disclosure.

[0164] exist Figure 7 In the configuration shown, Figure 3 Components that are identical to those in the drawings are marked with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0165] Figure 7 The circuit configuration of the pixel 300 is different from Figure 2 The circuit configuration of pixel 90 in FIG. 1 is that FDs 301 and 302 are provided instead of FD 93, and reset transistors 303 and 304 are provided instead of reset transistor FD 94. By switching the reset transistor 304 of pixel 300 between on and off states, the imaging mode can be switched between a high charge-to-voltage conversion efficiency mode and a low charge-to-voltage conversion efficiency mode.

[0166] Specifically, in the pixel 300 , the gate terminal of the amplifier transistor 95 is connected to the FD 301 , and between the power supply 97 and the FD 301 , the reset transistor 303 and the reset transistor 304 are connected in series via the FD 302 .

[0167] Different lines in the pixel drive lines 52 in the corresponding rows are connected to the gate terminals of the reset transistor 303 and the reset transistor 304. Different reset signals are supplied to these gate terminals via different lines. The reset signal to be supplied to the reset transistor 303 is turned on by the clearing scanning system of the vertical drive unit 54 to clear unnecessary charge from the photodiode 91.

[0168] When the image capture mode is the low charge-voltage conversion efficiency mode, the reset signal supplied to the reset transistor 304 is always kept on by the clear scan system. Therefore, in this case, when the reset signal supplied to the reset transistor 303 is turned on, the potential of the FD 301 becomes the potential VDD of the power supply 97, and the capacitance of the FD of the pixel 300 becomes only the capacitance of the FD 301. As a result, the charge-voltage conversion efficiency becomes high.

[0169] On the other hand, when the image capture mode is the low charge-voltage conversion efficiency mode, the reset signal supplied to the reset transistor 304 is always kept off by the clear scan system. Therefore, in this case, when the reset signal supplied to the reset transistor 303 is turned on, the potential of the FD 302 becomes the potential VDD of the power supply 97, and the capacitance of the FD in the pixel 300 becomes the sum of the capacitances of the FD 301 and FD 302. Consequently, the charge-voltage conversion efficiency becomes low.

[0170] In the pixel 300 configured as described above, the ratio of the charge-voltage conversion efficiency in the high charge-voltage conversion efficiency mode to the charge-voltage conversion efficiency in the low charge-voltage conversion efficiency mode (hereinafter referred to as the mode ratio) is determined based on the ratio of the capacitance of FD301 to the sum of the capacitances of FD301 and FD302. The capacitance of FD301 and the capacitance of FD302 contribute to the capacitance of the FD wiring connected to FD301 (not shown) and the capacitance of the FD wiring connected to FD302 (not shown), respectively.

[0171] Therefore, in the pixel 300, to obtain a desired mode ratio, a hollow area similar to the hollow area 135 (201 to 206 or 221) is formed around, for example, the FD wiring connected to FD301 of the two FD wirings independently connected to FD301 and FD302.

[0172] That is, as described above, by forming a hollow area around the FD wiring, the capacitance of the FD wiring can be reduced compared to a case where the hollow area is not formed. Therefore, the hollow area is formed so that the capacitance of the FD wiring connected to FD301 becomes the capacitance of the FD wiring corresponding to the capacitance of FD301, which is determined based on the capacitance of FD302 and the desired mode ratio.

[0173] The hollow area may be formed only around the FD wiring connected to FD302 or around two FD wirings connected to FD301 and FD302. Furthermore, FD301 and FD302 may be shared among a plurality of pixels 300.

[0174] As described above, in the CMOS image sensor according to the second embodiment, two FDs, FD301 and FD302, are formed. FD wiring lines are connected to FD301 and FD302. A hollow region is formed around at least one of these FD wiring lines. This arrangement reduces the capacitance of the FD wiring line with the hollow region compared to the capacitance of the FD wiring line without the hollow region. As a result, the mode ratio can be set to a desired ratio.

[0175] On the other hand, if this hollow area is not formed around the FD wiring connecting FD301 and FD302, the mode ratio must be adjusted through wiring layout. However, when the pixel size is small, the degree of freedom in wiring layout is low. Furthermore, the shared system of pixels 300 imposes limitations on wiring layout. Therefore, adjusting the mode ratio through wiring layout is difficult.

[0176] <Third embodiment>

[0177] (Layout Example of Each Section of a CMOS Image Sensor)

[0178] The configuration of a CMOS image sensor as a solid-state image capturing element according to a third embodiment of the present disclosure is similar to Figure 1 The configuration of the CMOS image sensor 50 shown in FIG is the same as that of FIG. Therefore, the description of the configuration is omitted. Further, in the subsequent drawings, the same reference numerals are given to the components that are the same as those of the CMOS image sensor 50. Where appropriate, repeated descriptions are omitted.

[0179] Figure 8 1 and 2 are views showing a layout example of each portion of a CMOS image sensor according to a third embodiment.

[0180] according to Figure 8 In the CMOS image sensor 320, a semiconductor substrate 321 is stacked on a semiconductor substrate 322. A pixel region 51 is provided on the semiconductor substrate 321, and a control circuit 331 and a logic circuit 332 are provided on the semiconductor substrate 322. One or more wiring layers are stacked on each of the semiconductor substrates 321 and 322. The semiconductor substrate 321 is stacked on the semiconductor substrate 322 so that the wiring layers are bonded together.

[0181] For example, the control circuit 331 is a circuit including the vertical driving unit 54, the column processor 55, the horizontal driving unit 56, and the system controller 57. For example, the logic circuit 332 is a circuit including the signal processor 58 and the memory unit 59.

[0182] In this case, the number of layers of the semiconductor substrate of the CMOS image sensor 320 is 2, but may be 1 or 3 or more. Further, the control circuit 331 may be formed on the semiconductor substrate 321 on which the pixel region 51 is provided.

[0183] (First Structural Example of Semiconductor Substrate 321)

[0184] Figure 9 From the wiring layer side Figure 8 A plan view of a first structural example of the pixel region 51 in FIG. Figure 10 Including along Figure 9 The cross-sectional view cut along A-A' Figure 9 For the convenience of explanation, Figure 9 The semiconductor substrate 321 and only a lowermost wiring layer are shown, and Figure 10 The semiconductor substrate 321 and only the two lowermost wiring layers are shown.

[0185] like Figure 9 and 10 As shown in FIG, in the CMOS image sensor 320, two pixels 90 adjacent in the horizontal direction share the FD 93. Figure 10 As shown in FIG, in the lowermost wiring layer 351 of the pixel region 51 , an FD wiring 361 for connecting the source of the reset transistor 94 between the FD 93 and the gate of the amplification transistor 95 is formed.

[0186] like Figure 10 As shown in FIG, the FD wiring 361 is connected to the FD 93 through a via 361A, to the source of the reset transistor 94 formed on the semiconductor substrate 321 through a via 361B, and to the gate of the amplifying transistor 95 through a via 361C.

[0187] Furthermore, if Figure 9 As shown in FIG, the gate of the transfer transistor 92 is connected to a TRG wiring 362, which is a wiring configuring the pixel drive line 52. Figure 10 As shown in FIG, various wirings 363 are formed in the wiring layer 352 on the wiring layer 351.

[0188] like Figure 9 and 10 In the wiring layer 351, a plurality of (in Figure 10 Furthermore, a plurality of (4 in the example) hollow regions (air gaps) 364A are formed between the FD wiring 361 and the semiconductor substrate 321 having different potentials. Figure 10 In this example, it is 6) the hollow region 364B. Furthermore, in the region above the FD wiring 361 of the wiring layer 352, a plurality of hollow regions 364C are formed.

[0189] As described above, hollow regions 364A to 364C are formed between the FD wiring 361 and other wiring or electrodes of the semiconductor substrate 321. With this arrangement, the dielectric constant between the FD wiring 361 and other wiring or electrodes is reduced, and the capacitance of the FD wiring 361 is reduced. As a result, the charge-voltage conversion efficiency is improved.

[0190] Furthermore, the hollow region formed between the FD wiring and other wiring is configured not as a single hollow region but as multiple hollow regions 364A. Therefore, even when increasing the distance between the FD wiring 361 and other wiring to reduce the capacitance of the FD wiring 361, the size of the single hollow region can be reduced. As a result, the hollow region can be easily formed.

[0191] In the wiring layers 351 and 352, an insulating film 353 (interlayer wiring film) such as a SiO film is formed in regions where the FD wiring 361, the TRG wiring 362, and the wiring 363, the hollow regions 364A to 364C, and transistors such as the transfer transistor 92 are not formed. In the third embodiment, the material of the insulating film 353 is silicon dioxide, but is not limited to this material.

[0192] As described above, the insulating film 353 exists between the hollow regions 364A to 364C. Since the hollow regions 364A to 364C are supported by the insulating film 353, the capacitance of the FD wiring 361 can be reduced compared to the case where the hollow regions 364A to 364C are supported by a conductor.

[0193] (Description of Method for Manufacturing First Structural Example of Semiconductor Substrate 321)

[0194] Figures 11 to 14 A schematic diagram illustrating a method for manufacturing a semiconductor substrate 321 on which a plurality of Figure 9 and Figure 10 The wiring layer 351 and the wiring layer 352 in the .

[0195] First, in Figure 11 In the first process, the photodiode 91, the FD 93, and transistors configuring the pixel 90 (such as the transfer transistor 92, the reset transistor 94, and the amplifying transistor 95) are formed on the semiconductor substrate 321. Thereafter, the insulating film 353 is formed on the semiconductor substrate 321.

[0196] exist Figure 11 In the second process, a photoresist 381 is applied to the insulating film 353 in areas other than the area corresponding to the hollow area between the FD wiring 361 and the semiconductor substrate 321, thereby forming a photoresist pattern. This photoresist pattern is then used to etch the insulating film 353. As a result, the insulating film 353 is removed from areas where the photoresist 381 is not formed (i.e., areas corresponding to the hollow area 364B). By modifying this photoresist pattern, the size of the hollow area 364B can be controlled.

[0197] exist Figure 12In the third process, the photoresist pattern is peeled off, and the insulating film 353 is formed by a film forming method with weak coverage. As a result, a hollow area 364B is formed between the FD wiring 361 and the semiconductor substrate 321. Figure 12 In the fourth process in , in the insulating film 353 , the wiring 361 and the through-holes 361A to 361C are formed by the damascene method so that the FD 93 is connected to the source of the reset transistor 94 and the gate of the amplifying transistor 95 .

[0198] exist Figure 13 In the fifth process, a photoresist pattern is formed on the insulating film 353 by applying a photoresist 381 to the region other than the region corresponding to the hollow region 364A between the FD wiring 361 and other wiring not shown in the wiring layer 351 (where the FD wiring 361 is formed). The insulating film 353 is then etched using this photoresist pattern. As a result, the insulating film 353 is removed from the region where the photoresist 381 is not formed (i.e., the region corresponding to the hollow region 364A).

[0199] exist Figure 13 In the sixth process, the photoresist pattern is peeled off and the insulating film 353 is formed by a film forming method with weak coverage. As a result, the hollow region 364A is formed. Figure 14 In the seventh process, the wiring 363 of the wiring layer 352 is formed by the damascene method.

[0200] exist Figure 14 In the eighth process, first, Figure 11 The second treatment in Figure 12 The third process in Figure 13 The hollow region 364C above the FD wiring 361 is formed in a similar manner to the fifth and sixth processes.

[0201] Specifically, a photoresist pattern is formed on the insulating film 353 by applying a photoresist 381 to the region other than the region corresponding to the hollow region 364C above the FD wiring 361. This photoresist pattern is then used to etch the insulating film 353. As a result, the insulating film 353 is removed from the region corresponding to the hollow region 364C. The photoresist pattern is then peeled off, and the insulating film 353 is formed using a weak coverage film formation method.

[0202] Figure 11 In the second processing, Figure 13 The fifth processing of Figure 14 The thickness (length in the direction perpendicular to the semiconductor substrate 321) of the insulating film 353 to be etched in the eighth process, that is, the thickness of each of the hollow regions 364A to 364C is less than several tenths of a micrometer.

[0203] As described above, because the insulating film 353 above the hollow regions 364A to 364C is formed by a film forming method with weak coverage, the insulating film 353 can be formed above the hollow regions 364A to 364C while maintaining the cavities of the hollow regions 364A to 364C. The quality of the insulating film 353 below the hollow regions 364A to 364C may be the same as or different from the quality of the insulating film 353 above the hollow regions 364A to 364C.

[0204] (Second Structural Example of Semiconductor Substrate 321)

[0205] Figure 15 For the Figure 9 A-A' cut Figure 8 5 is a cross-sectional view of a second structural example of the pixel region 51 of the semiconductor substrate 321. Figure 15 The semiconductor substrate 321 and only the two lowermost wiring layers are shown.

[0206] exist Figure 15 In the configuration shown in Figure 10 Components that are identical to those in the drawings are marked with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0207] Figure 15 The configuration of the semiconductor substrate 321 on which the wiring layer 351 and the wiring layer 352 are stacked is different from that of Figure 10 The configuration in FIG. 3 is that the barrier film 401 is formed so as to be in contact with the FD wiring 361 and the bottom surface of the hollow region 364A.

[0208] The stopper film 401 is a film such as a SiOC film for preventing etching of the insulating film 353 when the FD wiring 361 is formed by the damascene method.

[0209] (Description of Method for Manufacturing Second Structural Example of Semiconductor Substrate 321)

[0210] Figures 16 to 19 To illustrate the manufacture of Figure 15 Schematic diagram of a method of forming a semiconductor substrate 321 with wiring layers 351 and 362.

[0211] First, conduct Figure 11 and 12 The first to third processes are performed, and a hollow region 364B is formed between the FD wiring 361 and the semiconductor substrate 321. Figures 16 to 18 In the first to sixth processes, the FD wiring 361 and the through-holes 361A to 361C are formed by the damascene method.

[0212] That is, in Figure 16In the first process, the insulating film 353 is formed on the semiconductor substrate 321 on which the hollow region 364B is formed. Thereafter, the insulating film 353 is planarized.

[0213] exist Figure 16 In the second process, a barrier film 401 is formed on the insulating film 353. Figure 17 In the third process, on the barrier film 401, an insulating film 353 having a predetermined thickness is formed (stacked).

[0214] exist Figure 17 In the fourth process, the regions corresponding to the through-holes 361A to 361C of the insulating film 353 below the barrier film 401 are etched, and the regions corresponding to the FD wirings 361 of the insulating film 353 above the barrier film 401 are etched. The etching of the insulating film 353 above the barrier film 401 is stopped by the barrier film 401. That is, the bottom surface of the etched region of the insulating film 353 above the barrier film 401 is in contact with the upper surface of the barrier film 401.

[0215] exist Figure 18 In the fifth process, a copper (Cu) film 402 is formed on the uppermost insulating film 353. Figure 18 In the sixth process, unnecessary copper 402 over the insulating film 353 is removed. As a result, the FD wiring 361 and the through-holes 361A to 361C are formed.

[0216] Next, in Figure 19 In the seventh process, a photoresist pattern is formed on the insulating film 353 by applying a photoresist 381 to the region other than the region corresponding to the hollow region 364A between the FD wiring 361 and other wiring not shown in the wiring layer 351 (in which the FD wiring 361 is formed). The insulating film 353 is then etched using this photoresist pattern, with the etching being stopped by the stopper film 401. As a result, the insulating film 353 is removed from the region where the photoresist 381 is not formed (i.e., the region corresponding to the hollow region 364A).

[0217] Afterwards, proceed Figure 13 and Figure 14 The sixth to eighth processes are performed to form the hollow area 364A and the hollow area 364C.

[0218] With this arrangement, the bottom surfaces of all hollow regions 364A are in contact with the upper surface of the barrier film 401. That is, the bottom surfaces of all hollow regions 364A are positioned uniformly in the thickness direction. Consequently, variations in the depth (length in a direction perpendicular to the semiconductor substrate) of the hollow regions 364A are minimized. Consequently, variations in the capacitance of the FD wiring 361 are minimized.

[0219] exist Figure 19In the seventh process, after the etching of the insulating film 353 is stopped by the stopper film 401, further etching can be performed, such as Figure 20 As shown in .

[0220] (Third Structural Example of Semiconductor Substrate 321)

[0221] Figure 21 For the Figure 9 A-A' cut Figure 8 3 is a cross-sectional view of a third structural example of the pixel region 51 of the semiconductor substrate 321. Figure 21 The semiconductor substrate 321 and only the two lowermost wiring layers are shown.

[0222] exist Figure 21 In the configuration shown in Figure 10 Components that are identical to those in the drawings are marked with the same reference numerals, and repeated descriptions are omitted where appropriate.

[0223] Figure 21 The configuration of the semiconductor substrate 321 on which the wiring layer 351 and the wiring layer 352 are stacked is different from that of Figure 10 The configuration is that the lower parts of four continuous hollow areas 364A are connected together, and the insulating film around the upper part of the hollow area 364A is an insulating film 421, whose material is different from the material of the insulating film 353.

[0224] For example, the material of the insulating film 421 is SiN.

[0225] (Description of Method for Manufacturing the Third Structural Example of the Semiconductor Substrate 321)

[0226] Figure 22 and 23 To illustrate the manufacture of Figure 21 Schematic diagram of the method of wiring layer 351 and wiring layer 352 in FIG.

[0227] First, conduct Figure 11 and 12 The first to third processes are performed, and a hollow region 364B is formed between the FD wiring 361 and the semiconductor substrate 321. Figure 22 In the first process, the insulating film 421 is formed on the insulating film 353. Thereafter, the FD wiring 361 and the through holes 361A to 361C are formed in the insulating film 353 and the insulating film 421 so as to be in contact with the FD 93 by a damascene method.

[0228] Next, in Figure 22 In the second process, a photoresist pattern is formed on the insulating film 421 by applying the photoresist 381 in a region other than the region corresponding to the hollow region 364A.

[0229] Thereafter, the insulating film 353 and the insulating film 421 are etched using the photoresist pattern. As a result, the insulating film 353 and the insulating film 421 are removed from the region where the photoresist 381 is not formed (ie, the region corresponding to the hollow region 364A).

[0230] exist Figure 23 In the third process, isotropic etching of the insulating film 353 and the insulating film 421 is performed under the condition that the etching rate of the insulating film 353 becomes greater than the etching rate of the insulating film 421. As a result, only the insulating film 353 is etched, and the lower portions of the four hollow regions 364A are connected together.

[0231] exist Figure 23 In the fourth process, the photoresist pattern is stripped and the insulating film 353 is formed by a film forming method with weak coverage. In this case, although the lower portion of the hollow region 364A has a large size, the upper portion has a small size. Therefore, before the material of the insulating film 353 reaches the lower portion, the hollow region 364A is closed. As a result, the cavity of the hollow region 364A is maintained. After that, Figure 14 The seventh and eighth processes are performed, and a hollow area 364C is formed.

[0232] like Figure 24 As shown in FIG, in a manner similar to that applied to the hollow region 364A, the insulating film 421 may be formed around the upper portion of the hollow region 364B, and the lower portions of the hollow regions 364B may be connected together. Further, the size of the lower portion of each of the hollow regions 364A to 364C may be larger than the size of the upper portion of each of the hollow regions 364A to 364C, and the respective lower portions of the hollow regions 364A to 364C are not connected together.

[0233] (First Method of Manufacturing a CMOS Image Sensor)

[0234] Figures 25 to 27 For the purpose of illustrating the manufacturing Figure 8 Schematic diagram of a first method of a CMOS image sensor 320 is shown in FIG. Figures 11 to 14 The semiconductor substrate 321 manufactured by the method in the embodiment of the present invention is bonded to a semiconductor substrate 322 to manufacture the CMOS image sensor 320 .

[0235] In passing Figures 11 to 14 After the semiconductor substrate 321 on which the wiring layers 351 and 352 are stacked is manufactured by the manufacturing method in the above, the wiring layer 431 is further stacked on the semiconductor substrate 321. Figure 25In the first process, a photoresist pattern is formed on the insulating film 353 of the wiring layer 352 by applying a photoresist 381 around the area other than the pixel area 51 where the TSV 452 is to be formed. Thereafter, the insulating film 353 is etched using this photoresist pattern. With this arrangement, the insulating film 353 is removed from the area where the photoresist 381 is not formed (i.e., the area around the area where the TSV 452 is to be formed).

[0236] exist Figure 25 In the second process, the photoresist pattern is peeled off, and the insulating film 353 is formed by a weak coverage film forming method. As a result, a hollow region 432 is formed in a region around a region where the TSV 452 (connection portion) is to be formed.

[0237] exist Figure 26 In the third process, the semiconductor substrate 321 and the semiconductor substrate 322 are bonded together.

[0238] Specifically, in Figure 26 In the example of FIG. 3 , four wiring layers 441 to 444 in which respective wirings 440 are formed are stacked on the semiconductor substrate 322 . An insulating film 445 is formed in regions where the wirings 440 and the like are not formed in the wiring layers 441 to 444 .

[0239] The wiring 440 of the uppermost wiring layer 444 is made of, for example, aluminum (Al). The wiring 440 of the wiring layers 441 to 443 other than the uppermost layer is made of, for example, copper (Cu). The semiconductor substrate 321 is bonded to the semiconductor substrate 322 so that the uppermost wiring layer 431 of the semiconductor substrate 321 is bonded to the uppermost wiring layer 444 of the semiconductor substrate 322.

[0240] After the semiconductor substrate 321 and the semiconductor substrate 322 are bonded together, an insulating film 451 is formed on the surface facing the surface of the wiring layer 351 on which the semiconductor substrate 321 is stacked. Furthermore, color filters, on-chip lenses, and the like (not shown) are formed in the region corresponding to the pixel region 51 on the surface facing the surface of the wiring layer 351 on which the semiconductor substrate 321 is stacked. Furthermore, after bonding, the semiconductor substrate 321 and the semiconductor substrate 322 are thinned. With this arrangement, the CMOS image sensor 320 is formed to a desired thickness.

[0241] Next, in Figure 27 In the fourth process, the insulating film 451, the semiconductor substrate 321, the insulating film 353, and the region of the insulating film 445 where the TSV 452 is to be formed are etched, and the TSV 452 is formed. The TSV 452 is connected to the wiring 440 of the wiring layer 444 and the wiring 363 of the wiring layer 351, so that the semiconductor substrate 321 and the semiconductor substrate 322 are electrically connected to each other.

[0242] (Second Method of Manufacturing CMOS Image Sensor)

[0243] Figures 28 to 31 For the purpose of illustrating the manufacturing Figure 8 A schematic diagram of a second method of a CMOS image sensor 320 in which the sensor is formed by Figures 11 to 14 The semiconductor substrate 321 manufactured by the method is bonded to the semiconductor substrate 322.

[0244] In passing Figures 11 to 14 After the semiconductor substrate 321 on which the wiring layer 351 and the wiring layer 352 are stacked is manufactured by the manufacturing method in the above, the wiring layer 431 is further stacked. Figure 28 In the first process, the semiconductor substrate 321 and the semiconductor substrate 322 are bonded together so that the uppermost wiring layer 352 of the semiconductor substrate 321 and the uppermost wiring layer 442 of the semiconductor substrate 322 are bonded together.

[0245] After the semiconductor substrate 321 and the semiconductor substrate 322 are bonded together, an insulating film 451 is formed on the surface facing the wiring layer 351 on which the semiconductor substrate 321 is stacked. Furthermore, in the region corresponding to the pixel region 51 on the surface facing the wiring layer 351 on which the semiconductor substrate 321 is stacked, color filters, on-chip lenses, and the like (not shown) are formed. Furthermore, after bonding, the semiconductor substrate 321 and the semiconductor substrate 322 are thinned. With this arrangement, the CMOS image sensor 320 is formed to a desired thickness.

[0246] exist Figure 29 In the second process, a photoresist pattern is formed on the insulating film 451 by applying a photoresist 381 in the area around the region where the TSV 452 is to be formed in the non-pixel region 51. Then, the semiconductor substrate 321, the insulating film 451, and the insulating film 353 are etched using this photoresist pattern. With this arrangement, the semiconductor substrate 321, the insulating film 451, and the insulating film 353 are removed from the area where the photoresist 381 is not formed (i.e., the area around the region where the TSV 452 is to be formed).

[0247] exist Figure 30 In the third process, the photoresist pattern is stripped, and the insulating film 451 is formed by a weak coverage film forming method. As a result, a hollow region 432 penetrating the semiconductor substrate 321 is formed in a region around the region where the TSV 452 is to be formed.

[0248] exist Figure 31In the fourth process, the region of the insulating film 451, the semiconductor substrate 321, the insulating film 353, and the insulating film 445 where the TSV 452 is to be formed is etched, and the TSV 452 is formed.

[0249] like Figure 32 As shown in FIG, in the third process, when forming the insulating film 451, the insulating film 451 can be buried in the hollow region 432 in the semiconductor substrate 321. Further, the TSV 452 can connect the wiring 440 of the wiring layer 444 to the wiring 363 of the wiring layer 351 through one or two through holes.

[0250] As described above, by forming the hollow region 432 around the TSV 452 , the capacitance between the TSV 452 and the potential portion (eg, GND) of the semiconductor substrate 321 may be reduced.

[0251] In the third embodiment, the number of hollow regions 364A to 364C and hollow region 432 may be any number equal to or greater than 1. The hollow regions 364A to 364C and hollow region 432 may have any shape in which an insulating film is not formed by a film forming method with weak coverage.

[0252] <Fourth embodiment>

[0253] (Description of the arrangement of the hollow area in the pixel area)

[0254] Except that the CMOS image sensor in the fourth embodiment has an FD 93 shared between 2 (horizontal) × 2 (vertical) pixels 90 and the arrangement and shape of the hollow areas 364A to 364C are different from those of the hollow area 432, the configuration and structure of the CMOS image sensor as a solid-state image capturing element according to the fourth embodiment of the present disclosure are the same as the configuration and structure of the CMOS image sensor 320.

[0255] Therefore, the following description only describes the arrangement and shape of the hollow regions 364A to 364C and the hollow region 432. Furthermore, in subsequent drawings, the same reference numerals are given to components identical to those of the CMOS image sensor 320. Where appropriate, repeated descriptions are omitted.

[0256] Figure 33 1 is a plan view for explaining the arrangement of hollow regions in the pixel region 51 of the CMOS image sensor according to the fourth embodiment. Figure 33 4 is a plan view of the pixel region 51 of the semiconductor substrate 321 on which the wiring layer 351 , the wiring layer 352 , and the wiring layer 431 are stacked, as viewed from the side where the wiring layer 431 is located.

[0257] Figure 33A in FIG shows only the semiconductor substrate 321 and the wiring layer 351, and Figure 33 B in FIG. 4 shows only the semiconductor substrate 321 and the wiring layer 431 .

[0258] like Figure 33 As shown in FIG. 1A , in the CMOS image sensor according to the fourth embodiment, a hollow region 472 is formed between the FD wiring 361 and other wirings such as the wiring 471 in the same wiring layer 351. With this arrangement, the dielectric constant between the FD wiring 361 and other wirings in the wiring layer 351 is reduced. As a result, the charge-voltage conversion efficiency is improved.

[0259] Furthermore, if Figure 33 As shown in FIG. 4B , in the wiring layer 431, a hollow area 474 is formed between the vertical signal line 53 and other wirings such as the wiring 473 in the same wiring layer 431. With this arrangement, the dielectric constant between the vertical signal line 53 and other wirings in the wiring layer 431 is reduced, and the capacitance of the vertical signal line 53 is reduced. As a result, it is possible to prevent a delay in reading pixel signals.

[0260] exist Figure 33 In the example A in FIG, two hollow regions 472 are formed between the FD wiring 361 and other wirings. The number of hollow regions 472 may be any number equal to or greater than one. Similarly, the number of hollow regions 474 formed between the vertical signal line 53 and other wirings may be any number equal to or greater than one.

[0261] exist Figure 33 In the example shown in FIG. 4 , each of the hollow regions 472 and 474 has a rectangular (strip-shaped) shape when viewed from above the wiring layer 431. However, each of the hollow regions 472 and 474 may have any shape.

[0262] (Shape example of the hollow area in the pixel area)

[0263] Figure 34 FIG4 is a plan view of the pixel region 51 of the semiconductor substrate 321 on which the wiring layer 352 is stacked, viewed from the side where the wiring layer 351 is located, illustrating another example of the shape of the hollow region 472 .

[0264] like Figure 34 As shown in A in FIG. 3 , each of the hollow regions 472 may be circular (hole-shaped) when viewed from above the wiring layer 351, or may be, for example, Figure 34 As shown in B in FIG, it can be in a mesh shape.

[0265] Although not shown, each of the hollow regions 474 may have the same shape as the hollow region 472 .

[0266] (Example of the shape of the hollow area in the non-pixel area)

[0267] Figure 35 4 is a plan view of the CMOS image sensor according to the fourth embodiment as viewed from above the insulating film 451 , illustrating a shape example of each hollow region 432 formed around the TSV 452 which is not a pixel region 51 of the CMOS image sensor.

[0268] like Figure 35 As shown in A in FIG. 4 , each hollow region 432 may be in the shape of a rectangular ring when viewed from above the insulating film 451, or in the shape of a rectangular ring, for example. Figure 35 As shown in B in FIG, it can be in a circular ring shape. Further, as Figure 35 As shown in C in FIG. 4 , each hollow area 432 may be in a straight line shape (strip shape).

[0269] exist Figure 35 In the examples A and C in FIG, the number of hollow regions 432 formed around the TSV 452 is two, and Figure 35 In the example of B in , the number is one. However, the number of hollow areas 432 is not limited to these numbers and may be any number.

[0270] The shapes of the hollow area 432, the hollow area 472, and the hollow area 474 are not limited to Figure 34 and Figure 35 The shape shown in , as long as the hollow region has a shape in which the insulating film is not formed by a film forming method with weak coverage.

[0271] Further, in the fourth embodiment, hollow regions may be formed in the lower and upper portions of the FD wiring 361 in a manner similar to that in the third embodiment.

[0272] Furthermore, in the third embodiment, a hollow region may be formed around the vertical signal line 53 in a manner similar to that in the fourth embodiment. In the third and fourth embodiments, the region in which the hollow region is formed may be formed around wiring other than the FD wiring 361 and the vertical signal line 53, the capacitance of which is desired to be reduced.

[0273] In the third and fourth embodiments, a hollow region may be formed in the semiconductor substrate 322 .

[0274] <Fifth embodiment>

[0275] (Configuration Example of Image Capturing Device According to One Embodiment)

[0276] Figure 361 is a block diagram showing a configuration example of an image capturing device as an electronic device according to one embodiment of the present disclosure.

[0277] Figure 36 The image capture device 1000 in the embodiment is a video camera, a digital still camera, or the like. The image capture device 1000 includes a lens group 1001, a solid-state image capture element 1002, a digital signal processing (DSP) circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus 1009.

[0278] The lens group 1001 captures light (image light) incident from a subject and forms an image on the image capture surface of the solid-state image capture element 1002. The solid-state image capture element 1002 includes the above-mentioned CMOS image sensor. The solid-state image capture element 1002 converts the amount of incident light (in units of pixels) that forms an image on the image capture surface through the lens group 1001 into an electrical signal and supplies the electrical signal to the DSP circuit 1003 as a pixel signal.

[0279] The DSP circuit 1003 performs predetermined image processing on the pixel signal supplied from the solid-state image capturing element 1002 , supplies the processed image signal in units of frames to the frame memory 1004 , and temporarily stores the image signal in the frame memory 1004 .

[0280] The display unit 1005 includes, for example, a flat-panel display device such as a liquid crystal panel or an organic electroluminescence (EL) panel, and displays an image based on pixel signals in units of frames temporarily stored in the frame memory 1004 .

[0281] The recording unit 1006 includes a digital versatile disk (DVD), a flash memory, or the like, reads out pixel signals in units of frames temporarily stored in the frame memory 1004, and records the pixel signals.

[0282] Under user operation, the operation unit 1007 issues operation instructions regarding various functions of the image capturing apparatus 1000. The power supply unit 1008 supplies power to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, and operation unit 1007 as appropriate.

[0283] Electronic devices to which this technology is applied can be devices that use CMOS image sensors in their image capture units (photoelectric conversion units). In addition to the image capture device 1000, this technology can be applied to portable terminal devices with image capture functions and copiers that use CMOS image sensors in their image reading units.

[0284] (Examples of CMOS image sensors used)

[0285] Figure 37 FIG2 is a schematic diagram showing a usage example of the above CMOS image sensor.

[0286] For example, as described above, the CMOS image sensor can be used in various situations, such as sensing visible light, infrared light, ultraviolet light, and X-ray light.

[0287] - A device provided for capturing images for viewing, such as a digital camera, and a mobile device having camera functionality.

[0288] - A device provided for traffic use, such as an on-vehicle sensor that takes pictures of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and for identifying the driver's status, a monitoring camera that monitors traveling vehicles and roads, and a distance measurement sensor that measures the distance between vehicles.

[0289] - A device provided for home appliances such as televisions, refrigerators, and air conditioners for photographing a user's gesture to operate the home appliance according to the gesture.

[0290] - An apparatus provided for medical treatment and health care, such as an endoscope and an apparatus for performing angiography by receiving infrared light.

[0291] - A device provided for security, such as a surveillance camera for crime prevention and a camera for personal identity verification.

[0292] - A device is provided for cosmetic use, such as a skin measurement device that captures skin images and a microscope that captures scalp images.

[0293] - A device provided for sports, such as a sports camera and a wearable camera for sports applications.

[0294] - A device provided for use in agriculture, such as a camera for monitoring the status of fields and crops.

[0295] The effects described in this specification are illustrative and not limiting. There are other effects.

[0296] Further, the embodiments of the present disclosure are not intended to be limited to the embodiments described above, and various modifications are possible without departing from the scope of the present disclosure.

[0297] The present disclosure may also be applied to charge coupled device (CCD) image sensors, rather than being limited to CMOS image sensors.

[0298] The present disclosure can also be configured as follows. (1)

[0300] A solid-state image capturing element in which at least a portion of a region between a floating diffusion wiring connected to a floating diffusion node and wirings other than the floating diffusion wiring is a hollow region. (2)

[0302] The solid-state image capturing element according to (1), wherein the floating diffusion wiring and the hollow region are in contact with each other. (3)

[0304] The solid-state image capturing element according to (1), wherein the floating diffusion wiring and the hollow region are not in contact with each other. (4)

[0306] A solid-state image capturing element according to one of (1) to (3) above, wherein the hollow area is an area between the floating diffusion wiring and the wiring other than the floating diffusion wiring, and an area other than the area between the floating diffusion wiring and the TRG wiring connected to the transfer transistor. (5)

[0308] The solid-state image capturing element according to one of (1) to (4) above, wherein at least a portion of the periphery of the vertical signal line is a hollow area. (6)

[0310] The solid-state image capturing element according to one of (1) to (5) above, wherein the floating diffusion wiring is one of a plurality of floating diffusion wirings individually connected to a plurality of floating diffusion nodes. (7)

[0312] The solid-state image capturing element according to (1) above, wherein the number of the hollow regions is plural. (8)

[0314] The solid-state image capturing element according to (1) or (7) above, wherein an insulating film is formed in a region other than the hollow region in a region between the floating diffusion wiring and the wiring other than the floating diffusion wiring. (9)

[0316] The solid-state image capturing element according to (8) above, wherein a material of the insulating film formed around an upper portion of the hollow region and a material of the insulating film formed around a lower portion of the hollow region are different. (10)

[0318] The solid-state image capturing element according to (9) above, wherein a size of a lower portion of the hollow region is larger than a size of an upper portion. (11)

[0320] The solid-state image capturing element according to (10) above, wherein the number of the hollow regions is plural, and lower portions of the plural hollow regions are connected together, and upper portions thereof are connected together. (12)

[0322] The solid-state image capturing element according to any one of (1) and (7) to (11) above, wherein at least a portion of a region between the floating diffusion wiring and a semiconductor substrate in contact with the floating diffusion wiring is a hollow region. (13)

[0324] The solid-state image capturing element according to any one of (1) and (7) to (11) above, comprising:

[0325] a first semiconductor substrate on which the floating diffusion wiring, the wirings other than the floating diffusion wiring, and a wiring layer in which the hollow region is formed are stacked;

[0326] a second semiconductor substrate bonded to the first semiconductor substrate; and

[0327] A connection portion electrically connects the first semiconductor substrate to the second semiconductor substrate, wherein a hollow area is formed around the connection portion of the wiring layer. (14)

[0329] The solid-state image capturing element according to (13) above, wherein the hollow region formed around the connection portion of the wiring layer penetrates the first semiconductor substrate. (15)

[0331] An electronic device, comprising:

[0332] A solid-state image capturing element in which at least a portion of a region between a floating diffusion wiring connected to a floating diffusion node and wirings other than the floating diffusion wiring is a hollow region. (16)

[0334] A solid-state image capturing element comprising:

[0335] a first semiconductor substrate;

[0336] a second semiconductor substrate bonded to the first semiconductor substrate; and

[0337] A connection portion electrically connects the first semiconductor substrate to the second semiconductor substrate, wherein a hollow area is formed around the connection portion of the wiring layer stacked on the first semiconductor substrate.

[0338] [Reference Symbol List]

[0339] 50CMOS image sensor, 53 vertical signal line, 92 transfer transistor, 93FD, 132FD wiring, 133 wiring, 134TRG wiring, 135, 201 to 206, 221, 241 hollow areas, 301, 302FD, 320CMOS image sensor, 321, 322 semiconductor substrate, 351, 352 wiring layer, 353 insulating film, 361FD wiring, 364A to 364C hollow areas, 421 insulating film, 432 hollow area, 452TSV, 1000 image capture device, 1002 solid-state image capture element.

Claims

1. A light detection device, comprising: a semiconductor substrate including a floating diffusion node; as well as A wiring layer, the wiring layer comprising: a first wiring connected to the floating diffusion node; a first hollow region; and The second hollow region, wherein the first hollow region, the first wiring, and the second hollow region are sequentially arranged in a specific direction such that in the specific direction, the first wiring is located between the first hollow region and the second hollow region.

2. The light detection device according to claim 1, wherein The specific direction is a horizontal direction.

3. The light detection device according to claim 1, wherein The specific direction is a vertical direction.

4. The light detection device according to claim 1, wherein The wiring layer further includes: a second wiring line that is different from the first wiring line; and The third hollow region, and The first wiring, the third hollow area, and the second wiring are sequentially arranged in a horizontal direction.

5. The light detection device according to claim 4, wherein The third hollow region includes at least a portion of the first region between the first wiring and the second wiring.

6. The light detection device according to claim 4, further comprising: pass transistor, where The wiring layer further includes: a third wiring connected to the transfer transistor; and a fourth hollow region, and The fourth hollow region includes at least a portion of the second region between the first wiring and the third wiring.

7. The light detection device according to any one of claims 1 to 3, wherein The first wiring does not contact each of the first hollow area and the second hollow area.

8. A light detection device comprising: a semiconductor substrate including a floating diffusion node; Amplifying transistors; as well as A wiring layer, the wiring layer comprising: a first wiring connecting the floating diffusion node and the amplifying transistor; and A first hollow region, wherein the first wiring, the first hollow region, and the amplifying transistor are sequentially arranged in a specific direction such that the first hollow region is located between the first wiring and the amplifying transistor in the specific direction.

9. The light detection device according to claim 8, wherein The specific direction is a horizontal direction.

10. The light detection device according to claim 8, wherein The specific direction is a vertical direction.

11. The light detection device according to claim 8, wherein The wiring layer further includes: a second wiring line that is different from the first wiring line; and a second hollow region, and The first wiring, the second hollow area, and the second wiring are sequentially arranged in a horizontal direction.

12. The light detection device according to claim 11, wherein The second hollow region includes at least a portion of a first region between the first wiring and the second wiring.

13. The light detection device according to claim 11, further comprising: pass transistor, where The wiring layer further includes: a third wiring connected to the transfer transistor; and a third hollow region, and The third hollow region includes at least a portion of the second region between the first wiring and the third wiring.

14. The light detection device according to any one of claims 8 to 10, wherein: The first wiring does not contact the first hollow area.

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