Epitaxial wafer preparation method, epitaxial wafer and ultraviolet light emitting diode

Abstract

The application discloses an epitaxial wafer preparation method, an epitaxial wafer and an ultraviolet light emitting diode. The epitaxial wafer preparation method comprises the following steps: providing a substrate; sequentially stacking a buffer layer and an N-type semiconductor layer on the substrate; sequentially and alternately stacking a preset number of quantum well layers and quantum barrier layers to form a multi-quantum well layer on the N-type semiconductor layer; sequentially stacking an electron blocking layer and a P-type semiconductor layer on the last quantum barrier layer; wherein a first quantum barrier sublayer, a second quantum barrier sublayer, an insertion sublayer and a third quantum barrier sublayer are sequentially stacked on the quantum well layer to form the quantum barrier layer; the quantum well layer, the first quantum barrier sublayer, the second quantum barrier sublayer and the third quantum barrier sublayer are all AlGaN layers; the insertion sublayer is an MgN layer; and the Al component content of the first quantum barrier sublayer and the third quantum barrier sublayer is lower than that of the second quantum barrier sublayer. By adopting the application, the problem of low internal quantum efficiency in the epitaxial wafer in the prior art can be solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing an epitaxial wafer, the epitaxial wafer, and an ultraviolet light-emitting diode. Background Technology

[0002] Ultraviolet (UV) LEDs generally refer to LEDs with a light-emitting center wavelength below 400nm. Due to their unique wavelength characteristics, they are widely used in biomedicine, anti-counterfeiting, purification (e.g., water and air purification), computer data storage, and military applications. Furthermore, with technological advancements, new applications will continuously emerge to replace existing technologies and products, giving UV LEDs an even broader market prospect. Therefore, developing higher-performance UV LEDs has become particularly important.

[0003] However, compared with GaN-based blue LEDs, the development of ultraviolet LEDs faces many unique technical challenges, such as: the higher the Al content, the lower the crystal quality, and the dislocation density is generally around 10. 9 ~10 10 / cm 2 Even higher levels of Al content make epitaxial growth of AlGaN materials difficult. Furthermore, doping AlGaN materials is much more difficult than doping GaN. Regardless of whether it is N-type or P-type doping, the conductivity of the epitaxial layer decreases rapidly with the increase of Al content. Doping of P-AlGaN is particularly challenging because the activation efficiency of its dopant Mg is low, resulting in insufficient holes and low hole concentration, which in turn reduces the internal quantum efficiency of ultraviolet LEDs. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an epitaxial wafer preparation method, an epitaxial wafer, and an ultraviolet light-emitting diode, aiming to solve the problem of low quantum efficiency in epitaxial wafers in the prior art.

[0005] The embodiments of the present invention are implemented as follows:

[0006] A method for preparing an epitaxial wafer, the method comprising:

[0007] Provide substrate;

[0008] A buffer layer and an N-type semiconductor layer are sequentially stacked on the substrate;

[0009] A predetermined number of quantum well layers and quantum barrier layers are alternately stacked on the N-type semiconductor layer to form a multi-quantum well layer;

[0010] An electron blocking layer and a P-type semiconductor layer are sequentially stacked on the last quantum barrier layer; wherein, a first quantum barrier layer, a second quantum barrier layer, an insert layer and a third quantum barrier layer are sequentially stacked on the quantum well layer to form the quantum barrier layer;

[0011] The quantum well layer, the first quantum barrier layer, the second quantum barrier layer, and the third quantum barrier layer are all AlGaN layers, and the insert layer is a MgN layer. The Al content of the first quantum barrier layer and the third quantum barrier layer is lower than that of the second quantum barrier layer.

[0012] Furthermore, in the above-mentioned epitaxial wafer preparation method, when stacking the quantum barrier layer, an MO source is first introduced to stack the first quantum barrier layer on the quantum well layer, then the introduction of the MO source is stopped to stack the second quantum barrier layer on the first quantum barrier layer, then a Mg source is introduced to stack the insert layer on the second quantum barrier layer, and finally the introduction of the Mg source is stopped and the MO source is introduced again to stack the third quantum barrier layer on the insert layer.

[0013] Furthermore, in the above-mentioned epitaxial wafer preparation method, in the step of growing the quantum barrier layer, the MO source is stopped for 5-10 s, the Mg source is stopped for 5-10 s, and the Mg source flow rate is 80-90 Sccm.

[0014] Furthermore, in the above-mentioned epitaxial wafer preparation method, the growth temperature in the step of growing the multiple quantum well layer is 1050-1100℃.

[0015] Another object of the present invention is to provide an epitaxial wafer, which is prepared by any of the epitaxial wafer preparation methods described above, wherein the epitaxial wafer includes a multi-quantum well layer, and the multi-quantum well layer includes periodically alternating layers of quantum well layers and quantum barrier layers;

[0016] The quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer, an insert layer, and a third quantum barrier layer sequentially stacked on the quantum well layer. The quantum well layer, the first quantum barrier layer, the second quantum barrier layer, and the third quantum barrier layer are all AlGaN layers, and the insert layer is a MgN layer. The Al content of the first quantum barrier layer and the third quantum barrier layer is lower than that of the second quantum barrier layer.

[0017] Furthermore, in the aforementioned epitaxial wafer, the Al component content of the second quantum barrier layer is 80-100%.

[0018] Furthermore, in the aforementioned epitaxial wafer, the Mg doping concentration of the inserted sublayer is 1*10⁻⁶. 18 / cm 3 ~1*10 20 / cm 3 .

[0019] Furthermore, in the aforementioned epitaxial wafer, the thickness of the second quantum barrier layer is 1–3 nm.

[0020] Furthermore, the aforementioned epitaxial wafer further includes a substrate, a buffer layer, an N-type semiconductor layer, an electron blocking layer, and a P-type semiconductor layer;

[0021] The buffer layer, N-type semiconductor layer, multiple quantum well layer, electron blocking layer, and P-type semiconductor layer are sequentially stacked on the substrate.

[0022] Another object of the present invention is to provide an ultraviolet light-emitting diode comprising the epitaxial wafer described in any of the preceding claims.

[0023] Compared with the prior art, the present invention grows a first quantum barrier layer, a second quantum barrier layer, an insert layer, and a third quantum barrier layer sequentially in the quantum well layer during the growth of the quantum barrier layer. The Al content of the first and third quantum barrier layers is lower than that of the second quantum barrier layer, so that the second quantum barrier layer can effectively block electron overflow. Then, a MgN layer is inserted to provide more Mg doping, thereby increasing the hole concentration and thus improving the internal quantum efficiency. Attached Figure Description

[0024] Figure 1 This is a flowchart of the epitaxial wafer preparation method proposed in the first embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the epitaxial wafer structure proposed in the second embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the quantum barrier layer in the epitaxial wafer proposed in the second embodiment of the present invention.

[0027] Explanation of key symbols:

[0028] Substrate 10; buffer layer 20; N-type semiconductor layer 30; multiple quantum well layer 40; quantum well layer 41; quantum barrier layer 42; first quantum barrier layer 420; second quantum barrier layer 421; insert layer 422; third quantum barrier layer 423; electron blocking layer 50; P-type semiconductor layer 60. Detailed Implementation

[0029] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0030] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0032] Furthermore, the term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. In the detailed description and claims, a list of items connected by the term "one of" may mean any of the listed items. For example, if items A and B are listed, then the phrase "one of A and B" means only A or only B. In another instance, if items A, B, and C are listed, then the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements. In the detailed description and claims, a list of items connected by the terms "at least one of," "at least one of," or other similar terms may mean any combination of the listed items. For example, if items A and B are listed, then the phrase "at least one of A and B" or "at least one of A or B" means only A; only B; or A and B. In another instance, if items A, B, and C are listed, then the phrase "at least one of A, B, and C" or "at least one of A, B, or C" means only A; or only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0033] Example 1

[0034] Please see Figure 1 This is the epitaxial wafer preparation method proposed in the first embodiment of the present invention, which includes steps S10 to S11.

[0035] Step S10: Provide a substrate.

[0036] The substrate includes, but is not limited to, sapphire, SiC, Si-based, and GaN. In this embodiment, a Si-based substrate is used. Si-based substrates have advantages such as good thermal conductivity, low cost, mature process, and easy peeling.

[0037] Step S11: A buffer layer and an N-type semiconductor layer are sequentially stacked on the substrate.

[0038] Specifically, in this embodiment, the buffer layer is an AlN layer.

[0039] Step S12: A predetermined number of quantum well layers and quantum barrier layers are sequentially and alternately stacked on the N-type semiconductor layer to form a multi-quantum well layer.

[0040] The number of preset cycles can be set according to actual needs, such as 2, 3, 4, and 5, etc., and is not limited here.

[0041] Step S13: An electron blocking layer and a P-type semiconductor layer are sequentially stacked on the last quantum barrier layer; wherein, a first quantum barrier layer, a second quantum barrier layer, an insert layer and a third quantum barrier layer are sequentially stacked on the quantum well layer to form the quantum barrier layer.

[0042] Among them, the quantum well layer, the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer are all AlGaN layers, the insert layer is a MgN layer, and the Al composition content of the first quantum barrier layer and the third quantum barrier layer is lower than that of the second quantum barrier layer.

[0043] Understandably, during the growth of the quantum barrier layer, the first quantum barrier layer, the second quantum barrier layer, the insert layer, and the third quantum barrier layer are grown sequentially in the quantum well layer. The Al content of the first and third quantum barrier layers is lower than that of the second quantum barrier layer, which allows the second quantum barrier layer to effectively block electron overflow. Then, a MgN layer is inserted to provide more Mg doping, thereby increasing the hole concentration and thus improving the internal quantum efficiency.

[0044] Specifically, when growing the quantum barrier layer, an MO source is first introduced to grow a first quantum barrier layer on the quantum well layer. Then, the MO source is stopped to grow a second quantum barrier layer on the first quantum barrier layer. Next, a Mg source is introduced to grow an insert layer on the second quantum barrier layer. Finally, the Mg source is stopped and the MO source is introduced again to grow a third quantum barrier layer on the insert layer.

[0045] It should be noted that after growing the first quantum barrier layer, the MO source is then stopped to grow the second quantum barrier layer. Because Ga is extremely prone to escape under high-temperature growth conditions in AlGaN, after the growth is interrupted by stopping the MO source, during the subsequent growth process, Ga must compensate for the Ga in the boundary layer to achieve a dynamic equilibrium with the escaped Ga before it can enter the solid phase. Al, on the other hand, enters the solid phase more easily, causing Ga to escape from the boundary layer and Al to accumulate. This results in a second quantum barrier layer with a higher Al content than the first quantum barrier layer. Furthermore, a large number of Ga vacancies are generated during the growth pause. Inserting a MgN layer then facilitates Mg doping, providing more Mg doping and thus increasing the hole concentration, thereby improving the internal quantum efficiency.

[0046] In this embodiment, the MO source is a high-purity metal-organic compound that needs to be introduced during epitaxial growth. In this embodiment, the multiple quantum well layer is an AlGaN layer, and the MO source is a TMAl source and a TMGa source.

[0047] In this embodiment, the MO source is stopped for 5-10 seconds, the Mg source is stopped for 5-10 seconds, the Mg source flow rate is 80-90 Sccm, and the growth temperature is 1050-1100℃.

[0048] More specifically, in order to clearly understand the specific implementation process of the present invention, the specific growth process of the entire epitaxial wafer is described in detail below, which is one embodiment of the present invention. However, the growth process of the epitaxial wafer of the present invention is not limited thereto and does not constitute a limitation of the present invention.

[0049] The substrate was placed in the MOCVD reaction chamber, and TMAl and NH3 were introduced into the chamber to prepare an AlN thin film by chemical vapor deposition. Specifically, in this embodiment, the growth temperature of the AlN layer was 1250°C, the growth thickness was approximately 1.5 μm, and the growth pressure was 50 mbar.

[0050] The high-temperature AlN layer is grown primarily to address the lattice and thermal mismatch between the substrate and the AlGaN material. Therefore, in this embodiment, the layer is produced by intermittently introducing NH3 pulses into the reaction chamber under low pressure and high temperature conditions. This process yields an AlN layer with superior crystal quality. In practice, ammonia gas is intermittently introduced into the reaction chamber for 30 seconds on and 10 seconds off.

[0051] An N-type semiconductor layer is grown after an AlN layer, wherein the growth temperature is 1100 degrees, the growth thickness is 2 μm, the Al composition is 50%, the dopant is Si, and the doping concentration is 5E18-1E20.

[0052] Multiple quantum well layers are grown on an N-type semiconductor layer, wherein quantum well layers and quantum barrier layers are grown alternately during the growth of multiple quantum well layers, wherein the growth thickness of the quantum well layers is 2 nm and the Al composition is 25%.

[0053] An electron blocking layer was grown after a multi-quantum well layer, with a growth temperature of 1100 degrees, a growth thickness of 25 nm, and an Al composition of 65%.

[0054] A P-type semiconductor layer is grown behind an electron blocking layer. The P-type semiconductor is doped with Mg, has an Al content of 30%, a thickness of 200 nm, and a Mg doping concentration of 5E19.

[0055] Furthermore, in the specific implementation of this embodiment, trimethylaluminum (TMAl), trimethylgallium or triethylgallium (TMGa or TEGa), and NH3 are used as precursors for group III and group V sources, respectively; silane and magnesium pyrocene are used as precursors for N-type dopant and P-type dopant, respectively; and N2 and H2 are used as carrier gases.

[0056] Example 2

[0057] Please see Figures 2 to 3 The image shows an epitaxial wafer proposed in the first embodiment of the present invention. The epitaxial wafer is prepared by the epitaxial wafer preparation method in the first embodiment described above. The epitaxial wafer comprises:

[0058] Substrate 10, buffer layer 20, N-type semiconductor layer 30, multiple quantum well layer 40, electron blocking layer 50 and P-type semiconductor layer 60 are epitaxially grown on substrate 10 in sequence.

[0059] Preferably, the buffer layer is an AlN layer, and the N-type semiconductor layer 30 is N-type doped Al. x Ga (1-x) N-layer, electron blocking layer 50 is Al y Ga (1-y) The N-layer and the P-type semiconductor layer 60 are P-type doped Al. z Ga (1-z) N layers.

[0060] The multiple quantum well layer 40 includes periodically alternating quantum well layers 41 and quantum barrier layers 42. Specifically, the number of periods can be set according to actual conditions and is not limited here. In this embodiment, for example... Figure 1As shown, the number of periods is set to two. The quantum barrier layer 42 includes a first quantum barrier layer 420, a second quantum barrier layer 421, an insert layer 422, and a third quantum barrier layer 423, which are sequentially stacked on the quantum well layer 41. The quantum well layer 41, the first quantum barrier layer 420, the second quantum barrier layer 421, and the third quantum barrier layer 423 are all AlGaN layers, and the insert layer 422 is a MgN layer. The Al content of the first quantum barrier layer 420 and the third quantum barrier layer 423 is lower than that of the second quantum barrier layer 421.

[0061] Understandably, by setting a third quantum barrier layer 423 with a high Al content in the first quantum barrier layer 420 and the second quantum barrier layer 421, it can effectively block electron overflow. Then, inserting a MgN layer can provide more Mg doping, thereby increasing the hole concentration and thus improving the internal quantum efficiency.

[0062] Specifically, the Al composition of the second quantum barrier sublayer 421 is 80-100%, and the Mg doping concentration of the inserted sublayer 422 is 1*10⁻⁶. 18 / cm 3 ~1*10 20 / cm 3 The thickness of the second quantum barrier layer 421 is 1–3 nm.

[0063] The internal quantum efficiency of the epitaxial wafers corresponding to the second quantum barrier layer 421 with different thicknesses was tested, and the data are shown in Table 1 below.

[0064] Table 1

[0065]

[0066]

[0067] As can be clearly seen from the table, when the thickness of the second quantum barrier layer 421 is 1-3 nm, the internal quantum efficiency is stable at around 60%, and the improvement effect is more obvious when the thickness is 1-3 nm.

[0068] In summary, the epitaxial wafer preparation method and epitaxial wafer proposed in this invention involve first growing a first quantum barrier layer 420 during the growth of the quantum barrier layer 42, and then stopping the MO source to grow a second quantum barrier layer 421. Since Ga readily escapes from AlGaN under high-temperature growth conditions, after the growth is interrupted by stopping the MO source, Ga must compensate for Ga in the boundary layer during the subsequent growth process to achieve a dynamic equilibrium with Ga escape before entering the solid phase. Al, on the other hand, enters the solid phase more easily, causing Ga to escape from the boundary layer while Al accumulates, thus forming a second quantum barrier layer 421 with a high Al content. The second quantum barrier layer 421 effectively blocks electron overflow and generates a large number of Ga vacancies during the growth pause. Inserting a MgN layer then provides more Mg doping, thereby increasing the hole concentration and improving the internal quantum efficiency.

[0069] Example 3

[0070] The ultraviolet light-emitting diode proposed in the third embodiment of the present invention includes the epitaxial wafer in the second embodiment above, which is prepared by the epitaxial wafer preparation method in the first embodiment above.

[0071] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for preparing an epitaxial wafer, characterized in that, The method includes: Provide substrate; A buffer layer and an N-type semiconductor layer are sequentially stacked on the substrate; A predetermined number of quantum well layers and quantum barrier layers are alternately stacked on the N-type semiconductor layer to form a multi-quantum well layer; An electron blocking layer and a P-type semiconductor layer are sequentially stacked on the last quantum barrier layer; wherein, a first quantum barrier layer, a second quantum barrier layer, an insertion layer and a third quantum barrier layer are sequentially stacked on the quantum well layer to form the quantum barrier layer; The quantum well layer, the first quantum barrier layer, the second quantum barrier layer, and the third quantum barrier layer are all AlGaN layers, and the insert layer is a MgN layer. The Al content of the first quantum barrier layer and the third quantum barrier layer is lower than that of the second quantum barrier layer. When stacking the quantum barrier layers, an MO source is first introduced to stack the first quantum barrier layer on the quantum well layer, then the MO source is stopped to stack the second quantum barrier layer on the first quantum barrier layer, then a Mg source is introduced to stack the insert layer on the second quantum barrier layer, and finally the Mg source is stopped and the MO source is introduced again to stack the third quantum barrier layer on the insert layer.

2. The method for preparing an epitaxial wafer according to claim 1, characterized in that, In the step of growing the quantum barrier layer, the MO source is stopped for 5~10 s, the Mg source is stopped for 5~10 s, and the Mg source flow rate is 80~90 Sccm.

3. The method for preparing an epitaxial wafer according to claim 1, characterized in that, In the process of growing multiple quantum well layers, the growth temperature is 1050~1100℃.

4. An epitaxial wafer, characterized in that, The epitaxial wafer is prepared by the epitaxial wafer preparation method according to any one of claims 1 to 3, and the epitaxial wafer includes a multi-quantum well layer, wherein the multi-quantum well layer includes periodically alternating layers of quantum well layers and quantum barrier layers; The quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer, an insert layer, and a third quantum barrier layer sequentially stacked on the quantum well layer. The quantum well layer, the first quantum barrier layer, the second quantum barrier layer, and the third quantum barrier layer are all AlGaN layers, and the insert layer is a MgN layer. The Al content of the first quantum barrier layer and the third quantum barrier layer is lower than that of the second quantum barrier layer.

5. The epitaxial wafer according to claim 4, characterized in that, The Al component content of the second quantum barrier layer is 80-100%.

6. The epitaxial wafer according to claim 4, characterized in that, The Mg doping concentration of the inserted sublayer is 1*10⁻⁶. 18 / cm 3 ~1*10 20 / cm 3 .

7. The epitaxial wafer according to claim 4, characterized in that, The thickness of the second quantum barrier layer is 1~3nm.

8. The epitaxial wafer according to claim 4, characterized in that, The epitaxial wafer also includes a substrate, a buffer layer, an N-type semiconductor layer, an electron blocking layer, and a P-type semiconductor layer; The buffer layer, N-type semiconductor layer, multiple quantum well layer, electron blocking layer, and P-type semiconductor layer are sequentially stacked on the substrate.

9. An ultraviolet light-emitting diode, characterized in that, Includes the epitaxial wafer according to any one of claims 4 to 8.

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