Light emitting diode epitaxial wafer and manufacturing method thereof

Abstract

The application provides a light emitting diode epitaxial wafer and a manufacturing method thereof. The light emitting diode epitaxial wafer comprises a substrate, and a low-temperature nucleation layer, an undoped u-GaN layer, an interlayer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, a P-type electron blocking layer and a P-type GaN layer which are sequentially stacked on the substrate; the interlayer comprises a first sub-layer, a second sub-layer and a third sub-layer which are sequentially stacked on the undoped u-GaN layer, the first sub-layer is a low-temperature high-pressure grown Mg x N layer, the second sub-layer comprises periodically and alternately stacked high-pressure grown GaN layers and low-pressure grown Al y Ga 1‑y N layers, and the third sub-layer is a high-temperature low-pressure grown Al z Ga 1‑z N layer. The application solves the problems of defects and surface flatness reduction of the existing epitaxial wafer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of optoelectronic technology, in particular to a light emitting diode epitaxial wafer and a manufacturing method thereof. BACKGROUND

[0002] At present, GaN-based light emitting diodes have been widely used in solid-state lighting field and display field, attracting more and more people's attention. GaN-based light emitting diodes have realized industrial production and have been applied in backlight, lighting, landscape lamp and the like.

[0003] When GaN grows on a substrate, a large thermal stress and lattice mismatch will be generated, resulting in a large warpage of the epitaxial wafer. Especially after the undoped u-GaN layer is grown at high temperature, then the N-type GaN layer doped with Si is grown at high temperature, the accumulated stress is very large, and the warpage reaches a very large value, resulting in difficulty in Si doping, and causing defects such as surface fogging and cracking at the edge of the epitaxial wafer. However, since high temperature is beneficial to the improvement of atomic mobility, in order to improve the lattice quality of GaN, the undoped u-GaN and the N-type doped GaN both need to be grown at a high temperature of 1100-1150℃. High temperature will increase the stress of the epitaxial wafer and make the warpage larger, resulting in difficulty in N-type doping and causing defects such as surface fogging or cracking at the edge of the epitaxial wafer.

[0004] The existing research increases a low-temperature ALGaN layer between the undoped u-GaN and the N-type doped GaN to relieve the warpage of the bottom layer, but the lattice quality of the low-temperature ALGaN layer is very poor, which will introduce new defects, cause the antistatic ability of the epitaxial wafer to be poor, the number of defects to increase, the surface flatness to decrease, and the edge surface to be prone to fogging. SUMMARY

[0005] Based on this, the purpose of the present application is to provide a light emitting diode epitaxial wafer and a manufacturing method thereof, so as to fundamentally solve the problems of many defects and decreased surface flatness of the existing epitaxial wafer.

[0006] The light emitting diode epitaxial wafer according to an embodiment of the present application comprises:

[0007] a substrate, and a low-temperature nucleation layer, an undoped u-GaN layer, an insertion layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, a P-type electron blocking layer and a P-type GaN layer which are sequentially stacked on the substrate;

[0008] The insertion layer comprises a first sublayer, a second sublayer and a third sublayer which are sequentially stacked on the undoped u-GaN layer, the first sublayer is a Mg x N layer grown at low temperature and high pressure, the second sublayer comprises a GaN layer grown at high pressure and an Al y Ga layer grown at low pressure which are periodically and alternately stacked, and the third sublayer is a Mg1-y N layer, the third sub-layer being an Al z Ga 1-z N layer grown at a high temperature and a low pressure.

[0009] In addition, the light emitting diode epitaxial wafer according to the above-mentioned embodiment of the present application can further have the following additional technical features:

[0010] Further, in the first sub-layer, the x in the Al x N layer ranges from 0.1 to 0.3, and the thickness of the first sub-layer ranges from 3 to 10 nm.

[0011] In the second sub-layer, the Al y Ga 1-y N layer ranges from 0.05 to 0.2, the total thickness of the second sub-layer ranges from 0.5 to 1 um, and the GaN layer and the Al y Ga 1-y N layer in the second sub-layer are alternately stacked for 3 to 20 cycles.

[0012] In the third sub-layer, the Al z Ga 1-z N layer ranges from 0.1 to 0.3, and the thickness of the third sub-layer ranges from 0.3 to 0.5 um.

[0013] Further, the stress release layer comprises GaN layers and InGaN layers alternately stacked periodically, and the GaN layers and the InGaN layers are alternately stacked for 3 to 8 cycles, the total thickness of the stress release layer ranges from 50 to 300 nm, and the In component in the InGaN layers in the stress release layer accounts for 10% to 20% in mole.

[0014] Further, the multi-quantum well layer comprises quantum well layers and quantum barrier layers alternately stacked periodically, and the quantum well layers and the quantum barrier layers are alternately stacked for 3 to 15 cycles.

[0015] The quantum well layer is an InGaN layer, the quantum barrier layer is a GaN layer, and the In component in the InGaN layers in the multi-quantum well layer accounts for 10% to 35% in mole.

[0016] The thickness of a single quantum well layer ranges from 2 to 5 nm, and the thickness of a single quantum barrier layer ranges from 3 to 15 nm.

[0017] Further, the P-type electron blocking layer comprises Al a Ga 1-a N layers and In b Ga 1-b N layers alternately stacked periodically, and the Al

[0018] The Al a Ga 1-a N layer has a value range of a: 0.05≤a≤0.2, the In b Ga 1-b N layer has a value range of b: 0.1≤b≤0.5;

[0019] The total thickness of the P-type electron blocking layer is 20-50nm.

[0020] Further, the low-temperature nucleation layer is an AlGaN layer, and the thickness of the low-temperature nucleation layer is 30-100nm;

[0021] The thickness of the undoped u-GaN layer is 300-800nm;

[0022] The total thickness of the interposed layer is 1-1.5um;

[0023] The thickness of the N-type GaN layer is 1-3um, and the doping concentration of Si in the N-type GaN layer is 5×E 18 -1×E 19 atoms / cm 3 ;

[0024] The thickness of the P-type GaN layer is 200-300nm, and the doping concentration of Mg in the P-type GaN layer is 5×E 17 -1×E 20 atoms / cm 3 .

[0025] According to the method for manufacturing a light-emitting diode epitaxial wafer provided by the embodiment of the present application, the method comprises:

[0026] Providing a substrate;

[0027] Depositing a low-temperature nucleation layer and an undoped u-GaN layer on the substrate in sequence;

[0028] Depositing an interposed layer on the undoped u-GaN layer, wherein the interposed layer comprises a first sublayer, a second sublayer and a third sublayer deposited in sequence, the first sublayer is a low-temperature high-pressure grown Mg x N layer, the second sublayer comprises periodically and alternately stacked high-pressure grown GaN layers and low-pressure grown Al y Ga 1-y N layers, and the third sublayer is a high-temperature low-pressure grown Al z Ga 1-z N layer;

[0029] Depositing an N-type GaN layer, a stress release layer, a multi-quantum well layer, a P-type electron blocking layer and a P-type GaN layer on the interposed layer in sequence.

[0030] Further, the growth temperature of the first sub-layer is 800-900℃, and the growth pressure is 300-500torr;

[0031] The growth temperature of the second sub-layer is 1020-1050℃;

[0032] The growth temperature of the third sub-layer is 1100-1150℃, and the growth pressure is 100-200torr.

[0033] Further, the GaN layer in the second sub-layer is grown by using N2 as carrier gas, and the growth pressure is 300-500torr;

[0034] The Al y Ga 1-y N layer in the second sub-layer is grown by using N2 and H2 as carrier gas, and the growth pressure is 100-200torr.

[0035] Further, in the first sub-layer, the x in the Mg x N layer ranges from 0.1 to 0.3, and the thickness of the first sub-layer is 3-10nm;

[0036] In the second sub-layer, the y in the Al y Ga 1-y N layer ranges from 0.05 to 0.2, the total thickness of the second sub-layer is 0.5-1um, and the GaN layer and the Al y Ga 1-y N layer in the second sub-layer are alternately stacked for 3-20 times;

[0037] In the third sub-layer, the z in the Al z Ga 1-z N layer ranges from 0.1 to 0.3, and the thickness of the third sub-layer is 0.3-0.5um.

[0038] Compared with the prior art, by arranging an insertion layer between the undoped u-GaN layer and the N-type GaN layer, the insertion layer comprises a first sub-layer, a second sub-layer and a third sub-layer, the first sub-layer is a low-temperature high-pressure grown Mg x N layer, the second sub-layer comprises periodically alternately stacked high-pressure grown GaN layer and low-pressure grown Al y Ga 1-y N layer, and the third sub-layer is a high-temperature low-pressure grown Al z Ga 1-zIn the N-layer, the first sublayer is grown at a low temperature, which releases the underlying stress and alleviates the underlayer warping caused by the high-temperature growth of the undoped u-GaN layer; while Mg is grown under high-pressure conditions. x The N-layer is primarily for forming metal islands, which allows for the induction of three-dimensional growth in the second sublayer. High pressure conditions also facilitate the incorporation of Mg, promoting three-dimensional growth. Furthermore, Mg atoms serve as anchoring atoms for the subsequent island growth and merging. High-pressure growth of the GaN layer in the second sublayer promotes three-dimensional growth, where the islands grow vertically with Mg metal islands at their cores. Meanwhile, the growth of Al in the second sublayer... y Ga 1-y The low-pressure growth of N-layers is conducive to two-dimensional growth, thereby enabling the lateral growth of three-dimensional islands. This is achieved through the periodic alternating stacking of GaN and Al layers. y Ga 1-y The N-layer allows for a combination of vertical and horizontal growth of the three-dimensional islands, until the islands merge and fill to form a two-dimensional structure. The third sublayer is grown at high temperature, which increases the mobility of adsorbed atoms and suppresses defect formation. Simultaneously, the third sublayer is grown at low pressure, which is beneficial for two-dimensional growth. Therefore, the high-temperature, low-pressure growth conditions contribute to improved lattice quality. Furthermore, the covalent bond strength between Al and N atoms is much greater than that between Ga and N atoms, maintaining the integrity of the GaN lattice and reducing defect formation. The small size of Al atoms also facilitates filling vacancies in the epitaxial layers, providing a blocking and twisting effect on dislocations. This method, which involves growing a three-dimensional island in the second sublayer centered on Mg metal atoms in the first sublayer of the insertion layer to form a two-dimensional growth layer, and finally growing a high-temperature third sublayer to repair defects and prevent further defect growth, is beneficial for obtaining epitaxial layers with better lattice quality. This achieves the goals of releasing the underlying stress and alleviating warping while ensuring good lattice quality and not affecting antistatic properties. At the same time, the stress release and warping relief facilitate the incorporation of Si into the subsequently grown N-type GaN layer, reducing the operating voltage, effectively improving the surface flatness of the epitaxial wafer, reducing edge fogging and cracking, and solving the problems of multiple defects and decreased surface flatness in existing epitaxial wafers. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure of a light-emitting diode epitaxial wafer according to the first embodiment of the present invention;

[0040] Figure 2 This is a flowchart of a method for fabricating a light-emitting diode epitaxial wafer according to a second embodiment of the present invention.

[0041] The following detailed description of the embodiments will further illustrate the present invention in conjunction with the above-described accompanying drawings. Detailed Implementation

[0042] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0043] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] Example 1

[0046] Please see Figure 1 This is a schematic diagram of the structure of a light-emitting diode epitaxial wafer provided in an embodiment of the present invention. For ease of explanation, only the parts related to the embodiment of the present invention are shown. The light-emitting diode epitaxial wafer provided in the embodiment of the present invention includes:

[0047] Substrate 1, and on substrate 1, a low-temperature nucleation layer 2, an undoped u-GaN layer 3, an insertion layer 4, an N-type GaN layer 5, a stress relief layer 6, a multiple quantum well layer 71, a P-type electron blocking layer 8, and a P-type GaN layer 9 are sequentially stacked.

[0048] The insertion layer 4 includes a first sublayer 41, a second sublayer 42, and a third sublayer 43 sequentially stacked on an undoped u-GaN layer 3. The first sublayer 41 is Mg grown at low temperature and high pressure. x The N-layer, the second sub-layer 42, comprises periodically alternating layers of high-pressure grown GaN and low-pressure grown Al. y Ga 1-y The N-layer and the third sub-layer 43 are Al layers grown under high temperature and low pressure. z Ga 1-z N layers.

[0049] In one embodiment of the present invention, the substrate 1 includes, but is not limited to, sapphire substrate, silicon substrate, silicon carbide substrate, aluminum nitride substrate, gallium nitride substrate, and composite substrate such as silicon dioxide and sapphire. Specifically, in this embodiment, sapphire is used as the epitaxial layer growth substrate 1, which can be a patterned sapphire substrate or a sapphire flat substrate.

[0050] In one embodiment of the present invention, the low-temperature nucleation layer 2 is an AlGaN layer, wherein the thickness of the low-temperature nucleation layer 2 is 30-100 nm. The main function of the low-temperature nucleation layer 2 is to provide seed crystals and alleviate the lattice mismatch between the substrate 1 and the epitaxial layer. In a preferred embodiment of the present invention, the thickness of the low-temperature nucleation layer 2 is preferably 70 nm. Further, the thickness of the undoped u-GaN layer 3 is 300-800 nm, wherein the undoped u-GaN layer 3 is grown under high-temperature conditions, typically at a growth temperature of 1100℃-1150℃. In a preferred embodiment of the present invention, the thickness of the undoped u-GaN layer 3 is preferably 400 nm.

[0051] In one embodiment of the present invention, the insertion layer 4 includes a first sublayer 41, a second sublayer 42, and a third sublayer 43 sequentially stacked on an undoped u-GaN layer 3, wherein the first sublayer 41 is Mg grown at low temperature and high pressure. x The N-layer, the second sub-layer 42, comprises periodically alternating layers of high-pressure grown GaN and low-pressure grown Al. y Ga 1-y The N-layer and the third sub-layer 43 are Al layers grown under high temperature and low pressure. z Ga 1-z The N layers have a total thickness of 1-1.5 μm, and the insertion layer 4 has a total thickness of 1-1.5 μm.

[0052] Specifically, in the first sublayer 41, Mg x The value of x in layer N ranges from 0.1 to 0.3. The thickness of the first sublayer 41 is 3-10 nm, and its Mg is grown under low temperature and high pressure. x The growth temperature of the N-layer is 800-900℃, and the growth pressure is 300-500 torr. Because the epitaxial wafer experiences significant warpage after the high-temperature growth of the undoped u-GaN layer 3, a low-temperature growth is employed for the first sublayer 41 to release underlying stress and alleviate warpage. Meanwhile, high-pressure growth of the Mg layer... x The N layer is mainly for forming metal islands, which can induce the three-dimensional growth of the second sublayer 42. At the same time, the high pressure condition is conducive to the incorporation of Mg and also to three-dimensional growth. Furthermore, during subsequent growth, Mg atoms can be used as positioning atoms to grow and merge the islands.

[0053] Furthermore, in the second sub-layer 42, the GaN layer and Al in the second sub-layer 42 y Ga 1-y The N layers are stacked alternately with 3-20 cycles, and the total thickness of the second sublayer 42 is 0.5-1 μm. Al y Ga 1-y The value of y in layer N ranges from 0.05 to 0.2. The growth temperature of the second sublayer 42 is 1020-1050℃. Furthermore, the GaN layer is grown under high pressure (300-500 torr), with N2 introduced as a carrier gas during growth. Due to the high viscosity of N2, it is beneficial for three-dimensional growth. In this layer, the islands grow vertically with Mg metal islands as their cores. Meanwhile, Al... y Ga 1-y The N-layer is grown under low pressure, at a pressure of 100-200 torr. N2 and H2 are introduced as carrier gases during growth; the introduction of H2 is beneficial for two-dimensional growth, allowing the three-dimensional islands to grow laterally. Furthermore, GaN and Al layers are periodically and alternately stacked. y Ga 1-y The N layers allow for a combination of vertical and horizontal growth of the three-dimensional islands, until the islands are merged and filled into a two-dimensional growth.

[0054] Furthermore, in the third sublayer 43, Al z Ga 1-z The z-value range in layer N is 0.1 ≤ z ≤ 0.3, and the thickness of the third sublayer 43 is 0.3-0.5 μm. Its Al is grown under high temperature and low pressure. z Ga 1-z The growth temperature of the N layer is 1100-1150℃, and the growth pressure is 100-200 torr. Since the third sublayer 43 is grown at a high temperature, which increases the mobility of adsorbed atoms and suppresses defect formation, and simultaneously, the third sublayer 43 is grown at a low pressure, the low growth pressure is beneficial for two-dimensional growth. Therefore, the high-temperature, low-pressure growth conditions are conducive to improving lattice quality. Furthermore, because the covalent bond strength between Al and N atoms is much greater than that between Ga and N atoms, the integrity of the GaN lattice is maintained, reducing defect formation. Also, the small size of Al atoms is beneficial for filling vacancies in the epitaxial layer, allowing for dislocation blocking and distortion.

[0055] Therefore, by centering on the Mg metal atoms of the first sublayer 41 in the insertion layer 4, and then growing and merging the three-dimensional islands of the second sublayer 42 to form a two-dimensional growth, and finally growing the high-temperature third sublayer 43 to repair defects and prevent further defects, this method of first performing three-dimensional growth and then gradually healing and transitioning to two-dimensional growth is beneficial to obtaining an epitaxial layer with better lattice quality. This achieves the purpose of releasing the underlying stress and alleviating warping, while ensuring good lattice quality and not affecting the antistatic capability. At the same time, due to the stress release and the relief of warping, it is beneficial to the incorporation of Si in the subsequently grown N-type GaN layer 5, which reduces the operating voltage, effectively improves the surface flatness of the epitaxial wafer, and reduces edge fogging and cracking.

[0056] In one embodiment of the present invention, the N-type GaN layer 5 is a Si-doped N-type GaN layer 5 deposited and grown using SiH4 (silane) as an N-type dopant. The thickness of the N-type GaN layer 5 is 1-3 μm. As an example of the present invention, the preferred thickness of the N-type GaN layer 5 is 2 μm. This N-type GaN layer 5 serves as the main epitaxial layer providing electrons. Therefore, SiH4 is introduced during GaN growth to provide Si (silicon) elements, where Si is a tetravalent element and Ga in GaN is a trivalent element. When Si atoms replace Ga atoms, they provide electrons, thus forming the electron-providing N-type GaN layer 5. Simultaneously, by using an appropriate concentration of Si doping, defects and vacancies in the GaN material can be effectively filled, dislocations repaired, and further dislocation propagation prevented. As an example of the present invention, the Si doping concentration in the N-type GaN layer 5 is 5 × E. 18 atoms / cm 3 -1×E 19 atoms / cm 3 Furthermore, the Si doping concentration in its N-type GaN layer 5 is preferably 7 × E. 18 atoms / cm 3 .

[0057] In one embodiment of the present invention, the stress relief layer 6 comprises periodically alternating GaN layers and InGaN layers, with the number of alternating stacking periods being 3-8. The total thickness of the stress relief layer 6 is 50-300 nm, and the molar proportion of In component in the InGaN layer of the stress relief layer 6 is 10%-20%. Specifically, the GaN layer is first stacked on the N-type GaN layer 5, and then the InGaN layer is stacked on top of the GaN layer. Then, the GaN and InGaN layers are periodically alternatingly stacked to finally form the stress relief layer 6. In a preferred embodiment of the present invention, the number of alternating stacking periods of the GaN and InGaN layers is preferably 5, the thickness of the GaN layer is preferably 10 nm, and the thickness of the InGaN layer is preferably 3 nm. Specifically, the stress relief layer 6 is mainly used to release the underlying stress, preparing for the growth of the multi-quantum well layer 71.

[0058] In one embodiment of the present invention, the multiple quantum well layer 71 includes periodically alternating layers of quantum well layers 71 and quantum barrier layers 72, as specifically referred to Figure 1 As shown, the quantum well layer 71 is first stacked on the N-type GaN layer 5, and then the quantum barrier layer 72 is stacked on the quantum well layer 71. The quantum well layer 71 and the quantum barrier layer 72 are then periodically and alternately stacked to form the final multi-quantum well layer 71. The number of alternating stacking periods of the quantum well layer 71 and the quantum barrier layer 72 is 3-15. In a preferred embodiment of the invention, the number of alternating stacking periods of the quantum well layer 71 and the quantum barrier layer 72 is preferably 10, that is, the multi-quantum well layer 71 is composed of 10 alternating stackings of the quantum well layer 71 and the quantum barrier layer 72.

[0059] Furthermore, the quantum well layer 71 is an InGaN layer, and the quantum barrier layer 72 is a GaN layer. The thickness of a single quantum well layer 71 is 2-5 nm, and the thickness of a single quantum barrier layer 72 is 3-15 nm. The molar proportion of In in the InGaN layer of the multiple quantum well layers 71 is 10%-35%. In a preferred embodiment of the invention, the thickness of a single quantum well layer 71 is preferably 3 nm, and the thickness of a single quantum barrier layer 72 is 10 nm. It is understood that in other embodiments of the invention, the number of alternating stacking periods of the quantum well layer 71 and the quantum barrier layer 72, as well as the thicknesses of the quantum well layer 71 and the quantum barrier layer 72, can be other values, set according to actual usage needs, and are not specifically limited here.

[0060] In one embodiment of the present invention, the P-type electron blocking layer 8 comprises periodically alternating layers of Al a Ga 1- a N layers and In b Ga 1-b N layers, with an alternating stacking period of 3-15; Ala Ga 1-a The range of values ​​for 'a' in layer N is: 0.05 ≤ a ≤ 0.2, In b Ga 1-b The value of b in the N-layer ranges from 0.1 to 0.5; the total thickness of the P-type electron blocking layer 8 is 20-50 nm. In a preferred embodiment of the present invention, its Al... a Ga 1-a N layers and In b Ga 1-b The preferred number of cycles for the N-layer alternating stack is 8. As the chip size decreases, the current density increases, and electrons have a lower effective mass and a higher mobility, causing electrons to easily overflow from the multi-quantum well layer 71 to the P-type GaN layer 9 and recombine with holes, thus reducing luminous efficiency. At this time, the P-type electron blocking layer 8 is set to block electrons and prevent electron overflow.

[0061] In one embodiment of the present invention, the P-type GaN layer 9 is a Mg-doped P-type GaN layer 9 deposited and grown using Mg2Mg as a P-type dopant. The thickness of the P-type GaN layer 9 is 200-300 nm. This P-type GaN layer 9 serves as the main epitaxial layer providing holes. Therefore, CP2Mg is introduced during GaN growth to provide Mg, where Mg is a divalent element, while Ga in GaN is a trivalent element. When Mg atoms replace Ga atoms, they provide holes, thus forming the hole-providing P-type GaN layer 9. Simultaneously, by using an appropriate concentration of Mg doping, defects and vacancies in the GaN material can be effectively filled, dislocations repaired, and further dislocation propagation prevented. As an example of the present invention, the Mg doping concentration in the P-type GaN layer 9 is 5 × E. 17 -1×E 20 atoms / cm 3 .

[0062] Tests have shown that the LED epitaxial wafer with an insertion layer provided according to the embodiments of the present invention effectively reduces the operating voltage and effectively increases the surface flatness compared to existing LED epitaxial wafers without an insertion layer. The performance test results are shown in Table 1 below:

[0063]

[0064] Table 1

[0065] In summary, the light-emitting diode epitaxial wafer in the above embodiments of the present invention has an insertion layer disposed between an undoped u-GaN layer and an N-type GaN layer. The insertion layer includes a first sub-layer, a second sub-layer, and a third sub-layer, wherein the first sub-layer is Mg grown at low temperature and high pressure. xThe N-layer consists of a second sublayer comprising periodically alternating layers of high-pressure grown GaN and low-pressure grown Al. y Ga 1-y The Nth layer, and the third sublayer, are Al layers grown at high temperature and low pressure. z Ga 1-z In the N-layer, the first sublayer is grown at a low temperature, which releases the underlying stress and alleviates the underlayer warping caused by the high-temperature growth of the undoped u-GaN layer; while Mg is grown under high-pressure conditions. x The N-layer is primarily for forming metal islands, which allows for the induction of three-dimensional growth in the second sublayer. High pressure conditions also facilitate the incorporation of Mg, promoting three-dimensional growth. Furthermore, Mg atoms serve as anchoring atoms for the subsequent island growth and merging. High-pressure growth of the GaN layer in the second sublayer promotes three-dimensional growth, where the islands grow vertically with Mg metal islands at their cores. Meanwhile, the growth of Al in the second sublayer... y Ga 1-y The low-pressure growth of N-layers is conducive to two-dimensional growth, thereby enabling the lateral growth of three-dimensional islands. This is achieved through the periodic alternating stacking of GaN and Al layers. y Ga 1-y The N-layer allows for a combination of vertical and horizontal growth of the three-dimensional islands, until the islands merge and fill to form a two-dimensional structure. The third sublayer is grown at high temperature, which increases the mobility of adsorbed atoms and suppresses defect formation. Simultaneously, the third sublayer is grown at low pressure, which is beneficial for two-dimensional growth. Therefore, the high-temperature, low-pressure growth conditions contribute to improved lattice quality. Furthermore, the covalent bond strength between Al and N atoms is much greater than that between Ga and N atoms, maintaining the integrity of the GaN lattice and reducing defect formation. The small size of Al atoms also facilitates filling vacancies in the epitaxial layers, providing a blocking and twisting effect on dislocations. This method, which involves growing a three-dimensional island in the second sublayer centered on Mg metal atoms in the first sublayer of the insertion layer to form a two-dimensional growth layer, and finally growing a high-temperature third sublayer to repair defects and prevent further defect growth, is beneficial for obtaining epitaxial layers with better lattice quality. This achieves the goals of releasing the underlying stress and alleviating warping while ensuring good lattice quality and not affecting antistatic properties. At the same time, the stress release and warping relief facilitate the incorporation of Si into the subsequently grown N-type GaN layer, reducing the operating voltage, effectively improving the surface flatness of the epitaxial wafer, reducing edge fogging and cracking, and solving the problems of multiple defects and decreased surface flatness in existing epitaxial wafers.

[0066] Example 2

[0067] Please see Figure 2The figure shows a method for fabricating a light-emitting diode epitaxial wafer according to a second embodiment of the present invention, the method specifically including steps S11 to S14.

[0068] Step S11: Provide a substrate.

[0069] In this embodiment of the invention, the selected substrate includes, but is not limited to, sapphire substrates, silicon substrates, silicon carbide substrates, aluminum nitride substrates, gallium nitride substrates, and composite substrates such as those composed of silicon dioxide and sapphire. Specifically, in this embodiment, sapphire is used as the epitaxial layer growth substrate, on which periodically varying structures can be fabricated to form a patterned substrate. Composite patterned substrates such as SiO2-Al2O3 can also be used. Specifically, in this embodiment of the invention, a sapphire patterned substrate is used as the epitaxial layer growth substrate.

[0070] Furthermore, this invention employs a metal-organic chemical vapor deposition (MOCVD) apparatus to grow epitaxial wafers. High-purity ammonia (NH3) is used as the N (nitrogen) source, trimethylgallium (TMGa) and triethylgallium (TEGa) as the Ga (gallium) sources, trimethylindium (TMIn) as the In (indium) source, and trimethylaluminum (TMAl) as the Al (aluminum) source. Silane (SiH4) is used as the N-type dopant, and magnesium pyrocene (CP2Mg) as the P-type dopant. Simultaneously, high-purity H2 (hydrogen), high-purity N2 (nitrogen), or a mixture of high-purity H2 and high-purity N2 are used as the carrier gas for the MO source.

[0071] Specifically, the sapphire substrate is first subjected to high-temperature annealing in an H2 atmosphere to clean the substrate surface. The temperature is controlled at 1000℃-1200℃, and the substrate is subjected to high-temperature annealing for about 5 minutes in an H2 atmosphere. After the substrate surface is cleaned, nitriding is then performed.

[0072] Step S12: A low-temperature nucleation layer and an undoped u-GaN layer are sequentially deposited on the substrate.

[0073] In this embodiment of the invention, the low-temperature nucleation layer is an AlGaN layer, used to provide seed crystals and alleviate lattice mismatch between the substrate and the epitaxial layer. The specific deposition process is as follows: the temperature of the reaction chamber is controlled at 500℃-700℃, the pressure at 200-400 torr, the rotation speed of the graphite substrate is controlled at 500-1200 rpm, N2 and H2 are introduced as carrier gases, NH3 is introduced as the N (nitrogen) source, TMGa at a flow rate of 20-100 sccm is introduced as the Ga (gallium) source, and TMAl at a flow rate of 20-100 sccm is introduced as the Al (aluminum) source, thereby growing an AlGaN low-temperature nucleation layer, and controlling the thickness of the deposited AlGaN low-temperature nucleation layer to be 30-100 nm. As an example of the invention, a flow rate of 50 sccm of TMGa and a flow rate of 30 sccm of TMAl can be specifically introduced, and the thickness of the deposited AlGaN low-temperature nucleation layer is preferably controlled to be 70 nm.

[0074] Furthermore, in this embodiment of the invention, an undoped u-GaN layer is deposited on the low-temperature nucleation layer. The undoped u-GaN layer is formed by high-temperature deposition. Specifically, the deposition process involves controlling the temperature of the reaction chamber at 1100℃-1150℃, the pressure at 100-500 torr, the rotation speed of the graphite substrate at 500-1200 rpm, introducing N2 and H2 as carrier gases, introducing NH3 as the N (nitrogen) source, and introducing TMGa at a flow rate of 200-1000 sccm as the Ga (gallium) source, thereby growing an undoped u-GaN layer. The thickness of the deposited undoped u-GaN layer is controlled to be 300-800 nm. As an example of the invention, a flow rate of 500 sccm of TMGa can be introduced, and the thickness of the deposited undoped u-GaN layer is preferably controlled to be 400 nm.

[0075] Step S13: Deposit an insertion layer on the undoped u-GaN layer. The insertion layer includes a first sublayer, a second sublayer, and a third sublayer deposited sequentially. The first sublayer is Mg grown at low temperature and high pressure. x The N-layer consists of a second sublayer comprising periodically alternating layers of high-pressure grown GaN and low-pressure grown Al. y Ga 1-y The Nth layer, and the third sublayer, are Al layers grown at high temperature and low pressure. z Ga 1-z N layers.

[0076] In this embodiment of the invention, the first sublayer is Mg grown under low temperature and high pressure. xThe N-layer is deposited on an undoped u-GaN layer. The specific deposition process involves controlling the growth temperature in the reaction chamber at 800℃-900℃, the growth pressure at 300-500 torr, and the rotation speed of the graphite substrate at 500-1200 rpm. N2 and H2 are introduced as carrier gases, NH3 is introduced as the N (nitrogen) source, and magnesia-dicerocene is introduced at a flow rate of 50-200 sccm as the Mg source, thus growing Mg. x N layer, and control the thickness of the first sublayer deposited to be 3-10 nm, wherein Mg x The value of x in the N layer ranges from 0.1 to 0.3. Referring to the above-described fabrication process for the undoped u-GaN layer, since the epitaxial wafer warps significantly after high-temperature growth of the undoped u-GaN layer, low-temperature (800℃-900℃) growth of the first sublayer helps release underlying stress and alleviate warping. Meanwhile, high-pressure growth of Mg... x The N layer is mainly for forming metal islands, which can induce the three-dimensional growth of the second sublayer. At the same time, the high pressure condition is conducive to the incorporation of Mg and also to three-dimensional growth. Furthermore, during subsequent growth, Mg atoms can be used as positioning atoms to grow and merge the islands.

[0077] In this embodiment of the invention, the second sublayer consists of periodically alternating layers of high-pressure grown GaN and low-pressure grown Al. y Ga 1-y The process involves alternating N-layer growth, with the second sublayer deposited on top of the first sublayer. In other words, the initial layer is specifically Mg. x A GaN layer grown under high pressure is deposited on the first sublayer of the N-layer, followed by a low-pressure grown Al layer. y Ga 1-y An N-layer is deposited, followed by periodically alternating GaN and Al layers. y Ga 1-y N layers are combined to form the second sub-layer. In this embodiment, the second sub-layer consists of GaN and Al layers. y Ga 1-y The number of alternating N-layer stacks is 3-20; as an example of the present invention, the number of cycles is preferably 15, that is, the second sub-layer consists of a GaN layer and an Al layer. y Ga 1-y The structure consists of N alternating layers stacked 15 times. Furthermore, the total thickness of the second sublayer is 0.5-1 μm, Al... y Ga 1-y The range of y values ​​in layer N is: 0.05 ≤ y ≤ 0.2.

[0078] Specifically, the deposition process of the GaN layer in the second sublayer is as follows: the temperature of the reaction chamber is controlled at 1020-1050℃, the pressure is controlled at 300-500 torr, the rotation speed of the graphite substrate is controlled at 500-1200 rpm, only N2 is introduced as the carrier gas and H2 is not introduced, NH3 is introduced as the N (nitrogen) source and TMGa is introduced as the Ga (gallium) source, so that a high-pressure GaN layer is grown. At this time, the GaN layer is grown under high pressure with a growth pressure of 300-500 torr, and N2 is used as the carrier gas during the growth process. Since N2 has a large viscosity coefficient, it is conducive to three-dimensional growth. At this time, the islands in this layer are vertically grown with Mg metal islands as the core.

[0079] Specifically, in the second sub-layer Al y Ga 1-y The specific deposition process for the N-layer is as follows: the temperature of the reaction chamber is controlled at 1020-1050℃, the pressure at 100-200 torr, and the rotation speed of the graphite substrate is controlled at 500-1200 rpm. Simultaneously, N2 and H2 are introduced as carrier gases, NH3 is introduced as the N (nitrogen) source, TMGa as the Ga (gallium) source, and TMAl as the Al (aluminum) source, resulting in the deposition of low-pressure grown Al. y Ga 1-y N layers. At this time, Al y Ga 1-y The N-layer is grown under low pressure, with a growth pressure of 100-200 torr. N2 and H2 are introduced as carrier gases during the growth process, with the introduction of H2 favoring two-dimensional growth and enabling the three-dimensional island to grow laterally.

[0080] Furthermore, by periodically alternating layers of GaN and Al... y Ga 1-y The N-layer allows the three-dimensional islands to grow both vertically and horizontally, until the islands merge and fill in the two-dimensional growth, eventually depositing the second sublayer.

[0081] In this embodiment of the invention, the third sublayer is Al grown at high temperature and low pressure. z Ga 1-z The N layer, which is deposited on the second sublayer, has Al z Ga 1-z The specific deposition process for the N-layer is as follows: the temperature of the reaction chamber is controlled at 1100-1150℃, the pressure at 100-200 torr, and the rotation speed of the graphite substrate is controlled at 500-1200 rpm. Simultaneously, N2 and H2 are introduced as carrier gases, NH3 is introduced as the N (nitrogen) source, TMGa as the Ga (gallium) source, and TMAl as the Al (aluminum) source, resulting in the deposition of Al layers grown at high temperature and low pressure. z Ga 1-zN layers were deposited, and the thickness of the third sublayer was controlled to be 0.3-0.5 μm, while Al... z Ga 1-z The z-value range in the N-layer is 0.1 ≤ z ≤ 0.3. Furthermore, the total thickness of the intercalation layers is 1-1.5 μm. The third layer is grown at a high temperature of 1100-1150℃, which increases the mobility of adsorbed atoms and suppresses defect formation. Simultaneously, the third sublayer is grown under low pressure, which is beneficial for two-dimensional growth. Therefore, the high-temperature, low-pressure growth conditions are conducive to improving lattice quality. Furthermore, Al is selected for the third sublayer. z Ga 1-z The GaN layer, with its much stronger covalent bonds between Al and N atoms than between Ga and N atoms, maintains the integrity of the GaN lattice and reduces defect formation. Furthermore, the small size of Al atoms facilitates filling vacancies in the epitaxial layer, thus providing a blocking and twisting effect on dislocations.

[0082] Therefore, by centering on the Mg metal atoms of the first sublayer in the insertion layer, growing and merging the three-dimensional islands of the second sublayer to form a two-dimensional growth, and finally growing a high-temperature third sublayer to repair defects and prevent further defect growth, this method of first performing three-dimensional growth and then gradually healing and transitioning to two-dimensional growth is beneficial for obtaining an epitaxial layer with better lattice quality. This achieves the purpose of releasing the underlying stress and alleviating warping, while ensuring good lattice quality and not affecting antistatic capability. At the same time, due to stress release and the alleviation of warping, it is beneficial for the incorporation of Si in the subsequently grown N-type GaN layer, which reduces the operating voltage, effectively improves the surface flatness of the epitaxial wafer, and reduces edge fogging and cracking.

[0083] Step S14: Sequentially deposit an N-type GaN layer, a stress relief layer, a multiple quantum well layer, a P-type electron blocking layer, and a P-type GaN layer on the insertion layer.

[0084] In this embodiment of the invention, the specific deposition process for depositing an N-type GaN layer on the insertion layer is as follows: the reaction chamber temperature is controlled at 1100-1150℃, the pressure is controlled at 100-500 torr, the graphite substrate rotation speed is controlled at 500-1200 rpm, N2 and H2 are introduced as carrier gases, NH3 is introduced as the N (nitrogen) source, TMGa with a flow rate of 200-1000 sccm is introduced as the Ga (gallium) source, and SiH4 is introduced as the N-type dopant, while the Si (silicon) doping concentration is 5×E. 18 atoms / cm 3 -1×E 19 atoms / cm 3This allows for the growth of a Si-doped N-type GaN layer, with the thickness of the deposited N-type GaN layer controlled to be 1-3 μm. In a preferred embodiment of the invention, the TMGa flow rate is preferably 500 s ccm, and the Si doping concentration is preferably 7 × E. 18 atoms / cm 3 The thickness of the deposited N-type GaN layer is preferably controlled to be 2 μm.

[0085] This layer serves as the primary epitaxial layer for providing electrons. Therefore, SiH4 is introduced during GaN growth to provide Si elements, where Si is a tetravalent element and Ga is a trivalent element in GaN. When Si atoms replace Ga atoms, they provide electrons, thus forming an N-type GaN layer that provides electrons. At the same time, by doping with an appropriate concentration of Si, the defects and vacancies in the GaN material can be filled effectively, thereby repairing dislocations and preventing further extension of dislocations.

[0086] Furthermore, in this embodiment of the invention, the stress relief layer is formed by alternatingly growing GaN and InGaN layers in a periodic manner. Specifically, the stress relief layer is deposited on an N-type GaN layer; that is, a GaN layer is first deposited on the N-type GaN layer, then an InGaN layer is deposited on the GaN layer, and then the GaN and InGaN layers are periodically deposited alternately to form the stress relief layer. This stress relief layer is mainly used to release the underlying stress, preparing for the growth of multiple quantum well layers. In this embodiment, the number of alternating GaN and InGaN layers in the stress relief layer is 3-8; as an example of the invention, the number of alternating layers is preferably 5, that is, the second sublayer is composed of 5 alternating layers of GaN and InGaN layers. Furthermore, the total thickness of the stress relief layer is 50-300 nm, and the molar proportion of In in the InGaN layer of the stress relief layer is 10%-20%.

[0087] Specifically, the deposition process of the GaN layer in the stress relief layer is as follows: the temperature of the reaction chamber is controlled at 700-950℃, the pressure is controlled at 100-500 torr, the rotation speed of the graphite substrate is controlled at 500-1200 rpm, N2 and H2 are introduced as carrier gases, NH3 is introduced as the N (nitrogen) source, and TMGa with a flow rate of 50-300 sccm is introduced as the Ga (gallium) source, so that the GaN layer is grown and the thickness of the deposited GaN layer is controlled to be 10 nm.

[0088] Furthermore, the specific deposition process of the InGaN layer in the stress relief layer is as follows: the temperature of the reaction chamber is controlled at 700-950℃, the pressure is controlled at 100-500 torr, the rotation speed of the graphite substrate is controlled at 500-1200 rpm, N2 and H2 are introduced as carrier gases, NH3 is introduced as the N (nitrogen) source, TEGa with a flow rate of 50-1000 sccm is introduced as the Ga (gallium) source, and TMIn with a flow rate of 300-1000 sccm is introduced as the In (indium) source, so that the InGaN layer is grown, and the thickness of the deposited InGaN layer is controlled to be 3nm.

[0089] Furthermore, in this embodiment of the invention, the multiple quantum well layer is fabricated by periodically alternatingly growing quantum well layers and quantum barrier layers. Specifically, the quantum well layer is first stacked on the stress relief layer, and then the quantum barrier layer is stacked on top of the quantum well layer. Then, the quantum well layers and quantum barrier layers are periodically alternatingly stacked to finally form the multiple quantum well layer. In this embodiment, the number of alternating stacking periods of the quantum well layers and quantum barrier layers is 3-15; as a preferred embodiment of the invention, the number of periods can be 10, that is, the multiple quantum well layer is composed of 10 alternating stackings of quantum well layers and quantum barrier layers. Further, the quantum well layer is an InGaN layer, and the quantum barrier layer is a GaN layer. As an example of the invention, the thickness of a single quantum well layer is 2-5 nm, the thickness of a single quantum barrier layer is 3-15 nm, and the molar proportion of In component in the InGaN layer of the multiple quantum well layer is 10%-35%.

[0090] Specifically, the reaction chamber for growing the quantum well layer is heated to 720℃-800℃, the pressure is 100-500 torr, the graphite substrate rotation speed is 600-1000 rpm, NH3 is introduced as the N (nitrogen) source, TEGa at a flow rate of 300-500 sccm is introduced as the Ga (gallium) source, and TMIn at a flow rate of 1500-2500 sccm is introduced as the In (indium) source, thereby growing a Si-doped InGaN quantum well layer, and controlling the thickness of the deposited InGaN quantum well layer to be 2-5 nm. In a preferred embodiment of the present invention, the thickness of the quantum well layer is 3 nm.

[0091] Furthermore, the reaction chamber temperature for growing the quantum barrier layer is 830-950℃, the pressure is 100-500 torr, the rotation speed of the graphite pedestal supporting the substrate is 600-1000 rpm, NH3 is introduced as the N (nitrogen) source, and TEGa with a flow rate of 500-800 sccm is introduced as the Ga (gallium) source, so that a GaN quantum barrier layer is grown, and the thickness of the deposited GaN quantum barrier layer is controlled to be 3-15 nm. In a preferred embodiment of the present invention, the thickness of the quantum barrier layer is 10 nm.

[0092] Furthermore, in this embodiment of the invention, the P-type electron blocking layer comprises periodically alternating layers of Al. a Ga 1-a N layers and In b Ga 1-b N layers, specifically, its Al a Ga 1-a The N-layer is first deposited on the multi-quantum-well layer, In b Ga 1-b N layer redeposition on Al a Ga 1- a On layer N, Al is then periodically and alternately stacked. a Ga 1-a N layers and In b Ga 1-b The N-layer is used to ultimately form the P-type electron blocking layer. In this embodiment, Al... a Ga 1-a N layers and In b Ga 1-b The number of alternating N-layer stacks is 3-15; as a preferred embodiment of the present invention, the number of cycles can be 8, that is, its P-type electron blocking layer is composed of Al a Ga 1-a N layers and In b Ga 1-b It consists of N alternating layers stacked eight times. Furthermore, Al a Ga 1-a The range of values ​​for 'a' in layer N is: 0.05 ≤ a ≤ 0.2, In b Ga 1-b The value of b in the N-layer is in the range of 0.1≤b≤0.5; the total thickness of the P-type electron blocking layer is 20-50nm.

[0093] Specifically, the growth of Al a Ga 1-a The N-layer growth chamber was maintained at a temperature of 900℃-1000℃ and a pressure of 100-500 torr. The graphite substrate rotation speed was 600-1200 rpm. NH3 was introduced as the N (nitrogen) source, TMGa at a flow rate of 50-500 sccm was introduced as the Ga (gallium) source, and TMAl at a flow rate of 50-500 sccm was introduced as the Al (aluminum) source, thus growing Al... a Ga 1-a N layers.

[0094] Furthermore, growth In b Ga 1-bThe reaction chamber temperature for N was 900℃-1000℃, the pressure was 100-500 torr, the graphite substrate rotation speed was 600-1200 rpm, NH3 was introduced as the N (nitrogen) source, TMGa at a flow rate of 50-500 sccm was introduced as the Ga (gallium) source, and TMIn at a flow rate of 100-500 sccm was introduced as the In (indium) source, thus growing In. b Ga 1-b N layers.

[0095] Furthermore, in this embodiment of the invention, the specific deposition process for depositing a P-type GaN layer on a P-type electron blocking layer is as follows: the reaction chamber temperature is controlled at 800-1000℃, the pressure is controlled at 100-300 torr, the rotation speed of the graphite disk supporting the substrate is controlled at 800-1200 rpm, NH3 is introduced as the N (nitrogen) source, and TEGa with a flow rate of 600-1100 sccm is introduced as the Ga (gallium) source. During GaN growth, Mg2+ (CP2Mg) is introduced as the P-type dopant, and the Mg (magnesium) doping concentration is 5×E. 17 atoms / cm 3 -1×E 20 atoms / cm 3 This allows for the growth of Mg-doped P-type GaN layers, with the thickness of the deposited P-type GaN layers controlled to be 200-300 nm.

[0096] In summary, the method for fabricating a light-emitting diode epitaxial wafer in the above embodiments of the present invention involves setting an insertion layer between an undoped u-GaN layer and an N-type GaN layer. This insertion layer includes a first sub-layer, a second sub-layer, and a third sub-layer. The first sub-layer is Mg grown under low temperature and high pressure. x The N-layer consists of a second sublayer comprising periodically alternating layers of high-pressure grown GaN and low-pressure grown Al. y Ga 1-y The Nth layer, and the third sublayer, are Al layers grown at high temperature and low pressure. z Ga 1-z In the N-layer, the first sublayer is grown at a low temperature, which releases the underlying stress and alleviates the underlayer warping caused by the high-temperature growth of the undoped u-GaN layer; while Mg is grown under high-pressure conditions. x The N-layer is primarily for forming metal islands, which allows for the induction of three-dimensional growth in the second sublayer. High pressure conditions also facilitate the incorporation of Mg, promoting three-dimensional growth. Furthermore, Mg atoms serve as anchoring atoms for the subsequent island growth and merging. High-pressure growth of the GaN layer in the second sublayer promotes three-dimensional growth, where the islands grow vertically with Mg metal islands at their cores. Meanwhile, the growth of Al in the second sublayer... y Ga 1-yThe low-pressure growth of N-layers is conducive to two-dimensional growth, thereby enabling the lateral growth of three-dimensional islands. This is achieved through the periodic alternating stacking of GaN and Al layers. y Ga 1- y The N-layer allows for a combination of vertical and horizontal growth of the three-dimensional islands, until the islands merge and fill to form a two-dimensional structure. The third sublayer is grown at high temperature, which increases the mobility of adsorbed atoms and suppresses defect formation. Simultaneously, the third sublayer is grown at low pressure, which is beneficial for two-dimensional growth. Therefore, the high-temperature, low-pressure growth conditions contribute to improved lattice quality. Furthermore, the covalent bond strength between Al and N atoms is much greater than that between Ga and N atoms, maintaining the integrity of the GaN lattice and reducing defect formation. The small size of Al atoms also facilitates filling vacancies in the epitaxial layers, providing a blocking and twisting effect on dislocations. This method, which involves growing a three-dimensional island in the second sublayer centered on Mg metal atoms in the first sublayer of the insertion layer to form a two-dimensional growth layer, and finally growing a high-temperature third sublayer to repair defects and prevent further defect growth, is beneficial for obtaining epitaxial layers with better lattice quality. This achieves the goals of releasing the underlying stress and alleviating warping while ensuring good lattice quality and not affecting antistatic properties. At the same time, the stress release and warping relief facilitate the incorporation of Si into the subsequently grown N-type GaN layer, reducing the operating voltage, effectively improving the surface flatness of the epitaxial wafer, reducing edge fogging and cracking, and solving the problems of multiple defects and decreased surface flatness in existing epitaxial wafers.

[0097] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0098] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that, include: A substrate, and a low-temperature nucleation layer, an undoped u-GaN layer, an insertion layer, an N-type GaN layer, a stress-relieving layer, a multiple quantum well layer, a P-type electron blocking layer and a P-type GaN layer sequentially stacked on the substrate; The insertion layer comprises a first sublayer, a second sublayer, and a third sublayer sequentially stacked on the undoped u-GaN layer, wherein the first sublayer is Mg grown at low temperature and high pressure. x The N-layer, the second sub-layer comprising periodically alternating layers of high-pressure grown GaN and low-pressure grown Al. y Ga 1-y N layers, the third sublayer being Al grown at high temperature and low pressure. z Ga 1-z N layers; In the first sub-layer, the Mg x The value of x in layer N ranges from 0.1 to 0.3, and the thickness of the first sublayer is 3-10 nm. In the second sub-layer, the Al y Ga 1-y The value of y in layer N ranges from 0.05 to 0.

2. The total thickness of the second sublayer is 0.5-1 μm. The GaN layer and Al in the second sublayer... y Ga 1-y The number of cycles for N alternating layers is 3-20; In the third sub-layer, the Al z Ga 1-z The value of z in layer N is in the range of 0.1≤z≤0.3, and the thickness of the third sublayer is 0.3-0.5um.

2. The light-emitting diode epitaxial wafer according to claim 1, characterized in that, The stress relief layer comprises periodically alternating GaN and InGaN layers, with 3-8 alternating stacking periods. The total thickness of the stress relief layer is 50-300 nm, and the molar proportion of In component in the InGaN layer of the stress relief layer is 10%-20%.

3. The light-emitting diode epitaxial wafer according to claim 1, characterized in that, The multiple quantum well layer includes periodically alternating quantum well layers and quantum barrier layers, and the number of alternating stacking periods is 3-15. The quantum well layer is an InGaN layer, the quantum barrier layer is a GaN layer, and the molar proportion of In component in the InGaN layer of the multi-quantum well layer is 10%-35%. The thickness of a single quantum well layer is 2-5 nm, and the thickness of a single quantum barrier layer is 3-15 nm.

4. The light-emitting diode epitaxial wafer according to claim 1, characterized in that, The P-type electron blocking layer comprises periodically alternating layers of Al a Ga 1-a N layers and In b Ga 1-b N layers, with an alternating stacking period of 3-15; The Al a Ga 1-a The value range of 'a' in layer N is: 0.05 ≤ a ≤ 0.2, where In... b Ga 1-b The value range of b in layer N is: 0.1 ≤ b ≤ 0.5; The total thickness of the P-type electron blocking layer is 20-50 nm.

5. The light-emitting diode epitaxial wafer according to claim 1, characterized in that, The low-temperature nucleation layer is an AlGaN layer, and the thickness of the low-temperature nucleation layer is 30-100nm; The thickness of the undoped u-GaN layer is 300-800 nm; The total thickness of the insertion layer is 1-1.5 μm; The thickness of the N-type GaN layer is 1-3 μm, and the Si doping concentration in the N-type GaN layer is 5 × E. 18 -1×E 19 atoms / cm 3 ; The thickness of the p-type GaN layer is 200-300 nm, and the doping concentration of Mg in the p-type GaN layer is 5 × E. 17 -1×E 20 atoms / cm 3 .

6. A method for fabricating a light-emitting diode epitaxial wafer, characterized in that, The method includes: Provide a substrate; A low-temperature nucleation layer and an undoped u-GaN layer are sequentially deposited on the substrate; An insertion layer is deposited on the undoped u-GaN layer. The insertion layer includes a first sublayer, a second sublayer, and a third sublayer deposited sequentially. The first sublayer is Mg grown at low temperature and high pressure. x The N-layer, the second sub-layer comprising periodically alternating layers of high-pressure grown GaN and low-pressure grown Al. y Ga 1-y N layers, the third sublayer being Al grown at high temperature and low pressure. z Ga 1-z N layers; An N-type GaN layer, a stress-relieving layer, a multiple quantum well layer, a P-type electron blocking layer, and a P-type GaN layer are sequentially deposited on the insertion layer.

7. The method for fabricating a light-emitting diode epitaxial wafer according to claim 6, characterized in that, The growth temperature of the first sublayer is 800-900℃, and the growth pressure is 300-500 torr. The growth temperature of the second sublayer is 1020-1050℃; The growth temperature of the third sublayer is 1100-1150℃, and the growth pressure is 100-200 torr.

8. The method for fabricating a light-emitting diode epitaxial wafer according to claim 7, characterized in that, The GaN layer in the second sublayer is grown using N2 as the carrier gas at a growth pressure of 300-500 torr. Al in the second sublayer y Ga 1-y The N layer is grown using N2 and H2 as carrier gases at a growth pressure of 100-200 torr.

9. A method for fabricating a light-emitting diode epitaxial wafer according to claim 6, characterized in that, In the first sub-layer, the Mg x The value of x in layer N ranges from 0.1 to 0.3, and the thickness of the first sublayer is 3-10 nm. In the second sub-layer, the Al y Ga 1-y The value of y in layer N ranges from 0.05 to 0.

2. The total thickness of the second sublayer is 0.5-1 μm. The GaN layer and Al in the second sublayer... y Ga 1-y The number of cycles for N alternating layers is 3-20; In the third sub-layer, the Al z Ga 1-z The value of z in layer N is in the range of 0.1≤z≤0.3, and the thickness of the third sublayer is 0.3-0.5um.

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