Adaptive Gate Drive for Power Switching Transistors in Switching Power Converters

Abstract

The present invention is titled "Adaptive Gate Drive for Power Switching Transistors in a Switching Power Supply Converter." The present invention provides a gate drive control circuit that charges the gate of a power switching transistor during the conduction period of the power switching transistor. During a first interval of this conduction period, the gate drive control circuit charges the gate through a lower resistance. During a second interval of this conduction period, the gate drive control circuit charges the gate through a higher resistance. Finally, during a third interval of this conduction period, the gate drive control circuit charges the gate through another lower resistance.

Description

Technical Field

[0001] This application relates to a switched-mode power converter, and more particularly, to a switched-mode power converter having an adaptive gate drive for a power switching transistor. Background Art

[0002] During the operation of a flyback converter, a primary-side controller controls a switching device of a power-switching metal-oxide-semiconductor field-effect transistor (MOSFET) connected to a primary winding of a transformer. This power-switching transistor is typically an NMOS transistor having a drain connected to the primary winding and a source grounded. Before the power switch is turned on, the drain is charged to (or above) the input voltage of the primary winding. The input voltage is derived from the rectification of an AC mains voltage, which can exceed 100V during the alternating cycle of the input voltage mains. When the power-switching transistor is fully turned on, the drain voltage is pulled to ground potential. During conduction of the power-switching transistor, the drain of the power-switching transistor thus experiences a relatively high rate of voltage change (dV / dt). This rapid change in the drain voltage of the power-switching transistor can cause undesirable electromagnetic interference (EMI).

[0003] To reduce EMI caused by switching of the power-switching transistor, the power-switching transistor is typically driven by a relatively complex drive circuit that includes a high-voltage Miller capacitor, a bipolar junction transistor, a diode, and an external resistor. These drive circuit components increase cost and occupy printed circuit board space. To avoid this cost and complexity, a known approach uses a simplified drive circuit to drive the power-switching transistor, which divides the conduction period or process into two intervals with different drive resistors. During a first interval of the conduction period, the gate driver drives the gate of the power-switching transistor through a higher drive resistor to reduce the rate of change of the drain-to-source voltage (dV / dt) across the power-switching transistor. Once the drain voltage has dropped low enough, the gate driver drives the power-switching transistor through a lower drive resistor to rapidly increase the gate voltage and fully turn on the power-switching transistor.

[0004] The timing between high-resistance and low-resistance driving of the power-switching transistor gate is based on an output signal from a comparator. This comparator can compare the drain-to-source voltage or the gate-to-source voltage of the power-switching transistor with a threshold voltage. Figure 1An example gate driver 100 is shown. The gate driver 100 charges and discharges the gate of a power switch transistor M1 connected to the primary winding L1 of a transformer to control the switching of the power switch transistor M1. The gate driver control circuit 105 adjusts a drive resistance for driving the gate voltage of the power switch transistor M1 in response to a comparator 110 that compares the gate voltage of the power switch transistor M1 with a threshold voltage. The gate driver control circuit 105 starts the conduction period by charging the gate of the power switch transistor M1 with a higher drive impedance. The gate voltage of the power switch transistor will eventually rise above the threshold voltage of the comparator 110, causing the comparator 110 to establish an output signal. As used herein, an output signal is considered to be "established" when the binary signal is logically true, regardless of whether the logic convention is a logic high or a logic low. In response to the comparator establishing the output signal, the gate driver control circuit 105 charges the gate of the power switch transistor with a lower drive impedance. This lower drive impedance is applied for the remainder of the conduction period of the power switch transistor.

[0005] Although the gate driver 100 avoids the complexity and cost of the Miller capacitor approach, using such a gate driver results in an unduly long delay or duration during the conduction period of the power switch transistor. Such a long conduction time reduces the effective duty cycle, which decreases the efficiency under heavy loads. Additionally, the transition time between the high-impedance drive interval and the low-impedance drive interval is not optimal, which in turn unfavorably extends the conduction time.

[0006] Accordingly, there is a need in the art for a power switch transistor in a switched-mode power converter drive circuit to have a short conduction time while maintaining low EMI. SUMMARY OF THE INVENTION

[0007] According to a first aspect of the present disclosure, there is provided a drive control circuit for a power switch transistor in a switched-mode power converter, the drive control circuit including: a gate drive circuit configured to drive a gate voltage of the power switch transistor through a variable gate drive resistance; and an adaptive drive control circuit configured to command the gate drive circuit to use a first gate drive resistance during a first interval of the conduction period of the power switch transistor, a second gate drive resistance during a second interval of the conduction period of the power switch transistor, and a third gate drive resistance during a third interval of the conduction period of the power switch transistor.

[0008] According to a second aspect of the present disclosure, there is provided a method of adjusting the gate drive resistance for a power switching transistor in a switched-mode power converter. The method includes: during an initial interval while the power switching transistor is conducting, when the gate voltage of the power switching transistor is less than a first threshold voltage, charging the gate of the power switching transistor through a first resistor; starting timing of a longest duration in response to the gate voltage of the power switching transistor being greater than the first threshold voltage; and during a second interval while the power switching transistor is conducting and before the longest duration expires, charging the gate of the power switching transistor through a second resistor.

[0009] According to a third aspect of the present disclosure, there is provided a switched-mode power converter. The switched-mode power converter includes: an inductor; a power switching transistor connected to the inductor; and a gate drive control circuit configured to: charge the gate of the power switching transistor through a first resistor during a first interval of conduction, charge the gate of the power switching transistor through a second resistor during a second interval of conduction, and charge the gate of the power switching transistor through a third resistor during a third interval of conduction.

[0010] These and other aspects of the present invention will be more fully understood by reading the following detailed description. When reading the following description of specific exemplary embodiments in conjunction with the accompanying drawings, other aspects, features, and embodiments will become apparent to those of ordinary skill in the art. Although features may be discussed with respect to certain embodiments and the following figures, all embodiments may include one or more of the advantageous features discussed herein. In other words, although one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various embodiments discussed herein. In a similar manner, although the exemplary embodiments may be discussed below as device, system, or method embodiments, it should be understood that such exemplary embodiments may be implemented in a variety of devices, systems, and methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Shows a conventional drive circuit for a power switching transistor in a switched-mode power converter.

[0012] Figure 2 Shows a flyback converter having an improved drive circuit according to one aspect of the present disclosure.

[0013] Figure 3 Shows an improved drive circuit according to one aspect of the present disclosure.

[0014] Figure 4illustrates additional details of an improved drive circuit in accordance with one aspect of the present disclosure. Figure 3

[0015] Figure 5 illustrates Figure 4 some operating waveforms of the improved drive circuit.

[0016] The embodiments of the present disclosure and their advantages are best understood by reference to the following detailed description. It should be understood that like reference numerals are used to identify like elements shown in one or more of the figures. Detailed Description

[0017] The present invention provides an improved drive control circuit for a switched-mode power converter. The following discussion will relate to a flyback converter in particular, but it should be understood that the improved drive control circuit disclosed herein can be advantageously used to drive any suitable power switching transistor, such as in a buck converter or a boost converter. Figure 2 An example flyback converter 200 including an improved drive control circuit 205 is shown. The flyback converter 200 includes a transformer T having a primary winding W1 and a secondary winding W2. During operation, the drive control circuit 205 charges the gate of a power switching transistor M1 connected to the primary winding W1 to turn on the power switching transistor M1 during the on-time. The primary winding W1 is also connected to an input voltage terminal carrying a rectified input voltage (V_IN). When the power switching transistor M1 is turned on, a primary winding current begins to flow through the primary winding W1 and the power switching transistor M1 to ground. Once a desired peak winding current is reached, a primary side controller (not shown) can control the drive control circuit 205 to turn off the power switching transistor M1. As used herein, "connected" means a direct electrical connection such as through a conductive lead or an electrical connection through an intervening element such as a resistor or a diode.

[0018] A secondary side controller U2 controls a synchronous rectification (SR) switching transistor connected between a loop output port and the secondary winding W2. The SR control responds to monitoring the drain-to-source voltage (VDS) across the SR switching transistor. Based on the drain-to-source voltage VDS, the SR controller detects whether the power switching transistor M1 has turned off so that the SR switching transistor can be turned on to allow the secondary winding current to flow and charge an output voltage Vout supported by an output capacitor C1.

[0019] Figure 3 ​The gate drive control circuit 205 is shown in more detail in. For clarity of illustration, the flyback converter is represented only by the primary winding L1, the power switch transistor M1, and the input capacitor C1 that supports the input voltage. The modulation control circuit 300 controls the gate drive control circuit 205 with a pulse width modulation (PWM) control signal, for example, to generate a desired on-time of the power switch transistor M1. The modulation control circuit 300 can be part of a primary side controller or part of a secondary side controller. If the modulation control circuit 300 is located on the secondary side of the transformer, the PWM control signal will be transmitted across a ground isolation channel such as an opto-isolator. Regardless of where the modulation control circuit 300 is located, it generates the PWM control signal in response to feedback on various operating signals such as the output voltage Vout or the input voltage Vin.

[0020] The gate drive control circuit 205 includes an adaptive drive control circuit 305, a gate drive circuit 315, and a gate voltage monitor 310. The gate voltage monitor 310 includes at least two comparators that compare the gate voltage (Vgate) of the power switch transistor with corresponding threshold voltages. Specifically, one comparator uses a lower first threshold voltage Vth1 and outputs a comparator output signal Vcomp1 when the gate voltage rises to Vth1. Similarly, a second comparator uses a relatively larger second threshold voltage Vth2 and outputs a comparator output signal Vcomp2 when the gate voltage rises to Vth2. Thus, there are at least three intervals from the turn-on delay to the end of turn-on of the power switch transistor, which will be further explained herein. The first interval T1 starts from the turn-on delay until the gate voltage rises to Vth1. The second interval T2 starts from the end of interval T1 until the gate voltage rises to Vth2 (Vth2 is greater than Vth1). The final interval T3 starts when the gate voltage rises above Vth2 until the end of the conduction period. In an alternative embodiment, the transition between intervals T2 and T3 can be responsive to a timer expiration. The timer can start timing when interval T2 starts. Alternatively, the transition between intervals T2 and T3 can be responsive to any event that occurs first: the gate voltage rising above Vth2 or the timer expiration.

[0021] The gate drive circuit 315 drives the gate voltage through a drive impedance that varies according to the currently active intervals T1, T2, and T3. During interval T1, the gate drive circuit 315 charges the gate through a lower drive impedance. However, during interval T2, the gate drive circuit 315 charges the gate through a higher drive impedance. Finally, during interval T3, the gate drive circuit 315 charges the gate through another lower drive impedance. In some embodiments, the drive impedance during interval T1 may be greater than the drive impedance during interval T3. However, the drive impedances used during intervals T1 and T2 may be the same in alternative embodiments. Regardless of whether the drive impedance during interval T3 is less than or equal to the drive impedance used during interval T1, the drive impedance during interval T2 may be greater than either of those used during intervals T1 and T3. Note, however, that increasing the drive impedance during a critical conduction mode of operation where a relatively large amount of power must be delivered to the load would be undesirable. The drive impedance in interval T2 may thus be the same as or even lower than the drive impedance used during interval T1 in such a mode of operation.

[0022] Based on the durations of intervals T1 and T2, the adaptive drive control circuit 305 adjusts at least the threshold voltage Vth1 such that the conduction time encompassing T1 and T2 is neither too long nor too short. If the conduction time is too long, the effective duty cycle is affected such that there may be insufficient energy under heavy loads. Conversely, if the conduction time is too short, the rate of change of the dV / dt voltage at the drain of the power switch transistor M1 is too large, such that excessive EMI is generated. In some embodiments, the adaptive drive control circuit 305 may adjust the threshold voltages Vth1 and Vth2 based on the ratios T1 / T2 and T2 / T3. For example, the adaptive drive control circuit 305 may include a counter that is timed by a clock signal to provide a count representative of the duration of each interval T1 and T2. Thus, the ratio T1 / T2 may be the ratio of the count determined in interval T1 to the count determined in interval T2. Similarly, the ratio T2 / T3 may be the ratio of the count determined in interval T2 to the count determined in interval T3. Additionally, the threshold voltage may also be adjusted in response to the ratio T1 / T3.

[0023] Figure 4The gate drive control circuit 205 is shown in more detail. The gate drive circuit 315 includes a plurality of PMOS transistors from the first PMOS transistor P1 to the nth transistor Pn, where n is a positive integer. The source of each PMOS transistor is connected to the power supply voltage terminal, and the drain is connected to the gate of the power switch transistor M1 through a corresponding resistor. For example, the drain of transistor P1 is connected to the gate of the power switch transistor through resistor Z1, the drain of transistor P2 is connected to the gate of the power switch transistor through resistor Z2, and so on, such that the drain of the nth transistor Pn is connected to the gate of the power switch transistor through resistor Zn. In some embodiments, the resistors can be conceptual, and these "resistors" can be internal resistors of the chip or the on-resistance of the transistors.

[0024] To generate a low drive impedance, the adaptive drive control circuit 305 can turn on all (or most) of the transistors P1 to Pn. The drive impedance increases as the number of turned-on transistors decreases. To control the corresponding drive impedance according to whether the interval is T1, T2, or T3, the adaptive drive control circuit 305 can include a logic circuit 400. The logic circuit 400 can include a state machine, a microcontroller, or a microprocessor. During operation, the logic circuit 400 responds to the PWM control signal and then turns on the power switch transistor M1 for a desired conduction time. For a large pulse width, the conduction period is relatively long, and for a smaller pulse width, the conduction period is shorter. The start of this conduction period can be coordinated by a clock signal from the clock 405. The logic circuit 400 turns on the corresponding transistors P1 to Pn according to the gate drive signals g1 to gn. If the gate drive signals of these transistors are charged to the power supply voltage, the corresponding transistors are turned off. When the logic circuit 400 grounds the drive signal, the corresponding transistor is turned on. In an alternative embodiment, a current source can be used to control the drive impedance of the power switch transistor M1 during the conduction period.

[0025] To detect the end of interval T1, the gate voltage monitor 310 includes a first comparator C1 that compares the power switch transistor gate voltage to a first threshold voltage Vth1. When the gate voltage rises to Vth1, comparator C1 asserts an output signal Vcomp1. Logic circuit 400 may also be configured as a timer to time a maximum duration with a clock signal from clock source 405. The expiration of the maximum duration will trigger the end of interval T2, and once the maximum duration times out, logic circuit 400 commands a transition from interval T2 to interval T3. Alternatively (or in combination with the timer), a second comparator C2 that compares the power switch transistor gate voltage to a second threshold voltage Vth2 may also determine the end of interval T2. In some embodiments, the end of interval T2 may be determined by the expiration of the maximum duration set by the timer or by a gate voltage exceeding Vth2, depending on which event occurs first. When the gate voltage rises to equal Vth2, comparator C2 asserts an output signal Vcomp2. To add additional characterization of the gate voltage waveform, the gate voltage monitor 310 may include additional comparators. For example, the gate voltage monitor 310 may include a plurality of comparators ranging from comparator C1 to an nth comparator Cn that produces an nth comparator output signal Vcompn. Each comparator compares the gate voltage to its own threshold voltage to then assert its own comparator output signal. In this way, logic circuit 400 may sample the gate voltage waveform of power switch transistor M1 more finely to adjust the durations of intervals T1 and T2 accordingly. To make the adjustment, logic circuit 400 may include a counter that counts in response to a clock signal such as from clock 405. Thus, the count in each interval represents the duration of each interval. Logic circuit 400 may then calculate ratios T1 / T2, T2 / T3, and / or T1 / T3, as discussed previously. Based on the durations of intervals T1, T2, and T3, logic circuit 400 commands adjustable voltage reference 410 to adjust to the threshold voltages of the comparators.

[0026] As is known in the MOSFET art, after the gate-to-source voltage of the power switching transistor M1 has reached the transistor threshold voltage, a Miller plateau period occurs. The drain voltage then begins to drop due to channel conduction, which tends to pull the gate voltage lower through the gate-to-drain parasitic capacitance of the power switching transistor M1. The gate-to-drain parasitic capacitance is highly non-linear, such that it is relatively small when the drain voltage begins to drop and increases in magnitude as the drain voltage approaches ground. The net result is that the gate voltage is relatively constant during the Miller plateau and the plateau ends once the gate-to-drain capacitance has discharged. However, due to the non-linearity of the gate-to-drain parasitic capacitance, the drain voltage can discharge sufficiently before the end of the Miller plateau. Therefore, it is beneficial to transition from interval T2 to interval T3 before the end of the Miller plateau. Thus, using a timer to trigger the end of interval T2 is advantageous for increasing the switching speed.

[0027] Consider the advantages of the improved gate drive control disclosed herein as compared to the conventional use of gate voltage and threshold voltage to trigger the transition from an initial interval of relatively high drive resistance to a final interval of relatively low drive resistance. Such a comparison must wait until the Miller plateau has ended, since the gate voltage is relatively constant during the Miller plateau and thus does not rise above the conventional fixed threshold voltage until the end of the Miller plateau. But as previously mentioned, due to the non-linearity of the gate-to-drain parasitic capacitance, most of the drain voltage drop occurs in the initial interval of the Miller plateau. The rapidly changing portion of the drain voltage should be controlled so as not to generate excessive EMI. But the drain voltage changes relatively slowly in the final interval of the Miller plateau, since the drain voltage has largely discharged in the initial interval. Therefore, the use of a timer for triggering the transition from interval T2 to interval T3 (as opposed to increasing the switching speed but still reducing EMI) is highly advantageous.

[0028] Figure 5Some operating waveforms of an example gate drive control circuit are shown. Before the start of interval T1, the gate voltage Vgate of the power switch transistor M1 is grounded, causing the power switch transistor M1 to turn off. The drain voltage Vdrain of the power switch transistor is equal to the input voltage at this time (assuming discontinuous conduction operation mode, where the power switch transistor switches slowly enough such that the resonant oscillation of the drain voltage has subsided before the start of interval T1). When the pulse width modulation command PWM is established, interval T1 begins. The gate voltage Vgate then begins to rise relatively rapidly during interval T1 because the drive resistance Rg1 is relatively low. When the gate voltage rises to the first threshold voltage Vth1, the first comparator C1 will establish the output signal Vcomp1. When the gate voltage exceeds the first threshold voltage Vth1, interval T2 begins, during which the drive resistance Rg2 can be relatively high. As previously discussed, the adaptive adjustment of the first threshold voltage causes the Miller plateau (Vplateau) to begin during interval T2. Subsequently, the timer expires, which triggers the end of interval T2 before the end of the Miller plateau. In interval T3, once the Miller plateau ends, the gate voltage begins to rise rapidly again to cross the second threshold voltage Vth2. During interval T3, the drive resistance Rg3 is relatively low. Interval T3 continues until the end of the conduction period of the power switch transistor. Referring again to Figure 4 , it should be understood that the gate drive circuit 315 may include a pull-down transistor (not shown) that is turned on to discharge the gate of the power switch transistor, thereby ending the conduction time of the power switch transistor.

[0029] As Figure 5 shown, the three drive resistances Rg1, Rg2, and Rg3 can be different. During some operating modes, such as during discontinuous conduction mode, Rg2 can be higher than Rg1 and Rg3. In some embodiments, Rg1 can be greater than Rg3 but less than Rg2. The adaptive control of the gate drive of the power switch transistor M1 is quite advantageous, as it increases the effective duty cycle by turning on the channel as quickly as possible during interval T1. Additionally, interval T2 does not need to extend across the entire Miller plateau but still reduces EMI. Moreover, the threshold adjustment ensures that an optimized gate drive will be achieved under various process and operating conditions.

[0030] Some of those skilled in the art will now realize that various modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of the present invention without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments shown and described herein, as they are only some examples thereof, but should be fully commensurate with the scope of the appended claims below and their functional equivalents.

Claims

1. A gate drive control circuit for a power switching transistor in a switched-mode power supply converter, comprising: A gate drive circuit configured to charge the gate of the power switching transistor through a variable gate drive resistance; And An adaptive drive control circuit configured to command the gate drive circuit to use a first gate drive resistance during a first portion of the conduction period of the power switching transistor, a second gate drive resistance during a second portion of the conduction period of the power switching transistor, and a third gate drive resistance during a third portion of the conduction period of the power switching transistor; And A gate voltage monitor configured to monitor the gate voltage of the power switching transistor, wherein the adaptive drive control circuit is further configured to end the first portion of the conduction period of the power switching transistor and transition to the second portion of the conduction period of the power switching transistor in response to the gate voltage monitor comparing the gate voltage of the power switching transistor with a first threshold voltage, wherein the gate voltage monitor comprises: A first comparator configured to compare the gate voltage of the power switching transistor with the first threshold voltage, wherein the adaptive drive control circuit is further configured to command the gate drive circuit to use the second gate drive resistance in response to an assertion of an output signal from the first comparator, and wherein the second gate drive resistance is greater than the first gate drive resistance.

2. The gate drive control circuit according to claim 1, wherein The gate voltage monitor further comprises: A second comparator configured to compare the gate voltage of the power switching transistor with a second threshold voltage.

3. The gate drive control circuit according to claim 1, wherein The adaptive drive control circuit is further configured to: time a maximum duration at the start of the second portion of the conduction period of the power switching transistor, and trigger a transition from the second portion of the conduction period of the power switching transistor to the third portion of the conduction period of the power switching transistor in response to the expiration of the maximum duration.

4. The gate drive control circuit according to claim 3, wherein, The adaptive drive control circuit is further configured to: adjust the first threshold voltage in response to the duration of the first portion of the conduction period of the power switching transistor, and in response to the duration of the second portion of the conduction period of the power switching transistor.

5. The gate drive control circuit according to claim 3, wherein, The maximum duration is less than the duration of the Miller plateau period of the gate voltage of the power switching transistor.

6. The gate driving control circuit according to claim 5, wherein, The adaptive drive control circuit is further configured to adjust the first threshold voltage and the second threshold voltage such that the first threshold voltage is less than the Miller plateau value of the gate voltage of the power switching transistor, and such that the second threshold voltage is greater than the Miller plateau value.

7. The gate drive control circuit according to claim 1, Among them, The gate drive circuit includes a plurality of transistors coupled between the gate of the power switch transistor and a power supply node. Among them, the adaptive drive control circuit includes a logic circuit configured to: command a first number of the plurality of transistors to turn on during a first portion of the conduction period of the power switch transistor, and command a second number of the plurality of transistors to turn on during a second portion of the conduction period of the power switch transistor.

8. The gate drive control circuit according to claim 7, wherein The first number is greater than the second number.

9. The gate drive control circuit according to claim 7, wherein, Each of the plurality of transistors is coupled to the gate of the power switch transistor through a corresponding resistor.

10. A method for adjusting the gate drive resistance of a power switch transistor in a switched-mode power supply converter, the method comprising: During an initial portion of the conduction period of the power switch transistor, when the gate voltage of the power switch transistor is less than a first threshold voltage, charging the gate of the power switch transistor through a first resistor; Starting timing of a maximum delay period in response to the gate voltage of the power switch transistor being greater than the first threshold voltage; During a second portion of the conduction period of the power switch transistor and before the maximum delay period expires, charging the gate of the power switch transistor through a second resistor.

11. The method according to claim 10, further comprising: In response to the expiration of the maximum delay period, during a third portion of the conduction period of the power switch transistor, charging the gate of the power switch transistor through a third resistor.

12. The method according to claim 11, wherein, The third resistor is less than the second resistor.

13. The method according to claim 10, further comprising: Adjusting the first threshold voltage such that the Miller plateau value of the gate voltage of the power switch transistor is greater than the first threshold voltage.

14. The method according to claim 10, further comprising: Discharging the gate voltage of the power switch transistor at the end of the conduction period of the power switch transistor.

15. A switched-mode power supply converter, the switched-mode power supply converter comprising: An inductor; A power switch transistor connected to the inductor; And A gate drive control circuit configured to: charge the gate of the power switch transistor through a first resistor during a first portion of the conduction period of the power switch transistor, charge the gate of the power switch transistor through a second resistor during a second portion of the conduction period, and charge the gate of the power switch transistor through a third resistor during a third portion of the conduction period, wherein the second resistor is greater than the third resistor, and wherein the gate drive control circuit includes: a first comparator configured to compare the gate voltage of the power switch transistor with a first threshold voltage and assert an output signal; and a timer for timing a maximum duration in response to the start of the second portion of the conduction period. Wherein, the gate drive control circuit is further configured to use a second resistor in response to an assertion of an output signal from the first comparator, and wherein the second resistor is greater than the first resistor.

16. The switching power supply converter according to claim 15, wherein, The gate drive control circuit further includes a logic circuit configured to: select the first resistor during the first portion of the conduction period when the output signal from the first comparator indicates that the gate voltage of the power switch transistor is less than the first threshold voltage, and select the second resistor during the second portion of the conduction period and before the maximum duration expires.

17. The switching power supply converter according to claim 16, wherein, The logic circuit is further configured to select the third resistor during the third portion of the conduction period in response to the expiration of the maximum duration.

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