A frequency error correction method, system, device and all-digital phase-locked loop

Abstract

The application discloses a frequency error correction method, system, device and full-digital phase-locked loop, and the method comprises the following steps: adjusting the actual output frequency of a digital control oscillator according to the value of a frequency coarse adjustment control word, so that the quantization value of the actual frequency difference between the actual output frequency and a target output frequency is less than a preset integer value; detecting the frequency difference between the actual output frequency and the target output frequency to obtain a detection frequency difference, quantizing the detection frequency difference to obtain a quantization value of the detection frequency difference; comparing the quantization value of the detection frequency difference with a set threshold value, and correcting the quantization value of the detection frequency difference according to the comparison result. The application corrects the detection frequency difference exceeding the threshold value by setting the threshold value, improves the accuracy of the frequency difference as feedback in the full-digital phase-locked loop system, and effectively reduces the frequency search times. The application can be widely applied to the full-digital phase-locked loop system.

Description

Technical Field

[0001] This invention relates to a fully digital phase-locked loop system, and more particularly to a frequency discrimination error correction method, system, device, and fully digital phase-locked loop. Background Technology

[0002] Phase-locked loops (PLLs) are mainly divided into analog charge-pump PLLs and all-digital PLLs. All-digital PLLs, due to their high integration, flexible configurability, rapid process portability, and phase noise characteristics comparable to analog PLLs, have been increasingly used in frequency synthesizers in the radio frequency (RF) field.

[0003] The all-digital phase-locked loop system adopts a different frequency and phase discrimination mechanism than the analog phase-locked loop system. Its signal processing needs to be carried out in a unified discrete time domain. Metastability will cause sampling errors in the signal required for frequency discrimination, resulting in a frequency difference result with a large error, which will affect the feedback accuracy of the all-digital phase-locked loop system and increase the locking time during the locking process.

[0004] There are currently three main approaches to solving this problem: First, use additional circuitry to reduce the probability of metastability, which will increase the complexity and area of ​​the circuit implementation. Second, reduce the bandwidth of the filter in the loop system, i.e., reduce the effect of feedback in the loop, which undoubtedly greatly increases the locking time. Third, average the frequency discrimination results over multiple cycles to reduce the error; however, averaging over multiple cycles also increases the locking time exponentially.

[0005] Therefore, existing technologies still need to be improved and refined. Summary of the Invention

[0006] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a frequency discrimination error correction method, system, device and all-digital phase-locked loop.

[0007] The technical solution adopted in this invention is:

[0008] A frequency discrimination error correction method includes the following steps:

[0009] The actual output frequency of the numerically controlled oscillator is adjusted according to the value of the frequency coarse adjustment control word so that the quantized value of the actual frequency difference between the actual output frequency and the target output frequency is less than the preset integer value.

[0010] The frequency difference between the actual output frequency and the target output frequency is detected to obtain the detected frequency difference. The detected frequency difference is then quantized to obtain the quantized value of the detected frequency difference.

[0011] The quantized value of the detection frequency difference is compared with a set threshold, and the quantized value of the detection frequency difference is corrected based on the comparison result.

[0012] Furthermore, adjusting the actual output frequency of the numerically controlled oscillator based on the value of the frequency coarse adjustment control word includes:

[0013] Based on the correspondence rule between the value of the frequency coarse adjustment control word and the actual output frequency of the numerically controlled oscillator, the value of the frequency coarse adjustment control word corresponding to the target output frequency of the numerically controlled oscillator is obtained;

[0014] The output frequency of the numerically controlled oscillator is adjusted according to the value of the obtained coarse frequency control word, and used as the actual output frequency.

[0015] Further, the step of detecting the frequency difference between the actual output frequency and the target output frequency to obtain the detected frequency difference, and quantizing the detected frequency difference to obtain the quantized value of the detected frequency difference, includes:

[0016] The rising edge of the clock signal of the numerically controlled oscillator is used to sample and synchronize the reference signal to obtain the synchronized signal after sampling.

[0017] The rising edge of the synchronization signal is used to sample the time digital signal of the time-to-digital converter to obtain the quantized data of the sampled time digital signal.

[0018] The quantized value of the detection frequency difference is obtained based on the target output frequency of the numerically controlled oscillator, the frequency of the reference signal, and the quantized data of the sampled time digital signal.

[0019] Further, the step of comparing the quantized value of the detection frequency difference with a set threshold, and correcting the quantized value of the detection frequency difference based on the comparison result, includes:

[0020] When the quantized value of the detection frequency difference is positive and greater than the set threshold, the quantized value of the detection frequency difference is decremented by one.

[0021] When the quantization value of the detection frequency difference is negative and the absolute value of the quantization value is less than the set threshold, the quantization value of the detection frequency difference is incremented by one.

[0022] Another technical solution adopted in this invention is:

[0023] A frequency discrimination error correction system, comprising:

[0024] The frequency output module is used to adjust the actual output frequency of the numerically controlled oscillator according to the value of the frequency coarse adjustment control word, so that the quantized value of the actual frequency difference between the actual output frequency and the target output frequency is less than the preset integer value.

[0025] The frequency difference detection module is used to detect the frequency difference between the actual output frequency and the target output frequency, obtain the detected frequency difference, quantize the detected frequency difference, and obtain the quantized value of the detected frequency difference.

[0026] The frequency difference correction module is used to compare the quantized value of the detected frequency difference with a set threshold, and correct the quantized value of the detected frequency difference based on the comparison result.

[0027] Furthermore, adjusting the actual output frequency of the numerically controlled oscillator based on the value of the frequency coarse adjustment control word includes:

[0028] Based on the correspondence rule between the value of the frequency coarse adjustment control word and the actual output frequency of the numerically controlled oscillator, the value of the frequency coarse adjustment control word corresponding to the target output frequency of the numerically controlled oscillator is obtained;

[0029] The output frequency of the numerically controlled oscillator is adjusted according to the value of the obtained coarse frequency control word, and used as the actual output frequency.

[0030] Further, the step of detecting the frequency difference between the actual output frequency and the target output frequency to obtain the detected frequency difference, and quantizing the detected frequency difference to obtain the quantized value of the detected frequency difference, includes:

[0031] The rising edge of the clock signal of the numerically controlled oscillator is used to sample and synchronize the reference signal to obtain the synchronized signal after sampling.

[0032] The rising edge of the synchronization signal is used to sample the time digital signal of the time-to-digital converter to obtain the quantized data of the sampled time digital signal.

[0033] The quantized value of the detection frequency difference is obtained based on the target output frequency of the numerically controlled oscillator, the frequency of the reference signal, and the quantized data of the sampled time digital signal.

[0034] Further, the step of comparing the quantized value of the detection frequency difference with a set threshold, and correcting the quantized value of the detection frequency difference based on the comparison result, includes:

[0035] When the quantized value of the detection frequency difference is positive and greater than the set threshold, the quantized value of the detection frequency difference is decremented by one.

[0036] When the quantization value of the detection frequency difference is negative and the absolute value of the quantization value is less than the set threshold, the quantization value of the detection frequency difference is incremented by one.

[0037] Another technical solution adopted in this invention is:

[0038] A frequency discrimination error correction device, comprising:

[0039] At least one processor;

[0040] At least one memory for storing at least one program;

[0041] When the at least one program is executed by the at least one processor, the at least one processor implements the method described above.

[0042] Another technical solution adopted in this invention is:

[0043] A fully digital phase-locked loop includes a frequency discrimination module, which uses a frequency discrimination error correction method as described above to correct frequency errors.

[0044] The beneficial effects of this invention are: by setting a threshold to correct the detection frequency difference exceeding the threshold, this invention improves the accuracy of the frequency difference used as feedback in the all-digital phase-locked loop system and effectively reduces the number of frequency searches; without increasing circuit complexity, it improves the feedback accuracy of the all-digital phase-locked loop system, reduces the locking time of the all-digital phase-locked loop, and achieves fast locking. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a flowchart illustrating a frequency discrimination error correction method according to an embodiment of the present invention;

[0047] Figure 2 This is a timing diagram for sampling synchronization of the reference signal in an embodiment of the present invention;

[0048] Figure 3 This is a timing diagram showing the metastable phenomenon that occurs during the sampling synchronization process in an embodiment of the present invention. Detailed Implementation

[0049] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0050] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0051] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0052] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0053] like Figure 1 As shown, this embodiment provides a frequency discrimination error correction method, including the following steps:

[0054] S1. Adjust the actual output frequency of the numerically controlled oscillator according to the value of the frequency coarse adjustment control word so that the quantized value of the actual frequency difference between the actual output frequency and the target output frequency is less than the preset integer value.

[0055] Specifically, step S1 includes steps S11-S12:

[0056] S11. Based on the correspondence rule between the value of the frequency coarse adjustment control word and the actual output frequency of the numerically controlled oscillator, obtain the value of the frequency coarse adjustment control word corresponding to the target output frequency of the numerically controlled oscillator.

[0057] S12. Adjust the output frequency of the numerically controlled oscillator according to the value of the obtained frequency coarse adjustment control word, and use it as the actual output frequency.

[0058] In some optional embodiments, the preset integer value is 1, meaning that the actual output frequency and the target output frequency are very close, and the quantization value of the frequency difference is less than 1.

[0059] S2. Detect the frequency difference between the actual output frequency and the target output frequency, obtain the detected frequency difference, quantize the detected frequency difference, and obtain the quantized value of the detected frequency difference.

[0060] Step S2 includes steps S21-S23:

[0061] S21. The rising edge of the clock signal of the numerically controlled oscillator is used to sample and synchronize the reference signal to obtain the synchronized signal after sampling.

[0062] S22. The rising edge of the synchronization signal is used to sample the time digital signal of the time digital converter to obtain the quantized data of the sampled time digital signal.

[0063] S23. Based on the target output frequency of the numerically controlled oscillator, the frequency of the reference signal, and the quantized data of the sampled time digital signal, obtain the quantized value of the detection frequency difference.

[0064] In some embodiments, the rising edge of the clock signal of the numerically controlled oscillator is used to sample and synchronize the reference signal to obtain a synchronized signal after sampling. The specific timing relationship is as follows: Figure 2 As shown, the reference signal is sampled at each rising edge of the clock signal. At time T1, the rising edge of the clock signal samples the reference signal as high level, and the synchronization signal outputs a high level at time T1, thus completing the sampling synchronization of the reference signal.

[0065] In practice, the clock signal and the reference signal are asynchronous. When the reference signal changes at a time other than the rising edge of the clock signal, the synchronization signal can complete the correct change at the next rising edge of the clock signal immediately following the change of the reference signal. When the reference signal changes at a time near the rising edge of the clock signal, the reference signal sampled at the rising edge of the clock signal is an uncertain signal. The synchronization signal may output a level signal that is the same as the reference signal at the rising edge of the clock signal, or it may output a level signal that is opposite to the reference signal at the rising edge of the clock signal. Therefore, errors may occur in the sampling synchronization process.

[0066] In a specific example, such as Figure 3 As shown, the reference signal changes around time T1, the rising edge of the clock signal is at time T1, and the reference signal is a high-level signal at time T1. Because the time when the reference signal changes is too close to the rising edge of the clock signal, the rising edge of the clock signal samples an uncertain signal from the reference signal. Synchronization signal 1 outputs a high-level signal at time T1, while synchronization signal 2 outputs a low-level signal at time T1 and only outputs a high-level signal at time T2, which is one clock cycle later than synchronization signal 1. This sampling synchronization error introduces an integer error into the quantization data of the time digital signal, which in turn introduces an integer error into the quantization value of the frequency difference of the detection result.

[0067] In fact, in this embodiment, the quantized value of the actual frequency difference is less than an integer. When the quantized value of the frequency difference of the detection result introduces an integer error, the quantized value of the frequency difference of the detection result may be greater than an integer.

[0068] In general, due to the existence of metastability, there will be an error of ±1 (this value is determined according to the specific system) in the difference between the detected actual output frequency and the target output frequency.

[0069] S3. Compare the quantized value of the detection frequency difference with the set threshold, and correct the quantized value of the detection frequency difference based on the comparison result.

[0070] Step S3 includes steps S31-S32:

[0071] S31. When the quantized value of the detection frequency difference is positive and greater than the set threshold, the quantized value of the detection frequency difference is reduced by one.

[0072] S32. When the quantization value of the detection frequency difference is negative and the absolute value of the quantization value is less than the set threshold, the quantization value of the detection frequency difference is incremented by one.

[0073] Specifically, in this embodiment, the threshold is set to a quantization integer of one. When the quantization value of the frequency difference of the detection result is greater than one, the quantization value of the frequency difference of the detection result is reduced by one; when the quantization value of the frequency difference of the detection result is less than negative one, the quantization value of the frequency difference of the detection result is increased by one.

[0074] In some embodiments, a range is set based on a predetermined threshold, such as -1 to +1. If the ideal difference is 0.24, but the detected difference is 1.24 due to the presence of error, then 1 is subtracted from it to correct the error.

[0075] As can be seen from the above, the embodiments of the present invention utilize frequency preset word technology to ensure that the quantized value of the actual frequency difference is less than an integer. By setting a threshold, the detected frequency difference exceeding the threshold is corrected, thereby improving the accuracy of the frequency difference as feedback in the all-digital phase-locked loop system, effectively reducing the number of frequency searches, and reducing the locking time of the all-digital phase-locked loop without increasing circuit complexity, thus achieving fast locking.

[0076] In summary, this embodiment has the following advantages and beneficial effects compared to the prior art:

[0077] (1) No additional circuitry is required to avoid metastability, which reduces the complexity of circuit implementation and the circuit area.

[0078] (2) It does not require reducing the bandwidth of the filter in the loop system, which can greatly reduce the lock-in time.

[0079] (3) It does not require averaging the frequency discrimination results over multiple periods, which can significantly shorten the lock-in time.

[0080] (4) Frequency preset word technology is used to ensure that the quantized value of the actual frequency difference is less than an integer. By setting a threshold, the detected frequency difference exceeding the threshold is corrected, which improves the accuracy of the frequency difference used as feedback in the all-digital phase-locked loop system, effectively reduces the number of frequency searches, and reduces the locking time of the all-digital phase-locked loop without increasing circuit complexity, thus achieving fast locking. This invention can be applied to all-digital phase-locked loop systems and is applicable to both the tracking stage and the post-locking stage.

[0081] This embodiment also provides a frequency discrimination error correction system, including:

[0082] The frequency output module is used to adjust the actual output frequency of the numerically controlled oscillator according to the value of the frequency coarse adjustment control word, so that the quantized value of the actual frequency difference between the actual output frequency and the target output frequency is less than the preset integer value.

[0083] The frequency difference detection module is used to detect the frequency difference between the actual output frequency and the target output frequency, obtain the detected frequency difference, quantize the detected frequency difference, and obtain the quantized value of the detected frequency difference.

[0084] The frequency difference correction module is used to compare the quantized value of the detected frequency difference with a set threshold, and correct the quantized value of the detected frequency difference based on the comparison result.

[0085] As a further optional implementation, adjusting the actual output frequency of the numerically controlled oscillator based on the value of the frequency coarse adjustment control word includes:

[0086] Based on the correspondence rule between the value of the frequency coarse adjustment control word and the actual output frequency of the numerically controlled oscillator, the value of the frequency coarse adjustment control word corresponding to the target output frequency of the numerically controlled oscillator is obtained;

[0087] The output frequency of the numerically controlled oscillator is adjusted according to the value of the obtained coarse frequency control word, and used as the actual output frequency.

[0088] As a further optional implementation, the step of detecting the frequency difference between the actual output frequency and the target output frequency, obtaining the detected frequency difference, and quantizing the detected frequency difference to obtain a quantized value of the detected frequency difference includes:

[0089] The rising edge of the clock signal of the numerically controlled oscillator is used to sample and synchronize the reference signal to obtain the synchronized signal after sampling.

[0090] The rising edge of the synchronization signal is used to sample the time digital signal of the time-to-digital converter to obtain the quantized data of the sampled time digital signal.

[0091] The quantized value of the detection frequency difference is obtained based on the target output frequency of the numerically controlled oscillator, the frequency of the reference signal, and the quantized data of the sampled time digital signal.

[0092] As a further optional implementation, comparing the quantized value of the detection frequency difference with a set threshold, and correcting the quantized value of the detection frequency difference based on the comparison result, includes:

[0093] When the quantized value of the detection frequency difference is positive and greater than the set threshold, the quantized value of the detection frequency difference is decremented by one.

[0094] When the quantization value of the detection frequency difference is negative and the absolute value of the quantization value is less than the set threshold, the quantization value of the detection frequency difference is incremented by one.

[0095] This embodiment of the frequency discrimination error correction system can execute the frequency discrimination error correction method provided in the method embodiment of the present invention, and can execute any combination of the implementation steps of the method embodiment, and has the corresponding functions and beneficial effects of the method.

[0096] This embodiment also provides a frequency discrimination error correction device, including:

[0097] At least one processor;

[0098] At least one memory for storing at least one program;

[0099] When the at least one program is executed by the at least one processor, the at least one processor performs the following: Figure 1 The method shown.

[0100] This embodiment of the frequency discrimination error correction device can execute a frequency discrimination error correction method provided in the method embodiment of the present invention, and can execute any combination of implementation steps of the method embodiment, and has the corresponding functions and beneficial effects of the method.

[0101] This embodiment also provides a fully digital phase-locked loop, including a frequency discrimination module, wherein the frequency discrimination module employs as follows: Figure 1 The present invention illustrates a frequency discrimination error correction method for correcting frequency errors.

[0102] This embodiment of a fully digital phase-locked loop can execute a frequency discrimination error correction method provided in the method embodiment of the present invention, and can execute any combination of implementation steps of the method embodiment, possessing the corresponding functions and beneficial effects of the method.

[0103] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0104] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the described functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0105] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0106] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0107] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0108] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0109] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0110] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0111] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A frequency discrimination error correction method, characterized in that, Includes the following steps: The actual output frequency of the numerically controlled oscillator is adjusted according to the value of the frequency coarse adjustment control word so that the quantized value of the actual frequency difference between the actual output frequency and the target output frequency is less than a preset integer value; the preset integer value is 1. The frequency difference between the actual output frequency and the target output frequency is detected to obtain the detected frequency difference. The detected frequency difference is then quantized to obtain the quantized value of the detected frequency difference. The quantized value of the detection frequency difference is compared with a set threshold, and the quantized value of the detection frequency difference is corrected based on the comparison result. The set threshold is 1.

2. The frequency discrimination error correction method according to claim 1, characterized in that, The adjustment of the actual output frequency of the numerically controlled oscillator based on the value of the frequency coarse adjustment control word includes: Based on the correspondence rule between the value of the frequency coarse adjustment control word and the actual output frequency of the numerically controlled oscillator, the value of the frequency coarse adjustment control word corresponding to the target output frequency of the numerically controlled oscillator is obtained; The output frequency of the numerically controlled oscillator is adjusted according to the value of the obtained coarse frequency control word, and used as the actual output frequency.

3. The frequency discrimination error correction method according to claim 1, characterized in that, The process of detecting the frequency difference between the actual output frequency and the target output frequency, obtaining the detected frequency difference, and quantizing the detected frequency difference to obtain its quantized value includes: The rising edge of the clock signal of the numerically controlled oscillator is used to sample and synchronize the reference signal to obtain the synchronized signal after sampling. The rising edge of the synchronization signal is used to sample the time digital signal of the time-to-digital converter to obtain the quantized data of the sampled time digital signal. The quantized value of the detection frequency difference is obtained based on the target output frequency of the numerically controlled oscillator, the frequency of the reference signal, and the quantized data of the sampled time digital signal.

4. The frequency discrimination error correction method according to claim 1, characterized in that, The step of comparing the quantized value of the detection frequency difference with a set threshold and correcting the quantized value of the detection frequency difference based on the comparison result includes: When the quantized value of the detection frequency difference is positive and greater than the set threshold, the quantized value of the detection frequency difference is decremented by one. When the quantization value of the detection frequency difference is negative and the absolute value of the quantization value is less than the set threshold, the quantization value of the detection frequency difference is incremented by one.

5. A frequency discrimination error correction system, characterized in that, include: The frequency output module is used to adjust the actual output frequency of the numerically controlled oscillator according to the value of the frequency coarse adjustment control word, so that the quantized value of the actual frequency difference between the actual output frequency and the target output frequency is less than the preset integer value. The preset integer value is 1; The frequency difference detection module is used to detect the frequency difference between the actual output frequency and the target output frequency, obtain the detected frequency difference, quantize the detected frequency difference, and obtain the quantized value of the detected frequency difference. The frequency difference correction module is used to compare the quantized value of the detected frequency difference with a set threshold, and correct the quantized value of the detected frequency difference based on the comparison result; the set threshold is 1.

6. The frequency discrimination error correction system according to claim 5, characterized in that, The adjustment of the actual output frequency of the numerically controlled oscillator based on the value of the frequency coarse adjustment control word includes: Based on the correspondence rule between the value of the frequency coarse adjustment control word and the actual output frequency of the numerically controlled oscillator, the value of the frequency coarse adjustment control word corresponding to the target output frequency of the numerically controlled oscillator is obtained; The output frequency of the numerically controlled oscillator is adjusted according to the value of the obtained coarse frequency control word, and used as the actual output frequency.

7. The frequency discrimination error correction system according to claim 5, characterized in that, The process of detecting the frequency difference between the actual output frequency and the target output frequency, obtaining the detected frequency difference, and quantizing the detected frequency difference to obtain its quantized value includes: The rising edge of the clock signal of the numerically controlled oscillator is used to sample and synchronize the reference signal to obtain the synchronized signal after sampling. The rising edge of the synchronization signal is used to sample the time digital signal of the time-to-digital converter to obtain the quantized data of the sampled time digital signal. The quantized value of the detection frequency difference is obtained based on the target output frequency of the numerically controlled oscillator, the frequency of the reference signal, and the quantized data of the sampled time digital signal.

8. The frequency discrimination error correction system according to claim 5, characterized in that, The step of comparing the quantized value of the detection frequency difference with a set threshold and correcting the quantized value of the detection frequency difference based on the comparison result includes: When the quantized value of the detection frequency difference is positive and greater than the set threshold, the quantized value of the detection frequency difference is decremented by one. When the quantization value of the detection frequency difference is negative and the absolute value of the quantization value is less than the set threshold, the quantization value of the detection frequency difference is incremented by one.

9. A fully digital phase-locked loop, characterized in that, It includes a frequency discrimination module, which uses the method described in any one of claims 1-4 to correct frequency errors.

10. A frequency discrimination error correction device, characterized in that, include: At least one processor; At least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method of any one of claims 1-4.

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