Low-reflection back-illuminated image sensor

Abstract

An image sensor for short wavelength light includes a semiconductor membrane, circuit elements formed on a first surface of the semiconductor membrane, and a boron-coated textured surface on a second surface of the semiconductor membrane. The textured surface includes a pseudo-random, periodic, and / or random distribution of right-angle pyramids, inverted-angle pyramids, and / or nanopyramids. The textured surface reduces reflection of incident light across a wide band in the DUV and VUV regions, thus increasing the amount of light absorbed and improving the efficiency of the image sensor. The reflectance can be further reduced by applying an anti-reflective coating to the textured surface. The image sensor can be a two-dimensional area sensor or a one-dimensional array sensor, and incorporated into an inspection system.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 943,173, filed December 3, 2019, by inventors Yung-Ho Alex Chuang, Yinying Xiaoli, Sisir Yalamanchili, John Fielden, and David Brown, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to image sensors suitable for sensing radiation in deep ultraviolet (DUV) and vacuum ultraviolet (VUV) wavelengths, and methods for manufacturing such image sensors. These sensors are suitable for use in photomask, mask, or wafer inspection systems and other applications. Background Technology

[0004] The integrated circuit industry needs inspection tools to analyze the ever-shrinking features of integrated circuits, photomasks, photomasks, solar cells, and charge-coupled devices at increasingly higher resolutions and to detect defects that are approximately or smaller than the size of those features.

[0005] In many cases, inspection systems operating at short wavelengths (e.g., shorter than about 250 nm) can provide this resolution. Specifically, for photomask or photomask inspection, it is desirable to inspect samples using wavelengths equal to or close to those used for photolithography (e.g., about 193.4 nm for contemporary photolithography and about 13.5 nm for future EUV photolithography), because the phase shift of the inspection light caused by the pattern will be the same as or very similar to the phase shift caused during photolithography. For inspecting patterned semiconductor wafers, inspection systems operating over a relatively wide wavelength range (e.g., a wavelength range encompassing wavelengths in the near-UV, DUV, and / or VUV ranges) can be advantageous, as a wide wavelength range reduces sensitivity to small changes in layer thickness or pattern size (which can cause large changes in reflectivity at individual wavelengths).

[0006] High signal-to-noise ratio (SNR) is required to detect small defects or particles on photomasks, photocopies, and semiconductor wafers. High photon or particle flux density is necessary to ensure a high SNR during high-speed inspection, as the statistical fluctuations in the number of detected photons (Poisson noise) are a fundamental limitation to SNR. In many cases, approximately 100,000 or more photons per pixel are required. Because inspection systems are typically used 24 hours a day with only brief shutdowns, detectors are exposed to high doses of radiation after just a few months of operation.

[0007] Photons with a vacuum wavelength of 250 nm have an energy of approximately 5 eV. The band gap of silicon dioxide is approximately 10 eV. Although such wavelength photons would seem impossible for silicon dioxide to absorb, silicon dioxide grown on a silicon surface must have some dangling bonds at the silicon interface because the silicon dioxide structure cannot perfectly match the structure of silicon crystals. Furthermore, because silicon dioxide is amorphous, some dangling bonds may also exist within the material. In fact, there will be a non-negligible density of defects and impurities within the oxide and at the interface with the underlying semiconductor that can absorb photons with deep UV wavelengths (specifically, photons with wavelengths shorter than approximately 250 nm). Moreover, at high radiative flux densities, two high-energy photons can arrive near the same location within a very short time interval (nanoseconds or picoseconds), which can cause electrons to be excited to the conduction band of silicon dioxide by rapid, consecutive absorption events or two-photon absorption.

[0008] A further requirement for sensors used in inspection, metrology, and related applications is high sensitivity. As explained above, a high signal-to-noise ratio is necessary. If the sensor cannot convert a large percentage of incident photons into a signal, then a higher intensity light source is needed to maintain the same inspection or measurement speed than a more efficient sensor in an inspection or metrology system. Higher intensity light sources expose optical instruments and the samples being inspected or measured to higher light intensities, which can cause damage or degradation over time. Higher intensity light sources will also be more expensive or, specifically, may be unavailable at DUV and VUV wavelengths. Silicon reflects a high percentage of DUV and VUV light incident upon it. For example, at wavelengths near 193 nm, silicon with a 2 nm oxide layer (e.g., a native oxide layer) on its surface reflects approximately 65% ​​of the light incident upon it. For wavelengths near 193 nm, growing an oxide layer of approximately 21 nm on the silicon surface reduces the reflectivity to close to 40%. A detector with 40% reflectivity is significantly more efficient than a detector with 65% reflectivity, but lower reflectivity and therefore higher efficiency are desired.

[0009] DUV and VUV wavelengths are strongly absorbed by silicon. These wavelengths are largely absorbed within a silicon surface of approximately 10 nm to tens of nm. The efficiency of a sensor operating at DUV or VUV wavelengths depends on the fraction of electrons generated by absorbed photons that can be collected before electron recombination. Silicon dioxide can form a high-quality interface with silicon with a low defect density. Most other materials (including many commonly used in anti-reflective coatings) result in a very high density of electrical defects at the silicon surface when deposited directly on silicon. This high density of electrical defects on the silicon surface may not be a problem for sensors intended to operate at visible wavelengths, as these wavelengths typically travel to within silicon at approximately 100 nm or more before absorption and are therefore largely unaffected by electrical defects on the silicon surface. However, the absorption of DUV and VUV wavelengths near the silicon surface causes electrical defects on the surface and / or within layers trapped on the surface to lead to a large fraction of generated electrons recombination and loss at or near the silicon surface, resulting in inefficient sensors. Therefore, controlling the state of the silicon surface to minimize photoelectron loss is crucial.

[0010] Therefore, there is a need for image sensors that can efficiently detect high-energy photons, overcoming some or all of the aforementioned drawbacks. Summary of the Invention

[0011] According to one or more embodiments of this disclosure, a low-reflection backlit image sensor is disclosed. In one illustrative embodiment, the image sensor includes a semiconductor thin film comprising an epitaxial layer, wherein the epitaxial layer includes a first surface and a second textured surface opposite the first surface. In another illustrative embodiment, the image sensor includes one or more circuit elements formed on the first surface of the epitaxial layer. In another illustrative embodiment, the image sensor includes a boron layer disposed on the second textured surface of the epitaxial layer. In another illustrative embodiment, the second textured surface includes a pseudo-random distribution of at least one of upright pyramids, chamfered pyramids, or nanocones. In another illustrative embodiment, the second textured surface includes a periodic distribution of at least one of upright pyramids, chamfered pyramids, or nanocones. In another illustrative embodiment, the second textured surface includes a random distribution of at least one of upright pyramids, chamfered pyramids, or nanocones. In another illustrative embodiment, the image sensor is incorporated into an inspection system.

[0012] According to one or more embodiments of this disclosure, a method for manufacturing a low-reflection backlit image sensor is disclosed. In one illustrative embodiment, the method includes forming an epitaxial layer on a substrate. In another illustrative embodiment, the method includes forming a gate layer on the substrate. In another illustrative embodiment, the method includes forming one or more circuit element layers on the gate layer. In yet another illustrative embodiment, the method includes thinning the substrate to create a thinned substrate that exposes at least a portion of the epitaxial layer. In another illustrative embodiment, the method includes pre-etching the exposed portion of the epitaxial layer. In yet another illustrative embodiment, the method includes generating a surface texture on the exposed surface of the epitaxial layer. In yet another illustrative embodiment, the method includes forming a boron layer on the surface texture.

[0013] It should be understood that the above general description and the following detailed description are for illustrative and explanatory purposes only and do not necessarily limit the invention. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention. Attached Figure Description

[0014] Those skilled in the art can better understand the many advantages of this disclosure by referring to the accompanying drawings.

[0015] Figure 1 A block diagram illustrating a characterization system according to one or more embodiments of the present disclosure.

[0016] Figure 2 A flowchart illustrating a method for manufacturing an image sensor according to an exemplary embodiment of the present disclosure is provided.

[0017] Figures 3A to 3I This invention describes various pseudo-random and periodic patterning methods for implementation in an image sensor according to one or more embodiments of the present disclosure.

[0018] Figure 4A This illustration shows a cross-sectional view of a portion of an image sensor having a low-reflectivity backlit boron-coated textured surface according to one or more embodiments of the present disclosure.

[0019] Figure 4B This illustration shows a cross-sectional view of a portion of an image sensor with a low-reflectivity backlit boron-coated textured surface, according to one or more additional embodiments of this disclosure.

[0020] Figure 4C This illustration shows a cross-sectional view of a portion of an image sensor with a low-reflectivity backlit boron-coated textured surface, according to one or more additional embodiments of this disclosure.

[0021] Figure 5The diagram illustrates the reflectance versus wavelength curves for various image sensors. Detailed Implementation

[0022] This disclosure has been specifically shown and described with respect to particular embodiments and specific features. The embodiments set forth herein are intended to be illustrative rather than limiting. It will be readily apparent to those skilled in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of this disclosure. The subject matter of the disclosure will now be described in detail with reference to the accompanying drawings.

[0023] Embodiments of this disclosure are directed to image sensors for semiconductor testing and metrology. Specifically, image sensors with high quantum efficiency and long lifetime operation against DUV and / or VUV radiation are disclosed. These image sensors are thinned from the back side, making them highly sensitive to radiation illuminating the back side of the image sensor (when these image sensors are backlit). The back-side silicon surface can be textured by wet chemical etching or other structuring methods (e.g., reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), ultrafast laser etching, electrochemical etching, electron beam lithography or photolithographic defining etching, and mechanical grooving) to form upright or chamfered pyramids, nanocones (or other conical structures) on the surface. The textured surface reduces reflection of broadband incident light across DUV and VUV, thus increasing absorbed light intensity.

[0024] Wet chemical etching is relatively inexpensive and a more mature process than other structuring methods because it is widely used in CMOS manufacturing. Known techniques for wet chemical pyramidal etching of (100)-oriented silicon surfaces use alkaline media such as alkali metal hydroxides, alkali metal carbonates, ammonia, or choline. Various etchants known in this technique include, for example, ethylenediamine catechol (EDP), hydrazine, sodium hydroxide (NaOH), sodium carbonate (Na₂CO₃), trisodium phosphate (Na₃PO₄), sodium silicate (Na₂SiO₃), potassium hydroxide (KOH), and tetramethylammonium hydroxide (TMAH). The most common formulations include water, NaOH or KOH, and an alcohol. The alcohol component can be either ethylene glycol or isopropanol. Known methods for wet chemical structural etching of silicon are only related to the generation of pyramidal textures.

[0025] Depending on the specific texturing process, surface texturing of a silicon substrate selectively removes portions of the material, resulting in upright or chamfered pyramidal structures. Consequently, the material density at the surface can be reduced, leading to a decrease in complex dielectric contrast, which in turn reduces the wavelength dependence of surface reflection.

[0026] A thin layer (e.g., between about 2 nm and about 20 nm thick) of high-purity amorphous boron is deposited on textured silicon. In some embodiments, one or more additional material layers may be coated on the boron. The thickness and material of each layer may be selected to increase the transmission of the wavelength of interest to the image sensor. In one embodiment, an anti-reflective coating may be deposited on top of the boron layer. The anti-reflective coating material may include one or more of magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium oxide (TiO2), and aluminum oxide (Al2O3).

[0027] A pinhole-free, interconnected, substantially pure boron layer with a thickness ranging from 2 to 5 nm (e.g., about 2 to about 4 nm, encompassing all ranges and values ​​accurate to 0.1 nm) can be formed on clean silicon using a high-temperature deposition process (e.g., between about 600°C and about 800°C) or a low-temperature deposition process (e.g., between about 350°C and about 450°C). The boron layer prevents silicon oxidation by reliably and hermetically sealing the silicon surface against oxidation. It should be noted that a few atomic percentages of oxygen (e.g., less than 10% or less than 5%) may remain at the interface between the boron layer and the silicon surface, but this oxygen content will not increase significantly over time (e.g., within a one-year period) due to the hermetically sealed environment. This low oxygen-to-silicon ratio means that there is no interconnected silicon dioxide layer at the interface.

[0028] The image sensors described herein can be fabricated using CCD (charge-coupled device) or CMOS (complementary metal-oxide-semiconductor) technology. The image sensors can be two-dimensional region sensors or one-dimensional array sensors.

[0029] Methods for manufacturing high-quantum-efficiency image sensors for DUV and / or VUV imaging are described. Image sensors manufactured according to these methods are capable of long-lifetime operation under high-throughput DUV and VUV radiation. These methods include process steps of forming a textured surface on a semiconductor (preferably silicon) wafer and depositing a high-purity amorphous boron layer on top of the textured silicon surface. An optional anti-reflective coating may be formed on top of the boron layer.

[0030] A testing system is also described. This testing system includes an illumination source, optics, and a detector. The optics are configured to guide and focus radiation from the illumination source onto the sample. The detector is configured to receive reflected or scattered light from the sample, wherein the optics are further configured to collect, guide, and focus the reflected or scattered light onto the detector. The detector may include one or more image sensors. At least one image sensor includes a semiconductor thin film, wherein the semiconductor thin film includes circuit elements formed on one surface of the semiconductor thin film and a boron-textured surface on the opposite surface of the semiconductor thin film. Optionally, an anti-reflective coating may be formed on top of the boron layer.

[0031] Figure 1 A simplified schematic diagram of a characterization system 100 according to one or more embodiments of the present disclosure is provided. In one embodiment, the characterization system 100 (or “tool”) includes a characterization subsystem 101 and a controller 114. The characterization system 100 may be configured as an inspection system or a metrology system. For example, the characterization system 100 may be an optical-based inspection system (or “tool”), a review system (or “tool”), or an image-based metrology system (or “tool”). In this regard, the characterization subsystem 101 may be (but is not limited to) an inspection subsystem or metrology subsystem configured to inspect or measure a sample 108. The characterization subsystem 101 of the characterization system 100 may be communicatively coupled to the controller 114. The controller 114 may receive measurement data from the detector assembly 104 of the characterization subsystem to characterize (e.g., inspect or measure) the structure on or in the sample 108 and / or control one or more portions of the characterization system 100.

[0032] Sample 108 may comprise any sample known in the art, such as (but not limited to) a wafer, photomask, photomask, or the like. In one embodiment, sample 108 may be positioned on stage assembly 112 to facilitate movement of sample 108. Stage assembly 112 may comprise any stage assembly known in the art, including (but not limited to) XY stages, R-θ stages, and the like. In another embodiment, stage assembly 112 is capable of adjusting the height of sample 108 during inspection to maintain focus on sample 108. In yet another embodiment, characterization subsystem 101 may be movable up and down during inspection to maintain focus on sample 108.

[0033] In another embodiment, the characterization system 100 includes an illumination source 102 configured to generate an illumination beam 111. The illumination source 102 may include any illumination source known in the art suitable for generating the illumination beam 111. For example, the illumination source 102 may emit DUV and / or VUV radiation. For example, the illumination source 102 may include one or more lasers. In another example, the illumination source 102 may include a broadband illumination source.

[0034] In another embodiment, the characterization system 100 includes an illumination branch 107 configured to direct illumination from illumination source 102 to sample 108. Illumination branch 107 may include any number and type of optical components known in the art. In one embodiment, illumination branch 107 includes one or more optical elements 103. In this regard, illumination branch 107 may be configured to focus illumination from illumination source 102 onto the surface of sample 108. It should be noted that the one or more optical elements 103 may include any optical elements known in the art, including (but not limited to) one or more lenses (e.g., objective lens 105), one or more mirrors, one or more polarizers, one or more prisms, one or more beam splitters, and the like.

[0035] In another embodiment, the collection branch 109 is configured to collect illumination reflected, scattered, diffracted, and / or emitted from the sample 108. In another embodiment, the collection branch 109 may guide and / or focus the illumination from the sample 108 onto the sensor 106 of the detector assembly 104.

[0036] Detector 104 may include one or more image sensors 106 as described herein. For example, one or more image sensors 106 of this disclosure may include (but are not limited to) boron-coated, textured, backlit CCD sensors and boron-coated, textured, backlit CMOS sensors. Detector 104 may include a two-dimensional array sensor or a one-dimensional line sensor.

[0037] In some embodiments of the inspection system 100, lines on the sample 108 are illuminated, and scattered and / or reflected light is collected in one or more dark-field and / or bright-field collection channels. In such embodiments, the image sensor may be a line sensor. In some embodiments of the inspection system 100, multiple points on the sample 108 are illuminated, and scattered and / or reflected light is collected in one or more dark-field and / or bright-field collection channels. In such embodiments, the image sensor may be a two-dimensional array sensor.

[0038] In another embodiment, the detector assembly 104 is communicatively coupled to one or more processors 116 of the controller 114. The one or more processors 116 may be communicatively coupled to a memory 118. The one or more processors 116 are configured to execute a set of program instructions stored in the memory 118 to acquire measurement data from one or more sensors 106 of the detector assembly 104 and / or control one or more portions of the characterization system 100.

[0039] In one embodiment, the illumination source 102 is a continuous source. For example, the illumination source 102 may include (but is not limited to) an arc lamp, a laser-pumped plasma source, or a continuous wave (CW) laser. In another embodiment, the illumination source 102 is a pulsed source. For example, the illumination source 102 may include (but is not limited to) a mode-locked laser, a Q-switched laser, or a plasma source pumped by a mode-locked or Q-switched laser. Examples of suitable light sources that may be included in illumination source 102 are described in the following: U.S. Patent 7,705,331, entitled "Methods and systems for providing illumination of a specimen for a process performed on the specimen" by Kirk et al.; U.S. Patent 9,723,703, entitled "System and method for transverse pumping of laser-sustained plasma" by Bezel et al.; and U.S. Patent 9,865,447, entitled "High brightness laser-sustained plasma broadband source" by Chuang et al., each of which is incorporated herein by reference.

[0040] The following patents broadly describe the characterization system: U.S. Patent No. 9,891,177, entitled "TDI Sensor in a Darkfield System," published by Vazhaeparambil et al. on February 13, 2018; U.S. Patent No. 9,279,774, entitled "Wafer Inspection," published by Romanovsky et al. on March 8, 2018; U.S. Patent No. 7,957,066, entitled "Split Field Inspection System Using Small Catadioptric Objectives," published by Armstrong et al. on June 7, 2011; and U.S. Patent No. 7,957,066, entitled "Beam Delivery System for Laser Dark-Field Illumination in a Catadioptric Optical System," published by Zhuang et al. on October 19, 2010. U.S. Patent No. 7,817,260 entitled "Ultra-Broadband UV Microscope Imaging System with Wide Range Zoom Capability" issued by Shafer et al. on December 7, 1999; U.S. Patent No. 5,999,310 entitled "Ultra-Broadband UV Microscope Imaging System with Wide Range Zoom Capability" issued by Leong et al. on April 28, 2009; U.S. Patent No. 7,525,649 entitled "Surface Inspection System Using Laser Line Illumination with Two Dimensional Imaging" issued by Leong et al. on April 28, 2009; U.S. Patent No. 9,080,971 entitled "Metrology Systems and Methods" issued by Kandel et al. on July 14, 2015; and U.S. Patent No. 9,080,971 entitled "Broad Band Objective Having Improved Lateral Color Performance" issued by Zhuang et al. on January 6, 2009. The 7,474th page of "ColorPerformance"U.S. Patent No. 461, U.S. Patent No. 9,470,639 entitled "Optical Metrology With Reduced Sensitivity To Grating Anomalies" published by Zhuang et al. on October 18, 2016, U.S. Patent No. 9,228,943 entitled "Dynamically Adjustable Semiconductor Metrology System" published by Wang et al. on January 5, 2016, U.S. Patent No. 9,228,943 entitled "Dynamically Adjustable Semiconductor Metrology System" published by Wang et al. on January 5, 2016, U.S. Patent No. 5,608,526 entitled "Focused Beam Spectroscopic Ellipsometry Method and System" published by Piwonka-Corle et al. on March 4, 1997, and U.S. Patent No. 5,608,526 entitled "Focused Beam Spectroscopic Ellipsometry Method and System" published by Rosencwaig et al. on October 2, 2001, and Apparatus for Analyzing Multi-Layer Thin Film Stacks U.S. Patent No. 6,297,880, entitled "On Semiconductors," is incorporated herein by reference in its entirety.

[0041] It should be noted that the scope of this disclosure is not limited to the characterization system 100. Rather, a system incorporating one or more image sensors of this disclosure may include any other optical systems known in the art that include inspection systems, metrology systems, or lithography systems.

[0042] It should be noted that one or more components of system 100 may be communicatively coupled to various other components of system 100 in any manner known in the art. For example, one or more processors 116 may be communicatively coupled to each other and to other components via wired connections (e.g., copper wires, fiber optic cables, and the like) or wireless connections (e.g., RF coupling, IR coupling, WiMax, Bluetooth, 3G, 4G, 4G LTE, 5G, and the like).

[0043] One or more processors 116 may comprise any one or more processing elements known in the art. In this regard, one or more processors 116 may comprise any microprocessor-type device configured to execute software algorithms and / or instructions. One or more processors 116 may comprise a desktop computer, a host computer system, a workstation, a graphics computer, a parallel processor, or other computer systems (e.g., networked computers) configured to execute programs configured to operate system 100, as described in this disclosure. It should be appreciated that the steps described in this disclosure may be implemented by a single computer system or, alternatively, by multiple computer systems. Furthermore, it should be appreciated that the steps described in this disclosure may be implemented on any one or more of the one or more processors 116. Generally, the term "processor" may be broadly defined to encompass any device having one or more processing elements that execute program instructions from memory 118. Additionally, different subsystems of system 100 (e.g., illumination source 102, detector assembly 104, controller 114, and the like) may include processors or logic elements suitable for implementing at least a portion of the steps described in this disclosure. Therefore, the above description should not be construed as limiting this disclosure but is for illustrative purposes only.

[0044] Memory 118 may include any storage medium known in the art suitable for storing program instructions executable by one or more associated processors 116 and data received from a metrology subsystem and / or inspection subsystem. For example, memory 118 may include non-transitory memory media. For example, memory 118 may include (but is not limited to) read-only memory (ROM), random access memory (RAM), magnetic or optical storage devices (e.g., magnetic disks), magnetic tape, solid-state drives, and the like. It should be further noted that memory 118 may be housed in a common controller housing with one or more processors 116. In an alternative embodiment, memory 118 may be remotely located relative to the physical location of processors 116, controller 114, and the like. In another embodiment, memory 118 stores program instructions for causing one or more processors 116 to perform the various steps described in this disclosure.

[0045] Figure 2 A flowchart illustrating a method 200 for manufacturing an image sensor according to an exemplary embodiment of the present disclosure is provided.

[0046] In step 201, front-side circuit elements without metal interconnects are generated. These circuit elements can be generated using one or more standard semiconductor processing steps, such as photolithography, deposition, ion implantation, annealing, and / or etching. CCD and / or CMOS sensor elements and devices can also be generated during step 201. These circuit elements can be generated in an epitaxial (epi) layer on the front surface of the wafer and are therefore also referred to as front-side circuit elements. In an embodiment, the epitaxial layer is about 10 nm to about 40 nm thick. In an embodiment, both the epitaxial layer and the substrate are doped with a p-type dopant (e.g., boron), wherein the epitaxial layer has a dopant concentration much lower than that of the bulk wafer. The resistivity of the epitaxial layer can be between 10 and 2000 Ωcm, and the resistivity of the substrate can be less than about 1 Ωcm.

[0047] In step 203, the active sensor region is thinned from the back. For example, the active sensor region or even the entire wafer may be thinned from the back side. This thinning may include a combination of polishing and etching to expose the epitaxial layer. In one embodiment, the wafer is polished from the back side until it is about 200 nm to about 300 nm thick. Next, a material such as a photoresist or other suitable material is used to protect the front surface and the frame region around the active sensor region. Then, a chemical etchant can be used to etch away the bulk wafer above the active sensor region, thereby exposing the active sensor region. Because the bulk wafer has a much higher dopant concentration and defect density than the epitaxial layer, the etching rate of the bulk semiconductor material is much higher than that of the epitaxial layer. The etching process slows down as it reaches the epitaxial layer, thereby resulting in a uniform thickness film region. In another embodiment, the image sensor is bonded to a support wafer that may be made of quartz, silicon, sapphire, or other materials. Then, a polishing process or a combination of polishing and chemical etching can be used to polish the entire wafer until only the epitaxial layer remains.

[0048] In step 205, a protective layer is deposited on the front surface to protect the front-side circuitry during steps 207 through 213. For example, exposed silicon or polysilicon on the front surface may be protected, as subsequent etching and deposition steps can affect the silicon. In an embodiment, step 205 may be performed prior to step 203, such that the protective layer provides additional protection to the front surface during the back-side thinning process (step 203) or provides a flat surface for bonding to a support wafer. In an embodiment, the protective layer may include, for example, silicon nitride or other dielectric layers deposited using plasma-enhanced CVD deposition.

[0049] In step 207, a pseudo-random or periodic pattern is generated on the back surface of the wafer to provide surface texturing. In this step, the back surface can be cleaned and prepared before generating the pseudo-random or periodic pattern for surface texturing. For example, the pseudo-random or periodic texture pattern can be formed on the back surface of the wafer via a mask / etching process. The patterning step can be used to generate periodic chamfered pyramids, periodic upright pyramids, pseudo-random chamfered pyramids, pseudo-random upright pyramids, periodic nanocones, pseudo-random nanocones, or the like. Figures 3A to 3I The description will further detail the aspects related to the generation of various pattern structures.

[0050] Alternatively and / or additionally, the back surface may be cleaned and prepared to have a pre-etched surface roughness for surface texturing. During this cleaning, native oxides containing organic matter and metals, as well as any contaminants, should be removed from the back surface. In a preferred embodiment, cleaning can be performed using a diluted HF solution or an RCA cleaning process (which is a well-known set of wafer cleaning steps that includes the removal of organic contaminants, thin oxide layers, and ionic contamination). After cleaning and during preparation, the wafer is preferably dried using a Marangoni drying technique (a surface tension-based drying technique) or a similar technique to ensure the surface is dry and free of watermarks. After cleaning, grit of varying sizes can be used to remove wafer fragments from hundreds of nm to several μm to produce an appropriate pre-etched surface roughness, which facilitates anisotropic wet etching.

[0051] In embodiments, the back surface is etched to produce a pseudo-random, periodic, and / or random textured surface. In embodiments, anisotropic wet etching can be used to produce pseudo-random, periodic, and / or random surface textures on the silicon wafer. In a preferred embodiment, an alkaline solution (e.g., KOH containing IPA) can be used as the etchant. Anisotropy exists in the etching rate along different plane orientations. For example, the etching rate along the (100) plane is about 10 times faster than that along the (111) plane. This results in the formation of sharp pyramidal structures. The process of etching a crystalline silicon wafer using aqueous KOH is as follows. First, KOH is dissociated in water and K... + and OH - Ions. Secondly, OH- - Ions will erode the back bonds to create an H-terminated silicon surface. Then, OH groups... - Ions react with H-terminated silicon to convert it into an OH-terminated surface. Finally, the surface silicon is used as Si(OH)6. 2- Alternatively, K2SiO3 can be removed. Furthermore, IPA acts as a surfactant to open surface sites. The etching rate depends on the OH group. - The presence of ions and H2O concentration and their accessibility to surface sites cleaned by IPA.

[0052] Many formulations are available for wet etching to produce pseudo-random, periodic, pyramidal surfaces and / or random textures on silicon wafers and can be used in the embodiments of this disclosure. One formulation uses a solution of 6 (wt%) KOH and 4 (wt%) IPA in water to produce random upright pyramids. Photolithography can be used to pattern masks on silicon surfaces to enable the etching of pseudo-random and / or periodic upright or chamfered pyramids. Patterns produced by photolithography can have a pseudo-random structure, i.e., the pattern can be randomly presented at short scale lengths (e.g., less than a few micrometers), but the pattern can be repeated at scale lengths of tens of micrometers or longer.

[0053] Textured surfaces reduce incident light reflection over a broad spectral bandwidth, thus increasing absorbed light intensity. This phenomenon is described in U.S. Patent No. 6,451,218B1 (Sensors and Actuators A-Physical) 263,445 (2017), issued September 17, 2002, by BS Akila, K Vaitinathan, T Balaganapati, S Vinoth, and P Thilakan, and the entire contents of which are incorporated herein by reference. In alternative embodiments, silicon surfaces can be textured by one or more of wet chemical etching, reactive ion etching (RIE), ultrafast laser etching, electrochemical etching, electron beam lithography, and mechanical grooving. Wet chemical etching is relatively inexpensive compared to other structuring methods.

[0054] Known techniques for wet chemical pyramidal etching of (100) oriented silicon surfaces use alkaline media such as alkali metal hydroxides, alkali metal carbonates, ammonia, or choline. The most common formulations include water, sodium hydroxide or potassium hydroxide, and an alcohol. The alcohol component can be either ethylene glycol or isopropanol. Known methods for wet chemical structural etching of silicon are only related to the generation of pyramidal textures.

[0055] Depending on the specific texturing process, surface texturing of a silicon substrate selectively removes portions of the material, resulting in upright or chamfered pyramidal structures. Consequently, the material density at the surface can be reduced, leading to a decrease in complex dielectric contrast, which in turn reduces the wavelength dependence of surface reflection.

[0056] In the embodiments, upright or chamfered cone surface textures or nanocone surface textures can also be fabricated by other methods such as reactive ion etching (RIE) (with or without inductive coupling), ultrafast laser etching, electrochemical etching, electron beam lithography, and mechanical grooving.

[0057] In step 209, the back-side textured surface can be cleaned and prepared for boron deposition. During this cleaning, native oxides containing organic matter and metals, as well as any contaminants, should be removed from the back-side surface. In a preferred embodiment, cleaning can be performed using a diluted HF solution or an RCA cleaning process (which is a well-known set of wafer cleaning steps that includes the removal of organic contaminants, thin oxide layers, and ionic contamination). After cleaning and during preparation, the wafer is preferably dried using the Marangoni drying technique (a surface tension-based drying technique) or a similar technique to ensure the surface is dry and free of watermarks. In a preferred embodiment, the wafer is protected in a controlled atmosphere during step 211 (e.g., using dry nitrogen) to minimize the regrowth of native oxides prior to step 211.

[0058] In step 211, a boron layer is deposited on the textured surface. For example, an amorphous layer of pure boron can be deposited onto the textured silicon surface to hermetically seal the silicon and prevent oxidation. In an embodiment, this deposition can be performed using a mixture of diborane and hydrogen at a temperature of about 600 to 800°C to produce a pinhole-free, interconnected, substantially pure boron layer. In this embodiment, step 211 may further include diffusing boron into the textured silicon surface by raising the temperature to, for example, between 850°C and 900°C over a period of about 2 to about 10 minutes to produce a p-type doped silicon layer adjacent to the boron layer. In an alternative embodiment, a mixture of diborane, hydrogen, and nitrogen can be used to deposit a pinhole-free, interconnected, substantially pure boron layer at a temperature between about 350°C and about 450°C. In an embodiment, a thin boron-doped epitaxial silicon layer can be grown on the silicon surface immediately prior to the boron deposition. A detailed description of the growth of a thin boron-doped epitaxial silicon layer can be found in co-pending and co-assigned U.S. Patent Application 16 / 562,396 entitled “Back-illuminated Sensor and Method of Manufacturing a Sensor,” the entire contents of which are incorporated herein by reference. The thickness of the boron layer may vary depending on the intended application of the sensor. The boron layer thickness is typically between about 2 nm and about 20 nm, encompassing all ranges and values ​​accurate to 0.1 nm. The boron layer may have a uniform thickness or may be deposited on a pyramidal surface, differing from the remaining portion of the textured surface. The minimum thickness is generally limited by the need for a pinhole-free uniform film. The maximum thickness generally depends on the absorption of photons of interest by boron. The boron layer avoids silicon oxidation problems by reliably and hermetically sealing the silicon surface against oxidation. It should be noted that several atomic percentages of oxygen (e.g., less than 10% or less than 5%) may remain at the interface between the boron layer and the silicon surface, but this oxygen content may not increase significantly over time (e.g., within a one-year period) due to the hermetically sealed design. This low oxygen-to-silicon ratio means that there is no connected silica layer at the interface. More details about boron deposition can be found in Sarubbi et al., “Chemical vapor deposition of a-boron layers on silicon for controlled nanometer-deep p+-n junction formation” (J. Electronic. Material, Vol. 39, pp. 162–173, 2010) (the full text of which is incorporated herein by reference).

[0059] The term 'largely pure boron layer' should be interpreted as meaning that the layer is predominantly composed of elemental boron. Impurities such as silicon or carbon may be present on the surface or in the lattice. For example, boron silicide may be present at the interface between the boron layer and the substrate. Oxygen may be present in the bulk of the layer, but not in readily detectable amounts. Therefore, the layer may comprise boron, be composed of boron, or be substantially composed of boron. The boron layer may be greater than 75%, greater than 80%, greater than 85%, greater than 90%, greater than 95%, greater than 96%, greater than 97%, greater than 98%, or greater than 99% boron.

[0060] The purity and pinhole-free nature of the boron layer are crucial to the sensitivity and lifespan of the image sensors disclosed herein. If any native oxide film is not removed from the epitaxial layer surface prior to boron deposition, the native oxide will be affected by DUV and VUV photons, causing a degradation in sensor performance. Even if all native oxide is removed before boron deposition, if pinholes exist in the boron layer, oxygen can still reach the silicon through these pinholes and oxidize the silicon surface after processing.

[0061] In this embodiment, additional layers may be deposited on top of the boron layer during or after step 211. These additional layers may include an anti-reflective coating comprising one or more materials such as magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium oxide (TiO2), and aluminum oxide (Al2O3). Even though the anti-reflective coating is affected by DUV and VUV radiation, the presence of a boron layer between the anti-reflective coating and the epitaxial layer protects the epitaxial layer from charges and traps in the anti-reflective coating and ensures that the sensitivity of the image sensor is not significantly degraded.

[0062] In step 213, the protective layer is removed or patterned. For example, the protective layer may be removed, or vias or passages may be formed in the protective layer and / or the support wafer to allow electrical connections to the circuit elements. In one embodiment, the support wafer may be removed. This step may include fabricating one or more of interconnects, passages, and bonding pads. These interconnects may be formed of Al, Cu, or another metal. A passivation layer may be deposited on the front surface to protect the circuit elements and interconnects.

[0063] In step 215, the completed circuit element is packaged. The package may include flip-chip bonding or wire bonding of the chip to a substrate. The package may include a window that transmits wavelengths of interest, or may include a flange or seal for interfacing with a vacuum seal.

[0064] Figures 3A to 3I This invention describes various pseudo-random and periodic patterning methods for implementation in an image sensor according to one or more embodiments of the present disclosure.

[0065] Figure 3AThis illustration describes a surface 300 patterned via a mask and etching process according to one or more embodiments of the present disclosure. In this embodiment, anisotropic wet etching of the wafer surface is performed via a mask 302. The mask 302 may be a photoresist, polymer, or hard mask, such as a SiN mask. The wet etching process may include an alkaline etching formulation, such as KOH, TMAH, or the like. During this process, the etching erodes the Si lattice of the wafer. <111> Surface. This leads to etching beneath the mask because... <111> Faceted pyramids are attributed to preference <111> The planar etching process reveals the surface. This etching continues until the base and top of the pyramid become as small as possible. Finally, once etching is complete, the mask is removed. Solvents can be used to remove polymer or photoresist masks, and HF solutions can be used to remove hard masks such as SiN. The Si surface can then be cleaned using standard silicon surface cleaning methods (e.g., RCA, which uses HF etched in between to remove surface oxides grown during cleaning) to remove any remaining residue. Photosensitive etching protection is discussed in J. Dalvi-Malhotra et al., “A spin-on photosensitive polymericetch protection mask for anisotropic wet etching of silicon” (J. Micromech. Microeng.) 18(2008) 025029(8pp) (the full text of which is incorporated herein by reference). Puqun Wang et al. discussed upright nanopyramids in their paper "Periodic upright nanopyramids for light management applications in ultrathin crystalline silicon solar cells" (IEEE Journal of Photovoltaics, Vol. 7, No. 2, March 2017) (the full text of which is incorporated herein by reference).The wet etching of silicon is discussed in Chapter 22 of Miguel A. Gonsalves et al., *Handbook of Silicon Based MEMS Materials and Technologies (Second Edition)* (Micro and Nano Technologies, 2015, pp. 470-502) (the full text of which is incorporated herein by reference).

[0066] Figure 3B This description illustrates a mask 310 suitable for producing chamfered cones on a wafer surface 300 according to one or more embodiments of the present disclosure. In this embodiment, the selected aperture size is approximately 100 nm, and each exposed area is spaced 200 nm apart. It should be noted that the scope of this disclosure is not limited to this aperture size or spacing, which is for illustrative purposes only. The aperture size can be varied depending on the patterning method used. Patterning can be achieved using advanced lithography tools that can or can not utilize near-field optics to obtain smaller features. Electron beam lithography can also be used to produce patterns.

[0067] Figure 3C This description describes a mask 320, according to one or more embodiments of the present disclosure, suitable for producing upright pyramids on the surface 300 of a wafer. It should be noted that the pattern of the mask 320 is consistent with... Figure 3B The pattern of mask 310 depicted is reversed. It should be noted that the manufacturing method and dimensions of mask 310 can be extended to mask 320.

[0068] Figure 3D A mask 330, suitable for generating pseudo-random chamfered cones on a wafer surface 300, is described according to one or more embodiments of this disclosure. It should be noted that the method of manufacturing mask 310 can be extended to mask 330. For the purposes of this disclosure, a pseudo-random pattern is defined as any pattern lacking clear short-range order but exhibiting long-range order. Figure 3D This indicates that the achievable average chamfered cone size is approximately 200 nm for this pattern, but to identify periodicity within the pattern, we must consider larger regions, such as length scales of approximately 1000 nm. For unit cells that can be as large as mm or cm or even larger, this long-range order can be even larger. It should be noted that the scope of this disclosure is not limited to this. Figure 3D The approximately 200 nm aperture size or long-range ordered scale depicted is for illustrative purposes only.

[0069] Figure 3EThis description describes a mask 340, according to one or more embodiments of the present disclosure, suitable for generating pseudo-random upright pyramids on the surface 300 of a wafer. It should be noted that the pattern of the mask 340 is consistent with... Figure 3D The pattern of the mask 330 is depicted in reverse. It should be noted that the manufacturing method and dimensions of the mask 330 can be extended to the mask 340.

[0070] Figure 3F This description describes a surface 300 of periodic nanocones patterned via a mask 352 and an etching process, according to one or more embodiments of this disclosure. This type of etching can be achieved by using a photoresist mask or a hard mask (e.g., silicon dioxide or alumina or the like) with lower etch selectivity than Si to mask the silicon surface. The pattern can be defined by electron beam lithography or advanced lithography with multiple patterning. Etching can be performed via reactive ion etching (RIE) or inductively coupled reactive ion etching (ICPRIE) using etching chemicals (e.g., SF6 / C4F8 or SF6 / O2 or the like). The slope of the nanocone sidewalls can be varied by changing process conditions during etching (e.g., plasma power, gas mixing ratio, or substrate temperature). The following describe etching formulations: Zhang et al., Highly-ordered silicon inverted nanocone arrays with broadband light antireflectance (Nanoscale Research Letters (2015) 10:9); Yalamanchili S. et al., Enhanced absorption and <1% spectrum-and-angle-averaged reflection in tapered microwire arrays (ACS Photonics 2016, 3, 10, 1854-1861); Dasog M., Profiling photoinduced carrier generation in semiconductor microwire arrays via photoelectrochemical metal deposition (Nanoscale Research Letters (2015) 10:9); Lett. 2016, 16, 8, 5015-5021, each of which is incorporated herein by reference in its entirety.

[0071] Figure 3G This description illustrates a mask 360 suitable for generating periodic nanocones on a wafer surface 300 according to one or more embodiments of the present disclosure. In this embodiment, the aperture size is less than about 50 nm, and each exposed area is spaced about 200 nm apart. It should be noted that the scope of the present disclosure is not limited to this aperture size or spacing, which is for illustrative purposes only. The aperture size may be varied depending on the patterning method used. In embodiments, the masked areas may be defined by electron beam lithography by depositing Al2O3 into the apertures of a patterned resist and then performing a resist stripping process to remove the resist, resulting in the exhibited pattern.

[0072] Figure 3H The description describes a surface 300 comprising pseudo-random nanocones patterned via a mask 354 and an etching process, according to one or more embodiments of this disclosure. It should be noted that this can be achieved through methods similar to... Figure 3F The periodic pattern in the image is obtained using an etching recipe that employs a pseudo-random etch mask (e.g., a mask that can be defined by electron beam lithography). Figure 3H Pseudo-random nanocones. Due to the differences in the size of the shielding region, the nanocones can have small variations in their height and width.

[0073] Figure 3I This description describes a mask 380 suitable for generating pseudo nanocones on the surface 300 of a wafer according to one or more embodiments of the present disclosure. It should be noted that the method of manufacturing mask 360 can be extended to mask 380. Figure 3I This indicates that the achievable average nanocone size is a pseudo-random pattern of approximately 50 nm, but to identify periodicity within the pattern, we must consider larger regions, such as length scales of approximately 1000 nm. It should be noted that the scope of this disclosure is not limited to… Figure 3I The aperture size or long-range order scale of approximately 50 nm depicted is for illustrative purposes only.

[0074] Figure 4A This illustration shows a cross-sectional view of a portion of an image sensor 400a having a low-reflection backlit boron-coated textured surface 404 according to one or more embodiments of the present disclosure. It should be noted that... Figure 4AThe image is not drawn to scale because some features have been enlarged for clarity. In this embodiment, the silicon wafer is processed by one of the methods described herein. In this embodiment, circuit element 420 is fabricated on a first surface of epitaxial silicon layer 402. In this embodiment, a protective layer 422 is applied to protect circuit element 420. Protective layer 422 is as previously described herein and may include a support wafer bonded to the first surface of the epitaxial silicon layer. In this embodiment, a pseudo-random, periodic, and / or randomly distributed textured surface 404, including upright pyramids 410, covers the photosensitive portion of the second surface of the epitaxial silicon layer. This textured surface 404 causes a reduction in material density at the surface, resulting in a reduction in complex dielectric contrast, which in turn reduces the wavelength dependence of surface reflection, thereby increasing the amount of light absorbed and improving the reflectivity of the image sensor and thus improving the efficiency of the image sensor.

[0075] In this example, the plane of the first surface of the epitaxial silicon layer 402 prior to the fabrication of the circuit element has (100) a planar orientation (or belongs to a plane). <100> Any plane of the family), as shown in the figure. After etching, the second surface of the epitaxial silicon layer contains multiple faceted pyramidal peaks. Specifically, these upright pyramids 410 have (111) planes (or belong to the planes). <111> The triangular sides of any plane of the family and the base along the (100) plane, as shown in the diagram. It should be noted that even if one or more sides of the pyramid are... <111> The planes are not perfectly or precisely aligned, but reflectivity can be reduced as desired. In an embodiment, the image sensor 400a can be optimized for high sensitivity in a wavelength range from about 190 nm to about 450 nm. In this embodiment, the typical linear dimension 411 of the base of the pyramid is about 200 nm. Because the textured surface 404 includes a pseudo-random, periodic, and / or random distribution of the pyramids, some pyramids may have a base larger than this typical linear dimension and some pyramids will have a base smaller than this typical linear dimension. For example, about 80% or more of the pyramids may have a linear dimension between 150 nm and 300 nm. Different typical linear dimensions can be used in sensors optimized for other wavelength ranges. The typical linear dimension of the pyramid can be controlled by adjusting one or more etching conditions, such as etchant concentration, temperature, and / or etching time. Although Figure 4A The pyramidal base is depicted as aligned with the same distance from the first surface of the epitaxial silicon layer 402, but it should be noted that the scope of this disclosure is not limited to this alignment but is provided for convenience. In practice, the pyramids of surface 404 may not be precisely aligned.

[0076] In an embodiment, a thin layer 405 of high-purity amorphous boron (e.g., between about 2 nm and about 20 nm thick) is deposited on textured silicon 404. This boron layer 405 hermetically seals the textured silicon and prevents or limits oxidation. The boron layer 405 may be formed as previously described herein. For example, the boron layer 405 may be about 5 nm thick (or about 20 to 25 boron atom layers). The boron layer 405 may have a uniform thickness or may be deposited on a pyramidal surface, different from the remaining portion of the textured surface.

[0077] In an embodiment, an antireflective coating 406 may be applied to the textured surface 404 to further reduce reflectivity. The antireflective coating may include one or more of magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium oxide (TiO2), and aluminum oxide (Al2O3).

[0078] It should be noted that the textured silicon surface 404 described herein can be produced based on any type of silicon surface conditions. For example, surfaces that have been sawed, etched, ground, and polished can be processed to obtain the desired textured silicon surface 404.

[0079] Figure 4B This illustration shows a cross-sectional view of a portion of an image sensor 400b having a low-reflectivity backlit boron-coated textured surface 414 according to one or more additional embodiments of this disclosure. It should be noted that, unless otherwise stated, Figure 4A The description should be interpreted as extended to Figure 4B In one embodiment, circuit element 420 is fabricated on a first surface of epitaxial silicon layer 402. In another embodiment, a protective layer 422 is deposited on the first surface and protects circuit element 420. The protective layer 422 is, as previously described, and may include a support wafer bonded to the first surface of the epitaxial silicon layer. A pseudo-random, periodic, and / or randomly distributed textured surface 414, including a chamfered cone 430, covers the photosensitive portion of the second surface of the epitaxial silicon layer. This textured surface 414 causes a reduction in material density at the surface, resulting in a reduction in complex dielectric contrast, which in turn reduces the wavelength dependence of surface reflection, thereby increasing the amount of absorbed light and improving the reflectivity of the image sensor and thus improving the efficiency of the image sensor.

[0080] The plane of the first surface of the epitaxial silicon layer 402 prior to the fabrication of circuit elements has (100) planar orientation (or belongs to the plane). <100> Any plane of the family), as shown in the figure. After etching, the second surface of the epitaxial silicon layer includes several faceted chamfered pyramidal structures. Specifically, these chamfered pyramids 430 have (111) planes (or belong to the planes) <111> The triangular sides of any plane of the family and the base along the (100) plane, as shown in the diagram. It should be noted that even if one or more sides of the chamfered pyramid are... <111> The planes are not perfectly or precisely aligned, but reflectivity can be reduced as desired. In this embodiment, the image sensor 400b is optimized for high sensitivity in a wavelength range from about 190 nm to about 450 nm. In this embodiment, the typical linear dimension 431 of the base of the chamfered cone is about 200 nm. Because the textured surface 414 includes a pseudo-random, periodic, and / or random distribution of the chamfered cones, some chamfered cones may have a base larger than this typical linear dimension and some chamfered cones will have a base smaller than this typical linear dimension. For example, about 80% or more of the cones may have a linear dimension between 150 nm and 300 nm. Different typical linear dimensions can be used in sensors optimized for other wavelength ranges. The typical linear dimension of the chamfered cone can be controlled by adjusting one or more etching conditions, such as etchant concentration, temperature, and etching time. It should be noted that although Figure 4B The bottom of the chamfered cone (e.g., 430) is depicted as aligned to a single height, but it is expected that some chamfered cones may have bottoms of different heights, and this will not significantly affect the low reflectivity of the textured surface 414.

[0081] Similar to Figure 4A A thin layer 405 of high-purity amorphous boron (e.g., between about 2 nm and about 20 nm thick) can be deposited on textured silicon 414. This boron layer 405 hermetically seals the textured silicon and prevents or limits oxidation. The boron layer 405 can be as described above relative to... Figure 2 It is formed as described. For example, the boron layer 405 may be 5 nm thick or about 20 to 25 boron atom layers. The boron layer 405 may have a uniform thickness or may be deposited on the chamfered cone in a manner different from the remaining portion of the textured surface.

[0082] In an embodiment, an anti-reflective coating 406 may be applied to the textured surface 414 to further reduce reflectivity. The anti-reflective coating may include one or more of magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium oxide (TiO2), and aluminum oxide (Al2O3).

[0083] Figure 4CThis illustration shows a cross-sectional view of a portion of an image sensor 400c having a low-reflection backlit boron-coated textured surface 424 according to one or more additional embodiments of this disclosure. It should be noted that, unless otherwise stated, Figure 4A and Figure 4B The description should be interpreted as extended to Figure 4C In one embodiment, circuit element 420 is fabricated on a first surface of epitaxial silicon layer 402. In another embodiment, a protective layer 422 is deposited on the first surface and protects circuit element 420. A textured surface 424, comprising nanocones (e.g., black silicon) 440 with a pseudo-random, periodic, and / or randomly distributed pattern, at least covers the photosensitive portion of the second surface of the epitaxial silicon layer. This textured surface 424 causes a reduction in material density at the surface, resulting in a reduction in complex dielectric contrast. This leads to a reduction in the wavelength dependence of surface reflection, thereby increasing the amount of absorbed light and improving the reflectivity of the image sensor, and thus improving the efficiency of the image sensor.

[0084] In this embodiment, a thin layer 405 of high-purity amorphous boron (e.g., between about 2 nm and about 20 nm thick) is deposited on the textured silicon 424. As previously mentioned herein, this boron layer 405 hermetically seals the textured silicon and prevents or limits oxidation. The boron layer 405 may be formed as previously described herein. For example, the boron layer 405 may be 5 nm thick or about 20 to 25 layers of boron atoms. The boron layer 405 may have a uniform thickness or may be deposited on a chamfered pyramid, different from the remaining portion of the textured surface.

[0085] In an embodiment, an antireflective coating 406 may be applied to the textured surface 424 to further reduce reflectivity. The antireflective coating may include one or more of magnesium fluoride (MgF2), hafnium oxide (HfO2), strontium tetraborate (SrB4O7), silicon dioxide (SiO2), silicon nitride (Si3N4), titanium oxide (TiO2), and aluminum oxide (Al2O3).

[0086] In this embodiment, the image sensor 400c is optimized for high sensitivity in a wavelength range from about 190 nm to about 450 nm. In this embodiment, the typical height 441 of the nanocone is about 700 nm, and the typical radius 442 of the base of the nanocone is about 120 nm. The tip of the nanocone has a radius much smaller than the typical radius of the base. For example, the tip may have a radius of about 30 nm or less. Because the textured surface 424 includes a pseudo-random, periodic, and / or random distribution of nanocones, some nanocones may have a height greater than or less than 700 nm and a base radius greater than or less than 120 nm. For example, about 80% or more of the nanocones may have a height between 350 nm and 1000 nm, and about 80% or more of the nanocones may have a base radius between 80 nm and 160 nm. Different typical sizes can be used in sensors optimized for other wavelength ranges. The typical size of the nanocones can be controlled by adjusting one or more etching conditions, such as etchant concentration, plasma conditions, temperature, and etching time. It should be noted that although Figure 4C The base of the nanocone (e.g., 440) is depicted as aligned to a single height, but it is expected that some nanocones may have bases of different heights, and this will not significantly affect the low reflectivity of the textured surface 424.

[0087] Figure 5 The graphs 502 to 508 illustrate the reflectance versus wavelength behavior of various image sensors. As a reference example, graph 502 depicts the reflectance versus wavelength behavior of an image sensor with a back-illuminated boron-coated back surface. Graph 504 depicts the reflectance versus wavelength behavior of an image sensor with a low-reflectance back-illuminated boron-coated back surface having an upright pyramidal texture. Graph 506 depicts the reflectance versus wavelength behavior of an image sensor with a low-reflectance back-illuminated boron-coated back surface having a chamfered pyramidal texture. Graph 508 depicts the reflectance versus wavelength behavior of an image sensor with a low-reflectance back-illuminated boron-coated back surface having a nanocone texture. Lumerical FDTD is used to simulate the reflectance values ​​of periodic upright pyramids, chamfered pyramids, and nanocones. It is assumed that the incident light is along a plane perpendicular to the silicon substrate and consists of equal portions of a transverse electromagnetic wavefront and a transverse magnetic wavefront. Each simulation includes a uniform 5 nm boron layer on top of the silicon. Simulations of a planar sensor surface, a textured sensor surface with an upright pyramid, and a textured sensor surface with a chamfered pyramid respectively include an aluminum oxide coating on top of a boron layer with thicknesses of 16.5 nm, 48 nm, and 41 nm. Figure 5 This demonstrates how reflectance can be improved at wavelengths between 190nm and 450nm. A planar sensor (reference example) can achieve reflectance up to 40% within the wavelength range of interest. Easily accessible from... Figure 5The graphs clearly illustrate the difference in reflectance between the planar sensor and the textured surface sensor. The nanocone example exhibits the lowest reflectance value. The upright pyramid also has a fairly low reflectance, well below 10%. The chamfered pyramid has a reflectance below 10% across most wavelengths. It should be noted that... Figure 5 The diagram showing the structure of its reflectivity and the dimensions of the layers on the structure is for illustrative purposes only.

[0088] Those skilled in the art will recognize that the components, operations, devices, objects, and accompanying discussions described herein are used as examples to clarify concepts and are open to various configuration modifications. Therefore, the specific examples and accompanying discussions used herein are intended to represent their more general categories. In general, the use of any particular example is intended to represent its category, and the omission of specific components, operations, devices, and objects should not be considered a limitation.

[0089] The above description is presented to enable those skilled in the art to make and use the invention, as provided in the context of the particular application and its requirements. As used herein, directional terms such as “top,” “bottom,” “above,” “below,” “up,” “down,” “under,” and “downward” are intended to provide relative positions for description and not to specify an absolute reference frame. Those skilled in the art will appreciate various modifications to the described embodiments, and that the general principles defined herein can be applied to other embodiments. Therefore, the invention is not intended to be limited to the specific embodiments shown and described, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0090] Regarding the use of generally plural and / or singular terms in this document, those skilled in the art may convert plural to singular and / or singular to plural depending on the context and / or application. For clarity, various singular / plural arrangements are not explicitly described herein.

[0091] The topics described herein sometimes illustrate different components contained within or connected to other components. It should be understood that such depictions of architecture are merely illustrative, and in fact, many other architectures can be implemented to achieve the same functionality. Conceptually, any arrangement of components that achieve the same functionality is effectively “associated” to achieve the desired functionality. Therefore, regardless of the architecture or intermediate components, any two components combined herein to achieve a particular function can be considered “associated” with each other to achieve the desired functionality. Similarly, any two such associated components can also be considered “connected” or “coupled” with each other to achieve the desired functionality, and any two components that can be suchly associated can also be considered “coupleable” with each other to achieve the desired functionality. Specific examples of coupleability include (but are not limited to) physically matable and / or physically interactive components and / or wirelessly interactive and / or logically interactive components.

[0092] Furthermore, it should be understood that the invention is defined by the appended claims. Those skilled in the art will understand that, generally, the terminology used herein and, in particular, in the appended claims (e.g., the body of the appended claims) is intended to be “open-ended” (e.g., the term “comprising” should be interpreted as “comprising (but not limited to)”, the term “having” should be interpreted as “having at least”, the term “including” should be interpreted as “including (but not limited to)”, etc.). Those skilled in the art will further understand that if a specific number of claims is intended to be introduced, this intention will be explicitly stated in the claims, and if such a statement is not made, then this intention does not exist. For example, as an aid to understanding, the appended claims may contain the use of introductory phrases “at least one” and “one or more” to introduce the claims. However, the use of such phrases should not be construed as implying that the introduction of a claim statement by the indefinite article "a (a / an)" limits any particular claim containing such an introductory claim statement to an invention containing only one such statement, even if the same claim contains the introductory phrase "a or more" or "at least one" and an indefinite article such as "a (a / an)" (e.g., "a (a)" and / or "a (an)" should generally be interpreted as meaning "at least one" or "a or more"); the same applies to the use of definite articles used to introduce claim statements. Furthermore, even if a specific number of claim statements is explicitly stated, those skilled in the art will recognize that such a statement should generally be interpreted as meaning at least a certain number of statements (e.g., a bare statement of "two statements" without other modifiers generally means at least two statements or two or more statements). Furthermore, in examples where the convention of "at least one of A, B, and C and similar to thereof" is used, this structure is generally intended to be understood in the manner commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" would include (but is not limited to) systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or both A, B, and C, etc.). In examples where the convention of "at least one of A, B, or C and similar to thereof" is used, this structure is generally intended to be understood in the manner commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" would include (but is not limited to) systems having only A, only B, only C, both A and B, both A and C, both B and C, and / or both A, B, and C, etc.). Those skilled in the art will further understand that virtually any disjunctive terms and / or phrases presenting two or more alternatives, whether in the detailed description, claims, or drawings, should be understood to consider the possibility of including one, any one, or both of the items. For example, the phrase "A or B" will be understood to include the possibility of including "A" or "B" or "A and B".

Claims

1. An image sensor, comprising: Semiconductor thin film, including epitaxial layer, The epitaxial layer comprises a first surface and a second textured surface opposite the first surface, wherein the second textured surface comprises a distribution of nanocones configured to reduce reflection of deep ultraviolet (DUV) or vacuum ultraviolet (VUV) light, wherein at least a portion of the nanocones have a height between 350 nm and 1000 nm and a base radius between 80 nm and 160 nm. One or more circuit elements are formed on the first surface of the epitaxial layer; and A boron layer is disposed on the distribution of nanocones on the second textured surface of the epitaxial layer, wherein the boron layer adheres to and seals the distribution of nanocones and seals the second textured surface of the epitaxial layer.

2. The image sensor of claim 1, wherein the image sensor is configured to sense at least one of DUV radiation or VUV radiation.

3. The image sensor of claim 1, wherein the boron layer comprises 75% or more of a boron composition.

4. The image sensor of claim 1, wherein the distribution of the nanocones on the second textured surface comprises a pseudo-random distribution of the nanocones.

5. The image sensor of claim 1, wherein the distribution of the nanocones on the second textured surface comprises a periodic distribution of the nanocones.

6. The image sensor of claim 1, wherein the distribution of the nanocones on the second textured surface comprises a random distribution of the nanocones.

7. The image sensor according to claim 1, wherein the boron layer is between 2 nm and 20 nm thick.

8. The image sensor of claim 1, wherein the boron layer comprises less than 10% oxygen near the interface between the boron layer and the epitaxial layer.

9. The image sensor of claim 1, further comprising an anti-reflective coating disposed on the boron layer.

10. The image sensor of claim 9, wherein the antireflective coating comprises at least one of magnesium fluoride, hafnium oxide, strontium tetraborate, silicon dioxide, silicon nitride, titanium dioxide, or aluminum oxide.

11. The image sensor of claim 1, wherein the thickness of the epitaxial layer is greater than 10 µm.

12. The image sensor of claim 11, further comprising a doped layer formed in the second textured surface of the epitaxial layer and adjacent to the boron layer.

13. The image sensor according to claim 1, further comprising: A support chip attached to one or more of the circuit elements.

14. The image sensor according to claim 1, further comprising: A protective layer formed on one or more circuit elements.

15. The image sensor of claim 1, wherein the image sensor is incorporated in at least one of a charge-coupled device (CCD) and a CMOS device.

16. The image sensor of claim 1, wherein the second textured surface comprises a distribution of at least one of upright pyramids or chamfered pyramids, and wherein 80% or more of the base of said at least one of the upright pyramids or chamfered pyramids has a linear dimension between 150 nm and 300 nm.

17. The image sensor of claim 1, wherein 80% of the nanocone has a height between 350 nm and 1000 nm, and 80% of the nanocone has a base radius between 80 nm and 160 nm.

18. An inspection system comprising: Lighting source; A set of optical devices, including an objective lens, configured to guide and focus radiation from the illumination source onto the sample; A detector configured to receive light from the sample, wherein the set of optics is configured to collect, guide, and focus the light from the sample onto the detector, the detector comprising one or more image sensors, wherein at least one sensor includes: Semiconductor thin film, including epitaxial layer, The epitaxial layer comprises a first surface and a second textured surface opposite the first surface, wherein the second textured surface comprises a distribution of nanocones configured to reduce the reflection of DUV or VUV light, wherein at least a portion of the nanocones have a height between 350 nm and 1000 nm and a base radius between 80 nm and 160 nm. One or more circuit elements are formed on the first surface of the epitaxial layer; and A boron layer is disposed on the distribution of nanocones on the second textured surface of the epitaxial layer, wherein the boron layer adheres to and seals the distribution of nanocones and seals the second textured surface of the epitaxial layer.

19. The inspection system of claim 18, wherein the distribution of the nanocones on the second textured surface comprises a pseudo-random distribution of the nanocones.

20. The inspection system of claim 18, wherein the distribution of the nanocones on the second textured surface comprises a periodic distribution of the nanocones.

21. The inspection system of claim 18, wherein the distribution of the nanocones on the second textured surface comprises a random distribution of the nanocones.

22. The inspection system of claim 18, further comprising an anti-reflective coating disposed on the boron layer.

23. A method for manufacturing an image sensor, the method comprising: An epitaxial layer is formed on the substrate; A gate layer is formed on the substrate; One or more circuit element layers are formed on the gate layer; The substrate is thinned to produce a thinned substrate that exposes at least a portion of the epitaxial layer; Pre-etch the exposed portion of the epitaxial layer; A surface texture is generated on the exposed portion of the epitaxial layer, wherein the surface texture comprises a distribution of nanocones configured to reduce reflection of DUV or VUV light, wherein at least a portion of the nanocones have a height between 350 nm and 1000 nm and a base radius between 80 nm and 160 nm; and A boron layer is formed on the surface texture, wherein the boron layer adheres to and seals the distribution of the nanocones and seals the exposed portions of the epitaxial layer.

24. The method of claim 23, wherein the distribution of the nanocones of the surface texture comprises a pseudo-random distribution of the nanocones.

25. The method of claim 23, wherein the distribution of the nanocones of the surface texture comprises a periodic distribution of the nanocones.

26. The method of claim 23, wherein the distribution of the nanocones of the surface texture comprises a random distribution of the nanocones.

27. The method of claim 23, further comprising forming an anti-reflective coating on the boron layer.

28. The method of claim 23, further comprising forming a protective layer on the circuit element layer prior to pre-etching the exposed portion of the epitaxial layer.

29. The method of claim 23, further comprising doping at least one exposed portion of the epitaxial layer after the surface texture is generated.

30. A method for manufacturing an image sensor, the method comprising: An epitaxial layer is formed on the substrate; One or more circuit elements are formed on the epitaxial layer; Attach the support chip to the circuit element; Thin the substrate to expose the epitaxial layer; Pre-etch the exposed surface of the epitaxial layer; A surface texture is generated on the exposed surface of the epitaxial layer, wherein the surface texture comprises a distribution of nanocones configured to reduce reflection of DUV or VUV light, wherein at least a portion of the nanocones have a height between 350 nm and 1000 nm and a base radius between 80 nm and 160 nm; and A boron layer is formed on the surface texture, wherein the boron layer adheres to and seals the distribution of the nanocones and seals the exposed portions of the epitaxial layer.

31. The method of claim 30, wherein the distribution of the nanocones of the surface texture comprises a pseudo-random distribution of the nanocones.

32. The method of claim 30, wherein the distribution of the nanocones of the surface texture comprises a periodic distribution of the nanocones.

33. The method of claim 30, wherein the distribution of the nanocones of the surface texture comprises a random distribution of the nanocones.

34. The method of claim 30, further comprising forming an anti-reflective coating on the boron layer.

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