Method for managing flash memory module, flash memory controller and electronic device

Abstract

The present invention relates to a method for managing a flash memory module, a flash memory controller and an electronic device. The method comprises: dividing a plurality of blocks in the flash memory module into a plurality of groups, wherein each group comprises at least two blocks; establishing a valid data page table, wherein the valid data page table respectively records the indexes of the plurality of blocks and the corresponding number of valid data pages; establishing a group least valid data page array according to the valid data page table; referring to the group least valid data page array to select a target group having an overall least valid data page, wherein the overall least valid data page is obtained by selecting a minimum value in the least valid data page; searching the at least two blocks in the target group without searching the blocks in other groups to determine a target block having the overall least valid data page.

Description

Technical Field

[0001] The present invention relates to a flash memory controller, and more particularly to a flash memory module management method and a related flash memory controller. Background Art

[0002] In a flash memory module, because data stored in a data page of a block cannot be overwritten, when data is updated by new data, the new data must be stored in another data page, and the original data becomes invalid data. Therefore, when the data of the block is updated by the new data stored in the data page of another block, the number of valid data pages in the block will be reduced. In order to efficiently use the blocks of the flash memory module, the flash memory controller searches all blocks to find one or more blocks with the least valid data pages, and the flash memory controller performs a garbage collection operation to release these blocks with the least valid data pages. In other words, the flash memory controller moves the valid data pages of these blocks to other blocks, and then erases these blocks to become blank blocks.

[0003] Because the flash memory controller searches all blocks to find the block with the least valid data page, if the flash memory module includes many blocks (eg, one thousand blocks), the search time becomes long, which may cause system efficiency to decrease. Summary of the invention

[0004] An object of the present invention is to provide a control method for a flash memory module, which can group the blocks of the flash memory module so that the flash memory controller can efficiently find the block with the least valid data pages to solve the above-mentioned problem.

[0005] An embodiment of the present invention discloses a method for managing a flash memory module, the method comprising: dividing a plurality of blocks in the flash memory module into a plurality of groups, wherein each group comprises at least two blocks; establishing a valid data page table, wherein the valid data page table respectively records the indexes of the plurality of blocks and the corresponding number of valid data pages; establishing a group least valid data page array according to the valid data page table, wherein the group least valid data page array respectively records the group index and the corresponding least valid data page, wherein the least valid data page is obtained by selecting a minimum value among the number of valid data pages of the block in the group; referring to the group least valid data page array to select a target group having an overall least valid data page, wherein the overall least valid data page is obtained by selecting a minimum value among the least valid data pages in the group; searching the at least two blocks in the target group without searching blocks in other groups to determine a target block having the overall least valid data page; and adding the target block to a garbage collection queue.

[0006] Another embodiment of the present invention discloses a flash memory controller, wherein the flash memory controller is coupled to a flash memory module, and the flash memory controller includes a memory and a microprocessor, wherein the memory is used to store a program code, and the microprocessor is used to execute the program code to access the flash memory module, wherein the microprocessor divides a plurality of blocks in the flash memory module into a plurality of groups, wherein each group includes at least two blocks; the microprocessor establishes a valid data page table, wherein the valid data page table respectively records the indexes of the plurality of blocks and the corresponding number of valid data pages; the microprocessor establishes a grouped least valid data page array according to the valid data page table, wherein the The group least valid data page array records the group index and the corresponding least valid data page respectively, wherein the least valid data page is obtained by selecting a minimum value among the number of valid data pages of the blocks in the group; the microprocessor refers to the group least valid data page array to select a target group having an overall least valid data page, wherein the overall least valid data page is obtained by selecting a minimum value among the least valid data pages in the group; the microprocessor searches the at least two blocks in the target group without searching blocks in other groups to determine a target block having the overall least valid data page; and the microprocessor adds the target block to a garbage collection queue.

[0007] Yet another embodiment of the present invention discloses an electronic device, the electronic device comprising a flash memory module and a flash memory controller, the flash memory controller being used to access the flash memory module, wherein the flash memory controller divides a plurality of blocks in the flash memory module into a plurality of groups, wherein each group comprises at least two blocks; the flash memory controller establishes a valid data page table, wherein the valid data page table respectively records the indexes of the plurality of blocks and the corresponding number of valid data pages; the flash memory controller establishes a grouped least valid data page array according to the valid data page table, wherein the grouped least valid data page array respectively records the grouped indexes and the corresponding number of valid data pages. and a corresponding least valid data page, wherein the least valid data page is obtained by selecting a minimum value among the number of valid data pages of the blocks in the group; the flash memory controller refers to the group least valid data page array to select a target group having an overall least valid data page, wherein the overall least valid data page is obtained by selecting a minimum value among the least valid data pages in the group; the flash memory controller searches the at least two blocks in the target group without searching blocks in other groups to determine a target block having the overall least valid data page; and the flash memory controller adds the target block to a garbage collection queue. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0009] Figure 2 FIG. 4 is a schematic diagram of a three-dimensional NAND flash memory according to an embodiment of the present invention.

[0010] Figure 3 A flow chart of a method for managing the flash memory module is provided.

[0011] Figure 4 It shows the grouping according to an embodiment of the present invention.

[0012] Figure 5 FIG. 2 shows a valid data page table and a least valid page array according to an embodiment of the present invention.

[0013] Figure 6 is a flow chart of a method for managing the flash memory module according to another embodiment of the present invention.

[0014] Figure 7 It shows that different types of blocks are grouped according to an embodiment of the present invention.

[0015]

Explanation of symbols

[0016] 10: Electronic devices

[0017] 50: Host device

[0018] 52: Processor

[0019] 54: Power supply circuit

[0020] 100: Memory device

[0021] 110: Memory Controller

[0022] 112: Microprocessor

[0023] 112C: Program code

[0024] 112M: Read-only memory

[0025] 114: Control Logic Circuit

[0026] 116: Random Access Memory

[0027] 118: Transmission interface circuit

[0028] 120: Flash memory module

[0029] 122-1, 122-2, 122-N: Flash memory chip

[0030] 132: Encoder

[0031] 134: Decoder

[0032] 136: Randomizer

[0033] 138: De-Randomizer

[0034] 300, 302, 304, 306, 308,

[0035] 310, 312, 314, 600, 602

[0036] 604, 606, 608, 610, 612

[0037] 614, 616, 618, 620: Steps

[0038] 410_1~410_M: Grouping

[0039] 510: Valid data page table

[0040] 520: Group least valid data page array

[0041] 720_1~720_P: Grouping

[0042] M(1, 1, 1), M(2, 1, 1), M(Nx, 1, 1),

[0043] M(1, 2, 1), M(Nx, 2, 1), M(1, Ny, 1), M(Nx, Ny, 1),

[0044] M(1, 1, 2), M(2, 1, 2), M(Nx, 1, 2),

[0045] M(1, 2, 2), M(Nx, 2, 2),

[0046] M(1, Ny, 2), M(Nx, Ny, 2),

[0047] M(1, 1, Nz), M(Nx, 1, Nz),

[0048] M(1, 2, Nz), M(Nx, 2, Nz),

[0049] M(1, Ny, Nz), M(Nx, Ny, Nz),

[0050] M(nx, ny, nz): memory unit

[0051] MBLS(1, 1), MBLS(Nx, 1),

[0052] MBLS(1, 2), MBLS(Nx, 2),

[0053] MBLS(1, Ny), MBLS(Nx, Ny): Upper selection circuit

[0054] MSLS(1, 1), MSLS(Nx, 1),

[0055] MSLS(1, 2), MSLS(Nx, 2),

[0056] MSLS(1, Ny), MSLS(Nx, Ny): Bottom selection circuit

[0057] BL(1), BL(Nx): bit lines

[0058] WL(1, 1), WL(2, 1), WL(Ny, 1),

[0059] WL(1, 2), WL(2, 2), WL(Ny, 2),

[0060] WL(1, Nz), WL(2, Nz), WL(Ny, Nz): word lines

[0061] BLS(1), BLS(2), BLS(Ny): Upper selection line

[0062] SLS(1), SLS(2), SLS(Ny): Lower selection line

[0063] SL(1), SL(2), SL(Ny): Source lines

[0064] PS2D(1), PS2D(2), PS2D(Ny): Circuit Module

[0065] S(1, 1), S(Nx, 1),

[0066] S(1, 2), S(Nx, 2),

[0067] S(1, Ny), S(Nx, Ny): Secondary circuit modules

[0068] B_1~B_N, B_(N+1)-B_2N,

[0069] B _(2N+1)~B_(3N),

[0070] B _((M-1╳N+1))~B_(M╳N): Block DETAILED DESCRIPTION

[0071] Please refer to Figure 1 , Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), which may be collectively referred to as a processor 52, and may further include a power supply circuit 54 coupled to the processor 52. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52 and the memory device 100, and output one or more driving voltages to the memory device 100. The memory device 100 may be used to provide storage space for the host device 50, and obtain the one or more driving voltages from the host device 50 as power for the memory device 100. Examples of the host device 50 may include (but are not limited to): a multifunctional mobile phone, a wearable device, a tablet, and a personal computer such as a desktop computer and a notebook computer. Examples of the memory device 100 may include (but are not limited to): a solid state drive (SSD) and various types of embedded memory devices, such as embedded memory devices that comply with the Peripheral Component Interconnect Express (PCIe) standard. According to this embodiment, the memory device 100 may include a flash memory controller 110 and may further include a flash memory module 120, wherein the flash memory controller 110 may be used to control the operation of the memory device 100 and access the flash memory module 120, and the flash memory module 120 is used to store information. The flash memory module 120 may include at least one flash memory chip, such as a plurality of flash memory chips 122-1, 122-2, ..., 122-N, wherein "N" may represent a positive integer greater than 1.

[0072] like Figure 1As shown, the flash memory controller 110 may include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M), a control logic circuit 114, a random access memory (RAM) 116, and a transmission interface circuit 118, wherein the above elements may be coupled to each other via a bus. The random access memory 116 is implemented as a static random access memory (SRAM), but the present invention is not limited thereto. The random access memory 116 may be used to provide internal storage space for the flash memory controller 110. For example, the random access memory 116 may be used as a buffer memory to buffer data. In addition, the read-only memory 112M of the present embodiment may be used to store a program code 112C, and the microprocessor 112 may be used to execute the program code 112C to control the access of the flash memory module 120. Note that in some examples, the program code 112C may be stored in a random access memory 116 or any other type of memory. In addition, the control logic circuit 114 may be used to control the flash memory module 120, and the control logic circuit 114 may include an encoder 132, a decoder 134, a randomizer 136, a de-randomizer 138, and other circuits. The transmission interface circuit 118 may comply with a specific communication standard (such as a Serial Advanced Technology Attachment (SATA) standard, a Peripheral Component Interconnect (PCI) standard, a Peripheral Component Interconnect Express standard, a Universal Flash Storage (UFS) standard, etc.), and may communicate according to the specific communication standard, for example, for the memory device 100 to communicate with the host device 50, wherein the host device 50 may include a corresponding transmission interface circuit that complies with the specific communication standard to communicate with the memory device 100.

[0073] In the present embodiment, the host device 50 may transmit a host command and a corresponding logical address to the flash memory controller 110 to access the memory device 100. The flash memory controller 110 receives the host command and the logical address, and converts the host command into a memory operation command (hereinafter referred to as an operation command), and further uses the operation command to control the flash memory module 120 to perform operations such as reading, writing, and programming on memory cells (such as data pages) at certain physical addresses in the flash memory module 120, wherein the physical address corresponds to the logical address. When the flash memory controller 110 performs an erase operation on any flash memory chip 122-n among the multiple flash memory chips 122-1, 122-2, ... and 122-N (where "n" can represent any integer in the interval [1, N]), at least one block among the multiple blocks of the flash memory chip 122-n can be erased, wherein each block among the multiple blocks can include multiple pages (e.g., data pages), and an access operation (e.g., read or write) can be performed on one or more pages.

[0074] Figure 2 is a schematic diagram of a three-dimensional (3D) NAND flash memory according to an embodiment of the present invention. For example, any memory element in at least one of the aforementioned flash memory chips 122-1, 122-2, ... and 122-N may be based on Figure 2 The three-dimensional NAND flash memory is shown as an implementation, but the present invention is not limited thereto.

[0075] According to the present embodiment, the three-dimensional NAND flash memory may include a plurality of memory cells arranged in a three-dimensional structure, such as (Nx * Ny * Nz) memory cells {{M(1, 1, 1), …, M(Nx, 1, 1)}, {M(1, 2, 1), …, M(Nx, 2, 1)}, …, {M(1, Ny, 1), …, M(Nx, Ny, 1)}}, {{M(1, 1, 2), …, M(Nx, 1,2)}, {M(1, 2, 2), …, M(Nx, 2, 2)}, …, {M(1, Ny, 2), …, M(Nx, Ny, 2)}}, …, and {{M(1, 1, Nz), …, M(Nz, 2, 1)}}. The present invention may further include a plurality of selector circuits for performing selection control, such as (Nx * Ny) upper selection circuits {MBLS(1, 1), …, MBLS(Nx, 1)}, {MBLS(1, 2), …, MBLS(Nx, 2)}, … and {MBLS(1, Ny), …, MBLS(Nx, Ny)} arranged in an upper layer above the Nz layer, and (Nx * Ny) lower selection circuits {MSLS(1, 1), …, MSLS(Nx, 1)}, {MSLS(1, 2), …, MBLS(Nx, 2)}, … and {MBLS(1, Ny), …, MBLS(Nx, Ny)} arranged in a lower layer below the Nz layer. In addition, the three-dimensional NAND flash memory may include a plurality of bit lines and a plurality of word lines for access control, such as Nx bit lines BL(1), ..., and BL(Nx) arranged in a top layer above the upper layer, and (Ny * Nz) word lines {WL(1, 1), WL(2, 1), ..., WL(Ny, 1)}, {WL(1, 2), WL(2, 2), ..., WL(Ny, 2)}, ..., and {WL(1, Nz), WL(2, Nz), ..., WL(Ny, Nz)} arranged in the Nz layer, respectively.In addition, the three-dimensional NAND flash memory may include a plurality of selection lines for selection control, such as Ny upper selection lines BLS(1), BLS(2), ... and BLS(Ny) arranged in the upper layer, and Ny lower selection lines SLS(1), SLS(2), ... and SLS(Ny) arranged in the lower layer, and may further include a plurality of source lines for providing multiple reference levels, such as Ny source lines SL(1), SL(2), ... and SL(Ny) arranged in a bottom layer below the lower layer.

[0076] like Figure 2As shown, the three-dimensional NAND flash memory can be divided into Ny circuit modules PS2D(1), PS2D(2), ... and PS2D(Ny) distributed along the Y axis. For ease of understanding, the circuit modules PS2D(1), PS2D(2), ... and PS2D(Ny) may have certain electrical characteristics similar to a planar NAND flash memory (whose memory cells are arranged in a single layer), and therefore may be respectively regarded as a plurality of pseudo-2D circuit modules, but the present invention is not limited thereto. In addition, any circuit module PS2D(ny) among the circuit modules PS2D(1), PS2D(2), ... and PS2D(Ny) may include Nx secondary circuit modules S(1, ny), ... and S(Nx, ny), where "ny" may represent any integer in the interval [1, Ny]. For example, circuit module PS2D(1) may include Nx secondary circuit modules S(1, 1), ... and S(Nx, 1), circuit module PS2D(2) may include Nx secondary circuit modules S(1, 2), ... and S(Nx, 2), ..., and circuit module PS2D(Ny) may include Nx secondary circuit modules S(1, Ny), ... and S(Nx, Ny). In the circuit module PS2D(ny), any one of the secondary circuit modules S(1, ny), … and S(Nx, ny) may include Nz memory cells M(nx,ny, 1), M(nx, ny, 2), … and M(nx, ny, Nz), and may include a set of selection circuits corresponding to the memory cells M(nx, ny, 1), M(nx, ny, 2), … and M(nx, ny, Nz), such as an upper selection circuit MBLS(nx, ny) and a lower selection circuit MSLS(nx, ny), where “nx” may represent any integer in the interval [1, Nx]. The upper selection circuit MBLS(nx, ny), the lower selection circuit MSLS(nx, ny) and the memory cells M(nx, ny, 1), M(nx, ny,2), ... and M(nx, ny, Nz) can be implemented by transistors. For example, the upper selection circuit and the lower selection circuit MSLS(nx, ny) can be implemented by ordinary transistors without any floating gates, and any memory cell M(nx, ny, nz) among the memory cells M(nx, ny, 1), M(nx, ny, 2), ... and M(nx, ny, Nz) can be implemented by a floating gate transistor, where "nz" can represent any integer in the interval [1, Nz], but the present invention is not limited to this.In addition, the upper selection circuits MBLS(1, ny), ... and MBLS(Nx, ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line BLS(ny), and the lower selection circuits MSLS(1, ny), ... and MSLS(Nx, ny) in the circuit module PS2D(ny) can be selected according to the selection signal on the corresponding selection line SLS(ny).

[0077] In the flash memory module 120, when the block of any one of the flash memory chips 122-1 to 122-N is a single-level cell (SLC) block, each physical page in the block corresponds to a logical page, that is, each memory cell of the page is used to store only one bit, wherein a physical page may include a plurality of transistors controlled by a word line (for example, memory cells M(1, 1, Nz) to M(Nx, 1, Nz) corresponding to word line WL(1, Nz) form a physical page). When the block of any one of the flash memory chips 122-1 to 122-N is a multiple-level cell (MLC) block, each physical page in the block corresponds to two logical pages, that is, each memory cell of the page is used to store two bits. When the block of any one of the flash memory chips 122-1 to 122-N is used as a triple-level cell (TLC) block, each physical page in the block corresponds to three logical pages, that is, each memory cell of the page is used to store three bits. When the block of any one of the flash memory chips 122-1 to 122-N is used as a quad-level cell (QLC) block, each physical page in the block corresponds to four logical pages, that is, each memory cell of the page is used to store four bits.

[0078] Figure 3 1 is a flow chart of a method for managing a flash memory module 120. In step 300, the process starts, and the flash memory controller 110 and the flash memory module 120 are powered on from a power-off state. In step 302, the microprocessor 112 of the flash memory controller 110 starts to build a group minimum valid page array. Specifically, the blocks in the flash memory module 120 are divided into a plurality of groups, and each group includes a plurality of blocks. Figure 4A plurality of groups 410_1 to 410_M are shown according to an embodiment of the present invention, wherein group 410_1 includes blocks B_1 to B_N, group 410_2 includes blocks B_(N + 1) to B_2 * N, group 410_3 includes blocks B_(2*N+1) to 3 * N, ..., and group 410_M includes blocks B_((M-1 * N + 1)) to B_(M * N).

[0079] In a first embodiment of the grouping method, each group has the same number of blocks, and the remaining blocks are not grouped. For example, if there are one thousand blocks, thirty-two groups can be set, each group includes thirty-one blocks, and the remaining eight blocks are not grouped. In a second embodiment of the grouping method, different groups can have different numbers of blocks.

[0080] Please refer to Figure 5 , the microprocessor 112 establishes a valid data page table 510, wherein the valid data page table 510 records a plurality of block indexes and corresponding numbers of valid data pages, for example, the number of valid data pages in block B_1 is C_1, the number of valid data pages in block B_2 is C_2, the number of valid data pages in block B_3 is C_3, and so on. It is worth noting that some blocks in blocks B_1 to block B_(M*N) are blank, so the valid data page table 510 only records the blocks in which data is stored. If a write operation is performed on the flash memory module 120, for example, if new data is written to block B_2 and the new data is used to update the original data stored in block B_1 (for example, the new data and the original data have the same logical address), the valid data page table 510 can be updated by increasing the number C_2 and decreasing the number C_1. In addition, the valid data page table 510 can be stored in the RAM 116 or an external dynamic random access memory (DRAM).

[0081] According to the groups 410_1-410_M and the valid data page table 510, the microprocessor 112 establishes a grouped least valid data page array 520. Specifically, the grouped least valid data page array 520 records the group index (groupindex) between the blocks and the corresponding least valid data page. In detail, the microprocessor 112 refers to the valid data page table 510 to obtain the valid data page numbers C_1-C_N corresponding to the blocks B_1-B_N in the group 410_1, and the microprocessor 112 selects the minimum value among the numbers C_1-C_N as the least valid data page C_G1 recorded in the grouped least valid data page array 520. For example, if C_1, C_2, C_3, ..., C_N are 64, 40, 90, ..., 80 respectively, then the number C_2 can be selected, and the grouped least valid data page array 520 records the number C_2 as the least valid data page C_G1 corresponding to the group 410_1. Similarly, the microprocessor 112 refers to the valid data page table 510 to obtain the valid data page numbers C_(N + 1)-C_2 * N corresponding to the blocks B_(N + 1)-B_2 * N in the group 410_2, respectively, and the microprocessor 112 selects the minimum value of the numbers C_(N + 1)~C_2 * N as the least valid data page C_G2 recorded in the group least valid data page array 520. In addition, the group least valid data page array 520 can be stored in the RAM 116 or the DRAM.

[0082] In step 304, the microprocessor 112 determines whether the valid data page table 510 is updated and whether the number of valid data pages of at least one block is changed. If so, the process proceeds to step 306; if not, the process proceeds to step 312. If a write operation is performed on the flash memory module 120, the valid data page table 510 may be updated, and the number of valid data pages of one or more blocks may be increased, and / or the number of valid data pages of one or more blocks may be decreased.

[0083] In step 306, the microprocessor 112 determines the group of blocks having a changed number of valid data pages, and the microprocessor 112 refers to the group least valid data page array 520 to obtain the least valid data page corresponding to the determined group. For example, if the number C_3 corresponding to block B_3 is changed, the microprocessor 112 obtains the number C_G1 from the group least valid data page array 520.

[0084] In step 308 , the microprocessor 112 determines whether the number of valid data pages after the change in step 304 is less than the minimum number of valid data pages obtained in step 306 . If so, the process proceeds to step 310 ; if not, the process proceeds to step 304 .

[0085] In step 310, the microprocessor 120 updates the grouped least valid data page array 520 by using the valid data page number changed in step 304. For example, if the number C_G1 is equal to the number C_3 having a value of "40", and the number C_2 is updated to "38" in step 304, the microprocessor 112 updates the number C_G1 by using the number C_2.

[0086] In step 312 , it is determined whether the flash memory microprocessor 112 receives a shutdown notification from the host device 50 . If so, the process proceeds to step 314 to shut down the flash memory controller 110 and the flash memory module 120 . If not, the process proceeds to step 304 .

[0087] Figure 6 FIG. 6 is a flow chart of a method for managing a flash memory module 120 according to another embodiment of the present invention. In step 600, the process starts, and the grouped least valid data page array 520 has been stored in the RAM 116 or the external DRAM. In step 602, the microprocessor 112 refers to the grouped least valid data page array 520 to select the first group. Figure 4 For example, group 410_1 is selected, and the least valid data page C_G1 is used as the global least valid data page. In step 604, the microprocessor 112 determines whether the current group is the last group recorded in the group least valid data page array 520. If so, the process proceeds to step 612; if not, the process proceeds to step 606. In step 606, the microprocessor 112 selects the next group and obtains the least valid data page of the current group. In this case, group 410_2 is selected to obtain the least valid data page C_G2. In step 608, the microprocessor 112 determines whether the least valid data page obtained in step 608 is less than the global least valid data page. If so, the process proceeds to step 610; if not, the process proceeds to step 604. In step 610, the microprocessor 112 updates the global least valid data page by using the least valid data page obtained in step 606. For example, if the overall least valid data page is the least valid data page C_G1 , and the least valid data page C_G2 is smaller than the least valid data page C_G1 , the overall least valid data page becomes the least valid data page C_G2 .

[0088] In step 612, the microprocessor 112 sequentially searches for the block in the group with the least overall valid data page. In step 614, the microprocessor 112 determines whether the current block is the last block. If so, the process proceeds to step 618; if not, the process proceeds to step 616. In step 616, the microprocessor 112 refers to the valid data page table 510 to obtain the valid data page of the current block, and the microprocessor 112 determines whether the valid data page of the current block is equal to the least overall valid data page. If so, the process proceeds to step 618; if not, the process proceeds to step 614. In step 618, the microprocessor 618 selects the block with the least overall valid data page, and the microprocessor 618 adds the block to a garbage collection queue, wherein the blocks recorded in the garbage collection queue will undergo a garbage collection operation to move valid data to other blocks. In step 620, the process ends.

[0089] exist Figure 3 and Figure 6 In the illustrated embodiment, by establishing the grouped least valid data page array 520 and searching for the block with the least valid data page using the grouped least valid data page array 520, the microprocessor 112 can simply obtain the block with the least valid data page by searching or scanning the blocks within a group without searching the blocks belonging to other groups. Therefore, the search time is shortened and the system efficiency may not be reduced.

[0090] In one embodiment of the present invention, Figure 4 and Figure 5 As shown, all blocks in the flash memory module 120 need to be grouped in the grouped least valid data page array 520, that is, no matter whether they are SLC blocks, MLC blocks, TLC blocks, QLC blocks, data blocks or spare blocks, they need to be grouped in a single grouped least valid data page array 520. In another embodiment, two or more grouped least valid data page arrays are established according to the type of blocks. Figure 7 For example, the flash memory module 120 has different types of blocks such as SLC blocks and TLC blocks. The TLC blocks are grouped into a plurality of groups 710_1 to 710_K, and each group includes a plurality of TLC blocks. According to the number of valid data pages of the TLC blocks, the following structure can be established: Figure 5 In addition, the SLC blocks are grouped into a plurality of groups 720_1 to 720_P, and each group includes a plurality of SLC blocks, wherein according to the number of valid data pages of the SLC blocks, a first grouping least valid data page array is established as follows: Figure 5The second grouped least valid data page array is similar to the grouped least valid data page array 520. In this embodiment, garbage collection operations are performed on the TLC blocks and the SLC blocks respectively, that is, the microprocessor 112 determines the TLC block with the least valid data page according to the first grouped least valid data page array, and the microprocessor 112 determines the SLC block with the least valid data page according to the second grouped least valid data page array.

[0091] In another embodiment, only a portion of the blocks in the flash memory module 120 are grouped, while other blocks are not grouped. Figure 7 For example, the flash memory module 120 has different types of blocks such as SLC blocks and TLC blocks, and only TLC blocks are grouped to generate a grouped least valid data page array, while the SLC blocks are not grouped, that is, the grouped least valid data page array does not include information of the SLC blocks.

[0092] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for managing a flash memory module, comprising: Dividing a plurality of blocks in the flash memory module into a plurality of groups, wherein each group includes at least two blocks; Establishing a valid data page table, wherein the valid data page table respectively records the indexes of the plurality of blocks and the corresponding numbers of valid data pages; Establishing a group least valid data page array according to the valid data page table, wherein the group least valid data page array respectively records the group index and the corresponding least valid data page, and the least valid data page of each group is obtained by selecting a minimum value from the number of valid data pages of the blocks in the group; Referencing the group least valid data page array to select a target group having an overall least valid data page, wherein the overall least valid data page is obtained by selecting a minimum value among the least valid data pages of the plurality of groups; Searching the at least two blocks in the target group without searching blocks in other groups to determine a target block having the least overall valid data page; as well as The target block is added to a garbage collection queue.

2. The method according to claim 1, characterized in that The flash memory module includes a plurality of blocks of a first type and a plurality of blocks of a second type, and the grouped plurality of blocks only include the blocks of the first type but do not include the blocks of the second type.

3. The method according to claim 2, characterized in that The first type of block is a triple-level cell (TLC) block or a quad-level cell (QLC) block, and the second type of block is a single-level cell (SLC) block.

4. A flash memory controller, wherein the flash memory controller is coupled to a flash memory module, and the flash memory controller comprises: a memory for storing a program code; as well as a microprocessor, used to execute the program code to access the flash memory module; wherein the microprocessor divides the plurality of blocks in the flash memory module into a plurality of groups, wherein each group includes at least two blocks; the microprocessor establishes a valid data page table, wherein the valid data page table respectively records the indexes of the plurality of blocks and the corresponding number of valid data pages; the microprocessor establishes a group least valid data page array according to the valid data page table, wherein the group least valid data page array respectively records the group index and the corresponding least valid data page, and the least valid data page of each group is obtained by selecting a minimum value from the number of valid data pages of the blocks in the group; the microprocessor refers to the group least valid data page array to select a target group having an overall least valid data page, wherein the overall least valid data page is obtained by selecting a minimum value from the least valid data pages in the plurality of groups; the microprocessor searches the at least two blocks in the target group without searching the blocks in other groups to determine a target block having the overall least valid data page; And the microprocessor adds the target block to a garbage collection queue.

5. The flash memory controller according to claim 4, wherein: The flash memory module includes a plurality of blocks of a first type and a plurality of blocks of a second type, and the grouped plurality of blocks only include the blocks of the first type but do not include the blocks of the second type.

6. The flash memory controller according to claim 5, wherein: The first type of block is a triple-level cell (TLC) block or a quad-level cell (QLC) block, and the second type of block is a single-level cell (SLC) block.

7. An electronic device comprising: a flash memory module; and a flash memory controller for accessing the flash memory module; The flash memory controller divides the multiple blocks in the flash memory module into multiple groups, wherein each group includes at least two blocks; the flash memory controller establishes a valid data page table, wherein the valid data page table respectively records the indexes of the multiple blocks and the corresponding number of valid data pages; the flash memory controller establishes a group minimum valid data page array according to the valid data page table, wherein the group minimum valid data page array respectively records the group index and the corresponding minimum valid data page, and the minimum valid data page of each group is obtained by selecting a minimum value from the number of valid data pages of the blocks in the group; the flash memory controller refers to the group minimum valid data page array to select a target group with an overall minimum valid data page, wherein, The overall least valid data page is obtained by selecting a minimum value from the least valid data pages in the plurality of groups; the flash memory controller searches the at least two blocks in the target group without searching blocks in other groups to determine a target block having the overall least valid data page; And the flash memory controller adds the target block to a garbage collection queue.

8. The electronic device as claimed in claim 7, characterized in that: The flash memory module includes a plurality of blocks of a first type and a plurality of blocks of a second type, and the grouped plurality of blocks only include the blocks of the first type but do not include the blocks of the second type.

9. The electronic device as claimed in claim 8, characterized in that: The first type of block is a triple-level cell (TLC) block or a quad-level cell (QLC) block, and the second type of block is a single-level cell (SLC) block.

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