Time-varying decision feedback equilibrium

Abstract

This application relates to time-varying decision feedback equalization. A memory device may be coupled to a host device using one or more conductive lines. A receiver may receive a signal transmitted from another device via the conductive lines. The receiver may include decision circuitry for determining the voltage of the received signal based on the received signal and a feedback signal, and outputting an output signal. The receiver may include a variable time delay circuit configured to output a delayed version of the output signal, and a gain circuit configured to scale the delayed signal to generate the feedback signal. The variable time delay circuit may include a delay element with a variable delay parameter. The receiver may be coupled to a memory array storing information delivered by the output signal.

Description

[0001] Cross-reference of related applications

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 149,364, filed January 14, 2021, entitled "Time-Variable Decision Feedback Equilibrium," which has been assigned to its assignee and whose entire contents are expressly incorporated herein by reference. Technical Field

[0003] This technical field relates to time-varying decision feedback equilibrium. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of those states. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program the states into the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, and so on. Memory cells can be volatile or non-volatile. Even without an external power supply, non-volatile memories, such as FeRAM, can maintain their stored logic state for a long time. When disconnected from an external power supply, volatile memory devices, such as DRAM, may lose their stored state. Summary of the Invention

[0006] This document discloses an apparatus. The apparatus may include: a memory array; a first circuit coupled to the memory array and conductive lines configured to receive an input signal representing data written to or read from the memory array and to output a second signal, the first circuit being configured to determine a voltage of the first signal at least in part based on the input signal and a feedback signal at a sampling event; a second circuit coupled to the output of the first circuit and configured to apply one or more variable time delays to the second signal and output one or more delayed signals; and a third circuit coupled to the second circuit and the first circuit, the third circuit being configured to generate the feedback signal at least in part based on the one or more delayed signals output by the second circuit.

[0007] This document discloses a method. The method may include: at a sampling event, determining a voltage of a first signal based at least in part on a feedback signal and an input signal received via a conductive line and representing data written to or read from a memory array; outputting a second signal having a voltage level at least in part based on the voltage determined from the first signal; applying a variable time delay to the second signal to output a delayed signal; and generating the feedback signal at least in part based on the delayed signal.

[0008] This document discloses an apparatus. The apparatus may include: a memory array; and a controller coupled to the memory array, the controller being operable such that the apparatus: at a sampling event, determines a voltage of a first signal based at least in part on a feedback signal and an input signal received via a conductive line and representing data written to or read from the memory array; outputs a second signal having a voltage level at least in part based on the voltage determined by the first signal; applies a variable time delay to the second signal to output a delayed signal; and generates the feedback signal at least in part based on the delayed signal. Attached Figure Description

[0009] Figure 1 This section describes examples of systems that support time-varying decision feedback equilibrium, based on examples disclosed in this document.

[0010] Figure 2 This section describes an example of a circuit that supports time-varying decision feedback equalization, based on examples disclosed herein.

[0011] Figure 3 This section describes an example of a circuit that supports time-varying decision feedback equalization, based on examples disclosed herein.

[0012] Figure 4 This section describes an example of a signal graph supporting time-varying decision feedback equilibrium, based on examples disclosed herein.

[0013] Figure 5 This section describes an example of a circuit that supports time-varying decision feedback equalization, based on examples disclosed herein.

[0014] Figure 6 A block diagram of a receiving device supporting time-varying decision feedback equilibrium, based on examples disclosed herein, is shown.

[0015] Figure 7 The flowchart illustrates one or more methods for supporting time-varying decision feedback equilibrium, based on examples disclosed herein. Detailed Implementation

[0016] Signals transmitted between devices (e.g., a host device and a memory device) via conductive lines can be degraded when they reach the receiving device. In some instances, reflections of the transmitted signal occur on the conductive lines and interfere with subsequent portions of the signal (or subsequent signals transmitted via the conductive lines). To compensate for this interference, the receiving device may use equalization to cancel reflections (or other interference) caused by previous signals before processing the received signal. In some instances, the receiving device includes decision feedback equalization (DFE) circuitry configured to reduce interference in the received signal.

[0017] The DFE circuit may include decision circuitry that samples the received signal. In some instances, the decision circuitry may sample the received signal on a unit-interval basis. The decision circuitry may further output a digitized signal based on the received signal. The DFE circuitry may also include feedback circuitry that feeds back a time-delayed and scaled version of the signal (digital or analog) to subsequent portions of the received signal to cancel reflections caused by the received signal. The feedback circuitry may include a time-delay circuitry and a variable-gain circuitry. In some instances, the time-delay circuitry may apply a fixed time delay (e.g., full and / or fractional time delay) to the signal output by the decision circuitry, and the variable-gain circuitry may scale the time-delayed signal to produce the feedback signal. The DFE circuitry may subtract the feedback signal from the received signal to obtain the modified signal before the decision circuitry processes a modified signal that more closely represents the original transmitted signal.

[0018] However, the performance of a DFE circuit can be limited by the type, number, and / or fixed time delay of the delay elements included in the delay circuit. That is, in some instances, the DFE circuit contains only delay elements that introduce a delay equal to an integer multiple of the unit interval. In such cases, if the reflection delay of the information signal is a non-integer multiple of the unit interval, the feedback signal may not be aligned with the reflection of the information signal, thereby reducing the cancellation performance of the feedback signal. In some instances, to better align the feedback signal with the reflection and improve equalization performance, the DFE circuit may also include fractional delay elements that introduce a delay that is a non-integer multiple of the unit interval. However, increasing the number of delay elements in a DFE circuit that also includes fractional delay elements can increase the complexity, footprint, and / or power consumption of the DFE circuit.

[0019] Alternatively, a DFE circuit may include a limited number of delay elements (e.g., fewer than three delay elements)—for example, to save power, reduce complexity, and decrease footprint. In such cases, a limited number of delay elements can produce a fixed set of time-delayed signals that fail to overlap with more significant reflections occurring with non-overlapping delays. Therefore, significant reflections can be passed to the input of the decision circuit without any compensation. For example, if a DFE circuit includes a first delay element that applies a one-unit delay interval and a second delay element that applies three-unit delay intervals, the DFE circuit may not reduce reflections with two-unit delay intervals. In some instances, to avoid lost reflections, a DFE circuit may be configured with a large number of delay elements (e.g., full and fractional delay elements) and may activate a set of delay elements that reduce reflections by a threshold amount. In some cases, including and supporting a large number of delay elements can increase the complexity and footprint of the DFE circuit.

[0020] To improve the performance of a DFE circuit while using a reduced number of delay elements, the DFE circuit can be configured to include one or more variable time delay elements. The DFE circuit may include: a decision circuit that determines the voltage level of the received information signal and generates an output information signal; a delay circuit that includes one or more delay elements and generates one or more delayed signals based on the output information signal; and a variable gain circuit that includes one or more variable gain amplifiers and generates a feedback signal based on one or more delayed signals. In some instances, the delay parameters of the one or more delay elements may be programmable or adjustable such that the delayed signal is time-aligned with a significant reflection of the received information signal.

[0021] The features of this disclosure are initially described in the context of a system. The features of this disclosure are also described in the context of circuit and signal diagrams. These and other features of this disclosure are further illustrated and described with reference to device diagrams and flowcharts related to time-varying decision feedback equalization.

[0022] Figure 1 This describes an example of a system 100 supporting time-varying decision feedback equilibrium, as disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include electronic devices, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicle or other system components. For example, system 100 may describe aspects of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, etc. Memory device 110 may be a component of the system, operable to store data from one or more other components of system 100.

[0024] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or some other fixed or portable electronic device, and other examples. In some examples, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0025] Memory device 110 may be a standalone device or a component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors of the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 may be operable to store data of components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0027] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other using bus 135.

[0028] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or may be part of processor 125.

[0029] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tesserials, one or more segments), wherein each memory cell is operable to store at least one bit of data. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory or multi-die package or multi-chip memory or multi-chip package.

[0031] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions enabling the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0032] Local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, local memory controller 165 may be operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155 and local memory controller 165, or external memory controller 120 may perform the various functions described herein. Thus, local memory controller 165 may be operable to communicate with device memory controller 155, other local memory controllers 165, or directly with external memory controller 120 or processor 125, or a combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0033] External memory controller 120 may be operable to enable communication of one or more of the following between a component of system 100 or host device 105 (e.g., processor 125) and memory device 110: information, data, or commands. External memory controller 120 may translate or interpret the communication exchanged between a component of host device 105 and memory device 110. In some instances, the external memory controller 120 described herein, or other components of system 100 or host device 105, or their functionality, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, the external memory controller 120 described herein, or its functionality, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165) or vice versa.

[0034] Components of host device 105 may use one or more channels 115 to exchange information with memory device 110. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0035] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be conveyed through channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0036] In some instances, CA channel 186 may be operable to transmit commands between host device 105 and memory device 110, including control information (e.g., address information) associated with the command. For example, a command carried by CA channel 186 may include a read command with an address of the desired data. In some instances, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) for decoding one or more of the address or command data.

[0037] In some instances, clock signal channel 188 may be operable to transmit one or more clock signals between host device 105 and memory device 110. Each clock signal may be operable to oscillate between high and low states and may support coordination (e.g., in timing) between the actions of host device 105 and memory device 110. In some instances, the clock signal may be single-ended. In some instances, the clock signal may provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Therefore, the clock signal may be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., an oscillator, crystal, logic gate, transistor).

[0038] In some instances, data channel 190 may be operable to transmit one or more of data or control information between host device 105 and memory device 110. For example, data channel 190 may (e.g., bidirectionally) transmit information to be written to or read from memory device 110.

[0039] Channel 115 may contain any number of signal paths (including a single signal path). In some instances, channel 115 may contain multiple individual signal paths. For example, the channel may be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), x16 (e.g., containing sixteen signal paths), etc.

[0040] Signals transmitted through channel 115 can be modulated using one or more different modulation schemes. In some instances, a binary symbol (or binary level) modulation scheme can be used to modulate signals transmitted between host device 105 and memory device 110. The binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M equals 2. Each symbol of the binary symbol modulation scheme can be a digital data operable to represent a single bit (e.g., a symbol can represent logic 1 or logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or other schemes.

[0041] In some instances, non-binary symbol (or multi-level) modulation schemes can be used to modulate signals transmitted between host device 105 and memory device 110. The non-binary modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Unlike binary symbol modulation schemes, each symbol in a non-binary modulation scheme may be operable to represent more than one bit of digital data (e.g., the symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of non-binary modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or other schemes. The non-binary signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme comprising at least three levels to encode more than one bit of information. Non-binary modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0042] Memory device 110 may receive information signals (e.g., data signals, control signals, clock signals, etc.) from host device 105 via one or more channels 115—for example, during a write operation. Similarly, host device 105 may receive information signals from memory device 110 via one or more channels 115—for example, during a read operation. In some instances, channel characteristics (e.g., the frequency response of the channel, the impedance matching of the channel, etc.) may affect the transmission of information signals through the channel. In some instances (e.g., due to impedance mismatch between the conductor and the termination point), reflections of information signals may occur on the channel. The reflection of the information signal may be a time-delayed and attenuated version of the information signal, which, combined with a later portion of the information signal, results in a modified information signal (relative to the information signal transmitted from the transmitter) being received at the receiving device.

[0043] Memory device 110 may include decision circuitry that determines the voltage level of a received information signal. In some instances, the decision circuitry may periodically sample the received information signal based on the rising and / or falling edges of a clock. Each time the decision circuitry samples the received signal may be referred to as a sampling event. Sampling events may be separated from each other by a set duration (also referred to as a unit interval) based on the clock frequency. At the time of a sampling event, the decision circuitry may compare the voltage of the received information signal with one or more threshold voltages and output a voltage with a specific voltage level based on the comparison—for example, a voltage greater than or less than a threshold voltage or between a pair of threshold voltages. In some instances, variations in the information signal caused by reflection result in the decision circuitry outputting a signal with a voltage level inconsistent with the voltage level of the information signal initially transmitted from host device 105, leading to data storage / retrieval errors.

[0044] To compensate for variations in the transmitted signal that may occur during transmission, the receiving device (e.g., host device 105 or memory device 110) may apply equalization techniques to the received information signal. For example, the receiving device may use a DFE circuit, which includes a decision circuit (which may be or include a limiter), a delay circuit (which may include one or more delay elements, also referred to as tap delay), and a variable gain circuit (also referred to as a scaling circuit and may include one or more variable gain amplifiers). The decision circuit determines the voltage level of the signal received at its input—for example, by comparing the signal's voltage level with one or more threshold voltages. Based on these comparisons, the decision circuit outputs a signal (also referred to as an output signal) that transitions between different voltage levels within a set of possible voltage levels.

[0045] The signal output by the decision circuit can be received by a delay circuit, which can output one or more delayed versions (also referred to as delayed signals) of the output signal. In some instances, the delay circuit includes one or more delay elements, each of which outputs a corresponding delayed signal with a corresponding delay relative to the output signal. In some instances, each delay element outputs a delayed signal with a duration that is an integer multiple of a unit interval (e.g., one unit interval, two unit intervals, etc.) relative to the output signal. In some instances, one or more delay elements can output delayed signals with a duration that is not an integer multiple of a unit interval (e.g., one and a half unit intervals, one and three-quarter unit intervals, etc.), and may be referred to as fractional delay elements.

[0046] The variable gain can receive a delayed signal and output a scaled version of the delayed signal (also known as a feedback signal). In some instances, the variable gain outputs a feedback signal with a magnitude smaller than the corresponding delayed signal received at the variable gain—for example, the magnitude of the feedback signal can be matched to the magnitude of the reflected component of the input signal.

[0047] In some instances, the feedback signal can be applied to a subtraction circuit that also receives information signals from the transmitting device. The subtraction circuit subtracts the feedback signal from the information signal, which can cause the reflected components of the information signal to be reduced (or canceled) by scaling versions of one or more delayed signals. The subtraction circuit can output a modified signal based on the subtraction, which can be received at a decision circuit. In other instances, the feedback signal can be applied to a threshold generation circuit and used to modify the threshold voltage used by the decision circuit. In such cases, the received information signal can be directly input to a first input of the decision circuit, and the modified threshold voltage can be directly input to a second input of the decision circuit (and the decision circuit may be or include a comparator). In some instances, a training program is used to tune a variable gain to optimally reduce the reflected components of the received information signal—for example, by aligning the magnitudes of one or more feedback signals with the magnitudes of one or more corresponding reflections.

[0048] However, the performance of a DFE circuit can be limited by the type, number, and / or fixed time delay of the delay elements included in the delay circuit. That is, in some instances, the DFE circuit contains only delay elements that introduce delays that are integer multiples of the unit interval. In such cases, if the reflection delay of the information signal is a non-integer multiple of the unit interval, the feedback signal may not be aligned with the reflection of the information signal (or may be poorly aligned), thus reducing the cancellation performance of the feedback signal. In some instances, to better align the feedback signal with the reflection and improve equalization performance, the DFE circuit may also include fractional delay elements that introduce delays that are non-integer multiples of the unit interval. However, increasing the number of delay elements in a DFE circuit that also includes fractional delay elements can increase the complexity, footprint, and / or power consumption of the DFE circuit.

[0049] Alternatively, a DFE circuit may include a limited number of fixed-delay delay elements (e.g., less than three delay elements)—for example, to save power, reduce complexity, and decrease footprint. In such cases, a limited number of delay elements can produce a fixed set of time-delayed signals that fail to overlap with more significant reflections occurring with non-overlapping delays. Therefore, significant reflections can be passed to the input of the decision circuit without any compensation. For example, if a DFE circuit includes a first delay element applying a one-unit delay interval and a second delay element applying three-unit delay intervals, then the DFE circuit may not reduce reflections with two-unit delay intervals. In some instances, to avoid lost reflections, a DFE circuit may be configured with a large number of delay elements (e.g., full and fractional delay elements) and may activate a set of delay elements that reduce reflections by a threshold amount. However, including and supporting a large number of delay elements increases the complexity and footprint of the DFE circuit.

[0050] To improve the performance of a DFE circuit while using a reduced number of delay elements, the DFE circuit can be configured to include variable time delay elements. The DFE circuit may include: a decision circuit that determines the voltage level of the received information signal and generates an output information signal; a delay circuit that includes one or more variable time delay elements and generates one or more delayed signals based on the output information signal; and a variable gain circuit that includes one or more variable gain amplifiers and generates a feedback signal based on one or more delayed signals. In some instances, the delay parameters of the one or more delay elements may be programmable or adjustable such that the delayed signal generated by the delay circuit is time-aligned with a significant reflection of the received information signal. Techniques for determining the delay parameters of the delay elements may include a minimum mean square error technique based on the received information signal and the corresponding output information signal.

[0051] Figure 2 This describes an example of a circuit supporting time-varying decision feedback equalization, as disclosed herein. Circuit 200 includes a set of components configured to perform decision feedback equalization using variable time-delay elements. Circuit 200 may include input line 205, decision circuitry 210, output line 215, control circuitry 220, and feedback circuitry 225. Feedback circuitry 225 may include variable gain circuitry 230 and variable time-delay circuitry 235.

[0052] Input line 205 may be a conductive line coupling a transmitting device (e.g., a host device) to a receiving device (e.g., a memory device). In some instances, input line 205 is coupled to a channel, such as... Figure 1 The channel 115 (or a portion thereof) is coupled. In some instances, the channel response to input line 205 can be determined or estimated—for example, during a testing or modeling phase. The channel response can indicate the signal generated on input line 205 in response to a signal transmitted through input line 205. In some instances, the signal located at the end of input line 205 may differ from the signal located at the beginning of input line 205 (near the transmission device). Alternatively or additionally, reflection of the signal transmitted through input line 205 may occur after the initial transmission, wherein the reflection may be time-delayed and attenuated relative to the initial transmission. In some instances, signal reflection may interfere with other signals (or other portions of the same signal) subsequently transmitted through input line 205.

[0053] Decision circuit 210 can be configured to determine the voltage of a received signal corresponding to a signal transmitted via input line 205. In some instances, the signal transmitted via input line 205 may be referred to as an input (IN) signal. The input signal may contain (or represent) information stored in or read from a memory array. At discrete moments (also referred to as sampling events), decision circuit 210 may compare the received signal with one or more thresholds to determine the voltage of the received signal at each moment. For example, if a threshold is used, then decision circuit 210 may determine a first voltage (e.g., 1V) of the signal when the voltage of the received signal is higher than the threshold and a second voltage (e.g., 0V) of the signal when the voltage of the received signal is lower than the threshold at the first sampling event. Decision circuit 210 may output a signal that transitions between a set of voltages based on the comparisons—that is, decision circuit 210 may output a digitized signal. The signal output by decision circuit 210 may be referred to as an output (OUT) signal. The output signal may contain (or represent) information stored in or read from a memory array. In some instances, decision circuit 210 may include a comparator. In some instances, the decision circuit 210 may include a subtraction circuit and an analog-to-digital converter or comparator. In some instances, the comparator is a multi-stage comparator. The analog-to-digital converter and / or comparator may also be referred to as a limiter.

[0054] Output line 215 can be configured to couple the output of decision circuitry 210 to storage or data processing components. In some instances, output line 215 can be coupled to a controller for accessing the memory array or to the memory array itself. In other instances, output line 215 can be coupled to a processor at a host device, the processor being configured to use data in the output signal to perform functions.

[0055] Control circuit 220 can be configured to tune the delay parameters of variable time delay circuit 235. Alternatively, control circuit 220 can be configured to tune the scaling parameters of variable gain circuit 230. Control circuit 220 can be configured to generate a control (CTL) signal based on comparing the signal output from decision circuit 210 with the signal input to decision circuit 210. Control circuit 220 may use a least mean square technique to generate the control signal. In some instances, control circuit 220 includes a subtraction circuit that subtracts the output signal from the signal input to decision circuit 210 to generate the control signal. In other instances, control circuit 220 also includes a subtraction circuit that subtracts the output signal from the signal input to decision circuit 210, a delay circuit that delays the resulting signal, and additional subtraction circuitry that subtracts the resulting signal from a delayed version of the resulting signal to generate the control signal.

[0056] In some instances, control circuitry 220 may be configured to generate control signals solely for variable time delay circuitry 235. In other instances, control circuitry 220 may be configured to first generate control signals that set the delay parameters of variable time delay circuitry 235 and then generate control signals that set the scaling parameters of variable gain circuitry 230—a switching component may be used to route the control signals to the appropriate circuitry.

[0057] Feedback circuit 225 can be configured to generate a feedback signal based on a signal output by decision circuit 210, the feedback signal enabling decision circuit 210 to compensate for interference in the input signal. Feedback circuit 225 can be further configured to generate a feedback signal based on a control signal received from control circuit 220. That is, the feedback circuit can change the delay and weight of the feedback signal based on the control signal.

[0058] The variable time delay circuit 235 can be configured to generate one or more delayed (DLY) signals based on the signal output by the decision circuit 210, wherein the delay between the different delayed signals and the output signal can be different. In some instances, the amount of delay between the one or more delayed signals and the output signal can vary based on the number of delay elements included in the variable time delay circuit 235 and the timing and magnitude of reflections in the input signal. In some instances, the variable time delay circuit 235 applies a delay that causes the delayed signal to be aligned in time with the reflection of the input signal. In some instances, the variable time delay circuit 235 applies a delay that causes the delayed signal to be aligned with a subset of reflections, the delayed signal increasing (e.g., optimizing) the anti-reflection effect of the feedback signal. The variable time delay circuit 235 may include one or more variable time delay circuits, each of which may each include one or more delay elements (e.g., timing latches, capacitive elements, etc.). In some instances, the time delay parameters of the one or more variable time delay circuits are set based on a control signal output by the control circuit 220.

[0059] Variable gain circuit 230 can be configured to generate one or more feedback (FB) signals based on one or more delayed signals received from variable time delay circuit 235. Variable gain circuit 230 can be configured to apply a scaling factor to one or more delayed signals to obtain a scaled version of the delayed signal. In some instances, variable gain circuit 230 can modify (e.g., decrease or increase) the magnitude of the delayed signal to match the magnitude of a reflection, which is time-aligned with the corresponding delayed signal. Variable gain circuit 230 may include one or more variable gain amplifiers. In some instances, the gain of the variable gain amplifier is set based on a control signal output from control circuit 220.

[0060] Figure 3This describes an example of a circuit supporting time-varying decision feedback equalization, as disclosed herein. Circuit 300 includes a collection of components configured to perform decision feedback equalization using variable time-delay elements. Circuit 300 may be as described in the references... Figure 2 An example of circuit 200 is described. Circuit 300 may include input line 305, decision circuit 310, control circuit 320, output line 315, variable gain circuit 330, and variable time delay circuit 335, which may be used as a reference. Figure 2 Examples of the input line 205, decision circuit 210, control circuit 220, output line 215, and variable gain circuit 230 described herein. Circuit 300 may also include a first subtraction circuit 340-1. Variable time delay circuit 335 and second control circuit 320-2 may include one or more delay elements 345. Variable gain circuit 330 may include one or more variable gain amplifiers 350.

[0061] The first subtraction circuit 340-1 can be configured to subtract the feedback signal from the received input signal to obtain a compensated signal, also known as a modified (MOD) signal. In some instances, the modified signal corresponds to an input signal with reduced (or no) reflections. Therefore, the voltage distribution of the modified signal more closely corresponds to the voltage distribution of the original transmitted signal, and the likelihood that the decision circuit 310 determines an incorrect voltage level (a voltage level that does not match the corresponding voltage level of the original transmitted signal) in the modified signal can be reduced.

[0062] Multiple options for configuring control circuit 320 are available. In some instances, circuit 300 is configured with a first control circuit 320-1. The first control circuit 320-1 may include a second subtraction circuit 340-2, which may be configured to subtract the signal output by decision circuit 310 from the modified signal input to decision circuit 310. The difference between the two signals may be output as a control signal to variable time delay circuit 335 and / or variable gain circuit 330. In some instances, variable time delay circuit 335 may modify delay parameters based on the control signal, where the greater the difference between the two signals, the greater the modification of delay parameters may be. Therefore, as the difference between the output signal and the modified signal decreases, the delay parameters may become more stable. Similarly, if a control signal is provided to variable gain circuit 330, the magnitude of the modification of scaling parameters by variable gain circuit 330 may be based on the difference between the two signals.

[0063] In some instances, circuit 300 is configured with a second control circuit 320-2. The second control circuit 320-2 may similarly include a second subtraction circuit 340-2. Furthermore, the second control circuit 320-2 may include a first delay element 345-1, which may be configured to output a delayed version (also referred to as an error signal) of the signal output by the second subtraction circuit 340-2. The second control circuit 320-2 may also include a third subtraction circuit 340-3, which may be configured to subtract the delayed error signal from the error signal and output a control signal. By subtracting the delayed error signal from the error signal, the error gradient between the modified signal and the output signal can be used to control the variable time delay circuit 335 and / or the variable gain circuit 330. Therefore, if the error between the modified signal and the output signal reaches a steady-state offset, the variable time delay circuit 335 can maintain the delay parameters at their current values. Similarly, if a control signal is provided to the variable gain circuit 330, the variable gain circuit 330 can maintain the scaling parameters at their current values. Compared to the first control circuit 320-1, the second control circuit 320-2 prevents the variable time delay circuit 335 and / or the variable gain circuit 330 from continuously changing their delay and scaling parameters when the difference between the modified signal and the output signal is unstable and at zero. In some instances, both the first control circuit 320-1 and the second control circuit 320-2 are configured to first tune the delay parameters of the variable time delay circuit 335 and then tune the scaling parameters of the variable gain circuit 330.

[0064] The variable time delay circuit 335 may include second delay elements 345-2 to Nth delay elements 345-N. In some instances, the variable time delay circuit 335 may include a single variable time delay element (e.g., a single variable time delay element) or may include additional variable time delay elements. In some instances, the second delay element 345-2 may apply a first delay to the output signal and output a delayed signal to a neighboring delay element and a variable gain amplifier (e.g., a first variable gain amplifier 350-1). In some instances, the first delay causes the voltage peak of the first delayed signal to cancel out the scattered components of the received signal. In some instances, the first delay causes the voltage peak of the first delayed signal to be time-aligned with the reflected voltage peak of a portion of the input signal received at the first sampling event. A neighboring delay element (e.g., the Nth delay element 345-N) may apply an additional delay to the signal output by the second delay element 345-2 and output another delayed signal to another variable gain amplifier (e.g., the Nth variable gain amplifier 350-N). In some instances, the sum of the first delay and the second delay causes the voltage peak of the second delayed signal to be time-aligned with the voltage peak of another reflection of a portion of the input signal received at the first sampling event.

[0065] In some instances, the variable time delay circuit 335 may include one or more fixed time delay elements and one or more variable time delay elements. For example, the second delay element 345-2 may be replaced by a fixed time delay element. In such cases, the fixed time delay element may be aligned with a signal component (e.g., a reflected or scattered component) of the received signal observed within the second time delay. The signal component aligned with the fixed time delay element may have the maximum magnitude of the transient signal component contained in the received signal. Moreover, the variable time delay element may be tuned to cancel out other signal components (e.g., reflections) of the received signal that appear after the signal component (e.g., the initial reflection or scattered component) and may have a magnitude smaller than that of the signal component.

[0066] The variable gain circuit 330 may include a first variable gain amplifier 350-1 and an Nth variable gain amplifier 350-N. In some instances, the variable gain circuit 330 may include a single variable gain amplifier (e.g., a single variable gain amplifier) ​​or may include additional variable gain amplifiers. In some instances, the first variable gain amplifier 350-1 applies a first scaling factor to the delayed signal received from the second delay element 345-2 and outputs the scaled signal to the first subtraction circuit 340-1. In some instances, the first scaling factor causes the magnitude of the voltage peak of the first delayed signal to match (e.g., nearly) the magnitude of the reflection. Furthermore, the Nth variable gain amplifier 350-N may apply a second scaling factor to the Nth delayed signal received from the Nth delay element 345-N and output the scaled signal to the first subtraction circuit 340-1. In some instances, the Nth scaling factor causes the magnitude of the voltage peak of the Nth delayed signal to match (e.g., nearly) the magnitude of another reflection.

[0067] Figure 4 This describes an example of a signal diagram supporting time-varying decision feedback equalization, as disclosed herein. Signal diagram 400 depicts the response of a conductive line (or channel) to the transmission of a transmitted signal. Input signal 410 may be a voltage pulse. Received signal 415 may be a signal generated on the conductive line (e.g., near the receiving device) in response to the transmission of input signal 410 through the conductive line. The time axis of signal diagram 400 may be divided into unit intervals 425, the duration of which may correspond to the frequency of a clock used by the receiving device. In some instances, the duration of unit interval 425 corresponds to the duration between positive edges of a clock, the duration between negative edges of a clock, or the duration between a positive and a negative edge of a clock. The receiving device may be configured to sample the signal appearing on the conductive line at the beginning (or end) of each unit interval.

[0068] As depicted in signal diagram 400, the received signal 415 may contain multiple signal components, including a first signal component that appears for a first duration after the applied pulse (e.g., approximately a first time 430-1, also referred to as t0), where the first duration may be based on the propagation delay of the conductive line. In some instances, the signal component may also be referred to as a signal characteristic, and the signal component appearing after the first time 430-1 may be referred to as a transient component or reflection of the received signal 415.

[0069] The received signal 415 may also include a second signal component (also referred to as the first reflection 420-1) occurring during a second duration following the applied pulse (e.g., approximately the second time 430-2, also referred to as t1). The received signal 415 may also include a third signal component (also referred to as the second reflection 420-2) occurring during a third duration following the applied pulse (e.g., approximately the third time 430-3, also referred to as t2). The received signal 415 may also include a fourth signal component (also referred to as the third reflection 420-3) occurring during a fourth duration following the applied pulse (e.g., approximately the fourth time 430-4, also referred to as t3). The received signal 415 may also include a fifth signal component (also referred to as the fourth reflection 420-4) occurring during a fifth duration following the applied pulse (e.g., approximately the fifth time 430-5, also referred to as t4). In some instances, the received signal 415 may include fewer or more reflections. As depicted in signal diagram 400, the peaks of different reflections may not be perfectly aligned with the start / end of a unit interval, but may be offset by a certain amount. Additionally, some reflections may have peak values ​​at or near zero. In some instances, reflections are identified as signal components that appear after the initial transmission and have a magnitude exceeding a threshold. Reflections from the received signal 415 can affect (e.g., combine) the output signal from subsequent pulses originating from the input signal 410 (not shown). For example, if the input signal 410 transitions from a high voltage to a low voltage at a second time 430-2, then the second reflection 420-2 can combine with a first signal component of the resulting output signal, thereby increasing or decreasing the voltage of the resulting output signal.

[0070] As described herein, a DFE circuit can be used to compensate for reflections by generating a feedback signal that cancels out the reflections. The DFE circuit may include a decision circuit that samples the voltage of the received signal 415 at a first time 430-1 (e.g., which may correspond to sampling event 405) and outputs a voltage level based on the sampled voltage. For example, for a binary modulation scheme, if the decision circuit determines that the voltage of the received signal 415 is greater than a threshold voltage, then the decision circuit may output a high voltage.

[0071] In some instances, the DFE circuit may also include one or more fixed-time delay elements that output a delayed version of the signal output by the decision circuit, wherein the delayed version may also be referred to as the delayed signal. The DFE circuit may also include a variable-gain amplifier that outputs a scaled version of the delayed signal. In some instances, the fixed-time delay elements may introduce a delay that is an integer multiple of the duration of the unit interval 425. Therefore, the variable-gain amplifier may produce a scaled signal with peaks aligned with the start / end of the unit interval. As described herein, in some cases, the reflected peaks may not be aligned with the start / end of the unit interval, thereby reducing the cancellation effect of the scaled signal. Also as described herein, in some instances, the fixed-time delay elements may introduce a delay that is not an integer multiple of the duration of the unit interval 425 (e.g., using fractional delay elements). In such cases, the variable-gain amplifier may produce a scaled signal with peaks aligned with one or more reflected peaks.

[0072] However, in order to use fixed time delay elements to align the peak of the scaled signal with one or more reflected peaks, the DFE circuit may be configured with an excessive number of delay elements—for example, to ensure that an appropriate delay is applied to the received signal 415. To align the peak of the scaled signal with one or more reflected peaks having a reduced number of delay elements, the DFE circuit may be configured with variable time delay elements. Using variable time delay elements, the DFE circuit can modify the delay of the delay elements such that the corresponding peak of the scaled signal is aligned with one or more reflected peaks. In some instances, the DFE circuit includes one or more fixed time delay elements and one or more variable time delay elements.

[0073] In some instances, the DFE circuit may include as many delay elements as the reflections contained in the received signal 415. In such cases, a first delay element may be tuned to apply a delay corresponding to the duration between the peak of the sampling event 405 and the peak of the first reflection 420-1 to the signal output by the decision circuit, a second delay element may be tuned to apply a delay corresponding to the duration between the peak of the sampling event 405 and the peak of the second reflection 420-2 to the signal output by the decision circuit, and so on.

[0074] In other instances, the DFE circuit may include fewer delay elements than those included in the reflections in the received signal 415. In such cases, the delays of one or more variable time delay elements may be configured to cancel out reflections or combinations of reflections that have the greatest impact on subsequent signals. For example, if the DFE circuit includes one variable time delay element, then the DFE circuit may be configured to set the time delay of the variable time delay element to be equal to the duration between sampling event 405 and the second reflection 420-2—for example, to cancel out the second reflection 420-2. In another instance, if the DFE circuit includes two variable time delay elements, then the DFE circuit may be configured to set the time delay of the first time delay element to be equal to the duration between sampling event 405 and the second reflection 420-2 and the time delay of the second time delay element to be equal to the duration between sampling event 405 and the fourth reflection 420-4—for example, to cancel out the second reflection 420-2 and the fourth reflection 420-4. In some instances, if the DFE circuit includes a fixed time delay element and a variable time delay element, the DFE circuit may be configured such that the fixed time delay element cancels out the scattered components of the received signal 415 (e.g., during the first reflection 430-1), and the variable time delay element may be tuned to cancel out the second reflection 420-2.

[0075] In some instances, to determine which reflections to eliminate, reflections exceeding a first threshold (e.g., 0.2V) can be identified, and available time delay elements can be tuned to align the feedback signal with the identified reflections. If remaining time delay elements exist, then remaining reflections exceeding a second threshold (e.g., 0.1V) can be identified, and available time delay elements can be tuned to align another set of feedback signals with the identified reflections. This process continues until no remaining reflections can be canceled or no available time delay elements need to be tuned.

[0076] As described herein, DFE circuits can use various techniques to generate control signals for tuning variable time delay elements and / or variable gain elements—for example, using least mean square estimation techniques. In some instances, the DFE circuit first uses control signals to tune the variable time delay elements, whereby a variable time delay circuit containing the variable time delay elements can modify a first time delay element based on the control signals, then modify a second time delay element based on the control signals when the magnitude (or rate of change) of the error signal falls below a threshold, and so on. After tuning the variable time delay elements, the DFE circuit can use control signals to tune the variable gain amplifier, whereby a variable gain circuit containing the variable gain amplifier can modify a first variable gain amplifier based on the control signals, then modify a second variable gain amplifier based on the control signals when the magnitude (or rate of change) of the error signal falls below a threshold, and so on.

[0077] In some instances, the response of conductive lines can be estimated, measured, or modeled before the memory device is deployed, and the timing and magnitude of a set of resulting reflections can be determined or estimated accordingly. After identifying the timing and magnitude of the reflections, the time delay of a set of available variable time delay elements can be programmed based on the identified timing and magnitude of the resulting reflections. For example, the set of available variable time delay elements can be tuned to generate feedback signals that counteract (or reduce) more influential reflections (e.g., second reflection 420-2 and fourth reflection 420-4). In some instances, the time delay of the variable time delay elements is set by fusing one or more fuses contained in the time delay elements (e.g., melting the filaments in one or more fuses), which are used to set the timing of the variable time delay elements.

[0078] Figure 5 This describes an example of a circuit supporting time-varying decision feedback equalization, as disclosed herein. Circuit 500 includes a set of components configured to perform decision feedback equalization using variable time-delay elements. Circuit 500 may depict alternative configurations of the decision feedback equalization circuit—for example, relative to… Figure 3 Circuit 300. That is, circuit 500 performs feedback equalization by modifying the level of a threshold voltage compared to the voltage of the input signal, rather than applying a feedback signal to the input signal received through the input line. Circuit 500 may include input line 505, output line 515, and delay element 545, which may be as follows: Figure 3 Examples of the input line 305, output line 315, and delay element 345 described herein. Circuit 500 may also include a comparator 510 and a threshold determination circuit 520.

[0079] Comparator 510 can be configured to compare an input signal received via input line 505 with a dynamic threshold signal output by threshold determination circuit 520. Comparator 510 can also be configured to output an output signal having a voltage that transitions between a quantized set of voltage levels based on the comparison. Threshold determination circuit 520 can be configured to modify the threshold voltage based on a delay signal received from delay element 545. In some instances, circuit 500 includes control circuitry 510 for tuning the delay of delay element 545 based on signals input to the comparator, adjustments to the threshold signal, and signals output by comparator 510, as similarly described herein. The control circuitry can also be used to tune scaling parameters of a variable gain amplifier included in threshold determination circuit 520 based on signals input to comparator 510, adjustments to the threshold signal, and signals output by comparator 510, as similarly described herein.

[0080] Figure 6A block diagram 600 illustrates a receiving device 620 supporting time-varying decision feedback equalization, based on an example disclosed herein. The receiving device 620 may be as described in the references... Figures 1 to 5 Examples of aspects of the described host device or memory device. The receiving device 620 or its various components may be examples of components for performing various aspects of time-varying decision feedback equalization as described herein. For example, the receiving device 620 may include a limiter 625, a tap circuit 630, a gain amplifier 635, a subtractor 640, a control circuit 645, a threshold determination circuit 650, a comparator 655, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0081] Limiter 625 may be configured or otherwise supported to determine the voltage of a first signal at least in part based on a feedback signal and an input signal received via a conductive line representing data written to or read from a memory array at a sampling event. In some instances, limiter 625 may be configured or otherwise supported to output a second signal having a voltage level at least in part based on the voltage determined by the first signal. Tap circuitry 630 may be configured or otherwise supported to apply a variable time delay to the second signal to output a delayed signal. Gain amplifier 635 may be configured or otherwise supported to generate a feedback signal at least in part based on the delayed signal.

[0082] In some instances, the tap circuit 630 may be configured or otherwise supported to support means for setting a variable time delay to a first duration before receiving the input signal. In some instances, the tap circuit 630 may be configured or otherwise supported to support means for setting the variable time delay to a second duration after receiving the input signal.

[0083] In some instances, the tap circuit 630 may be configured or otherwise supported to include means for determining the duration of the variable time delay based at least in part on the magnitude of one or more characteristics of the input signal after the sampling event and the timing of those characteristics.

[0084] In some instances, the gain amplifier 635 may be configured or otherwise supported to support components for determining the amplification factor based at least in part on the duration of the variable time delay and the corresponding characteristics of the input signal.

[0085] In some instances, subtractor 640 may be configured or otherwise supported to modify the input signal at least in part based on the feedback signal to obtain the first signal. In some instances, control circuitry 645 may be configured or otherwise supported to determine the duration of the variable time delay at least in part based on the difference between the first signal and the second signal.

[0086] In some instances, the control circuitry 645 may be configured or otherwise supported to support means for outputting an error signal based at least in part on the difference between the first signal and the second signal. In some instances, the control circuitry 645 may be configured or otherwise supported to support means for delaying the error signal to obtain a delayed error signal. In some instances, the control circuitry 645 may be configured or otherwise supported to support means for determining the difference between the error signal and the delayed error signal, wherein the duration of the variable time delay is at least in part based on the difference between the error signal and the delayed error signal.

[0087] In some instances, the threshold determination circuit 650 may be configured or otherwise supported to include means for adjusting a reference signal at least in part based on the feedback signal. In some instances, the comparator 655 may be configured or otherwise supported to include means for comparing the first signal and the reference signal, wherein the first signal is equivalent to the input signal and the voltage level of the second signal is at least in part based on the comparison. In some instances, the limiter 625 may include or be a comparator 655.

[0088] Figure 7 The flowchart illustrates a method 700 for supporting time-varying decision feedback equilibrium based on examples disclosed herein. Operation of method 700 can be implemented by a receiving device or its components as described herein. For example, operation of method 700 can be performed by [reference needed]. Figures 1 to 6 The described receiving device is used to perform this function. In some instances, the receiving device may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the receiving device may use dedicated hardware to perform aspects of the described function.

[0089] At 705, the method may include determining the voltage of a first signal at least in part based on a feedback signal and an input signal received via a conductive line and representing data written to or read from the memory array at the time of a sampling event. Operation of 705 may be performed according to examples disclosed herein. In some examples, aspects of operation of 705 may be as described in references... Figure 6 The described limiter 625 is used to perform this function.

[0090] At 710, the method may include outputting a second signal having a voltage level at least partially based on determining the voltage of the first signal. Operation of 710 may be performed according to examples disclosed herein. In some examples, aspects of operation of 710 may be as described in references... Figure 6 The described limiter 625 is used to perform this function.

[0091] At 715, the method may include applying a variable time delay to the second signal to output a delayed signal. The operation of 715 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 715 may be as described in references... Figure 6 The described tap circuit 630 is used to execute this.

[0092] At 720, the method may include generating the feedback signal at least in part based on the delayed signal. Operation of 720 may be performed according to examples disclosed herein. In some instances, aspects of operation of 720 may be as described in references... Figure 6 The described gain amplifier 635 is used to perform this.

[0093] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include operations, features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: determining, at least in part, based on a feedback signal and an input signal received via a conductive line and representing data written to or read from a memory array, a voltage of a first signal at a sampling event; outputting a second signal having a voltage level at least in part based on the voltage determined by the first signal; applying a variable time delay to the second signal to output a delayed signal; and generating the feedback signal at least in part based on the delayed signal.

[0094] In some instances of the method 700 and apparatus described herein, the variable time delay is set to a first duration before the input signal becomes available and to a second duration after the input signal becomes available.

[0095] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for determining the duration of the variable time delay based at least in part on the magnitude of one or more characteristics of the input signal after the sampling event and the timing of the one or more characteristics of the input signal.

[0096] In some instances of the method 700 and apparatus described herein, and the method, apparatus and non-transitory computer-readable medium may further include operations, features, circuit systems, logic, components or instructions for determining an amplification factor based at least in part on the duration of the variable time delay and the magnitude of the corresponding characteristic of the input signal.

[0097] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: modifying the input signal at least in part based on the feedback signal to obtain the first signal; and determining the duration of the variable time delay at least in part based on the difference between the first signal and the second signal.

[0098] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: outputting an error signal at least in part based on the difference between the first signal and the second signal; delaying the error signal to obtain a delayed error signal; and determining the difference between the error signal and the delayed error signal, wherein the duration of the variable time delay may be at least in part based on the difference between the error signal and the delayed error signal.

[0099] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: adjusting a reference signal at least in part based on the feedback signal; and comparing the first signal and the reference signal, wherein the first signal is equivalent to the input signal and the voltage level of the second signal is at least in part based on the comparison.

[0100] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are also possible. Furthermore, parts from two or more methods can be combined.

[0101] Describe an apparatus. The apparatus may include: a memory array; a first circuit coupled to the memory array and a conductive line configured to receive an input signal representing data written to or read from the memory array and to output a second signal, the first circuit being configured to determine a voltage of the first signal at least in part based on the input signal and a feedback signal at a sampling event; a second circuit coupled to the output of the first circuit and configured to apply one or more variable time delays to the second signal and output one or more delayed signals; and a third circuit coupled to the second circuit and the first circuit, the third circuit being configured to generate the feedback signal at least in part based on the one or more delayed signals output by the second circuit.

[0102] In some instances of the device, the first circuitry includes a comparator, an analog-to-digital converter, a sensing amplifier, or a combination thereof; the second circuitry includes a timing latch, one or more capacitors, or a combination thereof; and the third circuitry includes a gain amplifier.

[0103] In some instances of the device, the second circuit includes a delay element configured to receive the second signal and output a delayed signal based at least in part on applying a variable time delay to the second signal, and the second circuit may be configured to set a delay parameter of the delay element based at least in part on one or more characteristics of the input signal that occurs after the sampling event.

[0104] In some instances of the device, a first characteristic of the input signal occurs for a first duration after the sampling event and a second characteristic of the input signal occurs for a second duration after the sampling event, which may be longer than the first duration. The magnitude of the first characteristic may be less than the magnitude of the second characteristic, and the second circuit may be configured to set the delay parameter of the delay element to be equal to the second duration, at least in part based on the fact that the magnitude of the first characteristic is less than the magnitude of the second characteristic.

[0105] In some instances of the device, the delay parameter of the delay element may be equal to the first duration before the input signal can be received.

[0106] In some instances of the device, a plurality of sampling events of the first signal include the sampling event, each of the plurality of sampling events being separated by a time interval, and the second duration being separated from the sampling event by a plurality of time intervals.

[0107] In some instances of the device, a plurality of sampling events of the first signal include the sampling event, each of the plurality of sampling events being separated by a time interval, and the second duration being separated from the sampling event by at least one time interval and a portion of a second time interval following the at least one time interval.

[0108] In some instances of the device, the second circuit includes a single delay element, which is equivalent to the delay element.

[0109] In some instances of the device, the second circuit includes a plurality of delay elements configured to receive the second signal and output a plurality of delayed signals at least in part based on the second signal, and the second circuit may be configured to set delay parameters of the plurality of delay elements at least in part based on a plurality of characteristics of the input signal.

[0110] In some instances of the device, the plurality of characteristics of the input signal appear after the sampling event for corresponding plurality of durations, the number of the plurality of delay elements may be less than the number of the plurality of characteristics, and the second circuit may be configured to set the delay parameter of the plurality of delay elements to be equal to the duration associated with the characteristic among the plurality of characteristics that affects the input signal during subsequent sampling intervals exceeding a threshold.

[0111] In some instances of the device, the one or more variable time delays may be based at least in part on the magnitude of one or more characteristics of the input signal after the sampling event and the timing of the one or more characteristics of the input signal.

[0112] In some instances, the device may include a fourth circuit coupled to the first circuit and configured to output an error signal for calibrating the second circuit based at least in part on the first signal and the second signal, wherein the second circuit may be configured to set the duration of the one or more variable time delays based at least in part on the error signal.

[0113] In some instances, the device may include a subtraction circuit coupled to the first circuit and the third circuit, the subtraction circuit being configured to output the first signal to the first circuit based at least in part on subtracting the input signal from the feedback signal.

[0114] In some instances of the device, the fourth circuit includes a second subtraction circuit that can be configured to output the error signal based at least in part on subtracting the first signal from the second signal.

[0115] In some instances of the device, the fourth circuit includes: a second subtraction circuit configured to output a first error signal based at least in part on subtracting the first signal from the second signal; a delay element configured to delay the first error signal to obtain a delayed error signal; and a third subtraction circuit configured to subtract the first error signal from the delayed error signal to obtain the error signal for calibrating the second circuit.

[0116] In some instances of the device, the fourth circuit may be further configured to output a second error signal for calibrating the third circuit based at least in part on the input signal and the second signal and the calibrated second circuit, and the third circuit may be configured to set one or more amplification factors of the one or more delayed signals based at least in part on the second error signal.

[0117] In some instances, the device may include a fourth circuit that includes the third circuit and is configured to modify the reference signal at least in part based on the feedback signal, and wherein the first circuit includes a comparator that is configured to receive the input signal and the reference signal and to generate the second signal at least in part based on the input signal and the reference signal, wherein the input signal may be equivalent to the first signal.

[0118] Describe another device. The device may include: a memory array; and a controller coupled to the memory array, the controller being operable such that, upon a sampling event, the device: determines a voltage of a first signal based at least in part on a feedback signal and an input signal received via a conductive line and representing data written to or read from the memory array; outputs a second signal having a voltage level at least in part based on the voltage determined by the first signal; applies a variable time delay to the second signal to output a delayed signal; and generates the feedback signal at least in part based on the delayed signal.

[0119] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, which may have various bit widths.

[0120] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to relationships between components that support signal flow between them. Components are considered to be in electronic communication (or conductive contact, connection, or coupling) with each other if any conductive path exists between them that can readily support signal flow between them. At any given time, the conductive path between components in electronic communication (or conductive contact, connection, or coupling) can be open or closed depending on the operation of the device containing the connected component. The conductive path between connected components can be a direct conductive path between the components or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0121] The term "coupling" refers to a condition that moves from an open-circuit relationship between components (where signals cannot currently travel between components via conductive paths) to a closed-circuit relationship between components (where signals travel between components via conductive paths). When a component (e.g., a controller) couples other components together, the component initiates a change that allows the flow of signals between other components via conductive paths that were previously not permitted.

[0122] The term "isolated" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it modifies the circuit to prevent signals from flowing between the components using previously permitted conductive paths.

[0123] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOS) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0124] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0125] The descriptions set forth herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to other instances." Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and arrangements are shown in block diagram form to avoid obscuring the concept of the described instances.

[0126] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a dash after the reference label and a second label to differentiate similar components. When only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, without regard to the second reference label.

[0127] The functions described herein can be implemented in hardware, processor-implemented software, firmware, or any combination thereof. If implemented in processor-implemented software, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using processor-implemented software, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0128] For example, the various illustrative blocks and modules described in this disclosure can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0129] As used herein (included in the claims), the word "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0130] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave), then the definition of media includes coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave). As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0131] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: Memory array; A first circuit coupled to the memory array and conductive lines configured to receive an input signal representing data written to or read from the memory array and to output a second signal, the first circuit being configured to determine the voltage of the first signal at least in part based on the input signal and the feedback signal at the time of a sampling event. A second circuit, coupled to the output of the first circuit, wherein the second circuit includes a plurality of delay elements and is configured to: Receive the second signal; The delay parameters of the plurality of delay elements are set at least in part based on a plurality of characteristics of the input signal, wherein the plurality of characteristics of the input signal occur for corresponding plurality of durations after the sampling event, and the number of the plurality of delay elements is less than the number of the plurality of characteristics; The delay parameter of the plurality of delay elements is set to be equal to the duration associated with the characteristic among the plurality of characteristics that affects the input signal during subsequent sampling intervals exceeding a threshold; Apply one or more variable time delays to the second signal; and At least in part, one or more delayed signals are output based on the second signal; and A third circuit, coupled to the second circuit and the first circuit, is configured to generate the feedback signal based at least in part on the one or more delayed signals output by the second circuit.

2. The memory device according to claim 1, wherein: The first circuit includes a comparator, an analog-to-digital converter, a sense amplifier, or a combination thereof; The second circuit includes a time latch, one or more capacitors, or a combination thereof; and The third circuit includes a gain amplifier.

3. The memory device according to claim 1, wherein: The second circuit includes a delay element configured to receive the second signal and output a delayed signal based at least in part on applying a variable time delay to the second signal; and The second circuit is configured to set the delay parameters of the delay element based at least in part on one or more characteristics of the input signal that occurs after the sampling event.

4. The memory device according to claim 3, wherein: The first characteristic of the input signal occurs for a first duration after the sampling event, and the second characteristic of the input signal occurs for a second duration after the sampling event that is longer than the first duration. The value of the first characteristic is less than the value of the second characteristic, and The second circuit is configured to set the delay parameter of the delay element to be equal to the second duration, at least in part based on the fact that the magnitude of the first characteristic is less than the magnitude of the second characteristic.

5. The memory device of claim 4, wherein the delay parameter of the delay element is equal to the first duration before the input signal is received.

6. The memory device according to claim 4, wherein: The plurality of sampling events of the first signal include the sampling events, wherein each of the plurality of sampling events is separated by a time interval, and The second duration is separated from the sampling event by multiple time intervals.

7. The memory device according to claim 4, wherein: The plurality of sampling events of the first signal include the sampling events, wherein each of the plurality of sampling events is separated by a time interval, and The second duration is separated from the sampling event by at least one time interval and a portion of a second time interval following the at least one time interval.

8. The memory device of claim 3, wherein the second circuitry includes a single delay element, the single delay element being equivalent to the delay element.

9. The memory device of claim 1, wherein the one or more variable time delays are based at least in part on the magnitude of one or more characteristics of the input signal after the sampling event and the timing of the one or more characteristics of the input signal.

10. The memory device of claim 1, further comprising: A fourth circuit, coupled to the first circuit and configured to output an error signal for calibrating the second circuit, based at least in part on the first signal and the second signal. The second circuit is configured to set the duration of the one or more variable time delays based at least in part on the error signal.

11. The memory device of claim 10, further comprising: A subtraction circuit coupled to the first circuit and the third circuit, the subtraction circuit being configured to output the first signal to the first circuit based at least in part on subtracting the input signal from the feedback signal.

12. The memory device of claim 11, wherein the fourth circuitry includes a second subtraction circuitry configured to output the error signal based at least in part on subtracting the first signal from the second signal.

13. The memory device of claim 11, wherein the fourth circuitry comprises: The second subtraction circuit is configured to output a first error signal based at least in part on subtracting the first signal from the second signal; A delay element configured to delay the first error signal to obtain a delayed error signal; and A third subtraction circuit is configured to subtract the first error signal and the delayed error signal to obtain the error signal used to calibrate the second circuit.

14. The memory device of claim 10, wherein: The fourth circuit is further configured to output a second error signal for calibrating the third circuit, based at least in part on the input signal, the second signal, and the calibrated second circuit. The third circuit is configured to set one or more amplification factors of the one or more delayed signals based at least in part on the second error signal.

15. The memory device of claim 1, further comprising: A fourth circuit, comprising the third circuit and configured to modify the reference signal at least in part based on the feedback signal, The first circuit includes a comparator configured to receive the input signal and the reference signal and to generate the second signal based at least in part on the input signal and the reference signal, wherein the input signal is equivalent to the first signal.

16. A method for operating a memory device, the method comprising: Set the variable time delay to the first duration; After setting the variable time delay to the first duration, an input signal is received via a conductive line, the input signal representing data written to or read from the memory array; At the time of sampling, the voltage of the first signal is determined at least in part based on the feedback signal and the input signal; The output has a second signal having a voltage level at least in part based on the voltage of the first signal; After receiving the input signal, the variable time delay is set to a second duration; Apply the variable time delay to the second signal to output a delayed signal; and The feedback signal is generated at least in part based on the delayed signal.

17. The method of claim 16, further comprising: The duration of the variable time delay is determined at least in part based on the magnitude of one or more characteristics of the input signal after the sampling event and the timing of the one or more characteristics of the input signal.

18. The method of claim 17, wherein generating the feedback signal comprises amplifying the delayed signal by an amplification factor, the method further comprising: The amplification factor is determined at least in part based on the duration of the variable time delay and the magnitude of the corresponding characteristic of the input signal.

19. The method of claim 16, further comprising: The input signal is modified, at least in part, based on the feedback signal, to obtain the first signal; and The second duration of the variable time delay is determined at least in part based on the difference between the first signal and the second signal.

20. The method of claim 19, further comprising: An error signal is output based at least in part on the difference between the first signal and the second signal; The error signal is delayed to obtain a delayed error signal; and Determine the difference between the error signal and the delayed error signal, wherein the duration of the variable time delay is at least partially based on the difference between the error signal and the delayed error signal.

21. The method of claim 16, further comprising: The reference signal is adjusted at least in part based on the feedback signal; and The first signal and the reference signal are compared, wherein the first signal is equivalent to the input signal and the voltage level of the second signal is at least partially based on the comparison.

22. A memory device comprising: Memory array; and A controller, coupled to the memory array, is operable to cause the memory device to: Set the variable time delay to the first duration; After the variable time delay is set to the first duration, an input signal is received via a conductive line, the input signal representing data written to or read from the memory array; At the time of sampling, the voltage of the first signal is determined at least in part based on the feedback signal and the input signal; The output has a second signal having a voltage level at least in part based on the voltage of the first signal; After receiving the input signal, the variable time delay is set to a second duration; Apply the variable time delay to the second signal to output a delayed signal; and The feedback signal is generated at least in part based on the delayed signal.

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