Control circuit for a switching power supply

Abstract

The application discloses a control circuit of a power supply circuit. The control circuit comprises a first comparator circuit, an error amplifier circuit, a clamping circuit and a logic decision circuit. The first comparator circuit is used for comparing a reference voltage and an output feedback voltage and outputting a first indication signal based on a comparison result. The error amplifier circuit is used for comparing the reference voltage and the output feedback voltage and outputting an error voltage signal based on a comparison result. The clamping circuit is used for comparing the error voltage signal and a preset clamping voltage and outputting a second indication signal based on a comparison result. The logic decision circuit outputs a hibernation indication signal according to the first indication signal and the second indication signal, and the hibernation indication signal is used for controlling whether a switching power supply is switched to a hibernation state. By comparing the output feedback voltage and the reference voltage, the hibernation indication signal is generated according to a comparison result, the switching power supply is switched to a hibernation state and a normal working state, and the switching efficiency of different load states is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a control circuit for a switching power supply. Background Technology

[0002] With the rapid development of integrated circuit technology, the application of a large number of smart terminals and handheld devices has placed increasingly higher demands on the efficiency of switching converters, especially under light load conditions. It is desirable to achieve high efficiency and have the ability to respond quickly when the output load switches from light load to heavy load to ensure that the output voltage drops slightly. In order to improve the efficiency of switching converters when switching the output load under light load conditions and reduce the voltage drop during load switching, a power control circuit is set in the switching power supply to realize the switching of the switching power supply state under different load conditions, thereby improving the efficiency of the switching converter. Summary of the Invention

[0003] The main objective of this application is to provide a control circuit for a switching power supply to solve the technical problem of low efficiency in existing switching power supply converters, thereby improving the switching efficiency of the switching power supply under different load conditions and increasing the efficiency of the switching converter.

[0004] To achieve the above objectives, this application proposes a control circuit for a switching power supply, comprising: a first comparator circuit, an error amplifier circuit, a clamping circuit, and a logic determination circuit.

[0005] The first comparator circuit is configured to compare a reference voltage and an output feedback voltage, and output a first indication signal from the output terminal of the first comparator circuit to the logic determination circuit based on the comparison result.

[0006] The error amplifier circuit is configured to compare a reference voltage and an output feedback voltage, and based on the comparison result, output an error voltage signal from the circuit of the error amplifier circuit and provide the error voltage signal to the clamping circuit.

[0007] The clamping circuit is configured to compare the error voltage signal with a preset clamping voltage, and based on the comparison result, output a second indication signal from the output terminal of the clamping circuit to the logic determination circuit;

[0008] The logic determination circuit is configured to output a sleep indicator signal based on the first indicator signal and the second indicator signal. The sleep indicator signal is used to control whether the switching power supply switches to a sleep state.

[0009] In some optional embodiments of this application, the first comparator circuit includes: a differential input pair circuit, a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, and a first output circuit.

[0010] The first differential input terminal of the differential input pair circuit is coupled to the reference voltage terminal for receiving the reference voltage, and the second differential input terminal of the differential input pair circuit is coupled to the output feedback voltage terminal for receiving the output feedback voltage.

[0011] The differential input pair circuit is configured to generate a first current signal based on the reference voltage and provide the first current signal to the first current mirror circuit via the first output terminal of the differential input pair circuit, and the differential input pair circuit is configured to generate a second current signal based on the output feedback voltage and provide the second current signal to the second current mirror circuit via the second output terminal of the differential input pair circuit;

[0012] The first current mirror circuit is configured to generate a first mirror signal of the first current signal and provide the first mirror signal to the first output circuit via a first node;

[0013] The second current mirror circuit is configured to generate a second mirror signal of the second current signal and provide the second mirror signal to the third current mirror circuit;

[0014] The third current mirror circuit is configured to generate a third mirror signal of the second mirror signal and provide the third mirror signal to the first output circuit via the first node;

[0015] The first output circuit is configured to compare the first mirror signal and the third mirror signal, and output the first indication signal based on the comparison result.

[0016] In some optional embodiments of this application, the error amplifier circuit includes: a differential input pair circuit, a second current mirror circuit, a fourth current mirror circuit, a fifth current mirror circuit, and a second output circuit.

[0017] The differential input pair circuit is configured to generate a first current signal based on the reference voltage and provide the first current signal to the fourth current mirror circuit via the first output terminal of the differential input pair circuit; and the differential input pair circuit is configured to generate a second current signal based on the output feedback voltage and provide the second current signal to the fourth current mirror circuit via the second output terminal of the differential input pair circuit.

[0018] The fourth current mirror circuit is configured to generate a fourth mirror signal of the first current signal and provide the fourth mirror signal to the second output circuit via the second node;

[0019] The second current mirror circuit is configured to generate a second mirror signal of the second current signal and provide the second mirror signal to the fifth current mirror circuit;

[0020] The fifth current mirror circuit is configured to generate a fifth mirror signal of the second mirror signal and provide the fifth mirror signal to the second output circuit via the second node;

[0021] The second output circuit is configured to compare the fourth mirror signal and the fifth mirror signal, and output the error voltage signal based on the comparison result.

[0022] In some optional embodiments of this application, the differential input pair circuit includes a first transistor and a second transistor.

[0023] Wherein, the gate of the first transistor is coupled to the reference voltage terminal, the first terminal of the first transistor is coupled to the first terminal of the second transistor, and the second terminal of the first transistor is coupled to the first current mirror circuit and the fourth current mirror circuit at the third node, for providing the first current signal to the first current mirror circuit and the fourth current mirror circuit.

[0024] The gate of the second transistor is coupled to the output feedback voltage terminal, and the second terminal of the second transistor is coupled to the second current mirror circuit at the fourth node to provide the second current signal to the second current mirror circuit.

[0025] In some optional embodiments of this application, the second output circuit includes a compensation network circuit.

[0026] The input terminal of the compensation network circuit is coupled to the output terminal of the fourth current mirror circuit, and the input terminal of the compensation network circuit is coupled to the output terminal of the fifth current mirror circuit, for generating the error voltage signal based on the current difference between the fourth and fifth mirror signals flowing into the compensation network circuit.

[0027] In some optional embodiments of this application, the clamping circuit includes a constant current generating circuit, a negative feedback clamping circuit, and a logic buffer circuit.

[0028] Wherein, the first terminal of the constant current generating circuit is coupled to the first voltage terminal, and the second terminal of the constant current generating circuit is coupled to the input terminal of the logic buffer circuit;

[0029] The negative feedback clamping circuit is configured to clamp the error voltage to be greater than or equal to the preset clamping voltage;

[0030] The input terminal of the logic buffer circuit is coupled to the output terminal of the negative feedback clamping circuit, and the logic buffer circuit is configured to output the second indication signal based on the comparison result between the error voltage and the preset clamping voltage.

[0031] In some optional embodiments of this application, the logic determination circuit is configured to output a sleep indication signal based on the first indication signal and the second indication signal.

[0032] When the first indicator signal is low and the second indicator signal is high, the logic determination circuit outputs the first sleep indicator signal, which is used to control the switching power supply to enter the sleep state.

[0033] When the first indicator signal is high or the second indicator signal is low, the logic determination circuit outputs a second sleep indicator signal, which is used to control the switching power supply to enter the normal working state.

[0034] In some optional embodiments of this application, the control circuit further includes: a second comparator circuit and a pulse signal generation circuit.

[0035] The second comparator circuit is configured to compare the error voltage signal with a preset detection voltage, and output a third indication signal from the output terminal of the second comparator circuit to the pulse signal generation circuit based on the comparison result.

[0036] The pulse signal generating circuit is configured to generate a duty cycle signal based on the third indication signal, the duty cycle signal being used to indicate the duty cycle of the output voltage under the operating state of the switching power supply.

[0037] In some optional embodiments of this application, the second comparator circuit includes an inductor current detection circuit and a PWM comparator.

[0038] The inductor current detection circuit is configured to generate a preset waveform voltage signal and provide the preset waveform voltage signal to the PWM comparator.

[0039] The non-inverting input of the PWM comparator is coupled to the output of the error amplifier circuit, and the inverting input of the PWM comparator is coupled to the output of the inductor current detection circuit. The PWM comparator is configured to compare the error voltage signal and the preset waveform voltage signal, and output a pulse width modulation signal through the output of the PWM comparator according to the comparison result, and provide the pulse width modulation signal to the pulse signal generation circuit.

[0040] In some optional embodiments of this application, the pulse signal generation circuit includes a logic buffer circuit and a logic control circuit.

[0041] The first input terminal of the pulse signal generation circuit is coupled to the output terminal of the PWM comparator, and the second input terminal of the pulse signal generation circuit is coupled to the oscillator circuit for receiving the oscillation signal. The logic control circuit is configured to generate the duty cycle signal according to the pulse width modulation signal and the oscillation signal.

[0042] The logic buffer circuit is coupled to the logic control circuit and is used to improve the driving capability of the pulse signal generation circuit.

[0043] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0044] In this application, the control circuit of the switching power supply includes a first comparator circuit, an error amplifier circuit, a clamping circuit, and a logic determination circuit. The first comparator circuit is configured to compare a reference voltage and an output feedback voltage, and output a first indication signal from its output terminal to the logic determination circuit based on the comparison result. The error amplifier circuit is configured to compare the reference voltage and the output feedback voltage, and output an error voltage signal from its output terminal based on the comparison result, and provide the error voltage signal to the clamping circuit. The clamping circuit is configured to compare the error voltage signal and a preset clamping voltage, and output a second indication signal from its output terminal to the logic determination circuit based on the comparison result. The logic determination circuit is configured to output a sleep indication signal according to the first and second indication signals. The sleep indication signal is used to control whether the switching power supply switches to a sleep state. This solves the technical problem of low efficiency in existing switching power supply converters and achieves the technical effect of improving the switching efficiency of the switching power supply under different load conditions. Attached Figure Description

[0045] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application. In the drawings:

[0046] Figure 1 A schematic block diagram of a control circuit for a switching power supply provided in this application;

[0047] Figure 2 A schematic block diagram of a control circuit for a switching power supply provided in this application;

[0048] Figure 3 An exemplary circuit diagram of a clamping circuit provided in this application;

[0049] Figure 4 An exemplary circuit diagram of a logic determination circuit provided in this application;

[0050] Figure 5 A schematic block diagram of the first power supply control circuit provided in this application;

[0051] Figure 6 An exemplary circuit diagram of a power control circuit provided in this application;

[0052] Figure 7 An exemplary circuit diagram of a switching power supply provided in this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0055] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled middle terminal of the transistor is referred to as the gate, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0056] In one optional embodiment of this application, a control circuit for a switching power supply is provided. Figure 1 A schematic block diagram of a control circuit for a switching power supply provided in this application, such as... Figure 1 As shown, the control circuit of the switching power supply includes a first comparator circuit 100, an error amplifier circuit 200, a clamping circuit 300, and a logic determination circuit 400.

[0057] The input terminals of the first comparator circuit 100 are coupled to the reference voltage terminal and the output feedback voltage terminal, respectively. The non-inverting input terminal of the first comparator circuit 100 is coupled to the reference voltage terminal, and the inverting input terminal of the first comparator circuit 100 is coupled to the output feedback voltage terminal. The output terminal of the first comparator circuit 100 is coupled to the logic determination circuit 400. The first comparator circuit 100 is configured to compare the reference voltage Vref and the output feedback voltage FB, and output a first indication signal C1 from the output terminal of the first comparator circuit 100 based on the comparison result. The first indication signal C1 is output to the logic determination circuit 400. The first indication signal C1 is an electrical signal used to indicate whether the switching power supply is switching its operating state.

[0058] The input terminals of the error amplifier circuit 200 are coupled to the reference voltage terminal and the output feedback voltage terminal, respectively. The non-inverting input terminal of the error amplifier circuit 200 is coupled to the reference voltage terminal, and the inverting input terminal of the error amplifier circuit 200 is coupled to the output feedback voltage terminal. The output terminal of the error amplifier circuit 200 is coupled to the clamping circuit 300. The second comparator circuit 200 is configured to compare the reference voltage Vref and the output feedback voltage FB, and based on the comparison result, outputs an error voltage signal Vc from the output terminal of the second comparator circuit 200 and provides the error voltage signal Vc to the clamping circuit.

[0059] The input terminal of the clamping circuit 300 is coupled to the output terminal of the error amplifier circuit 200, and the output terminal of the clamping circuit 300 is coupled to the logic determination circuit 400. The clamping circuit is configured to receive the error voltage signal Vc, compare the error voltage signal Vc with the preset clamping voltage, and generate a second indication signal C2 based on the comparison result. The second indication signal C2 is an electrical signal used to indicate whether the switching power supply is switching its working state.

[0060] The first input terminal of the logic determination circuit 400 is coupled to the output terminal of the first comparator circuit 100, the second input terminal of the logic determination circuit 400 is coupled to the output terminal of the clamping circuit 300, and the output terminal of the logic determination circuit 400 is coupled to the control terminal of the switching power supply. The logic determination circuit 400 is configured to control the switching power supply to switch to a sleep state according to the first indication signal C1 and the second indication signal C2. When the first indication signal C1 is low and the second indication signal C2 is high, the logic determination circuit outputs a sleep indication signal, which is used to control the switching power supply to enter a sleep state. When the first indication signal C1 is high and the second indication signal C2 is low, the logic determination circuit outputs a normal operation indication signal, which is used to control the switching power supply to switch from a sleep state to a normal operation state.

[0061] In another optional embodiment of this application, a first comparator circuit is provided. Figure 2 A schematic block diagram of a control circuit for a switching power supply provided in this application, such as... Figure 2 As shown, it includes a first constant current generating circuit 110, a differential input pair circuit 120, a first current mirror circuit 130, a second current mirror circuit 140, a third current mirror circuit 150, and a first output circuit 160.

[0062] The first terminal of the first constant current generating circuit 110 is coupled to the first voltage terminal V1, and the second terminal of the first constant current generating circuit is coupled to the differential input pair circuit 120. The first constant current generating circuit 110 is configured to generate a first constant current and output the first constant current through the second terminal of the first constant current generating circuit 110.

[0063] The first differential input terminal of the differential input pair circuit 120 is coupled to the reference voltage terminal to receive the reference voltage Vref. The second differential input terminal of the differential input pair circuit 110 is coupled to the output feedback voltage terminal to receive the output feedback voltage FB. The input terminal of the differential input pair circuit 120 is coupled to the first constant current generating circuit 110 to receive the first constant current. The differential input pair circuit 120 is configured to generate a first current signal based on the reference voltage and the first constant current and provide the first current signal to the first current mirror circuit 130 via the first output terminal of the differential input pair circuit 120. The differential input pair circuit 120 is also configured to generate a second current signal based on the output feedback voltage and provide the second current signal to the second current mirror circuit 140 via the second output terminal of the differential input pair circuit 120.

[0064] The first current mirror circuit 130 is configured to generate a first mirror signal of the first current signal and provide the first mirror signal to the first output circuit 160 via the first node N1; the second current mirror circuit 140 is configured to generate a second mirror signal of the second current signal and provide the second mirror signal to the third current mirror circuit 150; the third current mirror circuit 150 is configured to generate a third mirror signal of the second mirror signal and provide the third mirror signal to the first output circuit 160 via the first node N1; the first output circuit 160 is configured to compare the first mirror signal and the third mirror signal, and output a first indication signal of the first output current I1 based on the comparison result. An inverter is provided in the first output circuit 160 to improve the circuit driving capability and improve the efficiency of the first indication signal being transmitted to the logic determination circuit 400.

[0065] In another optional embodiment of this application, an error amplifier circuit is provided, wherein the second comparator circuit includes a differential input pair circuit 120, a second current mirror circuit 140, a fourth current mirror circuit 170, a fifth current mirror circuit 180, and a second output circuit, wherein the second output circuit includes a compensation network circuit 190.

[0066] The fourth current mirror circuit 170 is configured to generate a fourth mirror signal of the first current signal and provide the fourth mirror signal to the second output circuit via the second node N2; the second current mirror circuit 140 is configured to generate a second mirror signal of the second current signal and provide the second mirror signal to the fifth current mirror circuit 180; the fifth current mirror circuit 180 is configured to generate a fifth mirror signal of the second mirror signal and provide the fifth mirror signal to the second output circuit via the second node N2; the second output circuit is configured to compare the fourth mirror signal and the fifth mirror signal and output a second output current I2 based on the comparison result. The second output circuit is also provided with a compensation network circuit 190, which can be an RC compensation circuit. The second output current I2 flows into the compensation network circuit to generate an error voltage signal Vc.

[0067] In another optional embodiment of this application, a structure for a first comparator circuit and an error amplifier circuit is provided. Figure 2In the example, a high-voltage signal is output from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The differential input pair circuit 120 includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 is coupled to the reference voltage terminal, the first electrode of the first transistor M1 is coupled to the first electrode of the second transistor M2, and the second electrode of the first transistor is coupled to the first current mirror circuit 130 at the third node N3. The first current mirror circuit 130 includes a third transistor M3 and a fourth transistor M4. The first electrode of the third transistor M3 is coupled to the second voltage terminal V2, the second electrode of the third transistor M3 is coupled to the third node N3, and the gate of the third transistor M3 is coupled to the third node N3. The first electrode of the fourth transistor M4 is coupled to the second voltage terminal V2, the second electrode of the fourth transistor M4 is coupled to the first node N1, and the gate of the fourth transistor M4 is coupled to the gate of the third transistor M3. The second current mirror circuit 140 includes a fifth transistor. Transistor M5 and transistor M6 are connected as follows: the first terminal of transistor M5 is coupled to the second voltage terminal V2, the second terminal of transistor M5 is coupled to the fourth node N4, and the gate of transistor M5 is coupled to the fourth node N4; the first terminal of transistor M6 is coupled to the second voltage terminal V2, the gate of transistor M6 is coupled to the gate of transistor M5, and the second terminal of transistor M6 is coupled to the third current mirror circuit 150; the third current mirror circuit 150 includes transistor M7 and transistor M8. The first terminal of transistor M7 is coupled to the first voltage terminal V1, the second terminal of transistor M7 is coupled to the second terminal of transistor M6, and the gate of transistor M7 is coupled to the second terminal of transistor M6; the first terminal of transistor M8 is coupled to the first voltage terminal V1, the second terminal of transistor M8 is coupled to the first node N1, and the gate of transistor M8 is coupled to the gate of transistor M7. The fourth current mirror circuit 170 includes a third transistor M3 and a ninth transistor M9. The first terminal of the third transistor M3 is coupled to the second voltage terminal V2, the second terminal of the third transistor M3 is coupled to the third node N3, and the gate of the third transistor M3 is coupled to the third node N3. The first terminal of the ninth transistor M9 is coupled to the second voltage terminal V2, the second terminal of the ninth transistor M9 is coupled to the second node N2, and the gate of the ninth transistor M9 is coupled to the gate of the third transistor M3. The fifth current mirror circuit 180 includes a seventh transistor M7 and a tenth transistor M10. The first terminal of the seventh transistor M7 is coupled to the first voltage terminal V1, the second terminal of the seventh transistor M7 is coupled to the second terminal of the sixth transistor M6, and the gate of the seventh transistor M7 is coupled to the second terminal of the sixth transistor M6. The first terminal of the tenth transistor M10 is coupled to the first voltage terminal V1, the second terminal of the tenth transistor M10 is coupled to the second node N2, and the gate of the tenth transistor M10 is coupled to the gate of the seventh transistor M7.

[0068] In another optional embodiment of this application, a clamping circuit is provided. Figure 3An exemplary circuit diagram of a clamping circuit provided in this application is shown below. Figure 3 As shown, the clamping circuit includes a second constant current generating circuit 310, a negative feedback clamping circuit 320, and a logic buffer circuit 330. The second constant current generating circuit 310 is configured to generate a second constant current and output the second constant current through its second terminal. The first terminal of the second constant current generating circuit 310 is coupled to a first voltage terminal V1, and the second terminal of the second constant current generating circuit 310 is coupled to the input terminal of the logic buffer circuit 330. The input terminal of the negative feedback clamping circuit 320 is coupled to the output terminal of the error amplifier circuit 200 and is used to receive the error voltage signal Vc output by the error amplifier circuit 200. The negative feedback clamping circuit 320 is configured to clamp the error voltage signal Vc to be greater than or equal to a preset clamping voltage V0. The negative feedback clamping circuit 320 may include an eleventh transistor M11, a twelfth transistor M12, and an eleventh transistor M13. The first terminal of transistor M11 is coupled to the output terminal of error amplifier circuit 200, the second terminal of eleventh transistor M11 is coupled to the first voltage terminal V1, and the gate of eleventh transistor M11 is coupled to the second terminal of second constant current generating circuit 310; the first terminal of twelfth transistor M12 is coupled to the second voltage terminal V2, the second terminal of twelfth transistor M12 is coupled to the second terminal of second constant current generating circuit 310, and the gate of twelfth transistor M12 is coupled to the output terminal of error amplifier circuit 200; the input terminal of logic buffer circuit 330 is coupled to the output terminal of negative feedback clamping circuit 320, and logic buffer circuit 330 is configured to output a second indication signal C2 based on the comparison result of error voltage Vc and preset clamping voltage V0, and output through the output terminal of logic buffer circuit 330; logic buffer circuit 330 is provided with an inverter element to improve circuit driving capability.

[0069] The clamping circuit 300 is equipped with a preset clamping voltage V0. The clamping circuit 300 is coupled to the output of the second comparator circuit at the fifth node N5. It is used to receive the error voltage signal Vc output by the second comparator circuit and compare the error voltage signal Vc with the preset clamping voltage V0. If the error voltage signal Vc is greater than or equal to the preset clamping voltage, the second indication signal output by the output of the clamping circuit 300 is a low-level indication signal. If the error voltage signal Vc is less than the preset clamping voltage, the negative feedback clamping circuit in the clamping circuit 300 clamps the error voltage signal to the preset clamping voltage V0, and the second indication signal output by the output of the clamping circuit 300 is a high-level indication signal.

[0070] In another optional embodiment of this application, a logic determination circuit is provided. Figure 4 An exemplary circuit diagram of a logic decision circuit provided in this application, such as... Figure 4As shown, the logic determination circuit 400 includes a first signal input terminal, a second signal input terminal, and a third signal input terminal. The logic determination circuit 400 can be configured to include inverters, NAND gates, and / or NOR gate structures. The logic determination circuit 400 is configured to output a sleep indicator signal based on a first indicator signal C1 and a second indicator signal C2. The sleep indicator signal is used to control the switching power supply to switch to a sleep state. The first signal input terminal is coupled to the output terminal of the first comparator circuit 100, outputting the first indicator signal C1 to the first signal input terminal of the logic determination circuit 400. The second signal input terminal is coupled to the output terminal of the clamping circuit 300, outputting the second indicator signal C2 to the second signal input terminal of the logic determination circuit. The third signal input terminal is connected to the output terminal C3 of the zero-crossing detection circuit. The zero-crossing detection circuit is configured to prevent the operating current from crossing zero and control the operating current to flow in one direction. When the operating current is a positive current, it outputs the operating current; when the operating current is a reverse current, the zero-crossing detection circuit controls the operating current to be 0.

[0071] In another optional embodiment of this application, a different power control circuit is provided. Figure 5 The schematic block diagram of the first power control circuit provided in this application includes: a first comparator circuit 100, an error amplifier circuit 200, a clamping circuit 300, a logic determination circuit 400, a second comparator circuit 500, an inductor current detection circuit 600, and a pulse signal generation circuit 700.

[0072] The second comparator circuit 500 is configured to compare the error voltage signal Vc and the preset detection voltage R*IL, and based on the comparison result, output a third indication signal from the output terminal of the second comparator circuit 500 to the pulse signal generation circuit 700. The second comparator circuit 500 includes an inductor current detection circuit 600 and a PWM comparator. The inductor current detection circuit 600 is configured to generate a preset waveform voltage signal, generate a preset waveform detection voltage, and generate a preset detection voltage R*IL. The inductor current detection circuit 600 also provides the preset waveform voltage signal to the PWM comparator. The non-inverting input terminal of the PWM comparator is coupled to the output terminal of the error amplifier circuit, and the inverting input terminal of the PWM comparator is coupled to the output terminal of the inductor current detection circuit. The PWM comparator is configured to compare the error voltage signal and the preset waveform voltage signal, and based on the comparison result, output a pulse width modulation signal through the output terminal of the PWM comparator and provide the pulse width modulation signal to the pulse signal generation circuit.

[0073] The pulse signal generation circuit 700 is configured to generate a duty cycle signal D based on a third indication signal. This duty cycle signal indicates the duty cycle of the output voltage during the switching power supply's operation. The pulse signal generation circuit 700 includes a logic buffer circuit and a logic control circuit. The first input terminal of the pulse signal generation circuit is coupled to the output terminal of a PWM comparator. The second input terminal of the pulse signal generation circuit is coupled to an oscillator circuit to receive an oscillator signal Vz. When the switching power supply enters a sleep state, the oscillator signal Vz is a low-level signal; when the switching power supply switches to normal operating mode, the oscillator signal Vz is a pulse signal. The logic control circuit is configured to generate the duty cycle signal D based on the pulse width modulation signal and the oscillator signal Vz. The logic buffer circuit is coupled to the logic control circuit to improve the driving capability of the pulse signal generation circuit.

[0074] The logic determination circuit 400 is configured to generate a sleep indication signal based on the first indication signal C1 output by the first comparator circuit 100 and the second indication signal C2 output by the clamping circuit 300, and control the switching power supply to switch between sleep state and normal operation state. In sleep state, most working modules in the switching power supply are turned off except for the sleep detection module corresponding to the sleep detection circuit, so as to reduce system power consumption and enter a low power consumption mode to improve efficiency.

[0075] When the load is light, the output feedback voltage FB is higher than the reference voltage Vref. The first comparator circuit 100 outputs a first indicator signal C1 as a low-level signal. After processing by the error amplifier circuit 200 and the clamping circuit 300, the clamping circuit 300 outputs a second indicator signal C2 as a high-level signal. The logic determination circuit 400 outputs a sleep signal based on the first indicator signal C1 and the second indicator signal C2, controlling the switching power supply to shut down some working modules to reduce system power consumption and enter a low-power standby mode to improve efficiency.

[0076] When the load switches from light load to heavy load, the output feedback voltage FB drops. When the output feedback voltage FB is lower than the reference voltage Vref, the first comparator circuit 100 outputs the first indicator signal C1 as a high-level signal. After processing by the error amplifier circuit 200 and the clamping circuit 300, the clamping circuit 300 outputs the second indicator signal C2 as a low-level signal. The logic determination circuit 400 outputs a wake-up signal according to the first indicator signal C1 or the second indicator signal C2, controlling the switching power supply to exit the sleep state and enter the normal working mode.

[0077] In another optional embodiment of this application, a duty cycle signal output circuit is provided. Figure 6 An exemplary circuit diagram of a power control circuit provided in this application is shown below. Figure 6As shown, the circuit includes a second comparator circuit 500 and a pulse signal generation circuit 700. The second comparator circuit 500 can be configured as a PWM comparator to compare the error voltage signal Vc with the preset detection R*IL generated by the current inductor detection circuit 600. The pulse signal generation circuit 700 is configured to generate a duty cycle signal D based on the comparison result of the second comparator circuit 500. The pulse signal generation circuit 700 may include an inverter, a NOR gate, and / or a NAND gate. The first input terminal of the pulse signal generation circuit 700 is coupled to the output terminal of the second comparator circuit 500 to receive the comparison result output by the second comparator circuit 500. The second input terminal of the pulse signal generation circuit 700 is connected to the oscillator signal output terminal to receive the oscillator signal Vz. The pulse signal generation circuit 700 is configured to generate the duty cycle signal D based on the comparison result output by the second comparator circuit 500 and the oscillator signal Vz.

[0078] Figure 7 A schematic block diagram of a switching power supply provided in this application, such as... Figure 7 As shown, the switching power supply includes a control circuit, a drive circuit, a zero-crossing detection circuit, and a load terminal. The input terminal of the control circuit is coupled to a reference voltage Vref and an output feedback voltage FB, respectively. The control circuit is configured to generate a sleep indicator signal (Sleep) and a duty cycle signal D based on the reference voltage Vref and the output feedback voltage FB. The drive circuit is coupled to the input terminal of the control circuit and drives the switching power supply to adjust the output voltage in sleep mode, switching mode, or operating mode according to the sleep indicator signal (Sleep) and the duty cycle signal D. The drive circuit is coupled to the gates of transistors Q1 and Q2, respectively. The first terminal of transistor Q1 and the second terminal of transistor Q2 are coupled together. The second terminal of transistor Q1 is coupled to the input voltage VIN of the switching power supply. The first terminal of transistor Q1 is coupled to the load circuit to provide the output voltage VOUT of the switching power supply to the load circuit. The first terminal of transistor Q2 is coupled to the input terminal of the zero-crossing detection circuit, which is configured to prevent the operating current generated by the switching power supply from crossing zero. The zero-crossing detection circuit is coupled to the drive circuit to provide the zero-crossing detection signal to the drive circuit. Resistors R1 and R2 are configured to provide the output feedback voltage FB to the control circuit. Cout is the output capacitor.

[0079] The specific configuration of each unit of the control circuit in the above embodiments has been described in detail in the embodiments of the control circuit, and will not be elaborated here.

[0080] In summary, the control circuit structure in this embodiment compares the output feedback voltage of the switching power supply with the reference voltage using a first comparator circuit. Based on the comparison result, a sleep indicator signal is generated to control the switching power supply to switch between sleep and normal operation states. This improves the switching speed of the first indicator signal output by the first comparator circuit under different load conditions and enhances the switching efficiency of different load states.

[0081] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0082] Obviously, those skilled in the art should understand that the various units or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device, or fabricating them separately as individual integrated circuit modules, or fabricating multiple modules or steps into a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0083] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A control circuit for a switching power supply, characterized in that, include: The circuit consists of a first comparator circuit, an error amplifier circuit, a clamping circuit, and a logic decision circuit. The first comparator circuit is configured to compare a reference voltage and an output feedback voltage, and output a first indication signal from the output terminal of the first comparator circuit to the logic determination circuit based on the comparison result. The error amplifier circuit is configured to compare a reference voltage and an output feedback voltage, and based on the comparison result, output an error voltage signal from the circuit of the error amplifier circuit and provide the error voltage signal to the clamping circuit. The clamping circuit is configured to compare the error voltage signal with a preset clamping voltage, and based on the comparison result, output a second indication signal from the output terminal of the clamping circuit to the logic determination circuit; The clamping circuit includes a constant current generating circuit, a negative feedback clamping circuit, and a logic buffer circuit. Wherein, the first terminal of the constant current generating circuit is coupled to the first voltage terminal, and the second terminal of the constant current generating circuit is coupled to the input terminal of the logic buffer circuit; The negative feedback clamping circuit is configured to clamp the error voltage to be greater than or equal to the preset clamping voltage; The input terminal of the logic buffer circuit is coupled to the output terminal of the negative feedback clamping circuit, and the logic buffer circuit is configured to output the second indication signal based on the comparison result between the error voltage and the preset clamping voltage. The logic determination circuit is configured to output a sleep indicator signal based on the first indicator signal and the second indicator signal, the sleep indicator signal being used to control whether the switching power supply switches to a sleep state.

2. The control circuit according to claim 1, characterized in that, The first comparator circuit includes: a differential input pair circuit, a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, and a first output circuit. The first differential input terminal of the differential input pair circuit is coupled to the reference voltage terminal for receiving the reference voltage, and the second differential input terminal of the differential input pair circuit is coupled to the output feedback voltage terminal for receiving the output feedback voltage. The differential input pair circuit is configured to generate a first current signal based on the reference voltage and provide the first current signal to the first current mirror circuit via the first output terminal of the differential input pair circuit, and the differential input pair circuit is configured to generate a second current signal based on the output feedback voltage and provide the second current signal to the second current mirror circuit via the second output terminal of the differential input pair circuit; The first current mirror circuit is configured to generate a first mirror signal of the first current signal and provide the first mirror signal to the first output circuit via a first node; The second current mirror circuit is configured to generate a second mirror signal of the second current signal and provide the second mirror signal to the third current mirror circuit; The third current mirror circuit is configured to generate a third mirror signal of the second mirror signal and provide the third mirror signal to the first output circuit via the first node; The first output circuit is configured to compare the first mirror signal and the third mirror signal, and output the first indication signal based on the comparison result.

3. The control circuit according to claim 1, characterized in that, The error amplifier circuit includes: a differential input pair circuit, a second current mirror circuit, a fourth current mirror circuit, a fifth current mirror circuit, and a second output circuit. The differential input pair circuit is configured to generate a first current signal based on the reference voltage and provide the first current signal to the fourth current mirror circuit via the first output terminal of the differential input pair circuit; and the differential input pair circuit is configured to generate a second current signal based on the output feedback voltage and provide the second current signal to the fourth current mirror circuit via the second output terminal of the differential input pair circuit. The fourth current mirror circuit is configured to generate a fourth mirror signal of the first current signal and provide the fourth mirror signal to the second output circuit via the second node; The second current mirror circuit is configured to generate a second mirror signal of the second current signal and provide the second mirror signal to the fifth current mirror circuit; The fifth current mirror circuit is configured to generate a fifth mirror signal of the second mirror signal and provide the fifth mirror signal to the second output circuit via the second node; The second output circuit is configured to compare the fourth mirror signal and the fifth mirror signal, and output the error voltage signal based on the comparison result.

4. The control circuit according to claim 2 or 3, characterized in that, The differential input pair circuit includes a first transistor and a second transistor. Wherein, the gate of the first transistor is coupled to the reference voltage terminal, the first terminal of the first transistor is coupled to the first terminal of the second transistor, and the second terminal of the first transistor is coupled to the first current mirror circuit and the fourth current mirror circuit at the third node, for providing the first current signal to the first current mirror circuit and the fourth current mirror circuit. The gate of the second transistor is coupled to the output feedback voltage terminal, and the second terminal of the second transistor is coupled to the second current mirror circuit at the fourth node to provide the second current signal to the second current mirror circuit.

5. The control circuit according to claim 3, characterized in that, The second output circuit includes a compensation network circuit. The input terminal of the compensation network circuit is coupled to the output terminal of the fourth current mirror circuit, and the input terminal of the compensation network circuit is coupled to the output terminal of the fifth current mirror circuit, for generating the error voltage signal based on the current difference between the fourth and fifth mirror signals flowing into the compensation network circuit.

6. The control circuit according to claim 1, characterized in that, The logic determination circuit is configured to output a sleep indicator signal based on the first indicator signal and the second indicator signal. When the first indicator signal is low and the second indicator signal is high, the logic determination circuit outputs the first sleep indicator signal, which is used to control the switching power supply to enter the sleep state. When the first indicator signal is high or the second indicator signal is low, the logic determination circuit outputs a second sleep indicator signal, which is used to control the switching power supply to enter the normal working state.

7. The control circuit according to claim 1, characterized in that, The control circuit further includes: a second comparator circuit and a pulse signal generation circuit. The second comparator circuit is configured to compare the error voltage signal with a preset detection voltage, and output a third indication signal from the output terminal of the second comparator circuit to the pulse signal generation circuit based on the comparison result. The pulse signal generating circuit is configured to generate a duty cycle signal based on the third indication signal, the duty cycle signal being used to indicate the duty cycle of the output voltage under the operating state of the switching power supply.

8. The control circuit according to claim 7, characterized in that, The second comparator circuit includes an inductor current detection circuit and a PWM comparator. The inductor current detection circuit is configured to generate a preset waveform voltage signal and provide the preset waveform voltage signal to the PWM comparator. The non-inverting input of the PWM comparator is coupled to the output of the error amplifier circuit, and the inverting input of the PWM comparator is coupled to the output of the inductor current detection circuit. The PWM comparator is configured to compare the error voltage signal and the preset waveform voltage signal, and output a pulse width modulation signal through the output of the PWM comparator according to the comparison result, and provide the pulse width modulation signal to the pulse signal generation circuit.

9. The control circuit according to claim 7, characterized in that, The pulse signal generation circuit includes a logic buffer circuit and a logic control circuit. The first input terminal of the pulse signal generation circuit is coupled to the output terminal of the PWM comparator, and the second input terminal of the pulse signal generation circuit is coupled to the oscillator circuit for receiving the oscillation signal. The logic control circuit is configured to generate the duty cycle signal according to the pulse width modulation signal and the oscillation signal. The logic buffer circuit is coupled to the logic control circuit and is used to improve the driving capability of the pulse signal generation circuit.

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