Phase detector circuit, phase detector chip and clock data recovery circuit

Abstract

This application relates to a phase detector circuit, a phase detector chip, and a clock data recovery circuit. Under a preset level of the second sampling clock signal, a logic decision circuit directly generates a decision result based on the logical relationship between the first sampling signal, the synchronization signal, and the third sampling signal, instead of generating two intermediate signals first and then merging them. Subsequently, the second synchronization circuit latches the output after being synchronized by the second sampling clock signal. This scheme, because the entire decision process has only one combinational logic path, eliminates the problem of delay matching between the two signals, thus completely eliminating output transient fluctuations caused by inconsistent path delays. Simultaneously, the output is updated only at the edge of the second sampling clock signal, maintaining a constant output and avoiding additional phase differences introduced by delay mismatch, significantly improving the alignment accuracy of the clock and data. Furthermore, the phase detector circuit structure of this application is simpler than traditional structures, resulting in relatively smaller power consumption and area.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a phase detector circuit, a phase detector chip, and a clock data recovery circuit. Background Technology

[0002] In high-speed serial communication systems, the receiving end typically needs to recover the clock signal from the transmitted data stream using a Clock and Data Recovery (CDR) circuit to ensure correct data sampling. The phase detector, as the core module of the CDR circuit, is mainly used to detect the phase difference between the recovered clock and the input data. To reduce the implementation complexity and power consumption of CDR circuits, half-rate phase detector architectures have gradually been adopted. These can utilize a clock frequency half the data rate to perform dual-edge sampling of the data, thereby simplifying the design of the clock circuit.

[0003] However, half-rate phase detectors are typically built using multiple flip-flops and two XOR gates. Due to factors such as process variations, layout and routing differences, and load mismatches, a delay difference can exist between the two XOR gates in a half-rate phase detector. This delay difference causes a brief erroneous pulse in the phase detector's output each clock cycle, introducing an additional phase difference and reducing the alignment accuracy between the clock and data. Summary of the Invention

[0004] Therefore, it is necessary to provide a phase detector circuit, a phase detector chip, and a clock-data recovery circuit to address the problem that half-rate phase detectors easily introduce additional phase differences, reducing the alignment accuracy between clock and data.

[0005] This application provides a phase detector circuit, including a first sampling circuit, a second sampling circuit, a third sampling circuit, a first synchronization circuit, a second synchronization circuit, and a logic decision circuit;

[0006] The first sampling circuit is connected to a first sampling clock signal and input data respectively, and is used to sample the input data at the first edge of the first sampling clock signal to obtain a first sampling signal;

[0007] The second sampling circuit is connected to the first sampling clock signal and the input data respectively, and is used to sample the input data at the second edge of the first sampling clock signal to obtain a second sampling signal; wherein the polarity of the first edge and the second edge are opposite.

[0008] The first synchronization circuit is connected to the second sampling clock signal and the second sampling signal respectively, and is used to latch the second sampling signal at the third edge of the second sampling clock signal and output a synchronization signal; wherein, the second sampling clock signal and the first sampling clock signal are orthogonal; the trigger time of the third edge is located between the trigger times of the first edge and the second edge;

[0009] The third sampling circuit is connected to the second sampling clock signal and the input data respectively, and is used to sample the input data at the third edge of the second sampling clock signal to obtain the third sampling signal;

[0010] The logic decision circuit is connected to the first sampling circuit, the first synchronization circuit, and the third sampling circuit, and is used to generate a decision result based on the logical relationship between the first sampling signal, the synchronization signal, and the third sampling signal under a preset level state of the second sampling clock signal.

[0011] The second synchronization circuit is connected to the logic decision circuit and is used to latch and output the decision result at the edge when the second sampling clock signal changes from the preset level state.

[0012] In some embodiments, the logic decision circuit is configured to: output a first logic level representing a clock lag decision result when the synchronization signal is the same as the third sampling signal and different from the first sampling signal; output a second logic level representing a clock advance decision result when the first sampling signal is the same as the third sampling signal and different from the synchronization signal; and maintain the previous output state through internal hysteresis when the first sampling signal is the same as the synchronization signal.

[0013] In some embodiments, the logic decision circuit is configured to: output a first logic level representing a clock lag decision result when the synchronization signal is the same as the third sampling signal and different from the first sampling signal; output a second logic level representing a clock advance decision result when the first sampling signal is the same as the third sampling signal and different from the synchronization signal; and output a preset invalid level signal when the first sampling signal is the same as the synchronization signal.

[0014] In some embodiments, the first sampling circuit, the second sampling circuit, and the third sampling circuit are all D flip-flops.

[0015] In some embodiments, both the first synchronization circuit and the second synchronization circuit are D latches.

[0016] In some embodiments, the preset level state is a low level state, and the edge from which the preset level state changes is a rising edge; or the preset level state is a high level state, and the edge from which the preset level state changes is a falling edge.

[0017] In some embodiments, the phase detector circuit further includes a phase shifting circuit, the input terminal of which is used to input the first sampling clock signal, and the output terminal of which is connected to the third sampling circuit, the first synchronization circuit, the logic decision circuit and the second synchronization circuit, and the phase shifting circuit is used to convert the first sampling clock signal into the second sampling clock signal.

[0018] In some embodiments, the phase-shifting circuit is a delay-locked loop or a phase interpolator.

[0019] This application provides a phase detector chip, including the phase detector circuit described above.

[0020] This application provides a clock data recovery circuit, including a charge pump circuit, a filter circuit, an oscillator circuit, and the aforementioned phase detector circuit. The charge pump circuit is connected to the phase detector circuit and the filter circuit, and the filter circuit is connected to the oscillator circuit. The oscillator circuit is at least used to generate the first sampled clock signal.

[0021] The aforementioned phase detector circuit, phase detector chip, and clock data recovery circuit include a first sampling circuit and a second sampling circuit that sample data at the rising and falling edges of the first sampling clock signal, respectively, to obtain a first sampling signal and a second sampling signal. The second sampling signal is then latched at the third edge of the second sampling clock signal by a first synchronization circuit to obtain a synchronization signal, which is then transmitted to the logic decision circuit. The third sampling circuit samples the input data at the third edge of the second sampling clock signal to obtain a third sampling signal. At a preset level of the second sampling clock signal, the logic decision circuit directly generates a decision result based on the logical relationship between the first sampling signal, the synchronization signal, and the third sampling signal, rather than generating two intermediate signals and then merging them. Subsequently, the second synchronization circuit latches its output after being synchronized by the second sampling clock signal.

[0022] This scheme, because the entire decision process has only one combinational logic path, eliminates the problem of delay matching between two signals, thus completely eliminating output transient fluctuations caused by inconsistent path delays. Simultaneously, the output is updated only at the edge of the second sampling clock signal, maintaining a constant output and avoiding additional phase differences introduced by delay mismatch, significantly improving the alignment accuracy of the clock and data. Furthermore, the phase detector circuit structure of this application is simpler than traditional structures, resulting in relatively smaller circuit power consumption and area. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the phase detector circuit structure in one embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the phase detector circuit structure in another embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the phase detector circuit in operation according to one embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the clock data recovery circuit structure in one embodiment of this application. Detailed Implementation

[0028] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0030] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0031] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0032] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0033] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0034] Please see Figure 1 This application provides a phase detector circuit, including a first sampling circuit 11, a second sampling circuit 12, a third sampling circuit 13, a first synchronization circuit 14, a second synchronization circuit 16, and a logic decision circuit 15. The first sampling circuit 11 receives a first sampling clock signal (i.e., CKI) and input data (i.e., Din), and samples the input data at the first edge of the first sampling clock signal to obtain a first sampling signal (i.e., A1). The second sampling circuit 12 receives the first sampling clock signal and the input data, and samples the input data at the second edge of the first sampling clock signal to obtain a second sampling signal (i.e., A2); wherein the polarities of the first and second edges are opposite.

[0035] The first synchronization circuit 14 is connected to the second sampling clock signal (CKQ) and the second sampling signal, respectively. It is used to latch the second sampling signal at the third edge of the second sampling clock signal and output a synchronization signal (A2d). The second sampling clock signal and the first sampling clock signal are orthogonal. The trigger time of the third edge is located between the trigger times of the first edge and the second edge. The third sampling circuit 13 is connected to the second sampling clock signal and the input data, respectively. It is used to sample the input data at the third edge of the second sampling clock signal to obtain the third sampling signal (A3).

[0036] The logic decision circuit 15 is connected to the first sampling circuit 11, the first synchronization circuit 14, and the third sampling circuit 13. It is used to generate a decision result (i.e., B) based on the logical relationship between the first sampling signal, the synchronization signal, and the third sampling signal when the second sampling clock signal is at a preset level. The second synchronization circuit 16 is connected to the logic decision circuit 15. It is used to latch the decision result and output it at the edge when the second sampling clock signal changes from the preset level.

[0037] Input data refers to the serial data stream for which the clock needs to be recovered. The first sampling circuit 11 refers to a sampling circuit triggered by the first edge of the first sampling clock signal, used to sample the input data. The first sampling clock signal refers to the master clock used to control the sampling timing, and its frequency is half the data rate. The first edge refers to a specified transition direction of the first sampling clock signal (e.g., rising edge, 0 to 1).

[0038] The second sampling circuit 12 is a sampling circuit triggered by the second edge of the first sampling clock signal, and it is also used to sample the input data. The second edge refers to a transition direction with the opposite polarity (which can be understood as the transition direction) to the first edge. The first synchronization circuit 14 is a latching circuit triggered by the third edge of the second sampling clock signal, used to latch the second sampled signal and output a synchronization signal. The second sampling clock signal is a clock signal that is orthogonal to the first sampling clock signal (with a 90-degree phase difference), and the two have the same frequency. The third edge is a specified transition direction of the second sampling clock signal, and its trigger time is located between the trigger times of the first edge and the second edge.

[0039] The third sampling circuit 13, triggered by the third edge of the second sampling clock signal, is also used to sample the input data. The logic decision circuit 15 is a three-input combinational logic circuit that can directly generate a single-path decision result during the preset level state of the second sampling clock signal, based on the logical relationship between the first sampling signal, the synchronization signal, and the third sampling signal. The preset level state refers to a specified level range (e.g., high or low) of the second sampling clock signal, during which the logic decision circuit 15 performs operations. The decision result refers to the single-bit signal output by the logic decision circuit 15, representing the phase relationship (e.g., lag or lead) of the recovery clock relative to the data. The second synchronization circuit 16 is a latch circuit triggered by the edge of the second sampling clock signal transitioning from the preset level state, used to latch and output the decision result.

[0040] In this embodiment, the first and second edges of the first sampling clock signal divide each data bit period into two half-cycles. The first edge samples to obtain the first sampling signal, and the second edge samples to obtain the second sampling signal. These two signals reflect the level state of the data at different edge moments. To determine the phase relationship (leading or lagging) between the recovery clock and the data, a reference sampling point located between these two edges is also needed. This sampling point is used to capture the position information of the data transition. The third edge (provided by the orthogonal second sampling clock signal) falls exactly between the first and second edges, allowing the third sampling circuit 13 to sample the input data at this intermediate moment. Thus, the three sampling signals form a leading, middle, and trailing positional relationship in time, which allows the logic decision circuit 15 to accurately determine the direction of the clock edge relative to the data transition.

[0041] The structure of the logic decision circuit 15 is not unique. For example, in one embodiment, it can be configured using a combination of three-input AND, OR, and NOT gates, or a three-input lookup table. The specific configuration is not limited, as long as the following decision function can be achieved: When the synchronization signal is the same as the third sampling signal and different from the first sampling signal (indicating a data transition and clock lag), a first logic level (e.g., high level) is output; when the first sampling signal is the same as the third sampling signal and different from the synchronization signal (indicating a data transition and clock lead), a second logic level (e.g., low level) is output; when the first sampling signal is the same as the synchronization signal, it indicates no data transition.

[0042] The above scheme, because the entire decision process has only one combinational logic path, eliminates the problem of delay matching between two signals, thus completely eliminating output transient fluctuations caused by inconsistent path delays. Simultaneously, the output is updated only at the edge of the second sampling clock signal, maintaining a constant output and avoiding additional phase differences introduced by delay mismatch, significantly improving the alignment accuracy between the clock and data.

[0043] Furthermore, the above solution can achieve half-rate phase detection with fewer components, and its power consumption is lower and its area is smaller compared to traditional half-rate phase detection circuits.

[0044] In some embodiments, the logic decision circuit 15 is configured to: output a first logic level representing a clock lag decision result when the synchronization signal is the same as the third sampling signal and different from the first sampling signal; output a second logic level representing a clock advance decision result when the first sampling signal is the same as the third sampling signal and different from the synchronization signal; and maintain the previous output state through internal hysteresis when the first sampling signal is the same as the synchronization signal.

[0045] The clock lag decision result is represented by the first logic level output of logic decision circuit 15, indicating that the recovered clock phase lags behind the data edge. The clock lead decision result is represented by the second logic level output of logic decision circuit 15, indicating that the recovered clock phase leads the data edge. Internal hysteresis refers to the feedback hold mechanism introduced inside logic decision circuit 15, which maintains the previous valid decision result at the output when there is no data transition.

[0046] The logic decision circuit 15 integrates a hysteresis function. In addition to the basic three-input combinational logic (used to determine lead / lag when data changes), it adds a hold path that feeds back from the output to the input. This feedback path can be constructed by a transmission gate or a two-input AND-OR gate, without any specific limitation. Its conduction condition is controlled by the comparison result that the first sampled signal is equal to the synchronization signal.

[0047] In some embodiments, the logic decision circuit 15 first compares the first sampled signal and the synchronization signal to generate a no-transition flag signal. When this flag is false (i.e., the first sampled signal is not equal to the synchronization signal, indicating a data transition), the feedback path is broken, and the output is entirely determined by the combinational logic based on the relationship between the first sampled signal, the synchronization signal, and the third sampled signal. That is, if the synchronization signal is equal to the third sampled signal and not equal to the first sampled signal, the output clock lag decision result is given; if the first sampled signal is equal to the third sampled signal and not equal to the synchronization signal, the output clock lead decision result is given.

[0048] When the no-transition flag is true (the first sampling signal equals the synchronization signal), the feedback path is activated, feeding the current output value back to the input, forcing the output to remain unchanged from the previous state. In this way, the phase detector circuit output will not transition to an invalid level, thus avoiding providing incorrect charge / discharge commands to the subsequent charge pump.

[0049] The above scheme, by configuring the logic decision circuit 15 to maintain the previous output state by internal hysteresis when there is no data transition, not only retains the phase decision function, but also avoids random fluctuations in the output under high impedance or invalid state, enhances the stability of the phase detector circuit during data silence, and speeds up the locking speed of the clock data recovery loop.

[0050] In some embodiments, the logic decision circuit 15 is configured to: output a first logic level representing a clock lag decision result when the synchronization signal is the same as the third sampling signal and different from the first sampling signal; output a second logic level representing a clock advance decision result when the first sampling signal is the same as the third sampling signal and different from the synchronization signal; and output a preset invalid level signal when the first sampling signal is the same as the synchronization signal.

[0051] The preset invalid level signal refers to a fixed level (e.g., high or low level) output by the logic decision circuit 15 when there is no data transition, or to make the output stage present a high impedance state to indicate that there is no valid phase information in the current cycle.

[0052] In some embodiments, a no-transition detection circuit can be added inside the three-input logic gate. When the first sampled signal is detected to be equal to the synchronization signal, a fixed logic level (e.g., logic 0 or logic 1) is forced to be output instead of maintaining the previous state. This fixed level can be implemented using a multiplexer; that is, when there is a data transition, the decision result of the combinational logic is selected for output; when there is no data transition, a preset constant is selected for output. This scheme is suitable for applications with sufficiently high data transition density or where the loop filter can effectively filter out low-frequency disturbances.

[0053] Whether hysteresis or an invalid output level is used, since the output is still generated once during the clock level through a single combined path, there is no timing problem of merging two signals. Therefore, the additional phase difference introduced by the inconsistency of XOR gate delay in the traditional scheme can be avoided.

[0054] The above scheme ensures that the phase detector output has clear phase information only when a valid data edge occurs by outputting a preset invalid level signal when there is no data transition. This avoids misjudgment caused by invalid transitions, further improves the reliability of phase decision, and reduces jitter in the clock recovery circuit.

[0055] In some embodiments, the first sampling circuit 11, the second sampling circuit 12, and the third sampling circuit 13 are all D flip-flops.

[0056] A flip-flop is an edge-triggered memory cell that latches and outputs input data at a specified edge of a clock cycle. Flip-flops are the most basic timing units in digital integrated circuits, characterized by sampling input data only at the clock edge (rising or falling edge), with the output remaining unchanged at the rest of the time. The advantages of using flip-flops as sampling circuits are: compatibility with most digital standard cell libraries, easy direct use in integrated circuit designs; relatively low power consumption, as flip-flops only consume dynamic power at the clock edge; and precise definition of the sampling time by the clock edge, simplifying timing analysis and facilitating high-speed half-rate sampling.

[0057] In the phase detector circuit of this application, the first sampling circuit 11 uses a D flip-flop, which is triggered by the first edge of the first sampling clock signal; the second sampling circuit 12 uses a D flip-flop, which is triggered by the second edge of the first sampling clock signal; and the third sampling circuit 13 uses a D flip-flop, which is triggered by the third edge of the second sampling clock signal.

[0058] It is understood that the structure of a D flip-flop is not unique. In one embodiment, it can be a master-slave structure D flip-flop formed by cascading two D latches. In other embodiments, other types of D flip-flops can be used, such as transmission gate structure D flip-flops, etc., which are not limited here.

[0059] The above scheme uses D flip-flops as the first sampling circuit 11, the second sampling circuit 12, and the third sampling circuit 13. It has a simple structure, low power consumption, and is highly compatible with standard digital circuit libraries. It can reduce overall power consumption and chip area while maintaining high-speed sampling, which is beneficial for integration into low-power clock data recovery systems.

[0060] In some embodiments, both the first synchronization circuit 14 and the second synchronization circuit 16 are D latches.

[0061] A latch is a level-sensitive storage unit. When the enable clock is at a certain level, the input passes through to the output; when the enable clock is at the opposite level, the output retains the previously latched value.

[0062] The first synchronization circuit 14 employs a latch whose clock input is connected to the second sampling clock signal and is transparent in a preset level state (e.g., high level). When the second sampling clock signal is at this preset level, the latch directly outputs the second sampling signal as a synchronization signal; when the second sampling clock signal is at the opposite level, the synchronization signal is latched and remains unchanged. This adjusts the sampling time of the second sampling signal to be aligned with the working window of the logic decision circuit 15.

[0063] The second synchronization circuit 16 employs another latch, whose clock input is connected to the second sampling clock signal. This latch is transparent at the opposite level (e.g., high level). When the second sampling clock signal is at this level, the latch passes through the output of the logic decision circuit 15; when the second sampling clock signal transitions to another level, the latch latches the output and outputs a stable result on the next edge.

[0064] It is understood that the type of D latch is not unique. In one embodiment, a transmission gate type D latch, a gated D latch, etc. can be used, and no limitation is made here.

[0065] The above scheme uses a D latch as the first synchronization circuit 14 and the second synchronization circuit 16, which can complete signal synchronization and output latching under clock level conditions. This avoids the delay inconsistency problem caused by using multiple flip-flops for synchronization, simplifies timing control, and improves the accuracy of phase decision.

[0066] In some embodiments, the preset level state is a low level state, and the edge from which the preset level state changes is a rising edge; or the preset level state is a high level state, and the edge from which the preset level state changes is a falling edge.

[0067] The preset level state refers to the level of the second sampling clock signal during the effective operation of the logic decision circuit 15. The edge that transitions from the preset level state refers to the edge at which the second sampling clock signal transitions from the preset level to the opposite level, which is used to trigger the latch output of the second synchronization circuit 16.

[0068] In one implementation, the preset level state is low, meaning the logic decision circuit 15 operates when the second sampling clock signal is low; the transition edge from the preset level state is a rising edge, meaning the second synchronization circuit 16 latches the decision result when the second sampling clock signal transitions from low to high. In another optional implementation, the preset level state is high, meaning the logic decision circuit 15 operates when the second sampling clock signal is high; the transition edge from the preset level state is a falling edge, meaning the second synchronization circuit 16 latches the output when the second sampling clock signal transitions from high to low. These two configurations are functionally equivalent; only the clock polarity of the latch needs to be adjusted accordingly.

[0069] The above solution allows the circuit to be adapted to different clock system designs by flexibly selecting preset level states (high level or low level) and their transition edges, thereby enhancing the circuit's versatility and integration flexibility while maintaining low power consumption and low latency characteristics.

[0070] Please see Figure 2 In some embodiments, the phase detector circuit further includes a phase shift circuit 17. The input terminal of the phase shift circuit 17 is used to input the first sampling clock signal, and the output terminal of the phase shift circuit 17 is connected to the third sampling circuit 13, the first synchronization circuit 14, the logic decision circuit 15, and the second synchronization circuit 16. The phase shift circuit 17 is used to convert the first sampling clock signal into a second sampling clock signal.

[0071] The phase shift circuit 17 refers to the circuit module used to convert the input first sampling clock signal into a second sampling clock signal, requiring that the two be orthogonal (90-degree phase difference).

[0072] The input of the phase-shifting circuit 17 receives the first sampling clock signal, and the output generates a second sampling clock signal. This second sampling clock signal is then connected to the third sampling circuit 13, the first synchronization circuit 14, the logic decision circuit 15, and the second synchronization circuit 16, respectively. In practical clock data recovery systems, the first sampling clock signal is usually generated directly by a voltage-controlled oscillator, while the second sampling clock signal (quadrature clock) can be generated from the first sampling clock signal through the phase-shifting circuit 17. With the addition of the phase-shifting circuit 17, the entire phase detector circuit can function as an independent module. It only requires the input of the first sampling clock signal and input data to output a phase error signal, eliminating the need for an external quadrature clock and simplifying system integration. The phase-shifting circuit 17 can be located inside the phase detector circuit or integrated as part of the phase detector circuit with other circuits; the specific location is not limited.

[0073] The above scheme introduces a phase-shifting circuit 17 to convert the first sampling clock signal into an orthogonal second sampling clock signal, ensuring that the timing window of sampling and synchronization operation is correctly aligned, avoiding sampling errors caused by clock phase deviation, and thus further improving the accuracy of phase detection.

[0074] In some embodiments, the phase-shifting circuit 17 is a delay-locked loop or a phase interpolator.

[0075] A delay-locked loop (LLO) is a closed-loop circuit that generates a precise delay by comparing the phase of the input clock with that of a delayed clock, and is often used to generate quadrature clocks. A phase interpolator, on the other hand, is a circuit that generates an arbitrary intermediate phase by weighted synthesis of multiple phase inputs, and is typically used for fine-tuning the phase in high-speed serial interfaces.

[0076] When using a delay-locked loop (DLL) to generate a quadrature clock, its working principle is as follows: the first sampled clock signal is input into a voltage-controlled delay chain. The delay is adjusted by a phase detector circuit and a charge pump feedback to ensure that the output of the delay chain is delayed by exactly one-quarter of a cycle (90 degrees), thus obtaining the second sampled clock signal. The advantages of a DLL are that it can automatically compensate for process, voltage, and temperature variations, stably output a precise quadrature clock, and has a relatively simple structure and low power consumption.

[0077] When using a phase interpolator to generate quadrature clocks, it is typically necessary to input a multi-phase clock (e.g., 0 degrees, 90 degrees, 180 degrees, 270 degrees), and then select or interpolate the desired 90-degree phase using a digital control word. The advantage of a phase interpolator is that the phase adjustment step size can be very fine (e.g., one-sixty-fourth of a bit cycle), and it can be seamlessly integrated with a phase interpolator-based clock data recovery loop.

[0078] The above scheme uses a delay-locked loop or a phase interpolator as the phase shifting circuit 17, which can accurately generate quadrature clock signals and has good resistance to process-voltage-temperature drift, ensuring that the phase detector circuit can maintain stable phase detection performance under different operating conditions.

[0079] Please refer to the following: Figure 3 In some embodiments, clock lag is used as an example for explanation. The data transition (0→1) shown in the figure occurs before the rising edge of the first sampling clock signal CKI. Therefore, at the rising edge of CKI, the data has already transitioned from 0 to 1, and the second sampling signal A2=1 is obtained. When sampling at the rising edge of CKQ, since the trigger time of the rising edge of CKQ is located between the rising and falling edges of CKI, the data remains 1 and no 1→0 transition occurs, thus the third sampling signal A3=1 is obtained. At the falling edge of CKI, the data has already transitioned and stabilized at 0, and the first sampling signal A1=0 is obtained. The first synchronization circuit 14 latches A2=1 as the synchronization signal A2d=1 during the low level of the second sampling clock signal CKQ. The logic decision circuit 15 compares A1=0, A2d=1, and A3=1 during the low level of the second sampling clock signal. We get A1≠A3=A2d, which means the synchronization signal is the same as the third sampling signal and different from the first sampling signal. At this time, it will be determined that the clock is lagging, and the output will be a high level (i.e., 1), which is B.

[0080] Furthermore, the logic decision circuit 15 can output stably during the low level of the second sampling clock signal and is latched by the second synchronization circuit 16 triggered by the rising edge, maintaining an output of 0 or 1 within one data bit cycle (2Tb) (that is, PD output, the hysteresis in this embodiment corresponds to maintaining 1), and no other state will occur.

[0081] This application provides a phase detector chip, including the phase detector circuit described above.

[0082] The phase detector chip integrates the aforementioned phase detector circuit and can be directly used as a standard functional module in various clock data recovery systems.

[0083] The phase detector chip uses three flip-flops (sampling circuit), two latches (synchronization circuit), and one three-input logic gate (logic decision circuit 15). Compared with the scheme of five flip-flops and two XOR gates, it reduces two flip-flops and two XOR gates, thereby reducing power consumption and chip area.

[0084] Furthermore, since the logic decision circuit 15 generates the decision result all at once during the preset level state of the second sampling clock signal and latches the output by the second synchronization circuit 16, there is no problem of delay matching between the two XOR gates. This completely eliminates the additional static phase difference introduced by the path delay inconsistency, making the alignment accuracy between the recovery clock and the data depend only on the mismatch of the sampling flip-flops, rather than the delay matching of the logic gates. Moreover, this phase detector chip supports half-rate operation, making it suitable for high-speed communication systems.

[0085] The above solution integrates the phase detector circuit, achieving low power consumption, small area, and high phase accuracy half-rate phase detection function, which is especially suitable for clock data recovery systems in high-speed serial communication.

[0086] Please see Figure 4 This application provides a clock data recovery circuit, including a charge pump circuit 200, a filter circuit 300, an oscillator circuit 400 and the aforementioned phase detector circuit 100. The charge pump circuit 200 is connected to the phase detector circuit 100 and the filter circuit 300. The filter circuit 300 is connected to the oscillator circuit 400. The oscillator circuit 400 is used to generate at least a first sampling clock signal.

[0087] The clock data recovery circuit extracts the clock signal from the serial data stream and resamples the data using this clock to achieve clock-data synchronization. The charge pump circuit 200 charges or discharges the filter circuit 300 based on the lead / lag signal output from the phase detector. The filter circuit 300 is typically a passive or active low-pass filter that smooths the discrete current pulses output by the charge pump into a continuous control voltage. The oscillator circuit 400 generates a recovered clock based on the control voltage output from the filter circuit 300; the frequency and phase of its output clock are adjusted by the control voltage.

[0088] The clock data recovery circuit includes a charge pump circuit 200, a filter circuit 300, an oscillator circuit 400, and a phase detector circuit 100. The phase detector circuit 100 receives input data and a first sampling clock signal generated by the oscillator circuit 400 (or may also include a second sampling clock signal orthogonal to it), and outputs a lead / lag decision result to the charge pump circuit 200. The charge pump circuit 200 charges and discharges the filter circuit 300 according to the decision result. The filter circuit 300 outputs a smooth control voltage to the oscillator circuit 400. The oscillator circuit 400 adjusts the phase of the first sampling clock signal accordingly to form a closed-loop lock.

[0089] The above solution, by coordinating the phase detector circuit 100 with the charge pump, filter and oscillator, can achieve high-precision clock data recovery with low power consumption, eliminate the lock offset caused by the inconsistency of the internal delay of the phase detector, and improve the anti-jitter capability and data alignment accuracy of the overall clock data recovery circuit.

[0090] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A phase detector circuit, characterized in that, include: The first sampling circuit is connected to a first sampling clock signal and input data respectively, and is used to sample the input data at the first edge of the first sampling clock signal to obtain a first sampling signal; The second sampling circuit is connected to the first sampling clock signal and the input data respectively, and is used to sample the input data at the second edge of the first sampling clock signal to obtain a second sampling signal; wherein the polarity of the first edge and the second edge are opposite. A first synchronization circuit is connected to a second sampling clock signal and a second sampling signal, respectively, and is used to latch the second sampling signal at the third edge of the second sampling clock signal and output a synchronization signal; wherein the second sampling clock signal and the first sampling clock signal are orthogonal; the trigger time of the third edge is located between the trigger times of the first edge and the second edge; The third sampling circuit is connected to the second sampling clock signal and the input data respectively, and is used to sample the input data at the third edge of the second sampling clock signal to obtain the third sampling signal; A logic decision circuit, connected to the first sampling circuit, the first synchronization circuit, and the third sampling circuit, is used to generate a decision result based on the logical relationship between the first sampling signal, the synchronization signal, and the third sampling signal under a preset level state of the second sampling clock signal. The second synchronization circuit, connected to the logic decision circuit, is used to latch and output the decision result at the edge when the second sampling clock signal changes from the preset level state.

2. The phase detector circuit according to claim 1, characterized in that, The logic decision circuit is configured to output a first logic level characterizing the clock lag decision result when the synchronization signal is the same as the third sampling signal and different from the first sampling signal. When the first sampling signal is the same as the third sampling signal and different from the synchronization signal, a second logic level representing the clock advance decision result is output. And when the first sampling signal is the same as the synchronization signal, the previous output state is maintained by internal hysteresis.

3. The phase detector circuit according to claim 1, characterized in that, The logic decision circuit is configured to output a first logic level characterizing the clock lag decision result when the synchronization signal is the same as the third sampling signal and different from the first sampling signal. When the first sampling signal is the same as the third sampling signal and different from the synchronization signal, a second logic level representing the clock advance decision result is output. And when the first sampling signal is the same as the synchronization signal, a preset invalid level signal is output.

4. The phase detector circuit according to claim 1, characterized in that, The first sampling circuit, the second sampling circuit, and the third sampling circuit are all D flip-flops.

5. The phase detector circuit according to claim 1, characterized in that, Both the first synchronization circuit and the second synchronization circuit are D latches.

6. The phase detector circuit according to claim 1, characterized in that, The preset level state is a low level state, and the edge from which the preset level state changes is a rising edge; or the preset level state is a high level state, and the edge from which the preset level state changes is a falling edge.

7. The phase detector circuit according to claim 1, characterized in that, It also includes a phase-shifting circuit, the input of which is used to input the first sampling clock signal, and the output of which is connected to the third sampling circuit, the first synchronization circuit, the logic decision circuit and the second synchronization circuit. The phase-shifting circuit is used to convert the first sampling clock signal into the second sampling clock signal.

8. The phase detector circuit according to claim 7, characterized in that, The phase-shifting circuit is a delay-locked loop or a phase interpolator.

9. A phase detector chip, characterized in that, Includes the phase detector circuit as described in any one of claims 1-8.

10. A clock data recovery circuit, characterized in that, The circuit includes a charge pump circuit, a filter circuit, an oscillator circuit, and a phase detector circuit as described in any one of claims 1-8, wherein the charge pump circuit is connected to the phase detector circuit and the filter circuit, the filter circuit is connected to the oscillator circuit, and the oscillator circuit is used at least to generate the first sampling clock signal.

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