Integrated assembly and semiconductor memory device

Abstract

The present application relates to integrated assemblies and semiconductor memory devices. Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are located at a first spacing. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different from the first direction. Some of the conductive structures are electrically coupled to the circuit arrangement. The conductive structures are located at a second spacing different from the first spacing. A second dimension is a distance across the some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.

Description

Technical Field

[0001] Integrated assemblies. Integrated memory. Multi-layer assemblies. FinFET, CMOS, FinFET integration, CMOS integration, etc. Background Art

[0002] Memory is a type of integrated circuit used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be called bit lines, data lines, read lines, or data / read lines) and access lines (which may also be called word lines). Digit lines conductively interconnect memory cells along the columns of the array, and access lines conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of digit lines and access lines.

[0003] Memory cells can be either volatile or nonvolatile. Nonvolatile memory cells can store data for extended periods of time, including when the computer is turned off. Volatile memory is subject to wear and tear and is therefore refreshed / rewritten rapidly, in many cases multiple times per second. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In binary, these states are considered "0" or "1." In other systems, at least some individual memory cells may be configured to store information in more than two levels or states.

[0004] Some memory cells may include a transistor combined with a capacitor (or other suitable charge storage device). The transistor is used to selectively access the capacitor and may be referred to as an access device. The capacitor can electrostatically store energy as an electric field within the capacitor dielectric between two capacitor plates. The electrical state of the capacitor can be used to represent the memory state.

[0005] The word lines may be coupled to word line driver circuitry, and the digit lines may be coupled to sense amplifier circuitry.The word line driver circuitry and sense amplifier circuitry may be within the CMOS region of the integrated assembly.

[0006] Memory is one example of an integrated circuit system, and many other types of integrated circuit systems are known (eg, sensor circuitry, logic circuitry, etc.) In some applications, these other types of integrated circuit systems can be used in combination with integrated memory.

[0007] A continuing goal in integrated assembly manufacturing is to increase the level of integration, or in other words, to pack more memory into ever-shrinking spaces. New architectures for integrated assemblies need to be developed, and such new architectures need to be suitable for highly integrated applications. Summary of the Invention

[0008] Embodiments of the present disclosure provide an integrated assembly comprising: a CMOS region; fins extending across the CMOS region, the fins being located at a first spacing; a circuit arrangement associated with the CMOS region and comprising one or more segments of the fins, the circuit arrangement having a first dimension along a first direction; a second region proximate to the CMOS region; and conductive structures associated with the second region and extending along a second direction substantially orthogonal to the first direction; some of the conductive structures are electrically coupled to the circuit arrangement; the conductive structures are located at a second spacing different from the first spacing; the second dimension is a distance across some of the conductive structures along the first direction; the conductive structures are aligned with the circuit arrangement such that the second dimension is substantially the same as the first dimension.

[0009] Another embodiment of the present disclosure provides an integrated assembly comprising: a CMOS region; a fin associated with the CMOS region; a circuit arrangement associated with the CMOS region and comprising segments of one or more of the fins, the circuit arrangement comprising a first circuit arrangement and a second circuit arrangement; a memory region proximate the CMOS region and comprising two intersecting groups of conductive lines; the conductive lines of one of the groups are word lines and the conductive lines of the other group are digit lines; the word lines extend along a first direction and the digit lines extend along a second direction substantially orthogonal to the first direction; the first circuit arrangement has a first dimension along the first direction and the second circuit arrangement has a second dimension along the second direction; some of the word lines are coupled to the second circuit arrangement and some of the digit lines are coupled to the first circuit arrangement; a third dimension is along the second direction and is a distance across all of the word lines coupled to the second circuit arrangement, and a fourth dimension is along the first direction and is a distance across all of the digit lines coupled to the first circuit arrangement; the word lines are aligned with the second circuit arrangement such that the third dimension is substantially the same as the second dimension; and the digit lines are aligned with the first circuit arrangement such that the fourth dimension is substantially the same as the first dimension.

[0010] Yet another embodiment of the present disclosure provides an integrated assembly comprising: a semiconductor substrate; a CMOS region associated with the substrate; fins extending across the CMOS region and located at a first pitch; a circuit arrangement associated with the CMOS region and including segments of one or more of the fins, the circuit arrangement including a word line driver arrangement and a sense amplifier arrangement; a memory layer located above the substrate; word lines and digit lines associated with the memory layer; the word lines extending along a first direction and the digit lines extending along a second direction substantially orthogonal to the first direction; the word lines being located at a second pitch and the digit lines being located at a third pitch; the second pitch and the third pitch being substantially perpendicular to the first pitch; The digit lines are coupled to the sense amplifier arrangement at different spacings; the sense amplifier arrangement has a first dimension along a first direction, and the word line driver arrangement has a second dimension along a second direction; some of the word lines are coupled to the word line driver arrangement and some of the digit lines are coupled to the sense amplifier arrangement; a third dimension is along the second direction and is a distance across all of the word lines coupled to the word line driver arrangement, and a fourth dimension is along the first direction and is a distance across all of the digit lines coupled to the sense amplifier arrangement; the word lines are aligned with the word line driver arrangement such that the third dimension is substantially the same as the second dimension; and the digit lines are aligned with the sense amplifier arrangement such that the fourth dimension is substantially the same as the first dimension. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of an example region of an example integrated memory array.

[0012] Figure 2 is a diagrammatic top view of an example region of an example CMOS-containing semiconductor substrate.

[0013] Figure 3A and 3B A diagrammatic top view of an example region of an example semiconductor substrate containing CMOS and an example region of an integrated memory array proximate the substrate is shown.

[0014] Figure 4A 、 4B 4C are diagrammatic top views of an example region of an example CMOS-containing semiconductor substrate and one or more example regions of an integrated memory array proximate the substrate.

[0015] Figure 5 is a diagrammatic side view of an example region of an example multi-faceted assembly.

[0016] Figure 6 is a diagrammatic top view of an example region of an example CMOS-containing semiconductor substrate. DETAILED DESCRIPTION

[0017] Some embodiments include an architecture (integrated assembly) having a CMOS region with fins (i.e., a FinFET arrangement) and having conductive lines (e.g., word lines, digit lines, etc.) arranged at a suitable pitch to achieve a desired alignment of the conductive lines with circuit arrangements associated with the CMOS region (e.g., word line drivers, sense amplifiers, etc.). Figures 1 to 6 Example embodiments are described.

[0018] refer to Figure 1 , integrated assembly 200 is shown as including memory cells (MCs) 204 arranged within a memory array 202. The memory cells may be any suitable memory cells now known or yet to be developed. In some embodiments, the memory cells may be configured for use in dynamic random access memory (DRAM). In such embodiments, the memory cells may each include an access device (e.g., a transistor) combined with a storage element (e.g., a capacitor).

[0019] Word lines (access lines) 206 extend along a first direction (the illustrated x-axis direction) and across the memory array 202. The illustrated word lines are labeled WL1 through WL4. The word lines are coupled with word line driver circuitry 208 (eg, a word line driver).

[0020] Digital lines (bit lines, sense lines) 210 extend along a second direction (the illustrated y-axis direction) and across the memory array 202. The illustrated digit lines are labeled DL1 through DL4. The digit lines are coupled to sense circuitry (eg, sense amplifiers) 212.

[0021] The term "sense / access line" may be used generically to refer to both word lines and digit lines.

[0022] Each of the memory cells 204 can be considered to be uniquely addressed by one of the word lines 206 and one of the combined digit lines 210 .

[0023] In the embodiment shown, the second direction (y-axis direction) is orthogonal to the first direction (x-axis direction). Generally speaking, the digit line 210 extends orthogonally or at least substantially orthogonally relative to the word line 206; where the term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances.

[0024] In some embodiments, word lines 206 can be considered a first set of conductive lines and digit lines 210 can be considered a second set of conductive lines. The first and second sets of conductive lines cross each other and are shown as being orthogonal (or at least substantially orthogonal) to each other in the illustrated embodiment.

[0025] Word lines 206 are shown separated from each other by word line spacing 214 (WL spacing), and digit lines 210 are shown separated from each other by digit line spacing 216 (DL spacing). The word line spacing can be the same as the digit line spacing (or at least substantially the same as the digit line spacing), or it can be different from the digit line spacing. It should be noted that spacing is not simply the space between features, but refers to a measure of pattern repeat. Thus, spacing includes, for example, the width of a feature and the width of the space between adjacent features (or sometimes, half the width of the space and half the width of the feature). In the case of word lines and digit lines (where "WL / DL" is common to both word lines and digit lines), spacing can include the width of the WL / DL together with the width of the space between adjacent WL / DLs.

[0026] In practice, the semiconductor assembly may include one or more regions containing CMOS circuitry, and the driver circuitry 208 and readout circuitry 212 may be associated with the CMOS circuitry. A memory array may be formed in another region of the semiconductor assembly, and the word lines 206 and digit lines 210 may extend across the array and be coupled to circuitry associated with the CMOS circuitry (e.g., driver circuitry 208 and readout circuitry 212).

[0027] Aligning word lines 206 and digit lines 210 with CMOS circuitry can be challenging, and such challenges can be addressed using the embodiments described below. Word lines and digit lines are examples of conductive structures that can be aligned with a region containing CMOS circuitry (i.e., circuitry associated with a CMOS region). Although the embodiments described herein are primarily described with respect to aligning word lines and digit lines with circuitry associated with a CMOS region, one of ordinary skill will appreciate that the embodiments can be used to align conductive structures other than word lines and digit lines with circuitry associated with a CMOS region.

[0028] refer to Figure 2 , showing a portion of CMOS region 100. The CMOS region may be formed in a semiconductor base 12. Base 12 may include a semiconductor material; and may, for example, include, consist essentially of, or consist of single crystal silicon. Base 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any structure comprising semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials), and a layer of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above. In some applications, base 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like.

[0029] Fin 10 extends across CMOS region 100. The fin may be a raised area of ​​substrate 12. The fin may extend across the entire CMOS region 100 and be incorporated into a fin field effect transistor (FinFET). Fin 10 is located at a fin pitch (FP), where this fin pitch is established by the fabrication process used to form the fin.

[0030] The gate structure 14 extends across the fin 10. The gate structure may comprise any suitable material, and in some embodiments may comprise silicon (e.g., polycrystalline silicon, amorphous silicon, a mixture of polycrystalline silicon and amorphous silicon, etc.), metal, a metal-containing material (e.g., metal nitride, metal silicide, etc.), etc. The area of ​​the fin 10 below the gate structure 14 is shown in dashed (phantom) view to indicate that it will be Figure 2 is hidden by the gating structure in the top view.

[0031] The fin 10 is shown extending along a first direction (the direction of the illustrated A1 axis), and the gate structure 14 is shown extending along a second direction (the direction of the illustrated A2 axis); wherein the second direction is orthogonal to the first direction (or at least substantially orthogonal to the first direction). One of the illustrated A1 and A2 axes may correspond to Figure 1 The x-axis of the Figure 1 y-axis.

[0032] The gating structure 14 and the fin 10 are incorporated into a circuit arrangement (eg, a word line driver, a sense amplifier, etc.). A pair of example circuit arrangements are shown in FIG. Figure 2 The dashed boxes are used to diagrammatically illustrate the approximate boundaries of the circuit arrangements 16 and 18. In practice, one of the circuit arrangements 16 and 18 may correspond to word line driver circuitry and the other may correspond to sense amplifier circuitry. Figure 2 Regions 16 and 18 are shown as being close to each other in order to simplify the drawing. In practice, circuit arrangements 16 and 18 may be physically remote from each other. For example, regions 16 and 18 may be along different orthogonal edges of the memory array relative to each other in a conventional (planar) memory configuration (e.g., a DRAM configuration), may be located below different edges of the memory array in a CMOS below memory array configuration, and so on.

[0033] Each of the circuit arrangements 16 and 18 may be connected to a Figure 1 2. The circuit arrangements 16 and 18 are coupled to a plurality of conductive lines of the memory array 202. For example, a plurality of word lines may extend to word line driver circuitry, and a plurality of digit lines may extend to sense amplifier circuitry. It is desirable to align the circuit arrangements 16 and 18 with the conductive lines to which they are coupled (e.g., to align the sense amplifier circuitry with the digit lines 210 to which they are coupled, to align the word line driver circuitry with the word lines 206 to which they are coupled, etc.).

[0034] The fins 10 of the CMOS region 100 may be parallel to Figure 1 206 and 210 of the array 202 and may be orthogonal to another set of read / access lines. Specifically, if Figure 2 The A1 axis corresponds to Figure 1 , then the fin 10 is parallel to (or at least substantially parallel to) the digit line 210 and is orthogonal to (or at least substantially orthogonal to) the word line 206. Alternatively, if Figure 2 The A1 axis corresponds to Figure 1 The x-axis of the fin 10 is parallel to (or at least substantially parallel to) the word line 206 and is orthogonal to (or at least substantially orthogonal to) the digit line 210. Figure 1 The read / access lines 206 and 210 are connected to Figure 2 Two different sets of issues arise regarding the alignment of the circuit arrangements 16 and 18. Specifically, one set of issues is associated with the alignment of the conductive lines with the circuit arrangements having fins 10 that are parallel (or at least substantially parallel) to the conductive lines, and the other set of issues is associated with the alignment of the conductive lines with the circuit arrangements having fins 10 that are perpendicular (or at least substantially perpendicular) to the conductive lines. Both sets of issues are addressed in the subsequent discussion.

[0035] refer to Figure 3A , a portion of the array region 202 is shown proximate to a portion of the CMOS region 100. The array region 202 can generally be considered a second region that is provided proximate to a first region corresponding to the CMOS region 100.

[0036] The illustrated portion of array region 202 includes a set of conductive lines 30 arranged on a pitch P1. Lines 30 may be, for example, Figure 1 The word line 206 or digit line 210 of FIG. 1 may be referred to as a sense / access line to indicate that it may be a word line or a digit line.

[0037] Array region 202 is offset from the illustrated portion of CMOS region 100. Although array region 202 is shown as being laterally offset from the illustrated portion of the CMOS region, it should be understood that the array region may be located in any suitable position relative to the illustrated portion of the CMOS region and may, for example, be vertically offset from the illustrated portion of the CMOS region (i.e., may be located above the CMOS region in an array-under-CMOS configuration) instead of or in addition to being laterally offset from the illustrated portion of the CMOS region.

[0038] CMOS region 100 has fins 10 arranged at a pitch P2. In some embodiments, one of pitches P1 and P2 may be referred to as a first pitch, and the other may be referred to as a second pitch. The first pitch is different from the second pitch. In the illustrated embodiment, pitch P2 is greater than pitch P1 (i.e., readout / access lines 30 of array 202 are formed at a closer pitch than fins 10 of CMOS region 100).

[0039] CMOS region 100 is shown as including a circuit arrangement 16, wherein this circuit arrangement includes a segment of four of the fins 10 and includes two of the gate regions 14 extending across the fins. Circuit arrangement 16 may, for example, be a sense amplifier circuit system in some embodiments, a word line driver circuit system in some embodiments, or the like. Although the circuit arrangement is shown as including a segment of four fins, in other embodiments, the circuit arrangement may include more than four fins or fewer than four fins. The sense amplifier circuit system may include one or more sense amplifiers, and similarly, the word line driver circuit system may include one or more word line drivers.

[0040] The illustrated gating regions 14 each extend across all four of the fins 10 of the circuit arrangement 16. In other embodiments, one of the gating regions may extend across fewer fins than the other of the gating regions. The circuit arrangement may include any suitable number of gating regions and may include a different number of gating regions than the two illustrated.

[0041] In the illustrated application, eight of the lines 30 will be coupled to the circuit arrangement 16. These eight of the lines 30 may be a subset of the total number of digit lines or word lines of the array 202, and thus may represent some of the digit lines 210 or some of the word lines 206 of the array. For example, in some embodiments, the array may include hundreds, thousands, hundreds of thousands, millions, etc. of conductive lines 30 corresponding to the digit lines 210 or word lines 206, and the circuit arrangement 16 may be one of many circuit arrangements coupled to such conductive lines, such that only a small portion of the conductive lines may extend to the array. Figure 3A The specific circuit arrangement 16. Although Figure 3A and 3B All of the lines 30 are shown coupled to the circuit arrangement 16 of the CMOS region 100, but it should be understood that in other embodiments, only some of the lines 30 may be coupled to this circuit arrangement. For example, the lines may be part of the open architecture of a DRAM, wherein reference is made below to Figure 4C The example open architecture is discussed in more detail.

[0042] The circuit arrangement 16 has conductive pads 20 configured for coupling with sense / access lines 30. For purposes of illustration, the conductive pads 20 are shown arranged along columns, but may be located in any suitable position within the circuit arrangement 16.

[0043] Circuit arrangement 16 has a dimension D2 along a first direction corresponding to the direction of axis A1. Conductive wire 30 extends along a second direction that is orthogonal (or at least substantially orthogonal) to the first direction, where this second direction corresponds to the direction of axis A2. Dimension D1 spans all extensions of wire 30 to be coupled to circuit arrangement 16.

[0044] One of dimensions D1 and D2 may be referred to as a first dimension, while the other may be referred to as a second dimension. It is desirable that first dimension D1 and second dimension D2 be identical to each other (or at least substantially identical to each other, where the term "substantially identical" means identical within reasonable manufacturing and measurement tolerances). This enables circuit arrangement 16 to mate with conductive lines 30 coupled thereto, and thus conserves valuable semiconductor real estate compared to configurations in which dimensions D1 and D2 are not substantially identical to each other.

[0045] The illustrated embodiment has dimensions D1 and D2 that are the same (or at least substantially the same) as one another. This can be achieved by adjusting the gate lengths 22 of the CMOS devices within the circuit arrangement 16, and / or by adjusting the spacing 24 between adjacent CMOS devices to achieve a desired dimension D2 that matches dimension D1 of the array 202. In theory, the pitch P1 within the array 202 can be modified to match dimension D1 of the array with dimension D2 of the circuit arrangement 16, but this is generally not a practical approach because it is desirable for pitch P1 to be as small as possible to achieve a high degree of integration of the memory cells 204 within the memory array 202.

[0046] It is fairly straightforward for one of ordinary skill to adjust the gate length 22 and / or spacing 24 within the circuit arrangement 16 to achieve the desired dimension D2 that matches the dimension D1 .

[0047] refer to Figure 3B , showing conductive interconnect 26 formed to connect line 30 of array region 202 with conductive pad 20 associated with circuit arrangement 16. Thus, if circuit arrangement 16 is word line driver circuitry and line 30 is a word line, the word line driver circuitry is now coupled to the word line and may be utilized along the word line during activate / precharge operations associated with the memory cells; and if circuit arrangement 16 is sense amplifier circuitry and line 30 is a digit line, the sense amplifier circuitry is now coupled to the digit line and may be utilized along the digit line during read / write operations associated with the memory cells.

[0048] refer to Figure 4A , a portion of the array region 202 is shown as being close to a portion of the CMOS region 100. Figure 3A Compared with the embodiment, Figure 4AThe embodiment has conductive lines 30 of the array region 202 extending parallel (or at least substantially parallel) to the fins 10. The illustrated conductive lines 30 of the array region 202 will be coupled to the circuit arrangement 18 within the CMOS region 100 and thus for similar purposes to those described above with reference to FIG. Figure 3A For the reasons discussed, it may be desirable for the illustrated dimension D3 within array region 202 to be the same (or at least substantially the same) as dimension D4 within CMOS region 100 for matching dimensions D1 and D2. In some embodiments, one of dimensions D3 and D4 may be referred to as a first dimension and the other may be referred to as a second dimension.

[0049] Due to the difference between the pitch P1 of the conductive lines 30 within the array 202 and the pitch P2 of the fins 10 within the circuit arrangement 18, it may be difficult to match Figure 4A Dimensions D3 and D4.

[0050] Some embodiments recognize that dimension D3 can be matched to dimension D4 by adjusting the pitch P2 of fins 10 relative to the pitch P1 of conductive lines 30. Specifically, circuit arrangement 18 includes a particular number of fins 10 (in the illustrated embodiment, 10 such fins), and the circuit arrangement is coupled to a particular number of conductive lines 30 (in the illustrated embodiment, 12 conductive lines).

[0051] In some embodiments, the fin pitch P2 can be determined relative to the number of memory bits (megabits) associated with the conductive line 30. Specifically, Figure 1 Each of the memory cells 204 can be considered to be one megabit. In some embodiments, dimension D3 can be determined by multiplying the megabit spacing along the A1 axis (which will effectively be the spacing P1 between the conductive lines 30) by the number of megabits (nMbits) coupled to the circuit arrangement 16; that is, D3 = P1 × nMbit. Since dimension D4 is intended to be the same as dimension D3 (or at least substantially the same as dimension D3), the fin pitch can be determined by correlating the number of fins 10 within the circuit arrangement 18 with dimension D3, as will be understood by one of ordinary skill. The difficulty is that only some fin pitches are practically manufacturable, and therefore it may be useful to create a table of suitable fin pitches relative to a particular megabit arrangement and determine which fin pitches are practically manufacturable. In the illustrated embodiment, a first set of twelve conductive lines 30 of the array 202 are coupled to a second set of ten fins 10 of the CMOS region 100. In some embodiments, the number of conductive lines 30 relative to the number of fins 10 may be in a ratio of 12:10. For example, 24 conductive lines 30 can be coupled with 20 fins 10, 36 conductive lines 30 can be coupled with 30 fins 10, etc. The ratio of 12:10 is provided for illustrative purposes only. Any suitable ratio can be selected, as will be understood by a person of ordinary skill in the art.

[0052] refer to Figure 4B , showing conductive interconnect 26 formed to connect connection line 30 of array region 202 with conductive pad 20 associated with circuit arrangement 18. Thus, if circuit arrangement 18 is word line driver circuitry and line 30 is a word line, the word line driver circuitry is now coupled to the word line and may be utilized along the word line during read / write operations associated with the memory cells; and if circuit arrangement 18 is sense amplifier circuitry and line 30 is a digit line, the sense amplifier circuitry is now coupled to the digit line and may be utilized along the digit line during read / write operations associated with the memory cells.

[0053] Figure 3B and 4B The embodiment of FIG. 1 shows all of the conductive lines coupled to the circuit arrangements 16 and 18 within dimensions D1 and D3. In other embodiments, similar to FIG. Figure 3B and 4B The dimensions D1 and D3 may include one or more additional conductive lines that are not coupled to the circuit arrangement. For example, Figure 4C A region of an integrated assembly 300 comprising an open architecture is shown. The assembly includes a first memory array 202a (array-1), a second memory array 202b (array-2) laterally offset from the first memory array, and a CMOS region 100 laterally located between the first and second memory arrays. Each of the memory arrays is shown as including twelve digit lines 30 extending along an axis direction A2 and included in the CMOS region 100 described above with reference to FIG. Figure 4A Within the described dimension D3.

[0054] The CMOS region includes sense amplifier circuitry (SA) and is shown as including six sense amplifiers (SA1 through SA6) within circuit arrangement 18. As one skilled in the art will appreciate, the SAs shown in the diagrams can be considered simplified compared to actual SAs. The simplified SAs are utilized for illustrative purposes and to simplify the diagrams. As one skilled in the art will appreciate, the concepts described herein can be applied to more complex circuit configurations than those shown in the accompanying drawings.

[0055] Each of memory arrays 202a and 202b has six digit lines coupled to sense amplifiers within circuit arrangement 18, and six digit lines not coupled to such sense amplifiers (but which may be coupled to other sense amplifiers facing laterally outward of the display area of ​​assembly 300). In the embodiment shown, the digit lines not coupled to the illustrated sense amplifiers alternate with the digit lines coupled to the illustrated sense amplifiers, and more specifically, alternate along the direction of the A1 axis.

[0056] Figure 3A and 3BThe type of arrangement shown in FIG. 1 with some of the readout / access lines 30 of the array region having fins 10 perpendicular to the CMOS region 16 will generally be similar to that shown in FIG. Figures 4A to 4C 18 with the array region having fins 10 parallel to the CMOS region 18 (since FinFET fabrication processes typically form all fins parallel to one another on a substrate (e.g., a semiconductor chip) and form all gating structures parallel to one another and generally orthogonal to the fins). Figure 1 The digit lines 210 in the array 202 are configured such that the word line driver circuit system in the CMOS area will have fins 10 parallel to the word lines 206 in the array area, while the sense amplifier circuit system in the CMOS area will have fins 10 perpendicular to the digit lines 210 in the array area, or the word line driver circuit system in the CMOS area will have fins 10 perpendicular to the word lines 206, while the sense amplifier circuit system in the CMOS area will have fins 10 parallel to the digit lines 210 in the array area.

[0057] In some embodiments, Figure 3A The circuit arrangement 16 can be regarded as a first circuit arrangement, and Figure 4A The circuit arrangement 18 of FIG. 1 may be considered a second circuit arrangement. The word line 206 is coupled to one of the first circuit arrangement and the second circuit arrangement, and the digit line is coupled to the other of the first circuit arrangement and the second circuit arrangement (or the digit line may be coupled to the Figure 4C The arrangement coupling of the type shown in Figure 4A a subset of the common arrangements of ).

[0058] In some embodiments, the fins 10 can be considered to be at a first pitch ( Figure 3A and 4A P2, and Figure 2 On FP), Figure 1 The digit line 210 can be considered to be on the second spacing 216, and Figure 1 The word lines 206 can be considered to be on the third pitch 214. The first pitch and the second pitch can be different from the first pitch, and may or may not be different from each other. In some embodiments, the pitch of the word lines and the digit lines can be smaller than the pitch of the fins to enable the memory array 202 to be highly integrated.

[0059] In some embodiments, CMOS region 100 may be located below memory array 202 in a multi-level configuration. For example, Figure 5An example multi-level configuration 400 is shown that includes a substrate 12 and includes several memory levels 402-405 above the substrate. Although the illustrated configuration includes four memory levels, it should be understood that other configurations may have more or fewer than four memory levels. For example, some configurations may include only a single memory level. In some embodiments, substrate 12 may be referred to as a level disposed below memory levels 402-405.

[0060] The illustrated levels 12 and 402-405 can be viewed as examples of tiers stacked one on top of the other. The tiers can be located within different semiconductor dies, or at least two of the tiers can be located within the same semiconductor die. Memory tiers 402-405 can include memory arrays, or at least portions of memory arrays. The memory arrays within the various tiers can be identical to one another (e.g., all can be DRAM arrays, ferroelectric memory arrays, NAND memory arrays, etc.), or they can be different from one another (e.g., some can be DRAM arrays, while others can be NAND memory arrays, ferroelectric memory arrays, etc.). Furthermore, one or more of the upper tiers can include control circuitry, sensor circuitry, and the like.

[0061] The memory within layer 402 is schematically indicated as containing the above referenced Figure 1 A memory array 202 of the type described. Thus, word lines and digit lines (similar to Figure 1 The word lines 206 and digit lines 210 of the memory layer 402 may be associated with the memory layer 402.

[0062] CMOS region 12 is shown as including regions 16 and 18, and such regions are diagrammatically illustrated as being coupled to memory array 202 within level 402. In some embodiments, one of regions 16 and 18 includes sense amplifier circuitry, and the other includes word line driver circuitry. The sense amplifier circuitry can be coupled to digit lines of memory array 202, and the word line driver circuitry can be coupled to word lines of memory array 202.

[0063] In the embodiment shown, the electrical couplings from the memory circuitry within levels 402-405 to the CMOS circuitry within substrate 12 are shown as extending through the levels. This can be accomplished using sockets or other suitable areas as conduits for conductive lines passing through the various levels. Alternatively, at least some of the electrical couplings from the levels to the substrate can extend laterally around the levels.

[0064] In the illustrated embodiment, the CMOS circuitry within substrate 12 is directly beneath the memory arrays of levels 402 through 405. In other embodiments, at least some of the CMOS circuitry may be laterally offset relative to the memory circuitry within upper levels 402 through 405, as well as vertically offset relative to the memory circuitry within such levels.

[0065] Although it is usually advantageous to form Figure 2 The fins 10 extend parallel to each other and completely across the CMOS associated with the substrate 12 , but there may be applications where it is desirable to form the fins to have a different pitch in some areas of the substrate 12 than in other areas of the substrate 12 .

[0066] Figure 6 An example embodiment is shown in which substrate 12 includes a pair of regions 500 labeled as type-1 regions and a pair of regions 502 labeled as type-2 regions. Regions 500 may be similar to those described above with reference to Figure 4A C is coupled to the first set of conductive lines so that the fin 10 is parallel to the conductive lines, and the region 502 can be similar to the above reference Figure 3A and 3B The described manner couples to the second set of conductive lines such that the fins 10 are perpendicular to the conductive lines. In some embodiments, one of regions 500 and 502 will include sense amplifier circuitry while the other includes word line driver circuitry.

[0067] The embodiment shown has a region 500 schematically indicated as having a first spacing of fins across the CMOS, where this first spacing is designated as Pitch-1; and a region 502 schematically indicated as having a second spacing of fins across the CMOS, where this second spacing is designated as Pitch-2. The second spacing is different from the first spacing, and therefore a buffer zone 504 is provided between the region having Pitch-2 and the region having Pitch-1 (illustrated diagrammatically with stippling). The buffer zone may lack CMOS fins entirely and / or may have modified (or deformed) CMOS fins extending therein. In any case, the buffer zone may correspond to wasted semiconductor area because it may not be suitable for fabricating functional circuit devices. Therefore, Figure 6 The embodiments of the present invention may be primarily used in applications where it is realized that the advantages achieved by modifying the fin pitch in some areas of the CMOS circuitry relative to other areas outweigh the disadvantages associated with the loss of semiconductor footprint within the buffer area 504. Of course, if an application is developed that uses the buffer area 504 for functional circuit applications, then the buffer area 504 is not wasted space.

[0068] The assemblies and structures discussed above can be utilized within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, gaming, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0069] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0070] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in this disclosure. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be intended to provide linguistic variations within this disclosure to simplify the premise basis within the appended claims, and is not intended to indicate any significant chemical or electrical differences.

[0071] The terms "electrically connected" and "electrically coupled" may both be used in this disclosure. The terms are considered synonymous. The use of one term in some instances and the other in other instances may be intended to provide linguistic variation within this disclosure to simplify the underlying basis for the appended claims.

[0072] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in the specific orientation of the drawings or rotated relative to such orientation.

[0073] Unless otherwise specified, the cross-sectional views of the accompanying illustrations show only features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawings.

[0074] When a structure is referred to as being "on," "adjacent to," or "against" another structure, the structure may be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate upright alignment.

[0075] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may or may not extend generally orthogonally relative to an upper surface of the base.

[0076] Some embodiments include an integrated assembly having a CMOS region and having fins extending across the CMOS region. The fins are located at a first spacing. A circuit arrangement is associated with the CMOS region and includes one or more segments of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate to the CMOS region and includes a set of conductive wires (or other suitable conductive structures). The conductive wires (or other suitable conductive structures) extend along a second direction substantially orthogonal to the first direction. Some of the conductive wires (or other suitable conductive structures) in the set are electrically coupled to the circuit arrangement. The conductive wires (or other suitable conductive structures) are located at a second spacing different from the first spacing. The second dimension is a distance across some of the conductive wires (or other suitable conductive structures) along the first direction. The conductive wires (or other suitable conductive structures) are aligned with the circuit arrangement such that the second dimension is substantially the same as the first dimension.

[0077] Some embodiments include an integrated assembly comprising a CMOS region and fins associated with the CMOS region. A circuit arrangement is associated with the CMOS region and includes one or more segments of the fins. The circuit arrangement includes a first circuit arrangement and a second circuit arrangement. A memory region is proximate to the CMOS region and includes two intersecting groups of conductive lines. The conductive lines in one of the groups are word lines, and the conductive lines in the other group are digit lines. The word lines extend along a first direction, and the digit lines extend along a second direction substantially orthogonal to the first direction. The first circuit arrangement has a first dimension along the first direction, and the second circuit arrangement has a second dimension along the second direction. Some of the word lines are coupled to the second circuit arrangement, and some of the digit lines are coupled to the first circuit arrangement. A third dimension is along the second direction and spans all distances among the word lines coupled to the second circuit arrangement. A fourth dimension is along the first direction and spans all distances among the digit lines coupled to the first circuit arrangement. The word lines are aligned with the second circuit arrangement such that the third dimension is substantially the same as the second dimension. The digit lines are aligned with the first circuit arrangement such that the fourth dimension is substantially the same as the first dimension.

[0078] Some embodiments include an integrated assembly comprising a semiconductor substrate and a CMOS region associated with the substrate. Fins extend across the CMOS region and are located at a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement includes a word line driver arrangement and a sense amplifier arrangement. A memory layer is located above the substrate. Word lines and digit lines are associated with the memory layer. The word lines extend along a first direction, and the digit lines extend along a second direction substantially orthogonal to the first direction. The word lines are located at a second pitch, and the digit lines are located at a third pitch. The second pitch and the third pitch are different from the first pitch. The sense amplifier arrangement has a first dimension along the first direction, and the word line driver arrangement has a second dimension along the second direction. Some of the word lines are coupled to the word line driver arrangement, and some of the digit lines are coupled to the sense amplifier arrangement. The third dimension is along the second direction and is the distance across all word lines coupled to the word line driver arrangement. The fourth dimension is along the first direction and is the distance across all digit lines coupled to the sense amplifier arrangement. The word lines are aligned with the word line driver arrangement such that the third dimension is substantially the same as the second dimension. The digit lines are aligned with the sense amplifier arrangement such that the fourth dimension is substantially the same as the first dimension.

[0079] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Accordingly, the claims are to be given the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: CMOS area; a fin extending across the CMOS region, the fin being located at a first pitch; a circuit arrangement associated with the CMOS region and comprising segments of one or more of the fins; the circuit arrangement having a first dimension along a first direction; a second region proximate to the CMOS region; and conductive structures associated with the second region and extending along a second direction substantially orthogonal to the first direction; some of the conductive structures being electrically coupled to the circuit arrangement; the conductive structures being located at a second pitch different from the first pitch; the second dimension being a distance across the some of the conductive structures along the first direction; The conductive structure is aligned with the circuit arrangement such that the second dimension is substantially the same as the first dimension. 2 . The integrated assembly of claim 1 , wherein the fins extend along the first direction. The integrated assembly of claim 1 , wherein the fins extend along the second direction.

4. The integrated assembly of claim 1, wherein the conductive structure is a word line.

5. The integrated assembly of claim 1, wherein the conductive structure is a digit line.

6. The integrated assembly of claim 1, wherein the circuit arrangement comprises one or more word line drivers.

7. The integrated assembly of claim 1, wherein the circuit arrangement comprises one or more sense amplifiers.

8. The integrated assembly of claim 1, wherein the second region is laterally offset relative to the CMOS region.

9. The integrated assembly of claim 1, wherein the second region is vertically offset relative to the CMOS region.

10. The integrated assembly of claim 9, wherein the second region is directly above the CMOS region.

11. The integrated assembly of claim 1 , wherein only one of the conductive structures within the second dimension is the one of the conductive structures electrically coupled to the circuit arrangement.

12. The integrated assembly of claim 1, wherein other than the ones of the conductive structures that are electrically coupled to the circuit arrangement, another one of the conductive structures is located within the second dimension.

13. An integrated assembly comprising: CMOS area; a fin associated with the CMOS region; a circuit arrangement associated with the CMOS region and comprising segments of one or more of the fins; the circuit arrangement comprising a first circuit arrangement and a second circuit arrangement; a memory region proximate the CMOS region and comprising two intersecting groups of conductive lines; the conductive lines of one of the groups being word lines and the conductive lines of the other of the groups being digit lines; the word lines extending along a first direction and the digit lines extending along a second direction substantially orthogonal to the first direction; The first circuit arrangement has a first size along the first direction, and the second circuit arrangement has a second size along the second direction; some of the word lines are coupled to the second circuit arrangement and some of the digit lines are coupled to the first circuit arrangement; a third dimension along the second direction and across all of the word lines coupled to the second circuit arrangement, and a fourth dimension along the first direction and across all of the digit lines coupled to the first circuit arrangement; The word line is aligned with the second circuit arrangement such that the third dimension is substantially the same as the second dimension; and The digit line is aligned with the first circuit arrangement such that the fourth dimension is substantially the same as the first dimension.

14. The integrated assembly of claim 13, wherein the first circuit arrangement includes one or more sense amplifiers.

15. The integrated assembly of claim 13, wherein the second circuit arrangement includes one or more word line drivers.

16. The integrated assembly of claim 13, wherein the memory region is laterally offset relative to the CMOS region.

17. The integrated assembly of claim 13, wherein the memory region is vertically offset relative to the CMOS region.

18. The integrated assembly of claim 17, wherein the memory region is directly above the CMOS region.

19. The integrated assembly of claim 13, wherein the fins have substantially the same pitch across the first and second circuit arrangements.

20. The integrated assembly of claim 13, wherein the fins have a different pitch across the first circuit arrangement than across the second circuit arrangement.

21. The integrated assembly of claim 20, comprising a buffer region between the first circuit arrangement and the second circuit arrangement.

22. The integrated assembly of claim 21, wherein at least a portion of the buffer zone is devoid of the fin.

23. The integrated assembly of claim 13, wherein the fins are on a first pitch, the digit lines are on a second pitch, and the word lines are on a third pitch; and wherein the first pitch is different relative to the second pitch and the third pitch.

24. The integrated assembly of claim 23, the second spacing and the third spacing being smaller than the first spacing.

25. The integrated assembly of claim 23, wherein the second spacing is substantially the same as the third spacing.

26. An integrated assembly comprising: semiconductor substrates; a CMOS region associated with the substrate; a fin extending across the CMOS region and located at a first spacing; a circuit arrangement associated with the CMOS region and comprising segments of one or more of the fins; the circuit arrangement comprising a word line driver arrangement and a sense amplifier arrangement; a memory layer located above the substrate; word lines and digit lines associated with the memory plane; The word lines extend along a first direction, and the digit lines extend along a second direction substantially orthogonal to the first direction; the word lines are located at a second pitch, and the digit lines are located at a third pitch; the second pitch and the third pitch are different from the first pitch; The sense amplifier arrangement has a first size along the first direction, and the word line driver arrangement has a second size along the second direction; some of the word lines are coupled to the word line driver arrangement and some of the digit lines are coupled to the sense amplifier arrangement; a third dimension is along the second direction and is a distance across all of the word lines coupled to the word line driver arrangement, and a fourth dimension is along the first direction and is a distance across all of the digit lines coupled to the sense amplifier arrangement; The word lines are aligned with the word line driver arrangement such that the third dimension is substantially the same as the second dimension; and The digit lines are aligned with the sense amplifier arrangement such that the fourth dimension is substantially the same as the first dimension.

27. The integrated assembly of claim 26 , wherein the some of the digit lines coupled to the sense amplifier arrangement are first digit lines and alternate with second digit lines that are not coupled to the sense amplifier arrangement; and wherein the fourth dimension spans all extensions of the first digit lines and the same number of second digit lines as the first digit lines.

28. An integrated assembly according to claim 26, wherein the memory level is one of two or more levels above the semiconductor substrate, wherein each of the two or more levels has circuitry associated therewith, the circuitry being coupled to circuitry associated with the semiconductor substrate.

29. The integrated assembly of claim 26, the second spacing and the third spacing being smaller than the first spacing.

30. The integrated assembly of claim 26, wherein a memory array is associated with the memory level and directly above one or both of the sense amplifier arrangement and the word line driver arrangement.

31. The integrated assembly of claim 30, wherein the memory array comprises DRAM.

32. The integrated assembly of claim 26, wherein the second spacing is different from the third spacing.

33. The integrated assembly of claim 26, wherein the second spacing is substantially the same as the third spacing.

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