Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a gate structure on the substrate; forming grooves in the substrate on both sides of the gate structure, the substrate at the bottom of the grooves having a first crystal orientation; and forming source / drain doped layers in the grooves using an epitaxial process. The silicon source used in the epitaxial process includes a first silicon source and a second silicon source. The first silicon source is suitable for selective epitaxial growth of the source / drain doped layers, and the second silicon source is suitable for increasing the epitaxial growth rate of the source / drain doped layers along the first crystal orientation. In this embodiment, the second silicon source is suitable for increasing the epitaxial growth rate of the source / drain doped layers along the first crystal orientation, which is beneficial for increasing the thickness of the source / drain doped layers located at the bottom of the grooves, especially increasing the bottom thickness of the source / drain doped layers in long-channel devices. This makes it less likely for the source / drain contact plug to penetrate the source / drain doped layers, preventing the source / drain contact plug from contacting the high-resistivity region below the source / drain doped layers, thereby improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration to achieve higher computing speeds, larger data storage capacities, and more functions. Consequently, the gates of Complementary Metal Oxide Semiconductor (CMOS) transistors are becoming increasingly thinner and shorter than ever before. To obtain better electrical performance, it is typically necessary to control carrier mobility to improve semiconductor device performance. A key element in controlling carrier mobility is controlling the stress in the transistor channel to increase the drive current.

[0003] As the critical dimensions of devices continue to shrink, in order to ensure device performance, it is often necessary to use embedded epitaxial layers in the source and drain regions to change the stress in the channel region, thereby improving carrier mobility and thus enhancing device performance. For example, for NMOS devices, the N-type source and drain doped regions are now being etched with grooves and then epitaxially grown with high phosphorus concentration silicon phosphide layers, instead of simple N-type ion implantation. The silicon phosphide epitaxial layer can provide tensile stress to the channel region of the NMOS transistor, which is beneficial to improving the carrier mobility of the NMOS transistor.

[0004] However, the electrical performance of current semiconductor structures still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to increase the bottom thickness of the source and drain doped layer, so that the source and drain contact plugs are less likely to penetrate the source and drain doped layer and contact the high-resistivity region below, thereby improving the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a gate structure on the substrate; forming a groove in the substrate on both sides of the gate structure, wherein the substrate at the bottom of the groove has a first crystal orientation; and forming a source / drain doped layer in the groove using an epitaxial process, wherein the silicon source used in the epitaxial process includes a first silicon source and a second silicon source, the first silicon source being adapted to achieve selective epitaxial growth of the source / drain doped layer, and the second silicon source being adapted to increase the epitaxial growth rate of the source / drain doped layer along the first crystal orientation.

[0007] Optionally, the second silicon source is one or more of silane, ethylsilane, and propane.

[0008] Optionally, the first silicon source is dichlorosilane.

[0009] Optionally, the epitaxial process is a vapor phase epitaxy process; in the step of forming the source and drain doped layers using the epitaxial process, the gas flow rate ratio of the first silicon source and the second silicon source is 10:1 to 20:1.

[0010] Optionally, the epitaxial process is a vapor phase epitaxy process; the parameters of the epitaxial process include: the total gas flow rate of the silicon source gas is 100 sccm to 400 sccm.

[0011] Optionally, the epitaxial process further includes an impurity source; when forming an NMOS, the impurity source is an N-type impurity source.

[0012] Optionally, the N-type impurity includes P ions, As ions, or Sb ions.

[0013] Optionally, the N-type impurity is a phosphorus ion, and the impurity source is a phosphorus source; in the step of forming the source / drain doped layer, the material of the source / drain doped layer is a phosphorus silicon layer.

[0014] Optionally, the epitaxial process is a vapor phase epitaxy process, and the reaction gases of the epitaxial process include the first silicon source and the second silicon source, phosphorus source gas, carrier gas and etching gas; the parameters of the epitaxial process include: the flow rate of phosphorus source gas is 500 sccm to 1500 sccm, the process temperature is 600℃ to 700℃, the pressure is 100 Torr to 300 Torr, the flow rate of carrier gas is 2.5 slm to 10 slm, and the flow rate of etching gas is 100 sccm to 300 sccm.

[0015] Optionally, in the step of forming the source / drain doped layer, the phosphorus ion doping concentration in the source / drain doped layer is 1E21cm. -3 up to 5E21cm -3 .

[0016] Optionally, in the step of forming the source / drain doped layer, the portion of the source / drain doped layer located at the bottom of the groove is used as a bottom doped layer, and the thickness of the bottom doped layer is one-sixth to one-half of the groove width.

[0017] Optionally, in the step of forming the source / drain doped layer, the portion of the source / drain doped layer located at the bottom of the groove is used as a bottom doped layer, and the thickness of the bottom doped layer is 15 nm to 40 nm.

[0018] Optionally, the method for forming the semiconductor structure further includes: forming a source / drain contact plug on the source / drain doped layer that contacts the top surface of the source / drain doped layer.

[0019] Optionally, the source / drain contact plug also extends through a portion of the source / drain doped layer; the thickness of the source / drain doped layer at the bottom of the source / drain contact plug is 5 nm to 20 nm.

[0020] Optionally, after forming the source / drain doped layer and before forming the source / drain contact plug, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on a substrate on the side of the gate structure, the interlayer dielectric layer covering the source / drain doped layer; the step of forming the source / drain contact plug includes: forming a contact hole in the interlayer dielectric layer penetrating the top of the source / drain doped layer; and forming the source / drain contact plug in the contact hole that contacts the source / drain doped layer.

[0021] Optionally, the first crystal orientation is <100> Crystal orientation.

[0022] Optionally, the substrate of the groove sidewall has a second crystal orientation, the second crystal orientation being... <110> Crystal orientation.

[0023] Optionally, in the step of forming the groove, the cross-section of the groove is a rectangular structure.

[0024] Optionally, the step of forming the groove includes: using a dry etching process to etch a portion of the thickness of the substrate on both sides of the gate structure to form the groove.

[0025] Optionally, in the step of providing a substrate, the substrate includes a substrate and a fin protruding from the substrate; the gate structure is formed on the substrate and spans the fin, the gate structure covering a portion of the top and a portion of the sidewalls of the fin; the groove is formed in the fins on both sides of the gate structure.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0027] In the semiconductor structure formation method provided by this invention, an epitaxial process is used to form a source / drain doped layer in the groove. The silicon source used in the epitaxial process includes a first silicon source and a second silicon source. The second silicon source is suitable for increasing the epitaxial growth rate of the source / drain doped layer along the first crystal direction, thereby improving the epitaxial growth rate of the source / drain doped layer at the bottom of the groove. Correspondingly, this is beneficial for increasing the thickness of the source / drain doped layer at the bottom of the groove, especially for increasing the bottom thickness of the source / drain doped layer in long-channel devices. When a source / drain contact plug is subsequently formed on the source / drain doped layer, the source / drain contact plug is less likely to penetrate the source / drain doped layer. This helps ensure that at least a portion of the source / drain doped layer thickness is retained at the bottom of the source / drain contact plug, preventing the source / drain contact plug from contacting the high-resistance region below the source / drain doped layer. This, in turn, improves the contact performance between the source / drain contact plug and the source / drain doped layer, reduces contact resistance, and consequently improves the electrical performance of the semiconductor structure, such as increasing the saturation current.

[0028] Furthermore, the first silicon source is suitable for achieving selective epitaxial growth of the source and drain doped layers, which helps to ensure that the epitaxial process can meet the requirements of selective epitaxial growth of the source and drain doped layers. This ensures the selectivity of the epitaxial growth of the source and drain doped layers while increasing the epitaxial growth rate of the source and drain doped layers at the bottom of the groove, thereby increasing the bottom thickness of the source and drain doped layers.

[0029] Furthermore, by adjusting the silicon source in the epitaxial process, the bottom thickness of the source and drain doped layers is increased, thereby avoiding the need to improve the bottom thickness of the source and drain doped layers by adjusting the gate pitch and gate width (CD). This is beneficial for meeting the requirements of established design rules and improving compatibility. Attached Figure Description

[0030] Figures 1 to 4 This is a cross-sectional schematic diagram of each step in a method for forming a semiconductor structure.

[0031] Figures 5 to 11 This is a cross-sectional schematic diagram of each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0032] As can be seen from the background technology, the performance of current semiconductor structures still needs to be improved.

[0033] The following analysis, using a semiconductor structure formation method, explains why the performance of current semiconductor structures still needs improvement. Figures 1 to 4 This is a cross-sectional schematic diagram of each step in a method for forming a semiconductor structure.

[0034] Taking NMOS transistors as an example, in order to improve the carrier mobility of the NMOS transistor channel, the N-type source and drain doped layers are currently etched with grooves, and then a high phosphorus concentration silicon phosphate layer is epitaxially grown in the grooves.

[0035] Specifically, such as Figure 1 As shown, a substrate is provided, including a substrate (not shown) and a fin 10 located on the substrate, wherein a polysilicon gate 11 is formed across the fin 10. The polysilicon gate 11 serves as a dummy gate structure, occupying space for the formation of a metal gate structure.

[0036] like Figure 2 As shown, grooves 12 are formed in the fins 10 on both sides of the polysilicon gate 11.

[0037] like Figure 3 As shown, an epitaxial process is used to form a phosphorus silicon layer 13 in the groove 12, and the phosphorus silicon layer 13 is used as a source / drain doping layer.

[0038] To achieve a high phosphorus concentration, the epitaxial growth of the phosphorus-silicon layer 13 requires relatively high pressure, low carrier gas flow rate, and high silicon and phosphorus source gas flow rates. Under these conditions of high pressure and low carrier gas flow rate, only dichlorosilane typically enables selective epitaxial growth; other types of silicon sources result in a loss of epitaxial selectivity. Therefore, dichlorosilane is currently used as the silicon source for the epitaxial growth of the phosphorus-silicon layer 13.

[0039] Reference Figure 3 Under relatively high pressure, low carrier gas flow rate, and high silicon and phosphorus source gas flow rates, epitaxial growth at the bottom of the groove 12 is limited, while epitaxial growth on the sidewalls of the groove 12 plays a dominant role. For long-channel devices, the width of the groove 12 is large, making it difficult for the epitaxial layers formed on the sidewalls of the groove 12 to fuse together. Meanwhile, the limited epitaxial growth at the bottom of the groove 12 results in insufficient thickness t of the phosphorus-silicon layer 13 located at the bottom of the groove 12.

[0040] Reference Figure 4 When forming the source / drain contact plug 14 that contacts the source / drain doped layer, the thickness t of the silicon phosphorus layer 13 at the bottom of the groove 12 is too small. The process of forming the source / drain contact plug 14 is prone to penetrating the silicon phosphorus layer 13. Below the source / drain doped layer is a high-resistance region. If the source / drain contact plug 14 penetrates the silicon phosphorus layer 13 and contacts the high-resistance region below, it will seriously affect the performance of the device.

[0041] One approach to address these issues is to adjust the polysilicon gate pitch and poly CD (polydiameter discrepancy) of the device. This shortens the width of the etched trench, thereby improving the bottom thickness of the silicon phosphate layer. However, under established design rules, the polysilicon gate pitch is fixed, and the width of the polysilicon gate corresponds to the channel length. Changing the width of the polysilicon gate would significantly impact device performance. Therefore, in actual process flows, the values ​​of the polysilicon gate pitch and width are not easily adjusted.

[0042] Therefore, improving the bottom thickness of the source / drain doped layer without adjusting the gate pitch and width has become an urgent problem to be solved.

[0043] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a gate structure on the substrate; forming a groove in the substrate on both sides of the gate structure, wherein the substrate at the bottom of the groove has a first crystal orientation; and forming a source / drain doped layer in the groove using an epitaxial process, wherein the silicon source used in the epitaxial process includes a first silicon source and a second silicon source, the first silicon source being adapted to achieve selective epitaxial growth of the source / drain doped layer, and the second silicon source being adapted to increase the epitaxial growth rate of the source / drain doped layer along the first crystal orientation.

[0044] In the semiconductor structure formation method provided by this invention, an epitaxial process is used to form a source / drain doped layer in the groove. The silicon source used in the epitaxial process includes a first silicon source and a second silicon source. The second silicon source is suitable for increasing the epitaxial growth rate of the source / drain doped layer along the first crystal direction, thereby improving the epitaxial growth rate of the source / drain doped layer at the bottom of the groove. Correspondingly, this is beneficial for increasing the thickness of the source / drain doped layer at the bottom of the groove, especially for increasing the bottom thickness of the source / drain doped layer in long-channel devices. When a source / drain contact plug is subsequently formed on the source / drain doped layer, the source / drain contact plug is less likely to penetrate the source / drain doped layer. This helps ensure that at least a portion of the source / drain doped layer thickness is retained at the bottom of the source / drain contact plug, preventing the source / drain contact plug from contacting the high-resistance region below the source / drain doped layer. This, in turn, improves the contact performance between the source / drain contact plug and the source / drain doped layer, reduces contact resistance, and consequently improves the electrical performance of the semiconductor structure, such as increasing the saturation current.

[0045] Furthermore, the first silicon source is suitable for achieving selective epitaxial growth of the source and drain doped layers, which helps to ensure that the epitaxial process can meet the requirements of selective epitaxial growth of the source and drain doped layers. This ensures the selectivity of the epitaxial growth of the source and drain doped layers while increasing the epitaxial growth rate of the source and drain doped layers at the bottom of the groove, thereby increasing the bottom thickness of the source and drain doped layers.

[0046] Furthermore, by adjusting the silicon source in the epitaxial process, the bottom thickness of the source and drain doped layers is increased, thereby avoiding the need to improve the bottom thickness of the source and drain doped layers by adjusting the gate pitch and gate width (CD). This is beneficial for meeting the requirements of established design rules and improving compatibility.

[0047] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Figures 5 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0049] refer to Figure 5 Provides a base.

[0050] The substrate is used to provide a process platform for subsequent manufacturing processes.

[0051] In this embodiment, taking the substrate for forming a fin field-effect transistor (FinFET) as an example, in the step of providing the substrate, the substrate includes a substrate (not shown) and a fin 100 protruding from the substrate.

[0052] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0053] The fin 100 is used to provide a conductive channel for the field-effect transistor.

[0054] In this embodiment, the material of the fin 100 is the same as the material of the substrate, and the material of the fin 100 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming fins, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the fin may also be different from the material of the substrate.

[0055] Continue to refer to Figure 5 A gate structure 110 is formed on the substrate.

[0056] In this embodiment, the gate structure 110 is used as a dummy gate structure to occupy space for forming a metal gate structure.

[0057] In this embodiment, the gate structure 110 is formed on the substrate and spans the fin 100, and the gate structure 110 covers part of the top and part of the sidewall of the fin 100.

[0058] In this embodiment, the gate structure 110 includes a dummy gate oxide layer (not shown) and a dummy gate layer (not shown) located on the dummy gate oxide layer.

[0059] In this embodiment, the gate structure 110 is a polysilicon gate structure. Correspondingly, the material of the dummy gate oxide layer is silicon oxide or silicon oxynitride. In this embodiment, the material of the dummy gate layer is polysilicon.

[0060] In this embodiment, the substrate is used to form a long channel device, therefore, the spacing between adjacent gate structures 110 is also relatively large.

[0061] In this embodiment, during the step of forming the gate structure 110, a gate mask layer (not shown) is also formed on the top of the gate structure 110. The gate mask layer serves as an etching mask during the formation of the gate structure 110, and it also protects the top of the gate structure 110 during the formation of the semiconductor structure.

[0062] In this embodiment, the material of the gate mask layer is silicon nitride.

[0063] In this embodiment, after forming the gate structure 110, the method for forming the semiconductor structure further includes forming a sidewall 120 on the sidewall of the gate structure 110.

[0064] The sidewall 120 is used to protect the sidewall of the gate structure 110, and the sidewall 120 is also used to define the formation region of the source and drain doped layer.

[0065] The sidewall 120 can be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, boron nitride, and boron carbonitride. The sidewall 120 can be a single-layer structure or a multilayer structure.

[0066] In this embodiment, the sidewall 120 has an ONO (Oxide-Nitride-Oxide) structure, and the sidewall 120 includes a first silicon oxide layer, a silicon nitride layer located on the sidewall of the first silicon oxide layer, and a second silicon oxide layer located on the sidewall of the silicon nitride layer.

[0067] refer to Figure 6 A groove 130 is formed in the substrate on both sides of the gate structure 110, and the substrate at the bottom of the groove 130 has a first crystal orientation.

[0068] The groove 130 is used to provide space for the formation of source and drain doped layers.

[0069] In this embodiment, the groove 130 is formed in the fins 100 on both sides of the gate structure 110 and the sidewall 120.

[0070] In this embodiment, the substrate is used to form a long channel device, and the spacing between adjacent gate structures 110 is large. Therefore, the width of the groove 130 is also large.

[0071] In this embodiment, in the step of forming the groove 130, the cross-section of the groove 130 is a rectangular structure, that is, the bottom surface of the groove 130 is parallel or approximately parallel to the base surface, and the sidewall of the groove 130 is perpendicular or approximately perpendicular to the base surface.

[0072] In this embodiment, the first crystal orientation is <100> Crystal orientation. Specifically, in this embodiment, the substrate used is typically... <100> The substrate has a first crystal orientation, and the bottom surface of the groove 130 is parallel or approximately parallel to the substrate surface. Therefore, the substrate at the bottom of the groove 130 also has a first crystal orientation.

[0073] Accordingly, in this embodiment, since the sidewall of the groove 130 is perpendicular or approximately perpendicular to the substrate surface, the substrate of the sidewall of the groove 130 has a second crystal orientation, which is... <110> Crystal orientation.

[0074] In this embodiment, the step of forming the groove 130 includes: using a dry etching process (e.g., anisotropic dry etching process) to etch the substrate with a portion of the thickness on both sides of the gate structure 110 to form the groove 130. Specifically, a dry etching process is used to etch the fins 100 with a portion of the thickness on both sides of the gate structure 110.

[0075] Dry etching technology is characterized by anisotropic etching, meaning the longitudinal etching rate is greater than the transverse etching rate. This improves the control over the cross-sectional shape of the groove 130, thereby helping to ensure that the cross-sectional morphology of the groove 130 meets the process requirements. Specifically, dry etching technology is beneficial for giving the groove 130 a rectangular cross-sectional morphology.

[0076] refer to Figure 7 An epitaxial process is used to form a source / drain doped layer 200 in the groove 130. The silicon source used in the epitaxial process includes a first silicon source and a second silicon source. The first silicon source is suitable for selective epitaxial growth of the source / drain doped layer 200, and the second silicon source is suitable for increasing the epitaxial growth rate of the source / drain doped layer 200 along the first crystal direction.

[0077] During device operation, the source / drain doped layer 200 serves to provide a carrier source. In this embodiment, the source / drain doped layer 200 also serves to provide stress to the channel, thereby improving carrier mobility.

[0078] In this embodiment, the silicon source used in the epitaxial process includes a first silicon source and a second silicon source. The second silicon source is suitable for increasing the epitaxial growth rate of the source / drain doped layer 200 along the first crystal direction, thereby improving the epitaxial growth rate of the source / drain doped layer 200 at the bottom of the groove 130. Correspondingly, this is beneficial to increasing the thickness of the source / drain doped layer 200 at the bottom of the groove 130, especially increasing the bottom thickness of the source / drain doped layer 200 in long-channel devices. When a source / drain contact plug is subsequently formed on the source / drain doped layer 200 to contact the source / drain doped layer 200, the source / drain contact plug is less likely to penetrate the source / drain doped layer 200. This is beneficial to ensure that at least a portion of the source / drain doped layer 200 is still retained at the bottom of the source / drain contact plug, preventing the source / drain contact plug from contacting the high-resistance region below the source / drain doped layer 200. This is beneficial to improving the contact performance between the source / drain contact plug and the source / drain doped layer 200, reducing the contact resistance, and correspondingly improving the electrical performance of the semiconductor structure, such as increasing the saturation current.

[0079] In particular, in this embodiment, for long-channel devices, the width of the groove 130 is relatively large and the bottom area of ​​the groove 130 is large, making the problem of limited growth of the source / drain doped layer 200 in the groove 130 more obvious. In this embodiment, by using the first silicon source and the second silicon source together as silicon sources, it is beneficial to significantly increase the bottom thickness of the source / drain doped layer 200 of the long-channel device, thereby significantly improving the performance of the long-channel device.

[0080] Furthermore, the first silicon source is suitable for selective epitaxial growth of the source / drain doped layer 200, which helps to ensure that the epitaxial process can meet the requirements of selective epitaxial growth of the source / drain doped layer 200. In this way, while ensuring the selectivity of epitaxial growth of the source / drain doped layer 200, the epitaxial growth rate of the source / drain doped layer 200 at the bottom of the groove 130 is increased, thereby increasing the bottom thickness of the source / drain doped layer 200.

[0081] In this embodiment, the epitaxial process is a selective epitaxial process. The selective epitaxial process utilizes the basic principles of epitaxial growth and the characteristic that silicon is difficult to nucleate into a film on an insulator, thereby enabling epitaxial growth only in specific regions of the semiconductor structure. Specifically, in this embodiment, the exposed silicon in the semiconductor structure is only the bottom surface and sidewalls of the groove 130, thus allowing the epitaxial process to selectively grow within the groove 130.

[0082] Furthermore, this embodiment increases the bottom thickness of the source / drain doped layer 200 by adjusting the silicon source in the epitaxial process, thereby avoiding the need to improve the bottom thickness of the source / drain doped layer 200 by adjusting the gate pitch and gate width (CD). This is beneficial for ensuring that the gate pitch and gate width meet the requirements of the established design rules and improves compatibility.

[0083] Compared to the method of forming source / drain doped regions by ion implantation on the substrate, in this embodiment, the source / drain doped layer 200 is formed in the groove 130 by epitaxial process. This is beneficial for in-situ doping during the epitaxial process, resulting in a source / drain doped layer 200 with a higher doping concentration. At the same time, it is also beneficial to avoid damage to the device caused by ion implantation. In addition, after forming the source / drain doped layer 200, this embodiment usually performs heat treatment to activate the doped ions in the source / drain doped layer 200. Compared with the method of forming source / drain doped regions by ion implantation, the heat treatment in this embodiment does not require additional thermal energy to repair the lattice damaged by ion implantation, which helps to reduce the energy consumption (e.g., temperature, time) of the heat treatment.

[0084] In this embodiment, the first silicon source is dichlorosilane (SiH2Cl2). In the semiconductor field, dichlorosilane can typically achieve selective epitaxial growth under relatively high pressure and low carrier gas volume. Therefore, by using dichlorosilane as the first silicon source, it is beneficial to ensure that the epitaxial process can meet the selective epitaxial requirements of the source / drain doped layer 200.

[0085] Specifically, during the epitaxial process, an etching gas (e.g., HCl) is simultaneously introduced to remove the epitaxial material formed on undesirable areas (e.g., insulating materials). Compared to other types of silicon sources, when dichlorosilane is used as the silicon source, the epitaxial growth rate of silicon is relatively slow, which is beneficial for improving the controllability of epitaxial growth and ensuring that the etching gas can remove the epitaxial material formed on undesirable areas, thereby improving the selectivity of the epitaxial process.

[0086] Furthermore, compared to other types of silicon sources, when using dichlorosilane as a silicon source at relatively high pressure and low carrier gas flow rate, silicon exhibits better performance in the second crystal orientation. <110> The rate of epitaxial growth on the upper surface is greater than that in the first crystal orientation. <100> The growth rate of the source / drain doped layer 200 is greater on the sidewalls of the trench 130 than on the bottom of the trench 130 when the epitaxial process uses dichlorosilane as a single silicon source.

[0087] Therefore, in this embodiment, a second silicon source is added to work together with the first silicon source as a silicon source. The second silicon source is used to increase the growth rate of the source / drain doped layer 200 at the bottom of the groove 130. When the epitaxial process uses only the first silicon source, the bottom thickness T of the source / drain doped layer 200 is easily insufficient; when the epitaxial process uses only the second silicon source, the selectivity of epitaxial growth is easily insufficient to meet the requirements of the source / drain doped layer 200. In this embodiment, the first and second silicon sources are used together as the silicon source for epitaxial growth when forming the source / drain doped layer 200, thereby changing the growth morphology of the source / drain doped layer 200 in the groove 130 while meeting the selective epitaxy requirements, thereby increasing the bottom thickness T of the source / drain doped layer 200.

[0088] In this embodiment, the second silicon source is one or more of silane (SiH4), silane (Si2H6), and propane (Si3H8).

[0089] As an example, the second silicon source is silane. Under certain temperature and pressure conditions, silane is more conducive to silicon deposition than dichlorosilane. <100> Crystalline growth allows for greater thickness of the source / drain doped layer 200 at the bottom of the groove 130 by utilizing silane epitaxy.

[0090] In this embodiment, the epitaxial process is a vapor phase epitaxy process, and the silicon source used is a silicon source gas source.

[0091] In this embodiment, during the step of forming the source / drain doped layer 200 using an epitaxial process, the gas flow rate ratio of the first silicon source and the second silicon source should not be too small or too large. If the gas flow rate ratio of the first silicon source and the second silicon source is too small, there will be a relatively excessive amount of the second silicon source, which can easily reduce the selectivity of epitaxial growth; if the gas flow rate ratio of the first silicon source and the second silicon source is too large, there will be a relatively insufficient amount of the second silicon source, which can easily reduce the improvement effect on the bottom thickness of the source / drain doped layer 200. Therefore, in this embodiment, during the step of forming the source / drain doped layer 200 using an epitaxial process, the gas flow rate ratio of the first silicon source and the second silicon source is 10:1 to 20:1.

[0092] In this embodiment, since both the first silicon source and the second silicon source are used as silicon sources, the total flow rate of the silicon source gas can be appropriately adjusted during the epitaxial process. In this embodiment, the parameters of the epitaxial process include: the total flow rate of the silicon source gas is 100 sccm to 400 sccm.

[0093] In this embodiment, the epitaxial process further includes an impurity source, which is used to dopant ions in the source / drain doped layer 200 during the epitaxial process.

[0094] In this embodiment, when forming an NMOS transistor, the impurity source is an N-type impurity source. In this embodiment, the substrate is used to form the NMOS transistor. Compared to PMOS devices, to achieve a higher doping concentration in the source / drain doped layer 200 of the NMOS transistor, the epitaxial process for forming the source / drain doped layer 200 needs to be performed under relatively higher pressure, lower carrier gas volume, and higher silicon and phosphorus source gas flow rates. Under these conditions, the epitaxial growth rate at the bottom of the groove 130 is significantly limited. Therefore, in this embodiment, utilizing both the first and second silicon sources as silicon sources significantly improves the performance of the NMOS device, especially the performance of the N-type long-channel device.

[0095] In this embodiment, the N-type impurity includes P ions, As ions, or Sb ions.

[0096] As an example, the N-type impurity is a phosphorus ion, and the impurity source is a phosphorus source accordingly.

[0097] Accordingly, in the step of forming the source / drain doped layer, the material of the source / drain doped layer 200 is a silicon-phosphorus layer. In order to obtain a silicon-phosphorus layer with a high concentration of phosphorus ions, the epitaxial process of the source / drain doped layer 200 needs to be carried out under relatively high pressure, low carrier gas flow rate, and high silicon source and phosphorus source gas flow rates. Therefore, this embodiment can significantly improve the growth rate of the silicon-phosphorus layer at the bottom of the groove 130, which in turn helps to significantly increase the thickness of the silicon-phosphorus layer located at the bottom of the groove 130.

[0098] As an example, the phosphorus source is phosphine.

[0099] In other embodiments, when the N-type impurity is another type of ion, the impurity source is a different type of gas source. For example, when the N-type impurity is an As ion, the impurity source is an arsenic source, which includes arsine (AsH3); when the N-type impurity is an Sb ion, the impurity source is an antimony source, which may include trimethylantimony (Sb(CH3)3) and triethylantimony (Sb(C2H5)3).

[0100] In this embodiment, the epitaxial process is a vapor phase epitaxy process; the reaction gases of the epitaxial process include the first silicon source and the second silicon source, phosphorus source gas, carrier gas, and corrosive gas.

[0101] Although the epitaxial process utilizes the characteristic that silicon is difficult to nucleate and form a film on an insulator to achieve selective epitaxy, in the actual epitaxial process, it is still possible to grow a relatively thin epitaxial material on the insulating material. The corrosive gas is used to etch the epitaxial material during the epitaxial process, thereby removing the epitaxial material formed in the undesired area. The epitaxial material located in the groove 130 is relatively thick, and under the action of the corrosive gas, only a small thickness is etched, so that it can be retained as the source and drain doped layer 200.

[0102] In this embodiment, the parameters of the epitaxial process include: a phosphorus source gas flow rate of 500 sccm to 1500 sccm, a process temperature of 600°C to 700°C, a pressure of 100 Torr to 300 Torr, a carrier gas flow rate of 2.5 slm (standard litre per minute) to 10 slm, and a corrosion gas flow rate of 100 sccm to 300 sccm.

[0103] During the epitaxial process, the flow rate of the phosphorus source gas affects the doping concentration of phosphorus ions in the source / drain doped layer 200. Therefore, in order to ensure that the doping concentration of phosphorus ions in the source / drain doped layer 200 meets the process requirements, in this embodiment, the flow rate of the phosphorus source gas is 500 sccm to 1500 sccm.

[0104] During the epitaxial process, the process temperature should not be too low, otherwise it will easily reduce the growth rate of the source / drain doped layer 200; however, the process temperature should not be too high either, otherwise it will easily damage the device and produce side effects. Moreover, excessively high temperatures can also easily lead to a decrease in the concentration of the source / drain doped layer 200, and can also easily lead to a decrease in the selectivity of the epitaxial process. Therefore, in this embodiment, the process temperature of the epitaxial process is 600°C to 700°C.

[0105] During the epitaxial process, the pressure should not be too low, otherwise the growth rate of the source / drain doped layer 200 will be too slow, and the doping concentration of the source / drain doped layer 200 will also be affected. However, the pressure of the epitaxial process should not be too high either, otherwise it will lead to problems such as poor selectivity of epitaxial growth and shortened lifespan of the epitaxial process equipment. Therefore, in this embodiment, the pressure of the epitaxial process is 100 Torr to 300 Torr.

[0106] During the epitaxial process, the carrier gas flow rate should not be too low, otherwise it may lead to poor selectivity in epitaxial growth and reduce the uniformity of epitaxial growth. Conversely, the carrier gas flow rate should not be too high, otherwise it may reduce the proportion of silicon source gas or impurity source in the total reaction gas flow rate, which may affect the epitaxial growth rate or reduce the doping concentration of the source / drain doped layers 200. Therefore, in this embodiment, the carrier gas flow rate is 2.5 slm to 10 slm.

[0107] In this embodiment, nitrogen is used as the carrier gas during the epitaxial process. In other embodiments, hydrogen may also be used as the carrier gas.

[0108] During the epitaxial process, the flow rate of the corrosive gas should not be too low, otherwise it may increase the risk of epitaxial material residue in undesirable areas; however, the flow rate of the corrosive gas should not be too high either, otherwise it may reduce the epitaxial growth rate. Therefore, in this embodiment, the flow rate of the corrosive gas is 100 sccm to 300 sccm. In this embodiment, the corrosive gas is HCl.

[0109] In this embodiment, during the step of forming the source / drain doped layer 200 by setting the epitaxial process parameters within the aforementioned range, the phosphorus ion doping concentration in the source / drain doped layer 200 is 1E21cm⁻¹. -3 up to 5E21cm -3 .

[0110] In this embodiment, in the step of forming the source / drain doped layer 200, the portion of the source / drain doped layer 200 located at the bottom of the groove 130 serves as the bottom doped layer 210.

[0111] In this embodiment, with the epitaxial process parameters set within the aforementioned range, the thickness of the bottom doped layer 210 is one-sixth to one-half the width of the groove 130.

[0112] As an example, the thickness of the bottom doped layer 210 is 15 nm to 40 nm.

[0113] In this embodiment, compared with the prior art, the thickness of the bottom doped layer 210 is twice that of the prior art, thereby significantly increasing the thickness of the bottom doped layer 210.

[0114] In this embodiment, the portion of the source / drain doped layer 200 located at the bottom of the groove 130 serves as a side doped layer 220.

[0115] Reference Figure 8After forming the source / drain doped layer 200, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer 140 on a substrate on the side of the gate structure 110, wherein the interlayer dielectric layer 140 covers the source / drain doped layer 200.

[0116] The interlayer dielectric layer 140 is used to achieve electrical isolation between adjacent devices. Subsequent steps include forming source / drain contact plugs on the source / drain doped layer 200 that are in contact with the top surface of the source / drain doped layer 200. The interlayer dielectric layer 140 is also used to achieve electrical isolation between the source / drain contact plugs and other electrical connection structures.

[0117] The material of the interlayer dielectric layer 140 is an insulating material.

[0118] In this embodiment, the material of the interlayer dielectric layer 140 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0119] Reference Figure 9 In this embodiment, the gate structure 110 is a pseudo-gate structure. Therefore, after forming the interlayer dielectric layer 140, the method for forming the semiconductor structure further includes: removing the gate structure 110 and forming a gate opening (not shown) in the interlayer dielectric layer 140; and forming a metal gate structure 170 in the gate opening.

[0120] The metal gate structure 170 is used as a device gate structure. When the device is in operation, the metal gate structure 170 is used to control the opening and closing of the field-effect conductive channel.

[0121] In this embodiment, the metal gate structure 170 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0122] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer. The high-k gate dielectric layer is made of a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k gate dielectric layer is made of HfO2. In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0123] The work function layer is used to adjust the work function of the metal gate structure 170, thereby regulating the device threshold voltage. When forming a PMOS device, the work function layer is a P-type work function layer, and the material of the P-type work function metal includes one or more of TiN, Ta, TaN, TaSiN, and TiSiN; when forming an NMOS device, the work function layer is an N-type work function layer, and the material of the N-type work function metal includes one or more of TiAl, TaAlN, TiAlN, MoN, TaCN, and AlN.

[0124] The gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In this embodiment, the gate electrode layer is made of W.

[0125] refer to Figures 10 to 11 The method for forming the semiconductor structure further includes: forming a source / drain contact plug 160 on the source / drain doped layer 200 that contacts the top surface of the source / drain doped layer 200.

[0126] The source / drain contact plug 160 is used to realize the electrical connection between the source / drain doped layer 200 and external circuits or other interconnect structures.

[0127] As described above, the semiconductor structure formation method provided in this embodiment is beneficial to increasing the thickness of the source / drain doped layer 200 located at the bottom of the groove 130, especially increasing the bottom thickness of the source / drain doped layer 200 of the long channel device. Therefore, when a source / drain contact plug 160 is formed on the source / drain doped layer 200 to contact the source / drain doped layer 200, the source / drain contact plug 160 is not likely to penetrate the source / drain doped layer 200. This is beneficial to ensure that at least a portion of the thickness of the source / drain doped layer 200 is still retained at the bottom of the source / drain contact plug 160, preventing the source / drain contact plug 160 from contacting the high-resistance region below the source / drain doped layer 200. This is beneficial to improving the contact performance between the source / drain contact plug 160 and the source / drain doped layer 200, reducing the contact resistance, and correspondingly improving the electrical performance of the semiconductor structure, such as increasing the saturation current.

[0128] Specifically, the source / drain doped layer 200 is a highly doped region. Correspondingly, the source / drain doped layer 200 has a high ion concentration and a low resistance. This embodiment helps to ensure that the bottom of the source / drain contact plug 160 still retains at least a portion of the thickness of the source / drain doped layer 200, thereby ensuring that the source / drain contact plug 160 is in contact with the highly doped region. This helps to reduce the contact resistance between the source / drain contact plug 160 and the source / drain doped layer 200, improves the performance of the semiconductor structure, and especially improves the electrical performance of long-channel devices.

[0129] In this embodiment, the source / drain contact plug 160 is made of a conductive material. As an example, the material of the source / drain contact plug 160 is W. In other embodiments, the material of the source / drain contact plug can also be conductive materials such as Al, Cu, Ag, or Au.

[0130] In this embodiment, in order to ensure that the source / drain contact plug 160 can contact the source / drain doped layer 200, the process of forming the source / drain contact plug 160 will also perform over-etching (OE). Accordingly, the source / drain contact plug 160 also penetrates a portion of the thickness of the source / drain doped layer 200.

[0131] In this embodiment, based on the thickness of the bottom doped layer 210 and the amount of over-etching when forming the source / drain contact plug 160, the thickness of the source / drain doped layer 200 at the bottom of the source / drain contact plug 160 is 5nm to 20nm, so that the source / drain doped layer 200 at the bottom of the source / drain contact plug 160 still retains a sufficiently thick source / drain doped layer 200.

[0132] In this embodiment, the step of forming the source / drain contact plug 160 includes: as follows Figure 10 As shown, a contact hole 150 is formed in the interlayer dielectric layer 140 that penetrates the top of the source / drain doped layer 200; as Figure 11 As shown, a source / drain contact plug 160 is formed in the contact hole 150 to contact the source / drain doped layer 200.

[0133] In the step of forming the contact hole 150, in order to ensure that the source / drain doped layer 200 can be exposed, a certain amount of over-etching is also performed. The over-etching amount of the same contact hole etching process is basically the same. In this embodiment, the bottom thickness of the source / drain doped layer 200 is increased, thereby reducing the probability of over-etching through the bottom of the source / drain doped layer 200. This helps to ensure that the bottom of the contact hole 150 still retains a portion of the source / drain doped layer 200, so that the source / drain contact plug 160 stays in the source / drain doped layer 200 and contacts the source / drain doped layer 200.

[0134] In this embodiment, the process for forming the contact hole 150 includes a dry etching process.

[0135] In this embodiment, the process of forming the source / drain contact plug 160 in the contact hole 150 includes one or more of chemical vapor deposition, physical vapor deposition, and electrochemical plating.

[0136] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A gate structure is formed on the substrate; Grooves are formed in the substrates on both sides of the gate structure, and the substrates at the bottom of the grooves have a first crystal orientation; An epitaxial process is used to form a source / drain doped layer in the groove. The silicon source used in the epitaxial process includes a first silicon source and a second silicon source. The first silicon source is different from the second silicon source. The first silicon source is suitable for selective epitaxial growth of the source / drain doped layer, and the second silicon source is suitable for increasing the epitaxial growth rate of the source / drain doped layer along the first crystal direction, so as to increase the thickness of the source / drain doped layer located at the bottom of the groove.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second silicon source is one or more of silane, ethylsilane, and propane.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first silicon source is dichlorosilane.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The epitaxial process is a vapor phase epitaxy process; in the step of forming the source and drain doped layers using the epitaxial process, the gas flow rate ratio of the first silicon source and the second silicon source is 10:1 to 20:

1.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The epitaxial process is a vapor phase epitaxy process; the parameters of the epitaxial process include: the total gas flow rate of the silicon source gas is 100 sccm to 400 sccm.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The epitaxial process also includes an impurity source; when forming an NMOS, the impurity source is an N-type impurity source.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The N-type impurities include P ions, As ions, or Sb ions.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The N-type impurity is a phosphorus ion, and the impurity source is a phosphorus source; in the step of forming the source / drain doped layer, the material of the source / drain doped layer is a phosphorus silicon layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The epitaxial process is a vapor phase epitaxy process, and the reaction gases of the epitaxial process include the first silicon source and the second silicon source, phosphorus source gas, carrier gas and corrosion gas; The parameters of the epitaxial process include: a phosphorus source gas flow rate of 500 sccm to 1500 sccm, a process temperature of 600℃ to 700℃, a pressure of 100 Torr to 300 Torr, a carrier gas flow rate of 2.5 slm to 10 slm, and a corrosion gas flow rate of 100 sccm to 300 sccm.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming the source / drain doped layer, the phosphorus ion doping concentration in the source / drain doped layer is from 1E21cm-3 to 5E21cm-3.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the source / drain doped layer, the portion of the source / drain doped layer located at the bottom of the groove serves as the bottom doped layer, and the thickness of the bottom doped layer is one-sixth to one-half of the groove width.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the source / drain doped layer, the portion of the source / drain doped layer located at the bottom of the groove serves as the bottom doped layer, and the thickness of the bottom doped layer is 15 nm to 40 nm.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: forming a source / drain contact plug on the source / drain doped layer that contacts the top surface of the source / drain doped layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The source / drain contact plug also penetrates a portion of the source / drain doped layer; the thickness of the source / drain doped layer at the bottom of the source / drain contact plug is 5 nm to 20 nm.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the source / drain doped layer and before forming the source / drain contact plug, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on the substrate on the side of the gate structure, wherein the interlayer dielectric layer covers the source / drain doped layer; The step of forming the source / drain contact plug includes: forming a contact hole through the top of the source / drain doped layer into an interlayer dielectric layer; and forming the source / drain contact plug in the contact hole that contacts the source / drain doped layer.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first crystal orientation is <100> Crystal orientation.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate of the groove sidewall has a second crystal orientation, the second crystal orientation being... <110> Crystal orientation.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the groove, the cross-section of the groove is a rectangular structure.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the groove includes: using a dry etching process to etch a portion of the thickness of the substrate on both sides of the gate structure to form the groove.

20. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate, the substrate includes a substrate and fins protruding from the substrate; The gate structure is formed on the substrate and spans the fin, and the gate structure covers a portion of the top and a portion of the sidewalls of the fin. The grooves are formed in the fins on both sides of the gate structure.

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