Clamp for manufacturing semiconductor package and method of manufacturing semiconductor package

Abstract

A clamp for manufacturing a semiconductor package includes a bottom part and an upper part. The bottom part includes a base, a support plate, and at least one elastic connecting member. The support plate is located in a central region of the base. The at least one elastic connecting member is interposed between the support plate and the base. The upper part includes a cap and an outer flange. The cap is located above the support plate when the upper part is disposed on the bottom part. The outer flange is disposed at an edge of the cap and is connected with the cap. The outer flange contacts the base of the bottom part when the upper part is disposed on the bottom part. The cap includes an opening, which is a through hole. A vertical projection of the opening falls entirely on the support plate when the upper part is disposed on the bottom part. Embodiments of the present application also relate to a method of manufacturing a semiconductor package.

Description

Technical Field

[0001] Embodiments of this application relate to fixtures for manufacturing semiconductor packages and methods for manufacturing semiconductor packages. Background Technology

[0002] Semiconductor devices and integrated circuits used in various electronic devices, such as mobile phones and other mobile electronic devices, are typically fabricated on a single semiconductor wafer. The wafer die can be processed and packaged together with other semiconductor devices or dies at the wafer level, and various technologies and applications for wafer-level packaging have been developed. The integration of multiple semiconductor devices has become a challenge in this field. In response to the growing demand for miniaturization, higher speeds, and better electrical performance (e.g., lower transmission and insertion losses), more innovative packaging and assembly technologies are being actively researched. Summary of the Invention

[0003] Some embodiments of this application provide a fixture for manufacturing semiconductor packages, comprising: a bottom component including: a substrate; a support plate located in a central region of the substrate; and at least one resilient connector between the support plate and the substrate; and an upper component including: a cap located on the support plate when the upper component is disposed on the bottom component; and an outer flange disposed at the edge of the cap, connected to the cap, and contacting the substrate of the bottom component when the upper component is disposed on the bottom component, wherein the cap includes an opening that is a through hole, and the vertical projection of the opening falls entirely on the support plate when the upper component is disposed on the bottom component.

[0004] Other embodiments of this application provide a method of manufacturing a semiconductor package, comprising: bonding a semiconductor die to a circuit substrate; placing the circuit substrate having the bonded semiconductor die on a support plate of a bottom member of a jig; placing an upper member of the jig on the bottom member to close the jig, thereby pressing the semiconductor die against the upper member of the jig, wherein the upper member of the jig includes an opening and the back side of the semiconductor die is exposed by the opening; depositing a thermally conductive material on the back side of the semiconductor die within the opening; and removing the upper member to open the jig.

[0005] Other embodiments of this application provide a method of manufacturing a semiconductor package, comprising: disposing an adhesive material on the circuit substrate adjacent to at least one semiconductor die bonded to the circuit substrate; placing a metal overlay on the adhesive material, whereby the metal overlay extends over the semiconductor die; disposing the circuit substrate on a bottom member of a jig; disposing an upper member of the jig over the bottom member of the jig; tightening the upper member of the jig to the bottom member of the jig, thereby pressing the metal overlay against the circuit substrate and the semiconductor die; and curing the adhesive material while the jig presses the metal overlay against the circuit substrate and the semiconductor die. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1M This is a schematic cross-sectional view illustrating a structure produced during the manufacturing process of a semiconductor package according to some embodiments of the present invention.

[0008] Figures 2A to 2G This is a schematic perspective view of a fixture for manufacturing semiconductor packages according to some embodiments of the present invention.

[0009] Figure 3 This is a schematic top view of a clamp disposed on a carrier according to some embodiments of the present invention.

[0010] Figure 4 This is a schematic perspective view of a fixture for manufacturing semiconductor packages according to some embodiments of the present invention.

[0011] Figure 5 This is a schematic perspective view of a fixture for manufacturing semiconductor packages according to some embodiments of the present invention.

[0012] Figures 6A to 6C This is a schematic cross-sectional view illustrating a structure produced during the manufacturing process of a semiconductor package according to some embodiments of the present invention.

[0013] Figure 7 This is a schematic perspective view of a fixture for manufacturing semiconductor packages according to some embodiments of the present invention.

[0014] Figure 8 This is a schematic cross-sectional view of a fixture for manufacturing semiconductor packages according to some embodiments of the present invention.

[0015] Figures 9A to 9C This is a schematic cross-sectional view of some components of a fixture for manufacturing semiconductor packages according to some embodiments of the present invention.

[0016] Figure 10A and Figure 10B This is a schematic cross-sectional view of a fixture for manufacturing semiconductor packages according to some embodiments of the present invention.

[0017] Figures 11A to 11F This is a schematic cross-sectional view of a structure formed during a method of manufacturing a semiconductor package according to some embodiments of the present invention. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as "below," "under," "bottom component," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] Other components and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow testing of 3D packages or 3DIC devices, using probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0021] Figures 1A to 1MThis is a schematic cross-sectional view illustrating the structure produced during the manufacturing process of a semiconductor package SP10 according to some embodiments of the present invention. (Reference) Figure 1A A carrier C is provided. In some embodiments, the carrier C is a glass substrate, a metal plate, a plastic support plate, etc., but other suitable substrate materials can be used, provided that the material can withstand subsequent steps of the process. In some embodiments, a release layer (not shown) may be formed over the carrier C. In some embodiments, the release layer includes a photothermal conversion (LTHC) release layer, which facilitates the peeling of the carrier C from the semiconductor package when required by the manufacturing process.

[0022] In some embodiments, an external redistribution layer 100 is formed on a carrier C. In some embodiments, the external redistribution layer 100 includes dielectric layers 110 stacked alternately with one or more metallization layers 120. In some embodiments, the dielectric layer 110 includes at least two dielectric layers. The metallization layer 120 includes wiring conductive traces sandwiched between pairs of adjacent dielectric layers 110. In some embodiments, the material of the dielectric layer 110 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), any other suitable polymer-based dielectric material, or combinations thereof. The dielectric layer 110 can be formed using suitable manufacturing techniques such as spin coating, chemical vapor deposition (CVD), etc. In some embodiments, the material of the metallization layer 120 includes copper, aluminum, etc. In some embodiments, the material of the metallization layer 120 includes copper. Throughout this specification, the term "copper" is intended to include essentially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium. The metallization layer 120 can be formed, for example, by electroplating, deposition, and / or photolithography and etching. In some alternative embodiments, a higher metallization layer than... Figure 1A The additional metallization layers 120 and additional dielectric layers 110 shown depend on production requirements. In these embodiments, each metallization layer is sandwiched between a pair of consecutive dielectric layers. In some embodiments, the dielectric layer 110 further away from the carrier C is patterned to include openings 130 exposing portions of the metallization layer 120 further away from the carrier C. In some embodiments, this process can be implemented at the reconstructed wafer level, such that multiple packaging units PU are processed in the form of reconstructed wafers. Figure 1A In the cross-sectional view, two packaging units (PUs) are shown for simplicity; however, this is only for illustrative purposes, and the invention is not limited to the number of packaging units (PUs) produced in the reconstructed wafer.

[0023] refer to Figure 1BIn some embodiments, a TIV 210 and a semiconductor bridge 220 are provided on the outer redistribution layer 100. In some embodiments, the TIV 210 can be formed by filling openings in a patterned mask (not shown) with a conductive material. In some embodiments, the conductive material of the TIV 210 includes cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), combinations thereof, or other suitable metallic materials. In some embodiments, the conductive material can be formed by a plating process. The plating process can be, for example, electroplating, electroless plating, immersion plating, etc. In some embodiments, the conductive material can be deposited on a seed layer (not shown). In some embodiments, the formation of the seed layer can be skipped because the metallization layer 120 can serve as a seed for depositing the conductive material. However, the invention is not limited thereto. In some alternative embodiments, other suitable methods can be used to form the TIV 210. For example, prefabricated TIV 210 (e.g., prefabricated conductive pillars) can be picked up and placed onto the outer redistribution layer 100.

[0024] In some embodiments, a semiconductor bridge 220 is disposed on an outer redistribution layer 100 between TIVs 210. The semiconductor bridge 220 is bonded to some wiring conductive traces of the metallization layer 120. In some embodiments, the semiconductor bridge 220 includes a semiconductor substrate 221 having a through-semiconductor via (TSV) 222 and interconnect conductive patterns 223 formed therethrough. A dielectric layer 224 may be disposed at the bottom surface 220b of the semiconductor bridge 220, closer to the outer redistribution layer 100. The semiconductor substrate 221 may be made of a suitable semiconductor material, such as group III-V semiconductor materials of the periodic table. In some embodiments, the semiconductor substrate 221 includes: elemental semiconductor materials, such as silicon or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. The interconnect conductive patterns 223 are in electrical contact with conductive terminals 225 formed on the dielectric layer 224 at the bottom surface 220b of the semiconductor bridge 220. The conductive terminal 225 may be a microbump. For example, the conductive terminal 225 may include a conductive rod and a solder cap disposed on the conductive rod. In some embodiments, the conductive rod may be a copper rod. However, the invention is not limited thereto, and other conductive structures such as solder bumps or metal bumps (e.g., gold bumps) may also be used as the conductive terminal 225. In some embodiments, the semiconductor bridge 220 is configured with its bottom surface 220b pointing toward the outer redistribution layer 100, such that the conductive terminal 225 can be bonded to the metallization layer 120. The conductive terminal 225 may be bonded to the metallization layer 120, for example, by a reflow process.

[0025] In some embodiments, a sealant 230 is formed on the outer redistribution layer 100 to seal the TIV 210 and the semiconductor bridge 220. In some embodiments, the sealant 230 is formed by an overmolding process (e.g., by a compression molding process). The sealant 230 may initially cover the top surface 220t of the TIV 210 and the semiconductor bridge 220. In some embodiments, the material of the sealant 230 includes molding compounds, polymeric materials such as polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), combinations thereof, or other suitable polymer-based dielectric materials. In some embodiments, the sealant 230 may be formed by an overmolding process, initially covering the TIV 210 and the semiconductor bridge 220, and subsequently thinned until the top surface 220t of the TIV 210 and the semiconductor bridge 220 is exposed. For example, a planarization process can be implemented to remove portions of the sealant 230 and (if needed) portions of the semiconductor bridge 220 and / or TIV 210 from the sides of the top surfaces 220t and 210t. In some embodiments, planarizing the sealant 230 includes performing a mechanical polishing process and / or a chemical mechanical polishing (CMP) process. After planarization, the top surfaces 210t of the TIV 210, 220t of the semiconductor bridge 220, and 230t of the sealant 230 can be substantially flush with each other (at substantially the same horizontal height, coplanar with respect to each other). In some embodiments, the TIV 210, semiconductor bridge 220, and sealant 230 are considered portions of the bridging layer 200 stacked on the outer redistribution layer 100. That is, the semiconductor bridge 220 and TIV 210 are embedded in the bridging layer 200.

[0026] refer to Figure 1C An internal redistribution layer 300 is formed on the bridging layer 200. The internal redistribution layer 300 includes a dielectric layer 310, one or more metallization layers 320, and (optionally) under-bump metal 330. The internal redistribution layer 300 may have a structure similar to that previously described for the external redistribution layer 100 and be formed according to a process similar to that previously described for the external redistribution layer 100. In some embodiments, the (uppermost) dielectric layer 310 is patterned to expose the underlying metallization layer 320. Optionally, an under-bump metal 330 may be conformally formed in the openings of the exposed metallization layer 320 of the (uppermost) dielectric layer 310, which may further extend over a portion of the exposed surface of the (uppermost) dielectric layer 310. In some embodiments, the under-bump metal 330 includes multiple stacked layers of conductive material. For example, the under-bump metal 330 may include one or more metal layers stacked on a seed layer. In some embodiments, the outer redistribution layer 100, the bridging layer 200, and the inner redistribution layer 300 can be collectively referred to as a redistribution structure.

[0027] refer to Figure 1D In some embodiments, semiconductor dies 410 and 420 are disposed side-by-side above the internal redistribution layer 300 using a pick-and-place process. In some embodiments, semiconductor dies 410 and 420 are hermetically sealed chips. For example, semiconductor die 410 may include a substrate chip 411 having one or more stacks of chips 413 bonded thereon. Chips 413 may be vertically stacked and interconnected within the stacks via microbumps 415. A sealant 417 may be disposed on the substrate chip 411 to seal the stacks of chips 413 and the microbumps 415. Connectors 419 may be disposed on the substrate chip 411 on the opposite side relative to chips 413. Semiconductor die 420 may have a similar structure to semiconductor die 410, including a substrate chip 421, stacked chips 423 interconnected by microbumps 425, a sealant 427 sealing the chips 423 and the microbumps 425, and connectors 429.

[0028] In some embodiments, semiconductor dies 410, 420 are placed on an inner redistribution layer 300, wherein the sides of substrate chips 411, 421 formed thereon, having connectors 419, 429, point toward the inner redistribution layer 300. The back faces 410r, 420r of the semiconductor dies 410, 420 may include the back face of the topmost chip 413, 423 of the stack and the top surface of the sealant 417, 427. In some embodiments, the semiconductor dies 410, 420 included in a semiconductor package may have different dimensions, include different components, and / or include components of different sizes. For example, the semiconductor dies 410, 420 may differ depending on the number of chips 413, 423 included, the type of stacked chips 413, 423 or substrate chips 411, 421 included, etc. Each semiconductor die 410, 420 may be or include a logic die, such as a central processing unit (CPU) die, a graphics processing unit (GPU) die, a microcontroller unit (MCU) die, an input / output (I / O) die, a baseband (BB) die, or an application processor (AP) die. In some embodiments, one or both of the semiconductor dies 410, 420 may be memory dies.

[0029] In some embodiments, the interconnect conductive pattern 223 of the semiconductor bridge 220 electrically connects semiconductor dies 410 and 420 of the same package unit PU. That is, the electrical connection between semiconductor dies 410 and 420 is established through the internal redistribution layer 300 and the interconnect conductive pattern 223. In some embodiments, the internal redistribution layer 300 does not directly interconnect semiconductor dies 410 and 420. In some embodiments, the semiconductor bridge 220 connects at least one conductive trace of the metallization layer 320 electrically connected to semiconductor die 410 to another conductive trace of the metallization layer 320 connected to semiconductor die 420. In some embodiments, the semiconductor bridge 220 connects one or more conductive traces overlapping semiconductor die 410 to one or more conductive traces overlapping semiconductor die 420. In some embodiments, when there is a gap between adjacent semiconductor dies 410 and 420, the semiconductor bridge 220 extends over the gap. In some embodiments, the semiconductor bridge 220 serves as an interconnect structure for adjacent semiconductor dies 410, 420 and provides a shorter electrical connection path between adjacent semiconductor dies 410, 420.

[0030] In some embodiments, a sealant 500 is formed over the internal redistribution layer 300 to seal semiconductor dies 410, 420. The sealant 500 laterally surrounds the semiconductor dies 410, 420 and also extends into the gaps between the semiconductor dies 410, 420. In some embodiments, the material of the sealant 500 may be selected as described above with respect to sealant 230. The sealant 500 may be formed by a series of molding and planarization steps. For example, the sealant 500 may initially be formed by a molding process (such as compression molding) or a spin coating process to completely cover the semiconductor dies 410, 420. In some embodiments, planarizing the sealant 500 includes performing a mechanical polishing process and / or a chemical mechanical polishing (CMP) process. In some embodiments, a planarization process is performed until the back surfaces 410r, 420r of the semiconductor dies 410, 420 are exposed. In some embodiments, after the planarization process, the back surfaces 410r and 420r of the semiconductor dies 410 and 420 and the top surface 500t of the sealant 500 can be substantially at the same horizontal level (substantially coplanar) along the Z direction.

[0031] refer to Figure 1D and Figure 1EIn some embodiments, the second carrier C1 may be bonded to the side of the top surface 500t of the sealant, the reconstructed wafer may be flipped, and the original carrier C may be removed to expose the outer redistribution layer 100 for further processing. When a release layer (e.g., an LTHC release layer) is included, the release layer may be irradiated with a UV laser, making it easy to peel the carrier C and the release layer from the reconstructed wafer. However, the peeling process is not limited to this, and other suitable peeling methods may be used in some alternative embodiments. Openings may be formed in the outer redistribution layer 100 to expose the metallization layer 120 on opposite sides relative to the TIV 210 and the semiconductor bridge 220. Before providing the connection terminals 600 on the outer redistribution layer 100, an under-bump metallization 140 in contact with the metallization layer 120 may optionally be formed in the openings. The connection terminals 600 may be formed on the under-bump metallization 140 (if included) or on the exposed portion of the metallization layer 120. In some embodiments, connection terminals 600 are formed on the under-bump metal 140, connecting to semiconductor dies 410, 420 via an outer redistribution layer 100, a semiconductor bridge 220 (e.g., through TSV 222), a TIV 210, and an inner redistribution layer 300. In some embodiments, the connection terminals 600 are attached to the under-bump metal 140 with flux. In some embodiments, the connection terminals 600 are controlled-collapse chip-to-chip (C4) bumps. In some embodiments, the connection terminals 600 comprise a conductive material with low resistivity, such as Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof.

[0032] In some embodiments, reference Figure 1E and Figure 1F For example, a dicing step is performed to separate the individual packaged units PU in the plurality of packaged dies 10 by cutting along scribe lines SC arranged between the individual packaged units PU. In some embodiments, the dicing process typically includes a wafer dicing process performed using a rotating blade and / or a laser beam. In some embodiments, after dicing, the carrier C1 is separated from the packaged die 10.

[0033] refer to Figure 1GIn some embodiments, the packaged die 10 can be connected to a circuit substrate 700 via connection terminals 600. For example, the packaged die 10 can be disposed on the circuit substrate 700, and a soldering step can be performed thereon. In some embodiments, the circuit substrate 700 includes a core dielectric layer 710 having conductive traces 720 embedded therein. An upper solder mask 730 can be disposed on an upper side 700a of the circuit substrate 700, on the same side 700a where the packaged die 10 is disposed. The solder mask 730 can extend over the core dielectric layer 710 and can include an opening exposing the outermost conductive traces 720. Connection terminals 600 of the packaged die 10 can be disposed in the openings of the solder mask 730 to contact the conductive traces 720. In some embodiments, an underfill 800 may optionally be provided between the packaged die 10 and the circuit substrate 700. The underfill 800 may laterally wrap around the connection terminals 600, for example, to protect the connection terminals 600 from mechanical stress. In some embodiments, another solder mask 740 may be disposed on the core dielectric layer 710 at the bottom side 700b of the circuit substrate 700.

[0034] In some embodiments, a passive device 900 is provided on the upper side 700a of the circuit substrate 700 next to the packaged die 10. In some embodiments, the passive device 900 is placed above the circuit substrate 700 by a pick-and-place method. In some embodiments, the passive device 900 is a chip integrating passive devices and serves as a capacitor, inductor, resistor, etc. In some embodiments, each passive device 900 may independently serve as a capacitor, inductor, etc., with different capacitance values, resonant frequencies, and / or different sizes. In some embodiments, the passive device 900 is configured to face the circuit substrate 700 so as to connect with the conductive trace 720 of the circuit substrate 700. In some embodiments, the packaged die 10, circuit substrate 700, underfill 800, and passive device 900 may be collectively referred to as package module PM1. The back surfaces 410r and 420r of the semiconductor dies 410 and 420 may be part of the top surface of package module PM1. Although for illustrative purposes Figure 1G Only two passive devices 900 are shown within the packaging module PM1, but the present invention is not limited to the number of passive devices 900 included in the packaging module PM1. In fact, the present invention does not limit the possible structure of the packaging module PM1. Although the packaging module PM1 is shown in the accompanying drawings to illustrate some aspects of the invention, it is not limited to... Figures 1A to 1G The different structures shown for the packaging module PM1 or the packaging modules manufactured using different manufacturing processes are within the scope of this invention.

[0035] Figure 2A This is a schematic perspective view of a fixture 1000A for manufacturing semiconductor packages according to some embodiments of the present invention. Figure 3 This is a schematic top view of a clamp 1000A disposed on a carrier C2 according to some embodiments of the present invention. (Reference) Figure 1H , Figure 2A and Figure 3 In some embodiments, one or more bottom parts 1010 of the clamp 1000A may be arranged, for example, in an array on the carrier C2. It is obvious that, although in Figure 3 Six clamps 1000A are shown, but the invention is not limited to the number of clamps 1000A disposed on the carrier C2. In some embodiments, the clamp 1000A includes a bottom part 1010, a boat-shaped member 1030, and an upper part 1040. The bottom part 1010 of the clamp 1000A may be initially disposed on the carrier C2, and the corresponding boat-shaped member 1030 may be disposed on the bottom part 1010. One or more encapsulation modules PM1 may be disposed on the bottom part 1010 of the clamp 1000A and may be held in place by the boat-shaped member 1030. In some embodiments, the encapsulation module PM1 is disposed on the bottom part 1010 of the clamp 1000A, wherein the circuit substrate 700 points toward the bottom part 1010 of the clamp 1000A. For example, when the encapsulation module PM1 is disposed on the clamp 1000A, the circuit substrate 700 may extend through the boat-shaped member 1030 to contact the bottom part 1010 of the clamp 1000A. Although in Figure 3 Eight packaging modules PM1 are mounted on fixture 1000A, but the number of packaging modules PM1 on each fixture 1000A is not limited. In some alternative embodiments, fewer or more packaging modules PM1 may be mounted on the same fixture 1000A. In some embodiments, Figures 1H to 1M The cross-sectional view can be considered as corresponding to Figure 3 Cut off at the position of line I-I' in the middle.

[0036] In some embodiments, the bottom component 1010 of the clamp 1000A includes a base 1012 and may include one or more platforms 1014 formed in a central region of the base 1012. In some embodiments, the platforms 1014 are raised (along the Z direction) relative to the top surface of the base 1012. In some embodiments, the base 1012 presents a peripheral region surrounding the platforms 1014. In some embodiments, the peripheral region of the base 1012 may be considered as an annular region surrounding the platforms 1014 near the outer edge of the clamp 1000A. In some embodiments, a flat region of the base 1012 between adjacent platforms 1014 may also be considered as part of the peripheral region of the base 1012. In some embodiments, springs 1016 may be disposed on each platform 1014 to support a support plate 1018. In some embodiments, the number of springs 1016 disposed on the platforms 1014 is not particularly limited and may be, for example, between 0 and 200. In some embodiments, an encapsulation module PM1 is disposed on the support plate 1018 above the springs 1016. In some embodiments, the number of platforms 1014 with corresponding support plates 1018 can be as many as the number of packaging modules PM1 to be mounted on the fixture 1000A, such that each packaging module PM1 can have a dedicated platform 1014 and support plate 1018. In some embodiments, magnets 1020 can be embedded in the substrate 1012. For example, magnets 1020 can be fixed in the annular peripheral region of the substrate 1012. In some embodiments, magnets are arranged to be spaced regularly from each other along the edge of the substrate 1012. In some embodiments, one surface of magnet 1020 is exposed corresponding to the top surface of the substrate 1012. However, magnets 1020 can be embedded in the substrate 1012 such that the top surface of the substrate 1012 can be substantially flat except for the platform 1014, even where magnets 1020 are exposed.

[0037] In some embodiments, a boat-shaped member 1030 is disposed on a base member 1010 prior to the placement of the encapsulation module PM1. The boat-shaped member 1030 includes a body 1032 having one or more encapsulation openings 1034 formed therein. The body 1032 may be a monolithic block, such as a parallelepiped block with a rectangular cover area. The encapsulation opening 1034 is a through-hole having a cover area substantially matching the cover area of ​​the encapsulation module PM1. The encapsulation opening 1034 may be slightly larger than the encapsulation module PM1, such that the encapsulation module PM1 can be accommodated within the encapsulation opening 1034 and held in proper position on the base member 1010. In some embodiments, the boat-shaped member 1030 of the fixture 1000A may include as many encapsulation openings 1034 as the platform 1014 and the support plate 1018. For example, the boat-shaped member 1030 shown in the figures includes eight encapsulation openings 1034. In some embodiments, an alignment mechanism may be provided between the base member 1010 and the boat-shaped member 1030. For example, alignment pins 1019 can be formed on the support plate 1018 at one or more corners of the support plate 1018. Alignment holes 1036 can be formed in the body 1032 at selected alignment locations to provide proper alignment between the bottom member 1010 and the boat member 1030 when the alignment pins 1019 are inserted into the alignment holes 1036. Figure 2A In the embodiment, alignment holes 1036 are formed at the four corners of the encapsulation opening 1034, and alignment pins 1019 are formed at the four corners of the support plate 1018. However, the invention is not limited thereto. In some alternative embodiments, fewer alignment pins 1019 (and corresponding alignment holes 1036) may be formed on the support plate 1018. For example, alignment pins 1019 may be formed only at some corners of the support plate 1018 (e.g., at one, two, or three corners). As an example, in Figure 2B A perspective view of a clamp 1000B according to some embodiments of the present invention is shown. The clamp 1000B is similar to... Figure 2A Fixture 1000A. Fixture 1000B and Figure 2A The difference between the clamps 1000A and those 1000A may be that two alignment pins 1019 are formed on the support plate 1018. For example... Figure 2BAs shown, alignment pins 1019 can be formed at different locations on the support plate 1018. In some embodiments, the alignment pins 1019 can be arranged symmetrically on the support plate 1018, such that the boat-shaped member 1030B can be positioned on the base member 1010B according to more than one orientation. For example, the pattern of the alignment pins 1019 and the alignment holes 1036 allows the boat-shaped member 1030B to rotate 180 degrees about each of the X, Y, or Z directions and still be correctly inserted into the base member 1010B. In some embodiments, by employing a configuration with higher symmetry, the automated assembly of the clamp 1000B can be simplified. In some alternative embodiments, the alignment pins 1019 may not be formed on all but only on a few of the support plates 1018. For example, in Figure 2C In the clamp 1000C, the bottom member 1010C includes: a support plate 10181 in which one or more alignment pins 1019 (e.g., one, two, three, four, etc.) are formed; and a support plate 10182 in which no alignment pins are formed. In some embodiments, the alignment pins 1019 may be formed in an asymmetrical or less symmetrical pattern. In some alternative embodiments, the alignment pins 1019 may not be formed on the support plate 1018 but directly on the base 1012. In still some alternative embodiments, alignment pins may be formed on the boat-shaped member 1030D to accommodate alignment holes 1017 (or alignment sleeves, not shown) formed in the base 1012D of the bottom member 1010D, such as... Figure 2D The fixture 1000D is shown. As illustrated in the example above, the present invention does not limit the position and number of alignment pins and corresponding alignment holes.

[0038] In some embodiments, after the packaging module PM1 is placed on the fixture 1000A, the upper component 1040 of the fixture 1000A is placed on the corresponding lower component 1010, for example as... Figure 1I As shown. Reference Figure 1I and Figure 2AThe coverage area of ​​the upper component 1040 of the fixture 1000A substantially matches the coverage area of ​​the corresponding base 1012. The upper component 1040 is placed above the bottom component 1010. In some embodiments, before placing the upper component 1040, the upper component 1040 is vertically aligned with the bottom component 1010, such that the coverage area of ​​the upper component 1040 matches the coverage area of ​​the bottom component 1010. In some embodiments, the upper component 1040 includes a cap 1042 and an outer flange 1044. The outer flange 1044 may be disposed at the periphery of the cap 1042. That is, the outer flange 1044 may be located at the edge of the cap 1042 and protrude toward the base 1012. In some embodiments, the cap 1042 is located on the support plate 1018 and the encapsulation module PM1 disposed thereon. In some embodiments, if the outer flange 1044 extends from the cap 1042 to the base 1012 in a vertical direction (e.g., the Z direction), then the cap 1042 can be considered to extend in orthogonal X and Y directions to cover the coverage area of ​​the base 1012. In some embodiments, the outer flange 1044 and the cap 1042 are integrally formed. That is, the outer flange 1044 and the cap 1042 can be formed as a single component that engages with each other without a clear interface between them.

[0039] In some embodiments, the outer flange 1044 reaches the base 1012 where the magnet 1020 is disposed. In some embodiments, the outer flange 1044 contacts the base 1012 corresponding to an annular peripheral region of the base 1012. In some embodiments, the magnet 1050 is embedded in the outer flange 1044 at a position corresponding to the magnet 1020. In some embodiments, the magnets 1020 and 1050 may be polarized to attract each other. In some embodiments, the upper part 1040 of the clamp 1000A may be secured to the lower part 1010 by the attractive force generated by the magnets 1020 and 1050. In some embodiments, the magnet 1020 may have different polarizations relative to adjacent magnets 1020. For example, given three magnets 1020 arranged in a row, the central magnet 1020 may have opposite polarizations relative to the other two magnets 1020. In the upper component 1040, the three corresponding magnets 1050 can also be polarized, such that the central magnet 1050 is attracted to the central magnet 1020, while the other two magnets 1050 are attracted to the other two magnets 1020. In some embodiments, the polarization patterns of the magnets 1020 and 1050 can be employed so that the magnets 1020 and 1050 hold the upper component 1040 and the lower component 1010 of the clamp 1000A together, and also ensure proper alignment between the upper component 1040 and the lower component 1010. However, the invention is not limited thereto. In some alternative embodiments, the magnets 1020 and 1050 can be omitted, and the upper component 1040 and the lower component 1010 can be held together by other fasteners (e.g., mechanical fasteners such as screws or clamps). For example, in Figure 2EIn the jig 1000E shown, the base 1012E of the bottom member 1010E includes a threaded hole 1020E formed in the annular peripheral region. A screw 1050E extends from above the cap 1042E through the outer flange 1044E of the upper member 1040E to be received in the threaded hole 1020E. Other aspects of the jig 1000E may be similar to those previously described for... Figure 2A As described in the 1000A clamp.

[0040] In some embodiments, the outer flange 1044 extends toward the substrate 1012 and surrounds the platform 1014 and the packaging module PM1 disposed on the substrate 1012. In some embodiments, the outer flange 1044, the cap 1042, and the substrate 1012 define a hollow space for receiving the packaging module PM1. That is, the packaging module PM1 may be contained within a clamp 1000A. In some embodiments, an opening 1046 is formed through the cap 1042 such that the top surface of the packaging module PM1 is at least partially exposed by the clamp 1000A. For example, the back faces 410r and 420r of the semiconductor dies 410 and 420 are exposed through the opening 1046. In some embodiments, the opening 1046 may be formed in the cap 1042 such that the cap 1042 still contacts the packaging module PM1 along the edge of the opening 1046. In some embodiments, the area of ​​the opening 1046 in the XY plane is smaller than the span of the underlying packaging module PM1 and the support plate 1018. In some embodiments, the vertical projection of the area of ​​the opening 1046 may fall entirely on the underlying support plate 1018. In some embodiments, the vertical projection of the area of ​​opening 1046 may fall entirely on the portion of the support plate 1018 exposed by the encapsulation opening 1034. In some embodiments, the encapsulation module PM1 may be pushed against the cap 1042 by the action of the spring 1016, such that the encapsulation module PM1 seals the bottom of opening 1046. For example, sealant 500 may contact and push against the cap 1042 at the edge of opening 1046. However, the invention is not limited thereto. For example, in an encapsulation module (not shown) where the back side of the encapsulation module substantially coincides with the back side of the chip (e.g., corresponding to the back side of a semiconductor substrate), the edge of the back side of the chip may contact the cap 1042 around opening 1046, and the remaining portion of the back side of the chip may be exposed by opening 1046. In some embodiments, the height of the outer flange 1044 may be selected along the Z direction such that the encapsulation module PM1 seals opening 1046. In some embodiments, the spring 1016 may be omitted, and the compressive force on the encapsulation module PM1 may be generated by the relative height of the encapsulation module PM1 and the outer flange 1044. For example, in Figure 2F In the fixture 1000F shown, the support plate 1018 is formed directly on the base 1012F, without... Figure 2AThe clamp 1000A contains a spring or platform. The compressive force on the packaging module can be adjusted by selecting the height of the outer flange 1040F. In some embodiments, the upper part 1040F and the lower part 1010F can be connected by screws 1050F received in threaded holes 1020F formed in the base 1012F to further adjust the compressive force generated by the clamp 1000F. However, the invention is not limited thereto, and in some alternative embodiments, other fasteners (e.g., such as...) can be used. Figure 2A (Magnets, clamps, etc. in the clamp 1000A). In some alternative embodiments, other elastic elements besides springs may be included to push the package module PM1 against the upper component 1040. For example, an elastic pad 1016G, such as a rubber pad, may be disposed between the platform 1014 and the support plate 1018, as... Figure 2G The bottom component 1010G of the fixture 1000G is shown. The elastic properties of the elastic pad 1016G can be selected to allow sufficient thrust to be applied to the package module PM1. In some embodiments, the number of openings 1046 is the same as the number of package modules PM1 surrounding the fixture 1000A, with one opening 1046 for each package module PM1.

[0041] In some embodiments, the bottom component 1010, boat-shaped component 1030, and upper component 1040 of the fixture 1000A can be independently formed from any suitable material. For example, the materials used for the bottom component 1010, boat-shaped component 1030, and upper component 1040 can independently include stainless steel, iron, copper, titanium, other metals, ceramic materials, or any material capable of withstanding subsequent steps in the manufacturing process. In some embodiments, the fixture 1000A may undergo anodizing or passivation treatment (e.g., using nickel) to enhance its environmental resistance and reduce interference in subsequent manufacturing steps.

[0042] In some embodiments, a back-side metallization layer 1110 is formed on the portion of the top surface of the packaging module PM1 exposed by the opening 1046, such as Figure 1JAs shown. In some embodiments, the back metallization layer 1110 may include a thermally conductive material, such as cobalt (Co), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), zirconium (Zr), hafnium (Hf), nickel (Ni), silver (Ag), gold (Au), zinc (Zn), NiV, combinations thereof, or other suitable metallic materials. In some embodiments, the back metallization layer 1110 is formed by a suitable deposition process such as sputtering or evaporation. In some embodiments, because the package module PM1 is pressed against the cap 1042 to seal the opening 1046 (e.g., by the action of the spring 1016), material for the back metallization layer 1110 can be selectively formed on the top surface of the package module PM1 without penetrating and depositing in other areas of the package module PM1 (e.g., on the circuit substrate 700). That is, the upper part 1040 including the opening 1046 can be used as a deposition mask during the formation of the back metallization layer 1110, thereby protecting areas of the package module PM1 where the back metallization layer 1110 is not needed. In some embodiments, material for the back-side metallization layer 1110 may initially be deposited on the upper component 1040 of the fixture 1000A and within the opening 1046. Reference Figure 1J and Figure 1K In some embodiments, the package module PM1 can be recovered from the jig 1000A. For example, the jig 1000A can be opened by removing the upper part 1040, and the package module PM1 can be picked up from the opened jig 1000A. In some embodiments, the package module PM1 can be simply placed on the bottom part 1010 of the jig 1000A without additional adhesive, held in place by the boat-shaped part 1030. In such embodiments, the package module PM1 with the back metallization layer 1110 formed thereon can be easily recovered from the jig 1000A without additional processes to handle adhesive materials, remove protective adhesive, etc. In some embodiments, the package module PM1 can be recovered from the jig 1000A after the back metallization layer 1110 has been formed. The jig 1000A can then be cleaned to remove the material of the back metallization layer 1110 formed on the upper part 1040 for reuse in the manufacture of other package modules PM1.

[0043] refer to Figure 1L In some embodiments, the thermal interface material (TIM) 1120 may then be disposed on the back metallization layer 1110, such as Figure 1KAs shown. In some embodiments, TIM 1120 is an adhesive material. In some embodiments, TIM 1120 includes grease-based materials, phase change materials, gels, adhesives, polymers, metallic materials, or combinations thereof. In some embodiments, TIM 1120 includes lead-tin based solder (PbSn), lead-free solder, silver paste (Ag), gold, tin, gallium, indium, carbon composites, graphite, carbon nanotubes, or other suitable thermally conductive materials. In some embodiments, TIM 1120 is a gel-type material. Depending on the type of material used, TIM 1120 can be formed by deposition, lamination, printing, plating, or any other suitable technique. For example, a gel-type material can be distributed on the packaging module PM1. In some alternative embodiments, TIM 1120 can be a film-type material. For example, TIM 1120 can be a sheet of conductive material (e.g., carbon nanotubes, graphene, or graphite) or a composite film having conductive materials, such as fillers (e.g., powders, sheet particles, nanotubes, fibers, etc.) embedded in a substrate material.

[0044] In some embodiments, adhesive 1200 is disposed on an upper side 700a of circuit substrate 700, near the outer edge 700e of circuit substrate 100. In some embodiments, the outer edge 700e of circuit substrate 700 is a peripheral surface connecting the upper side 700a to the opposite bottom side 700b. In some embodiments, adhesive 1200 forms a frame according to the contour of the outer edge 700e of circuit substrate 700. For example, if circuit substrate 700 has a rectangular coverage area, adhesive 1200 may have a rectangular frame shape. Similarly, if circuit substrate 700 has a circular coverage area, adhesive 1200 may have a circular frame shape. In some embodiments, multiple portions of adhesive 1200 are disposed on circuit substrate 700. That is, the frame formed by adhesive 1200 may be discontinuous, such that gaps exposing circuit substrate 700 exist between continuous portions of adhesive 1200. Encapsulated die 10 and passive device 900 are disposed within the frame formed by adhesive 1200. In some embodiments, adhesive 1200 includes thermosetting adhesives, light-curing adhesives, thermally conductive adhesives, thermosetting resins, waterproof adhesives, laminating adhesives, or combinations thereof. In some embodiments, adhesive 1200 includes a thermally conductive adhesive. In some embodiments, adhesive 1200 includes a metal layer (not shown) on which solder paste (not shown) is deposited. Depending on the type of materials used, adhesive 1200 can be formed by deposition, lamination, printing, plating, or any other suitable technique.

[0045] Figure 1MThis is a cross-sectional view of a semiconductor package SP10 according to some embodiments of the present invention. In some embodiments, manufacturing the semiconductor package SP10 includes providing a metal overlay 1300 on a circuit substrate 700, for example on... Figure 1L The structure is shown. In some embodiments, the metal cover 1300 may be made of a conductive material. For example, the metal cover 1300 may include a metallic material, such as copper. In some embodiments, the metal cover 1300 may be anodized or passivated (e.g., using nickel) before being mounted on the circuit substrate 700 to enhance its environmental resistance. In some embodiments, the coverage area of ​​the metal cover 1300 substantially matches the coverage area of ​​the circuit substrate 700. In some embodiments, the metal cover 1300 includes a cap 1310 and a flange 1320. The metal cover 1300 is placed over the circuit substrate 700. In some embodiments, before placing the metal cover 1300, the metal cover 1300 is vertically aligned with the circuit substrate 700, and the coverage area of ​​the metal cover 1300 matches the coverage area of ​​the circuit substrate 700. The flange 1320 may be disposed at the periphery of the cap 1310. That is, the flange 1320 may be located at the edge of the cap 1310 and protrude toward the circuit substrate 700. In some embodiments, a cover 1310 is disposed over the circuit substrate 100 and the semiconductor package 200. In some embodiments, if a flange 1320 extends from the cover 1310 to the circuit substrate 700 in a vertical direction (e.g., the Z direction), the cover 1310 can be considered to extend in the X and Y directions to cover a coverage area of ​​the circuit substrate 700. In some embodiments, the flange 1320 and the cover 1310 are integrally formed. That is, the flange 1320 and the cover 1310 may be formed as a single component that engages with each other without a clear interface between them. In some embodiments, the flange 1320 extends toward the circuit substrate 700 and surrounds the packaged die 10 and passive device 900. In some embodiments, the flange 1320 reaches the circuit substrate 700 where an adhesive 1200 is disposed. The adhesive 1200 can secure the flange 1320 to the circuit substrate 700. In some embodiments, the adhesive 1200 is disposed on the circuit substrate 700 only where the flange 1320 is expected to contact the circuit substrate 700. In some embodiments, the back metallization layer 1110, TIM 1120, and metal overlay 1300 can facilitate the dissipation of heat generated during use of the semiconductor package SP10.

[0046] As disclosed above, in some embodiments, the packaged die 10 can initially be processed in the form of a reconstructed wafer, and the packaged die 10 can be diced from the reconstructed wafer and connected to the circuit substrate 700 to form a package module PM1 (e.g., as shown above). Figure 1GAfter (as shown), a back-side metallization layer 1110 is formed. Because the back-side metallization layer 1110 has not yet been formed when the packaged die 10 is diced or connected to the circuit substrate 700, the material of the back-side metallization layer 1110 can be selected with less consideration for material behavior during sawing or reflow processes. Therefore, the material of the back-side metallization layer 1110 can be selected from a wider range of candidates, for example, with more consideration for the material's heat dissipation properties. In some embodiments, the material can be selected from a fixture 1000A for semiconductor manufacturing (e.g., Figure 2A As shown in the diagram, the package module PM1 is placed in a fixture, which can be used as a deposition mask during the formation of the back metallization layer 1110. In doing so, the fixture 1000A protects surfaces of the package module PM1 where the back metallization layer 1110 is not desired or necessary to deposit. In some embodiments, the bottom part 1010 and the upper part 1040 of the fixture 1000A can be held together by the action of paired magnets 1020, 1050 (or other mechanical fasteners), allowing the assembly and disassembly of the fixture 1000A to be performed without additional curing, processing, or cleaning steps. Therefore, the manufacturing process of the semiconductor package SP10 can be simplified, thereby increasing process yield and reducing manufacturing costs.

[0047] Figure 4 This is a schematic perspective view of a fixture 1400 for manufacturing semiconductor packages according to some embodiments of the present invention. The fixture 1400 has... Figure 2A It has a similar structure to the 1000A clamp. Figure 2A 1000A clamp and Figure 4 The difference between the 1400 and other fixtures is that... Figure 4 The fixture 1400 is suitable for manufacturing larger semiconductor packages (e.g., semiconductor packages with a larger coverage area). Therefore, while the base components 1410 and 1010 of fixtures 1400 and 1000A have substantially the same coverage area (occupying the same space in the XY plane), fewer (e.g., four instead of eight) but larger platforms 1414 are formed on the base 1412 of fixture 1400. Similarly, the boat-shaped component 1430 has fewer package openings 1434 formed in the body 1432, but the dimensions of the package openings 1434 (e.g., dimensions DX and DY along the X and Y directions) can be larger than... Figure 2A The corresponding size of the encapsulation opening 1034. Similarly, the upper component 1440 includes a smaller but larger opening 1446 formed in the cap 1442. Clamp 1400 and Figure 2AAnother difference between the clamps 1000A and 1400A is that alignment pins 1419 are formed on the base 1412 instead of on the support plate 1418. For example, alignment pins 1419 are located at the four inner corners of the annular peripheral region of the base 1412. Thus, four alignment holes 1436 are formed in the body 1432 of the boat-shaped member 1430. Other aspects of the two clamps 1000A, 1400 can be the same as previously described. For example, an array of springs 1416 is arranged between the platform 1414 and the support plate 1418, and magnets 1420 are embedded in the base 1412, for example in the annular peripheral region, to hold the upper member 1440 and the lower member 1410 together by interacting with magnets 1450 embedded in the outer flange 1444 of the upper member 1440.

[0048] Figure 5 This is a schematic perspective view of a fixture 1500 for manufacturing semiconductor packages according to some embodiments of the present invention. The fixture 1500 has... Figure 2A It has a similar structure to the 1000A clamp. Figure 2A 1000A clamp and Figure 5 The difference between the 1500 and other fixtures is that... Figure 5 The clamp 1500 is suitable for manufacturing a larger semiconductor package (e.g., a large-scale semiconductor package). Therefore, while the bottom components 1510 and 1010 of clamps 1500 and 1000A have substantially the same coverage area (occupying the same space in the XY plane), clamp 1500 includes a single support plate 1515. In some embodiments, the support plate 1515 may optionally be disposed on a spring or other elastic element (not shown), similar to the above description. Figure 2A As discussed with respect to support plate 1018. In some alternative embodiments, support plate 1515 is disposed directly on base 1512, and may even be integrally formed with base 1512. In some embodiments, the bottom component 1510 of clamp 1500 does not include a platform (such as...). Figure 2A Platform 1014). Conversely, the base 1512 has a greater thickness in the annular peripheral region than the corresponding support plate 1515, such that a groove 1518 is formed therein where the support plate 1515 is located. An elastic element (not shown) (when included) is provided at the bottom of the groove 1518 to support the support plate 1515. In some embodiments, the clamp 1500 does not include a boat-shaped element (such as...). Figure 2AThe boat-shaped member 1030). In some embodiments, because the support plate 1515 is located within the recess 1518, the recess 1518 can hold the package module (not shown) in place when it is positioned within the fixture 1500. However, the invention is not limited thereto, and in some alternative embodiments, the fixture 1500 may also include a boat-shaped member (not shown), for example, to adapt the fixture 1500 to manufacture semiconductor packages of different sizes and / or to manufacture multiple semiconductor packages together. In some embodiments, the boat-shaped member may be accommodated in the recess 1518, so that no further alignment mechanism is required. However, the invention is not limited thereto, and in some alternative embodiments, alignment mechanisms (e.g., pins and corresponding holes) may also be included. In some embodiments, the upper member 1540 has a similar structure to the upper member 1040, but for including fewer (e.g., a single) openings 1546 in the cap 1542. In some embodiments, a fixture 1500 may be provided having a plurality of upper components 1440, with openings 1446 of different sizes or numbers, such that package modules of different sizes can be disposed within the fixture 1500, and the openings 1446 remain sealed during the formation of the back-side metallization layer and / or TIM. Other aspects of the fixture 1500 may be similar to those previously described for... Figure 2A As described in the clamp 1000A. For example, a magnet 1520 is embedded in the base 1512, for example in the annular peripheral region, to hold the upper part 1540 and the lower part 1510 together by interacting with a magnet 1550 embedded in the outer flange 1544 of the upper part 1540.

[0049] In some embodiments of the present invention, combinations can be made in various ways. Figures 2A to 2G , Figure 4 and Figure 5 The components of fixtures 1000A-1000G, 1400, and 1500. For example, even when multiple packaging modules are manufactured within the same fixture as discussed for fixtures 1000A-1000G or 1400, support plates 1018 or 1418 can be disposed within recesses of the corresponding bases 1012, 1412, as discussed for fixture 1500. Similarly, even when the support plate is as Figure 5 The clamp 1500 is housed in a recess in the base, and alignment pins such as 1019 or 1419 can also be included in the support plate. As a further example, optional fastening devices can be used for clamps 1400 and 1500, as described above for... Figure 2E and Figure 2F The clamps 1000E and 1000F are described. Furthermore, in any of the clamps 1000A-1000E, 1400, or 1500, the spring can be replaced by other elastic elements, such as... Figure 2G 1016G flexible pads.

[0050] Figures 6A to 6C This is a schematic cross-sectional view of a structure produced during the manufacturing process of a semiconductor package SP20 according to some embodiments of the present invention. Figure 7 This is a schematic perspective view of the 1600A fixture used in manufacturing the SP20 semiconductor package. Figure 6A The image shows a packaging module PM2 with a TIM 1120 formed thereon, according to some embodiments of the present invention. The packaging module PM2 may have the same features as previously described. Figure 1G The encapsulation module PM1 has a similar structure to the one discussed, and can be constructed in accordance with previous references. Figures 1A to 1G The process is similar to that described in some embodiments. Figure 6A The structure can be achieved by forming TIM 1120 on the back surfaces 410r and 420r of semiconductor dies 410 and 420, and by providing adhesive 1200 on the upper side 700a of circuit substrate 700. Figure 1G The structure was obtained.

[0051] In some embodiments, reference Figure 6A and Figure 6B The metal overlay 1300 can be bonded to the circuit substrate 700 using a jig 1600A. For example, the metal overlay 1300 can be disposed on the circuit substrate 700, with the flange 1320 contacting the adhesive 1200. Once the metal overlay 1300 is in contact with the adhesive, the adhesive 1200 can be pre-cured, for example, at a temperature between 50 and 200°C for a period of time, typically between 10 and 900 seconds. In some embodiments, the thickness along the Z-direction of the TIM 1120 can be determined during the pre-curing step. Similarly, the pre-curing step can determine the warpage of the resulting semiconductor package.

[0052] Figure 7 This is a schematic perspective view of fixture 1600A. (Reference) Figure 6B and Figure 7In some embodiments, a package module PM2 having a metal cover 1300 (optionally pre-bonded) thereon can be disposed on a bottom part 1610 of a fixture 1600A. In some embodiments, the bottom part 1610 of the fixture 1600A includes a substrate 1611 and (optionally) a platform 1613. The package module PM2 is disposed in the central region of the substrate 1611 and disposed on the platform 1613 when the platform 1613 is formed. The platform 1613 may be surrounded by an annular peripheral region of the substrate 1611. In some embodiments, the package module PM2 is configured such that a circuit substrate 700 contacts the bottom part 1610. The upper part 1620 of the fixture 1600A can then be placed and secured on the bottom part 1610 of the fixture 1600A in such a way that the package module PM2 and the metal cover 1300 are compressed by the action of the fixture 1600A. In some embodiments, the upper component 1620 includes a cap 1621 located on the encapsulation module PM2 and the metal cover 1300, and an outer flange 1622 disposed on the periphery of the cap 1621. In some embodiments, the outer flange 1622 is located on the annular peripheral region of the base 1611. In some embodiments, the thickness of the outer flange 1622 along the Z direction may be greater than the thickness of the cap 1621 along the Z direction. That is, the upper component 1620 may have a groove corresponding to the cap 1621.

[0053] An array of springs 1623 may be disposed in a recess in the upper component 1620. In some embodiments, one terminal of the spring 1623 is attached to a cap 1621, and the other terminal of the spring 1623 is attached to a rigid plate 1624. In some embodiments, each rigid plate 1624 has approximately 0 to 200 springs 1623. In some embodiments, the rigid plate 1624 has elastic pads 1625 and release layers 1626 sequentially stacked on opposite sides of the springs 1623. In some embodiments, the elastic pads 1625 may comprise thermoplastic resins such as polyetherimide (PEI) or polyetheretherketone (PEEK), (meth)acrylic resin, epoxy resin, combinations thereof, etc. In some embodiments, such as Figure 8 As shown in the fixture 1600B, the resilient pad 1625B may further include a carbon-based filler 16251 dispersed in one or more of the aforementioned resins 16252. In some embodiments, the carbon-based filler 16251 may be any one of diamond, graphite, amorphous carbon, or combinations thereof. In some alternative embodiments, the resilient pad 1625 may be formed of a carbon-based material, for example, comprising graphite, amorphous carbon, or carbon nanotubes. Figure 9AThe image schematically illustrates a rigid plate 1624 and a flexible pad 1625C of a fixture 1600C according to some embodiments of the invention. In the fixture 1600C, the flexible pad 1625C comprises carbon nanotubes 16253 dispersed in a resin 16252, for example, the resin 16252 may be selected from the materials listed above. In some alternative embodiments, the flexible pad 1625D may be formed of carbon nanotubes 16253 attached to the rigid plate 1624 without being dispersed in a resin, such as… Figure 9B The fixture 1600D is shown in the diagram. The carbon nanotube 16253 can be attached to the rigid plate 1624 at one end and to the release layer 1626 at the other end. That is, the carbon nanotube 16253 can be oriented perpendicular to the main extension plane of the rigid plate 1624 and the release layer 1626. In some alternative embodiments, such as... Figure 9C As shown in the clamp 1600E, the elastic pad 1625 can be entirely formed of carbon nanotubes 16253. The carbon nanotubes 16253 can be configured to lie parallel to each other on the main extension plane of the rigid plate 1624, sandwiched between the rigid plate 1624 and the release layer 1626. That is, the carbon nanotubes 16253 can be configured such that their wall length dimension contacts the rigid plate 1624 on one side and the release layer 1626 on the opposite side. In some embodiments, the rigid plate 1624 and the elastic pad 1625 apply pressure to the metal cover 1300 by the action of the spring 1623. In some alternative embodiments, an elastic element other than a spring can be disposed between the rigid plate 1624 and the cap 1621. For example, in Figure 10A In the fixture 1600F shown, the upper component 1620F includes a compressible pad 1623F disposed between the cap 1621 and the rigid plate 1624. In some other alternative embodiments, such as Figure 10BAs shown in the clamp 1600G, a rigid plate 1624 can be directly connected to the cap 1621, and the pressure on the packaging module PM2 can be adjusted by setting the distance between the upper component 1620G and the bottom component 1610. In some embodiments, a release layer 1626 is included to prevent or reduce the possibility of the metal cover 1300 sticking to the elastic pad 1625. In some embodiments, the release layer 1626 may include a polymeric material, such as polyimide, (meth)acrylate, or epoxy resin. In some embodiments, the clamping force can be controlled by selecting a spring 1623 (or pad 1623F) with an appropriate spring (or elasticity) constant. In some embodiments, the rigid plate 1624, the rubber pad 1625, and the release layer 1626 have a coverage area in the XY plane similar to that of the metal cover 1300, such that the upper component 1620 can apply substantially uniform pressure. In some embodiments, the upper component 1620 is tightened to the bottom component 1610, for example, by a threaded screw 1630. In some embodiments, a through-hole 1628 is formed in the outer flange 1622, through which a screw 1630 is inserted. The threaded end of the screw 1630 is received in a threaded blind hole 1615 formed in the annular peripheral region of the bottom member 1610. The head of the screw 1630 is located on the outer flange 1622, and optionally has an intermediate washer 1640. In some embodiments, the washer 1640 prevents the screw 1630 from seizing onto the outer flange 1622 when tightened. The pressure applied by the upper member 1620 on the bottom member 1610 can be set by adjusting the amount of tightening of the screw 1630.

[0054] In some embodiments, alignment and height adjustment mechanisms are provided on the annular peripheral regions of the base 1611 and the outer flange 1622. For example, a height setting sleeve 1617 may be formed around a threaded blind bore 1615 to receive a screw 1630. The height setting sleeve 1617 may be a hollow channel through which the screw 1630 passes before being received in the threaded blind bore 1615. The height setting sleeve 1617 may be made of a rigid material capable of withstanding pressure applied by the upper part 1620 when the screw 1630 is tightened to set the distance between the upper part 1620 and the lower part 1610 of the clamp 1600A. In some embodiments, an alignment pin 1619 is formed on the lower part 1610, for example at a corner of the annular peripheral region. In some embodiments, the alignment pin 1619 may be received in an alignment sleeve 1627 formed on the outer flange 1622. In some alternative embodiments, the alignment pin 1619 may be received in an alignment hole (not shown) formed in the outer flange 1622. In some embodiments, the alignment hole is a blind hole. In some alternative embodiments, the alignment hole is a through hole.

[0055] In some embodiments, the bottom part 1610 and the upper part 1620 of the clamp 1600A can be independently formed from any suitable material. For example, the materials used for the bottom part 1610 and the upper part 1620 can independently include stainless steel, iron, copper, titanium, other metals, ceramic materials, or any material capable of withstanding subsequent steps in the manufacturing process. In some embodiments, the clamp 1600A may undergo anodizing or passivation (e.g., using nickel) to enhance its environmental resistance and reduce interference in subsequent manufacturing steps.

[0056] In some embodiments, the packaging module PM2 and the metal cover 1300 may be held in the clamp 1600A during the curing of the adhesive 1200 and TIM 1120. In some embodiments, during the curing step, pressure is applied to the metal cover 1300 and the packaging module PM2 by the action of the clamp 1600A according to the mechanism described above. In some embodiments, curing may be carried out at a temperature in the range of 125 to 150°C using a clamping force of about 0.1 to 150 kgf. In some embodiments, the spring 1623 may increase the uniformity of the force applied to the metal cover 1300. In some embodiments, the height setting sleeve 1617 may increase the uniformity of the applied force. After curing, the clamp 1600A may be opened, for example, by loosening the screw 1630 and removing the upper part 1620, and the semiconductor package SP 20 may be recovered (e.g., in Figure 6C(As shown in the figure). In some embodiments, by holding the semiconductor package SP20 in the fixture 1600A during the curing step, the contact area between the TIM 1120 and the metal cover 1300 can be increased. In some embodiments, the contact area can be measured, for example, by ultrasonically scanning the semiconductor package SP20. In some embodiments, the increased contact area can enhance the thermal performance of the semiconductor package SP20. For example, the area coverage of the TIM 1120 after bonding the metal cover 1300, as measured by ultrasonic scanning, can increase by approximately 40% compared to the case without using the fixture 1600A. In some embodiments, the area coverage of the TIM 1120 observed when bonding the metal cover 1300 using the fixture 1600A can approach 100%, for example, approximately 99%. In some embodiments, the stability of the semiconductor package SP20 can also be increased. For example, when the fixture 1600A is used during the curing step, less delamination of the TIM 1120 and the metal cover 1300 can be observed after stress testing of the semiconductor package SP20. For example, for semiconductor packages manufactured using fixtures such as jig 1600A, a reduction in area coverage of TIM 1120 can be observed by approximately 3%. In contrast, for packages manufactured without fixtures such as jig 1600A, a reduction in area coverage to approximately 30% of the original value can be observed when performing similar stress tests. In some embodiments, the use of jig 1600A is compatible with automated processes. That is, the assembly and disassembly of jig 1600A can be performed in an automated manner, for example, without human intervention.

[0057] It should be pointed out that, although in Figure 7 The clamp 1600A is shown as designed for a single package module, but the invention is not limited thereto. For example, multiple arrays of springs 1623 or compressible pads 1623F can be attached to the cap 1621, and each array can be connected to a dedicated rigid plate 1624, elastic pads 1625, and release layer 1626. A corresponding platform 1613 can be formed on the substrate 1611. In some embodiments, components of several embodiments described above can be suitably combined. For example, Figures 7 to 9B Any of the flexible pads 1625 and 1625B-1625E can be used as Figure 2G The flexible pad is 1016G. As another example, similar to... Figures 2A to 2G and Figure 4 The jigs 1000A-1000G, 1400, and 1430 (boat-shaped parts not shown) can optionally be included. Figures 7 to 10BThe packaging module is held in place on the bottom part 1610 of the clamps 1600A-1600G. Furthermore, although the invention relates to manufacturing... Figures 7 to 10B The clamps 1600A-1600G are for different semiconductor packages (e.g., Figure 1M Semiconductor package SP10 and Figure 6C SP20) proposed Figures 2A to 2G Fixtures 1000A-1000G and Figure 4 and Figure 5 The fixtures 1400 and 1500 are used, but the invention is not limited thereto. In some embodiments, a first fixture, such as one of fixtures 1000A-1000G, 1400, or 1500, may be used to form a back-side metallization layer 1100 on the top surface of the package module, and a second fixture, such as one of fixtures 1600A-1600G, may be used during the subsequent process of attaching a metal cover.

[0058] Figures 11A to 11F This is a schematic cross-sectional view of a structure formed during a method of manufacturing a semiconductor package SP30 according to some embodiments of the present invention. The manufacturing of the semiconductor package SP30 can be similar to that previously discussed for semiconductor packages SP10 and SP20, and aspects not explicitly addressed below can be considered similar. Figure 11A The package module PM3 is provided. In some embodiments, the package module PM3 may be formed when the packaged die 12 is bonded to the circuit substrate 700. In some embodiments, the packaged die 12 is a chip-on-wafer package, including, for example, semiconductor dies 1710, 1720 bonded to an interposer 1730 via microbumps 1740. Semiconductor dies 1710, 1720 may have the same characteristics as the previously described semiconductor dies 410, 420 (e.g., in...). Figure 1D(As shown in the diagram) A similar structure is implemented and functions similarly to the previously described semiconductor dies 410, 420. In some embodiments, semiconductor dies 1710, 1720 are disposed on an interposer 1730, wherein corresponding contact pads 1713, 1723 and (if included) contact bars 1717, 1727 point toward the interposer 1730. The interposer 1730 may include: an interconnect layer 1731 including a dielectric layer 1732; and a conductive pattern 1733 extending through the dielectric layer 1732. Microbumps 1740 may connect the conductive pattern 1733 to the conductive pads 1713, 1723 or the conductive bars 1717, 1727. The interconnect layer 1731 may be formed on a semiconductor substrate 1735 through which a through-semiconductor via (TSV) 1737 extends. Contact pads 1739 may be disposed on opposite sides of the semiconductor substrate 1735 relative to semiconductor dies 1710, 1720. TSV 1737 can establish an electrical connection between conductive pattern 1733 and contact pad 1739. One or more portions of underfill 1750 can be disposed between semiconductor dies 1710, 1720 and interposer 1730 to surround microbumps 1740. Sealant 1760 can be formed on interposer 1730 to laterally wrap semiconductor dies 1710, 1720 and underfill 1750. In some embodiments, the back surfaces 1710r, 1720r of semiconductor dies 1710, 1720 and the top surface 1760t of sealant 1760 are substantially at the same horizontal level along the Z direction. In some embodiments, interposer 1730 on which semiconductor dies 1710, 1720 are bonded is disposed on circuit substrate 700 and connected to circuit substrate 700, for example, via connection terminal 1800. Underfill 800 can be disposed between packaged die 12 and circuit substrate 700 to surround connection terminal 1800. In some embodiments, the passive device 900 is disposed on the same side 700a of the circuit substrate 700 relative to the packaged die 12.

[0059] exist Figure 11B In this configuration, one or more packaged modules PM3 are disposed within fixture 1000A, similar to the previous reference. Figure 1H and Figure 1IAs discussed above. In short, the package module PM3 is disposed on the bottom part 1010 of the fixture 1000A, for example, one package module PM3 per support plate 1018. The package module PM3 is disposed on the bottom part 1010, with the circuit substrate 700 pointing towards the bottom part 1010. The boat-shaped member 1030 helps to hold the package module PM3 in proper position on the bottom part 1010. Similar to previously described, the upper part 1040 of the fixture 1000A is removably secured to the bottom part 1010, for example, by pairs of magnets 1020, 1050 respectively embedded in the base 1012 of the bottom part 1010 and the outer flange 1044 of the upper part 1040. Also for the package module PM3, the back faces 1710r, 1720r of the semiconductor dies 1710, 1720 are exposed by openings 1046 formed in the cap 1042 of the upper part 1040. In some embodiments, the encapsulation module PM3 presses against the upper component 1040 such that the cap 1042 can contact the sealant 1760 of the encapsulation module PM3 to seal the bottom of the opening 1046.

[0060] exist Figure 11C In the package, a back-side metallization layer 1110 is formed in the opening 1046, on the back surfaces 1710r and 1720r of the semiconductor dies 1710 and 1720, and possibly on the sealant 1760. As previously described, because the package module PM3 is pressed against the cap 1042 to seal the opening 1046 (e.g., by the action of the spring 1016), material for the back-side metallization layer 1110 can be selectively formed on the top surface of the package module PM3 without penetrating and depositing in other areas of the package module PM3 (e.g., on the circuit substrate 700). Reference Figure 11C and Figure 11D In some embodiments, the packaging module PM3 is retrieved from the fixture 1000A, and then the TIM 1120 is disposed on the back metallization layer 1110. In some embodiments, adhesive 1200 is disposed on the upper side 700a of the circuit substrate 700, near the outer edge 700e of the circuit substrate 700.

[0061] exist Figure 11E In this embodiment, a metal overlay 1300 is disposed on a circuit substrate 700, contacting adhesive 1200 and TIM 1120. A package module PM3 with the metal overlay 1300 (potentially pre-bonded) is disposed on a bottom part 1610 of a clamp, such as a clamp 1600A. An upper part 1620 of the clamp 1600A is disposed on the bottom part 1610 to clamp the package module PM3 to apply pressure while curing the adhesive 1200, similar to a previously referenced embodiment. Figure 6B and Figure 6C As described. (Reference) Figure 11FAfter the adhesive 1200 has cured, the semiconductor package SP30 can be recovered from the fixture 1600A.

[0062] It should be pointed out that, although in Figures 11A to 11F The process illustrates fixtures 1000A and 1600A, but the invention is not limited thereto, and any other fixtures according to the invention may be used depending on production requirements.

[0063] According to some embodiments of the invention, a jig for manufacturing a semiconductor package is provided. The jig includes an upper part and a bottom part adapted to house a package manufactured therebetween. When the package is positioned between the parts of the jig, a compressive force is applied to the package. The compressive force can be generated by setting the distance between the upper and bottom parts of the jig, taking into account the dimensions of the package (e.g., height). In some embodiments, an elastic element may be included to press the package against the upper part of the jig. In some embodiments, the compressive force on the package can be used to ensure that openings formed in the upper part are sealed, thereby exposing only the desired surfaces of the package at their bottom. By doing so, the jig can act as a mask during material deposition on the exposed surfaces of the package, while protecting other surfaces. In some embodiments, the compressive force can be applied to the package during curing to ensure satisfactory adhesion between the metal overlay and the thermal interface material disposed on the back side of the package.

[0064] According to some embodiments of the present invention, a jig for manufacturing semiconductor packages includes a bottom component and an upper component. The bottom component includes a substrate, a support plate, and at least one resilient connector. The support plate is located in the central region of the substrate. The at least one resilient connector is located between the support plate and the substrate. The upper component includes a cap and an outer flange. When the upper component is disposed on the bottom component, the cap is located above the support plate. The outer flange is disposed at the edge of the cap and connected to the cap. When the upper component is disposed on the bottom component, the outer flange contacts the substrate of the bottom component. The cap includes an opening, which is a through-hole. When the upper component is disposed on the bottom component, the vertical projection of the opening falls entirely on the support plate.

[0065] According to some embodiments of the present invention, a fixture for manufacturing a semiconductor package includes a bottom component, an upper component, and screws. The bottom component includes a substrate. The substrate has a central region and a peripheral region surrounding the central region. A threaded hole is formed in the peripheral region of the substrate. The upper component includes a cap, at least one spring, and an outer flange. When the upper component is positioned above the bottom component, the cap extends above the central region of the substrate. The at least one spring has a terminal connected to the cap and another terminal connected to a rigid plate. The outer flange is positioned at the edge of the cap. A through-hole is formed in the outer flange. When the upper component is mounted above the bottom component, the screw extends across the outer flange through the through-hole to be tightened into the threaded hole in the bottom component.

[0066] According to some embodiments of the present invention, a method for manufacturing a semiconductor package includes the following steps: A semiconductor die is bonded to a circuit substrate. The circuit substrate having the bonded semiconductor die is placed on a support plate of a bottom member of a clamp. An upper member of the clamp is placed on the bottom member to close the clamp, thereby pressing the semiconductor die against the upper member of the clamp. The upper member of the clamp includes an opening, and the back side of the semiconductor die is exposed through the opening. A thermally conductive material is deposited on the back side of the semiconductor die within the opening. The upper member is removed to open the clamp.

[0067] According to some embodiments of the present invention, a method for manufacturing a semiconductor package includes the following steps: An adhesive material is disposed on a circuit substrate adjacent to at least one semiconductor die bonded to a circuit substrate. A metal overlay is placed on the adhesive material. The metal overlay extends over the semiconductor die. The circuit substrate is disposed on a bottom member of a jig. An upper member of the jig is disposed above the bottom member of the jig. The upper member of the jig is tightened to the bottom member of the jig. By doing so, the metal overlay is pressed against the circuit substrate and the semiconductor die. The adhesive material is cured while the jig presses the metal overlay against the circuit substrate and the semiconductor die.

[0068] Some embodiments of this application provide a jig for manufacturing semiconductor packages, comprising: a bottom component including: a substrate; a support plate located in a central region of the substrate; and at least one resilient connector between the support plate and the substrate; and an upper component including: a cap located above the support plate when the upper component is disposed on the bottom component; and an outer flange disposed at the edge of the cap, connected to the cap, and contacting the substrate of the bottom component when the upper component is disposed on the bottom component, wherein the cap includes an opening, the opening being a through-hole, and the vertical projection of the opening falls entirely on the support plate when the upper component is disposed on the bottom component. In some embodiments, the bottom component further includes an alignment pin, and the jig for semiconductor manufacturing further includes a boat-shaped member having a package opening and an alignment hole formed therethrough, wherein when the boat-shaped member is disposed on the bottom component, the alignment pin is received in the alignment hole, and the package opening exposes at least a portion of the support plate. In some embodiments, the vertical projection of the opening falls entirely on the portion of the support plate exposed by the package opening. In some embodiments, the at least one resilient connector is one of an array of resilient connectors, and the resilient connector is a spring. In some embodiments, the bottom member has a platform formed in a central region of the base, and the at least one resilient connector contacts the platform on one side and the support plate on the opposite side. In some embodiments, the support plate is one of a plurality of support plates located in the central region of the base, and the opening of the cap is one of a plurality of openings formed in the cap, and when the upper member is disposed on the bottom member, the vertical projection of the opening of the cap falls entirely on the corresponding lower support plate. In some embodiments, the clamp further includes: a first magnet fixed in the base and having a surface exposed at the top surface of the base; and a second magnet fixed in the outer flange and having a surface exposed at the bottom surface of the outer flange, wherein when the upper member is disposed on the bottom member, the second magnet overlaps with the first magnet. In some embodiments, the support plate and the at least one resilient connector are disposed in a groove in the base.

[0069] Other embodiments of this application provide a method of manufacturing a semiconductor package, comprising: bonding a semiconductor die to a circuit substrate; placing the circuit substrate having the bonded semiconductor die on a support plate of a bottom member of a jig; placing an upper member of the jig on the bottom member to close the jig, thereby pressing the semiconductor die against the upper member of the jig, wherein the upper member of the jig includes an opening and the back side of the semiconductor die is exposed by the opening; depositing a thermally conductive material on the back side of the semiconductor die within the opening; and removing the upper member to open the jig. In some embodiments, the thermally conductive material comprises a metallic material. In some embodiments, the thermally conductive material is further deposited on the upper member of the jig. In some embodiments, the manufacturing method further comprises: placing a metal boat-shaped member on the bottom member of the jig, wherein the metal boat-shaped member includes an opening exposing the support plate of the bottom member, and wherein the circuit substrate having the bonded semiconductor die is disposed on the support plate within the opening of the boat-shaped member. In some embodiments, the manufacturing method further includes: depositing a thermal interface material on the thermally conductive material; and bonding a metal overlay to the circuit substrate, wherein the metal overlay contacts the thermal interface material. In some embodiments, bonding the metal overlay to the circuit substrate includes: depositing an adhesive on the circuit substrate; placing the metal overlay on the adhesive; placing the circuit substrate having the bonded semiconductor die, the metal overlay, and the adhesive in a second clamp; tightening the second clamp to apply pressure to the metal overlay in the stacking direction of the metal overlay and the circuit substrate; and performing a heating step to cure the adhesive.

[0070] Some embodiments of this application provide a method of manufacturing a semiconductor package, comprising: disposing an adhesive material on the circuit substrate adjacent to at least one semiconductor die bonded to the circuit substrate; placing a metal overlay on the adhesive material, whereby the metal overlay extends over the semiconductor die; disposing the circuit substrate on a bottom member of a jig; disposing an upper member of the jig over the bottom member of the jig; tightening the upper member of the jig to the bottom member of the jig, thereby pressing the metal overlay against the circuit substrate and the semiconductor die; and curing the adhesive material while the jig presses the metal overlay against the circuit substrate and the semiconductor die. In some embodiments, the manufacturing method further comprises: pre-curing the adhesive material before disposing the circuit substrate in the jig. In some embodiments, the upper member of the jig includes a rigid pad, a flexible pad, and a release layer stacked sequentially above a cap, wherein the release layer contacts the metal overlay when the upper member of the jig is disposed on the bottom member of the jig. In some embodiments, the upper component of the clamp further includes a resilient connector disposed between the cap and the rigid pad. In some embodiments, the resilient pad includes carbon nanotubes contacting the rigid pad and the release layer on opposite sides. In some embodiments, the manufacturing method further includes forming a thermally conductive material on the back side of the die before placing the metal overlay on the circuit substrate, wherein the metal overlay contacts the thermally conductive material.

[0071] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A fixture for manufacturing semiconductor packages, comprising: The bottom component includes: a base; a support plate located in the central region of the base; and at least one resilient connector located between the support plate and the base; and The upper component includes: a cap, which, when disposed on the bottom component, is located above the support plate; and an outer flange, disposed at the edge of the cap, connected to the cap, and contacting the base of the bottom component when the upper component is disposed on the bottom component. The cap includes an opening, which is a through hole, and when the upper component is mounted on the lower component, the vertical projection of the opening falls entirely on the support plate. The encapsulation module is pressed against the cap to seal the opening through the elastic connector, and the top surface of the encapsulation module is exposed through the opening.

2. The clamp according to claim 1, in, The bottom component also includes alignment pins, and The fixture for semiconductor manufacturing also includes a boat-shaped member having a packaging opening and an alignment hole formed therethrough. When the boat-shaped component is disposed on the bottom component, the alignment pin is accommodated in the alignment hole, and the encapsulation opening exposes at least a portion of the support plate.

3. The clamp according to claim 2, wherein, The vertical projection of the opening falls entirely on the portion of the support plate exposed by the encapsulation opening.

4. The clamp according to claim 1, wherein, The at least one elastic connector is one of an array of elastic connectors, and the elastic connector is a spring.

5. The clamp according to claim 1, wherein, The bottom component has a platform formed in the central region of the base, and the at least one elastic connector contacts the platform on one side and the support plate on the opposite side.

6. The clamp according to claim 1, wherein, The support plate is one of a plurality of support plates located in the central region of the base, and the opening of the cap is one of a plurality of openings formed in the cap, and when the upper component is disposed on the lower component, the vertical projection of the opening of the cap falls entirely on the corresponding lower support plate.

7. The clamp according to claim 1, further comprising: A first magnet is fixed in the substrate and has a surface exposed at the top surface of the substrate; as well as The second magnet is fixed in the outer flange and has a surface exposed at the bottom surface of the outer flange. When the upper component is disposed on the lower component, the second magnet overlaps with the first magnet.

8. The clamp according to claim 1, wherein, The support plate and the at least one elastic connector are disposed in the groove of the base.

9. A method for manufacturing a semiconductor package, comprising: Bonding the semiconductor die to the circuit substrate; The circuit substrate having the semiconductor die with the said connection is placed on the support plate of the bottom part of the fixture; The upper part of the clamp is placed on the lower part to close the clamp, thereby pressing the semiconductor die against the upper part of the clamp, wherein the upper part of the clamp includes an opening and the back side of the semiconductor die is exposed by the opening; Using the upper component of the fixture as a mask, thermally conductive material is deposited on the back side of the semiconductor die within the opening; and Remove the upper component to open the clamp.

10. The manufacturing method according to claim 9, wherein, The thermally conductive material includes metallic materials.

11. The manufacturing method according to claim 9, wherein, The thermally conductive material is further deposited on the upper component of the fixture.

12. The manufacturing method according to claim 9, further comprising: Place the metal boat-shaped piece on the bottom part of the clamp. The metal boat-shaped member includes an opening in the support plate that exposes the bottom component, and the circuit substrate having the joined semiconductor die is disposed on the support plate within the opening of the boat-shaped member.

13. The manufacturing method according to claim 9, further comprising: A thermal interface material is disposed on the thermally conductive material; as well as A metal overlay is bonded to the circuit substrate, wherein the metal overlay contacts the thermal interface material.

14. The manufacturing method according to claim 13, wherein, Bonding the metal overlay to the circuit substrate includes: An adhesive is applied to the circuit substrate; Place the metal covering onto the adhesive; The circuit substrate having the semiconductor die with the said joint, the metal cover and the adhesive is disposed in the second fixture; Tighten the second clamp to apply pressure to the metal cover in the stacking direction of the metal cover and the circuit substrate; and A heating step is performed to cure the adhesive.

15. A method for manufacturing a semiconductor package, comprising: An adhesive material is disposed on the circuit substrate adjacent to at least one semiconductor die bonded to the circuit substrate; A metal overlay is placed on the adhesive material, whereby the metal overlay extends over the semiconductor die; The circuit substrate is mounted on the bottom component of the fixture; The upper part of the clamp is positioned above the lower part of the clamp; Tighten the upper part of the clamp to the bottom part of the clamp, thereby pressing the metal cover against the circuit substrate and the semiconductor die; as well as The adhesive material is cured while the clamp presses the metal cover against the circuit substrate and the semiconductor die. The upper component of the clamp has a rigid plate, which acts on the metal cover through an elastic element.

16. The manufacturing method according to claim 15, further comprising: The adhesive material is pre-cured before the circuit substrate is placed in the fixture.

17. The manufacturing method according to claim 15, wherein, The upper component of the clamp includes a rigid plate, a resilient pad, and a release layer stacked sequentially above the cap, wherein the release layer contacts the metal cover when the upper component of the clamp is disposed on the bottom component of the clamp.

18. The manufacturing method according to claim 17, wherein, The elastic element is a spring or a compressible pad.

19. The manufacturing method according to claim 17, wherein, The elastic pad includes carbon nanotubes that contact the rigid plate and the release layer on opposite sides.

20. The manufacturing method according to claim 15, further comprising: Before placing the metal overlay on the circuit substrate, a thermally conductive material is formed on the back side of the die, wherein the metal overlay contacts the thermally conductive material.

Images