Semiconductor element with programmable cell and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device having a programmable cell and a method of fabricating the semiconductor device. The semiconductor device has a substrate, a lower conductive layer disposed in the substrate, an isolation layer disposed on the substrate, a first conductive layer disposed on the isolation layer and above the lower conductive layer, a second conductive layer disposed on the isolation layer and above the lower conductive layer and spaced apart from the first conductive layer, a conductive plug electrically coupled to the lower conductive layer, and an upper conductive layer electrically coupled to the first conductive layer and the second conductive layer. The first conductive layer has a first work function, the second conductive layer has a second work function, and the second work function is different from the first work function. The lower conductive layer, the isolation layer, the first conductive layer, and the second conductive layer together configure a programmable cell.

Description

[0001] CROSS-REFERENCE

[0002] This disclosure claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 149,032, filed January 14, 2021, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor device and a method of fabricating the semiconductor device. In particular, the present disclosure relates to a semiconductor device having a programmable cell and a method of fabricating the semiconductor device having the programmable cell. BACKGROUND

[0004] Semiconductor devices are used in different electronic applications, such as personal computers, cell phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually reduced to meet the increasing demand for computing power. However, during the process of reducing the size, different problems are increased, and such problems continue to increase in number and complexity. Therefore, there are still challenges in achieving improved quality, yield, performance, and reliability, as well as reducing complexity.

[0005] The above description of background art is provided merely for generally presenting the technological background of the present disclosure and does not admit that any of the above description of background art discloses the subject matter of the present disclosure, forms the prior art of the present disclosure, and any of the above description of background art should not be considered as a part of the present disclosure. SUMMARY

[0006] One embodiment of the present disclosure provides a semiconductor device having a substrate, a lower conductive layer disposed in the substrate, an isolation layer disposed on the substrate, a first conductive layer disposed on the isolation layer and above the lower conductive layer, a second conductive layer disposed on the isolation layer and above the lower conductive layer and spaced apart from the first conductive layer, a conductive plug electrically coupled to the lower conductive layer, and an upper conductive layer electrically coupled to the first conductive layer and the second conductive layer. The first conductive layer has a first work function, the second conductive layer has a second work function, and the second work function is different from the first work function. The lower conductive layer, the isolation layer, the first conductive layer, and the second conductive layer together configure a programmable cell.

[0007] In some embodiments, the first conductive layer and the second conductive layer comprise doped polysilicon, doped polygermanium, or a combination thereof, and the first conductive layer and the second conductive layer have the same electrical type.

[0008] In some embodiments, the lower conductive layer comprises doped silicon, doped germanium, doped silicon germanium, or a combination thereof, and the lower conductive layer has an electrical type that is the same as the first conductive layer and the second conductive layer.

[0009] In some embodiments, the semiconductor element further comprises a well region disposed in the substrate and surrounding the lower conductive layer. The well region has an electrical type that is opposite to the lower conductive layer.

[0010] In some embodiments, the semiconductor element further comprises a plurality of auxiliary layers covering the first conductive layer and the second conductive layer. The plurality of auxiliary layers comprises titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

[0011] In some embodiments, the semiconductor element further comprises a plurality of gap spacers disposed on sidewalls of the first conductive layer and disposed on sidewalls of the second conductive layer.

[0012] In some embodiments, the lower conductive layer comprises tungsten, aluminum, titanium, copper, or a combination thereof.

[0013] In some embodiments, the first conductive layer and the second conductive layer comprise different materials, the first conductive layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, platinum, or a combination thereof, and the second conductive layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, platinum, or a combination thereof.

[0014] Another embodiment of the present disclosure provides a semiconductor element having a substrate; a lower conductive layer disposed in the substrate; a first gate structure comprising a first gate dielectric layer disposed on the lower conductive layer, a first work function layer disposed on the first gate dielectric layer, and a first fill layer disposed on the first work function layer, wherein the first work function layer has a first work function; a second gate structure comprising a second gate dielectric layer disposed on the lower conductive layer and spaced apart from the first gate dielectric layer, a second work function layer disposed on the second gate dielectric layer, and a second fill layer disposed on the second work function layer, wherein the second work function layer has a second work function; a conductive plug electrically coupled to the lower conductive layer; and an upper conductive layer electrically coupled to the first gate structure and the second gate structure. The second work function is different from the first work function. The lower conductive layer, the spacer layer, the first gate structure, and the second gate structure together configure a programmable cell.

[0015] In some embodiments, the first gate dielectric layer and the second gate dielectric layer have the same thickness.

[0016] In some embodiments, the semiconductor element further includes a plurality of gap sub-elements disposed on both sides of the first gate structure and on both sides of the second gate structure.

[0017] In some embodiments, the semiconductor element further includes a first wetting layer disposed between the first work function layer and the first fill layer. The first wetting layer includes titanium, tantalum, nickel, or cobalt.

[0018] In some embodiments, the semiconductor element further includes a first barrier layer disposed between the first wetting layer and the first fill layer. The first barrier layer includes titanium nitride, tantalum nitride, or a combination thereof.

[0019] In some embodiments, the first gate dielectric layer and the second gate dielectric layer have a U-shaped cross-sectional profile.

[0020] In some embodiments, the lower conductive layer includes doped silicon, doped germanium, doped silicon germanium, or a combination thereof.

[0021] In some embodiments, the lower conductive layer includes tungsten, aluminum, titanium, copper, or a combination thereof.

[0022] Another embodiment of the present disclosure provides a semiconductor element having a substrate; a lower conductive layer disposed in the substrate; an isolation layer disposed on the substrate; a first gate structure disposed on the isolation layer and over the lower conductive layer, and including a first work function layer and a first fill layer; a second gate structure disposed on the isolation layer, over the lower conductive layer, and spaced apart from the first gate structure, and including a second work function layer and a second fill layer; a conductive plug electrically coupled to the lower conductive layer; and an upper conductive layer electrically coupled to the first gate structure and the second gate structure. The first work function layer has a first work function. The second work function layer has a second work function different from the first work function. The lower conductive layer, the isolation layer, the first gate structure, and the second gate structure together configure a programmable cell.

[0023] Another embodiment of the present disclosure provides a method of fabricating a semiconductor element, including providing a substrate; forming a lower conductive layer in the substrate; forming an isolation layer on the substrate; forming a first conductive layer on the isolation layer and over the lower conductive layer, wherein the first conductive layer has a first work function; and forming a second conductive layer on the isolation layer and over the lower conductive layer, and spaced apart from the first conductive layer, the second conductive layer having a second work function different from the first work function. The lower conductive layer, the isolation layer, the first conductive layer, and the second conductive layer together configure a programmable cell.

[0024] In some embodiments, the steps of forming the first conductive layer and forming the second conductive layer include forming a first intermediate conductive layer and a second intermediate conductive layer on the isolation layer; forming a first mask layer to cover the second intermediate conductive layer and expose the first intermediate conductive layer; performing a first implantation process to convert the first intermediate conductive layer into the first conductive layer; removing the first mask layer; forming a second mask layer to cover the first conductive layer and expose the second intermediate conductive layer; performing a second implantation process to convert the second intermediate conductive layer into the second conductive layer; and removing the second mask layer. The first implantation process and the second implantation process are performed with different doping concentrations.

[0025] In some embodiments, the lower conductive layer, the first conductive layer, and the second conductive layer have the same electrical type.

[0026] Due to the design of the semiconductor element of the present disclosure, after a programming process, the resistance of the programmable cell can be fine-tuned by controlling the applied programming voltage. In addition, various programming voltages can be selected and applied to program the programmable cell. Furthermore, the programmable cell can be programmed by a relatively small (or weak) voltage. Therefore, more surface area can be provided for other functional elements, such as logic functional elements.

[0027] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter. The present disclosure is to be considered as including all such additional technical features and advantages from the following detailed description as well as from the appended claims. It is to be understood that the features of the present disclosure can be utilized in a wide variety of embodiments and that the present disclosure can be practiced in a wide variety of configurations without departing from the scope of the present disclosure. It should be further understood that various changes in the details of the construction and the arrangement of parts can be made without departing from the scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0028] The disclosed subject matter will become more fully understood from the detailed description and the accompanying drawings, wherein like elements are referred to by like reference numerals.

[0029] FIG. 1 is a flowchart illustrating a method of fabricating a semiconductor element according to an embodiment of the present disclosure.

[0030] FIGS. 2-8 is a cross-sectional view illustrating a fabrication process of a semiconductor element according to an embodiment of the present disclosure.

[0031] FIGS. 9-13 is a cross-sectional view illustrating various semiconductor elements according to some embodiments of the present disclosure.

[0032] FIG. 14 is a flowchart illustrating a method of manufacturing a semiconductor element according to another embodiment of the present disclosure.

[0033] FIGS. 15-28 is a cross-sectional view illustrating a manufacturing flow of a semiconductor element according to another embodiment of the present disclosure.

[0034] FIG. 29 and FIG. 30 is a cross-sectional view illustrating a semiconductor element according to some embodiments of the present disclosure.

[0035] Explanation of Reference Numerals:

[0036] 1A: Semiconductor element

[0037] 1B: Semiconductor element

[0038] 1C: Semiconductor element

[0039] 1D: Semiconductor element

[0040] 1E: Semiconductor element

[0041] 1F: Semiconductor element

[0042] 1G: Semiconductor element

[0043] 1H: Semiconductor element

[0044] 1I: Semiconductor element

[0045] 10: Manufacturing method

[0046] 101: Substrate

[0047] 103: Lower conductive layer

[0048] 105: Isolation layer

[0049] 107: Conductive plug

[0050] 109: Conductive via

[0051] 111: Upper conductive layer

[0052] 113: Gap sub

[0053] 115: Interlayer dielectric layer

[0054] 117: Interlayer dielectric layer

[0055] 121: Interlayer dielectric layer

[0056] 123: Auxiliary layer

[0057] 125: Well region

[0058] 20: Manufacturing method

[0059] 200: first gate structure

[0060] 201: first conductive layer

[0061] 203: first gate dielectric layer

[0062] 205: first work function layer

[0063] 207: first fill layer

[0064] 209: first wetting layer

[0065] 211: first barrier layer

[0066] 300: second gate structure

[0067] 301: second conductive layer

[0068] 303: second gate dielectric layer

[0069] 305: second work function layer

[0070] 307: second fill layer

[0071] 309: second wetting layer

[0072] 311: second barrier layer

[0073] 400: third gate structure

[0074] 401: third conductive layer

[0075] 403: third gate dielectric layer

[0076] 405: third work function layer

[0077] 407: third fill layer

[0078] 409: third wetting layer

[0079] 411: third barrier layer

[0080] 601: intermediate conductive layer

[0081] 603: intermediate conductive layer

[0082] 605: intermediate conductive layer

[0083] 607: mask layer

[0084] 609: mask layer

[0085] 611: mask layer

[0086] 613: dummy conductive layer

[0087] 615: hard mask layer

[0088] 617: dielectric material

[0089] 619: first work function material

[0090] 621: second work function material

[0091] 623: third work function material

[0092] 625: fill material

[0093] 627: mask layer

[0094] 629: mask layer

[0095] 631: mask layer

[0096] 701: first trench

[0097] 703: second trench

[0098] 705: third trench

[0099] IMP1: first implant process

[0100] IMP2: second implant process

[0101] IMP3: third implant process

[0102] S11: step

[0103] S13: step

[0104] S15: step

[0105] S17: step

[0106] S21: step

[0107] S23: step

[0108] S25: step

[0109] S27: step

[0110] S29: step

[0111] Z: direction DETAILED DESCRIPTION

[0112] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0113] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0114] It should be understood that when a component is formed on, connected to, and / or coupled to another component, it may include embodiments in which these components are in direct contact, and may also include embodiments in which additional components are formed between these components so that these components are not in direct contact.

[0115] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0116] Unless otherwise indicated herein, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, terms such as "same," "equal," "planar," or "coplanar" as used herein do not necessarily mean an exact, identical orientation, layout, location, shape, size, amount, or other measure, but rather mean within acceptable variation, including nearly identical orientation, layout, location, shape, size, amount, or other measure, which can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar can be exact, identical, equal, or planar, or can be within acceptable variation, including nearly identical, equal, or planar, which can occur, for example, due to manufacturing processes.

[0117] In the present disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are included in the range of semiconductor devices.

[0118] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the opposite direction of the Z-direction arrow.

[0119] It should be understood that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion, deposition, growing, implantation, photolithography, dry etching, and wet etching.

[0120] FIG. 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. FIGS. 2-8 This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0121] Please refer to FIG. 1 and FIG. 2 In step S11, a substrate 101 is provided, and a conductive layer 103 may be formed in the substrate 101.

[0122] Please refer to FIG. 2 The substrate 101 may be a bulk semiconductor substrate, a multilayer or gradient substrate, or the like. For example, the substrate 101 may contain a semiconductor material, such as an elemental semiconductor, a compound or alloy semiconductor, or a combination thereof; the elemental semiconductor is such as silicon or germanium; the compound or alloy semiconductor is such as silicon carbide, silicon germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, indium aluminum arsenide, indium gallium arsenide, indium arsenide, indium gallium phosphide, indium phosphide, indium antimonide, or indium gallium arsenide phosphide. The substrate 101 may be doped or undoped.

[0123] Please refer to FIG. 2 The lower conductive layer 103 may be formed in the substrate 101, and the upper surface of the lower conductive layer 103 may be substantially coplanar with the upper surface of the substrate 101. In some embodiments, the lower conductive layer 103 may define an operating region of a programmable unit.

[0124] In some embodiments, the fabrication technique of the lower conductive layer 103 can include an implantation process. That is, the lower conductive layer 103 can be converted from a portion of the substrate 101. The dopant(s) of the implantation process can include p-type impurities (dopants) or n-type impurities (dopants). The p-type impurities can be added to an intrinsic semiconductor to create a deficiency of valence electrons. In a silicon-containing substrate, the p-type dopants, i.e., the impurities, include boron, aluminum, gallium, and indium, but are not limited thereto. The n-type impurities are added to an intrinsic semiconductor to contribute free electrons to the intrinsic semiconductor. In a silicon-containing substrate, the n-type dopants, i.e., the impurities, include antimony, arsenic, and phosphorus, but are not limited thereto. In some embodiments, the doping concentration of the lower conductive layer 103 can be between about 1E19 atoms / cm 3 and about 1E21 atoms / cm 3 After the implantation process, the lower conductive layer 103 can have an electrical type, such as n-type or p-type.

[0125] In some embodiments, an anneal process can be performed to activate the lower conductive layer 103. The anneal process can have a temperature between about 800 °C and about 1250 °C. The anneal process can have a process duration between about 1 millisecond and about 500 milliseconds. For example, the anneal process can be a rapid thermal anneal, a laser spike anneal, or a flash lamp anneal.

[0126] Referring to FIG. 1 and FIG. 3 at step S13, an isolation layer 105 can be formed on the substrate 101.

[0127] Referring to FIG. 3 , the isolation layer 105 can be formed on the substrate 101 and can cover the lower conductive layer 103. For example, the isolation layer 105 can include an oxide, a nitride, an oxynitride, a silicate (e.g., a metal silicate), an aluminate, a titanate, a nitride, a high dielectric constant dielectric material, or a combination thereof. For example, the fabrication technique of the isolation layer 105 can include a suitable deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, evaporation, chemical solution deposition, or other suitable deposition processes. The thickness of the isolation layer 105 can be varied depending on the deposition process and the composition and amount of the materials used. For example, the thickness of the isolation layer 105 can be between about and about In some embodiments, the isolation layer 105 may comprise multiple layers. For example, the isolation layer 105 may be an oxide-nitride-oxide (ONO) structure. As another example, the isolation layer 105 may comprise a lower layer comprising silicon oxide and an upper layer comprising a dielectric material with a high dielectric constant.

[0128] Examples of high dielectric constant materials (dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. For example, such high dielectric constant materials may also contain multiple dopants, such as lanthanum and aluminum.

[0129] In some embodiments, an interfacial layer (not shown) may be formed between the substrate 101 and the isolation layer 105. For example, the interfacial layer may comprise silicon oxide, silicon nitride, silicon oxynitride, other semiconductor oxides, or combinations thereof. The interfacial layer can be formed to any suitable thickness using any suitable process, including thermal growth, atomic layer deposition, chemical vapor deposition, high-density plasma chemical vapor deposition, spin-on deposition, or other suitable deposition processes. For example, the thickness of the interfacial layer may be between approximately... To about Between, or between approximately To about Between. During the manufacture of semiconductor device 1A, this interface layer can facilitate the formation of isolation layer 105.

[0130] Please refer to FIG. 1 and FIGS. 4-7 In step S15, a first conductive layer 201, a second conductive layer 301 and a third conductive layer 401 may be formed on the isolation layer 105.

[0131] Please refer to FIG. 4The intermediate conductive layers 601, 603, 605 can be formed on the isolation layer 105 and can be directly above the lower conductive layer 103. The intermediate conductive layers 601, 603, 605 can be spaced apart from each other. For example, the intermediate conductive layers 601, 603, 605 can include undoped polysilicon, undoped polygermanium, undoped polysilicon germanium, or a combination thereof. It should be understood that the number of the intermediate conductive layers is for illustrative purposes only. The number of the intermediate conductive layers can be greater than or less than three. For example, the number of the intermediate conductive layers can be two. For another example, the number of the intermediate conductive layers can be four.

[0132] Referring to FIG. 5 A mask layer 607 can be formed on the isolation layer 105. The mask layer 607 can cover the intermediate conductive layers 603, 605 and expose the intermediate conductive layer 601 (as shown in FIG. 4 In some embodiments, the mask layer 607 can be a photoresist layer. A first implantation process IMP1 can then be performed to implant dopants into the intermediate conductive layer 601 and convert the intermediate conductive layer 601 into the first conductive layer 201. The dopants can be p-type dopants or n-type dopants, where p-type dopants are, for example, boron, aluminum, gallium, and indium, and n-type dopants are, for example, antimony, arsenic, and phosphorus. The implantation concentration of the first implantation process IMP1 can be between about 1E19 atoms / cm 2 and about 1E21 atoms / cm 2 The first conductive layer 201 can have a first doping concentration. After the first implantation process IMP1, the mask layer 607 can be removed.

[0133] Referring to FIG. 6 A mask layer 609 can be formed on the isolation layer 105. The mask layer 609 can cover the intermediate conductive layer 605 and the first conductive layer 201 and expose the intermediate conductive layer 603 (as shown in FIG. 4 In some embodiments, the mask layer 609 can be a photoresist layer. A second implantation process IMP2 can then be performed to implant the dopants into the intermediate conductive layer 603 and convert the intermediate conductive layer 603 into the second conductive layer 301. The dopants can be p-type dopants or n-type dopants, where p-type dopants are, for example, boron, aluminum, gallium, and indium, and n-type dopants are, for example, antimony, arsenic, and phosphorus. The implantation concentration of the second implantation process IMP2 can be between about 1E19 atoms / cm 2 and about 1E21 atoms / cm 2In some embodiments, the doping type used in the first implantation process IMP1 is the same as the doping type used in the second implantation process IMP2. The second conductive layer 301 may have a second doping concentration. After the second implantation process IMP2, the masking layer 609 may be removed.

[0134] Please refer to FIG. 7 A masking layer 611 may be formed on the isolation layer 105. The masking layer 611 may cover the first conductive layer 201 and the second conductive layer 301, and expose the intermediate conductive layer 605. In some embodiments, the masking layer 611 may be a photoresist layer. A third implantation process IMP3 may then be performed to dope the plurality of dopants into the intermediate conductive layer 605 and convert the intermediate conductive layer 605 into the third conductive layer 401. The plurality of dopants may be p-type dopants or n-type dopants, and p-type dopants may be, for example, boron, aluminum, gallium and indium, and n-type dopants may be, for example, antimony, arsenic and phosphorus. The doping concentration of the second implantation process IMP2 may be between approximately 1E19 atoms / cm 2 Up to approximately 1E21 atoms / cm 2 In some embodiments, the doping type used in the third implantation process IMP3 is the same as the doping type used in the second implantation process IMP2. The third conductive layer 401 may have a third doping concentration. After the third implantation process IMP3, the masking layer 611 may be removed.

[0135] In some embodiments, the first doping concentration of the first conductive layer 201, the second doping concentration of the second conductive layer 301, and the third doping concentration of the third conductive layer 401 may be different. For example, the doping concentration of the third conductive layer 401 may be greater than the second doping concentration of the second conductive layer 301 and the first doping concentration of the first conductive layer 201. The second doping concentration of the second conductive layer 301 may be greater than the first doping concentration of the first conductive layer 201. It should be understood that the order of doping concentrations of the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 is merely illustrative. The order of doping concentrations may be changed depending on the circuit design.

[0136] In some embodiments, an annealing process may be performed to activate the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401. The temperature of the annealing process may be between approximately 800°C and approximately 1250°C. The annealing process may have a process duration between approximately 1 millisecond and approximately 500 milliseconds. For example, the annealing process may be a rapid thermal anneal, a laser spike anneal, or a flash lamp anneal.

[0137] Referring to FIG. 1 and FIG. 8 At step S17, an upper conductive layer 111 can be formed electrically coupled to the first, second and third conductive layers 201, 301 and 401, and a conductive plug 107 can be formed electrically coupled to the lower conductive layer 103.

[0138] Referring to FIG. 8 An interlayer dielectric layer 115 can be formed on the isolation layer 105 to cover the first, second and third conductive layers 201, 301 and 401. For example, the interlayer dielectric layer 115 can include silicon nitride, silicon oxide, silicon oxynitride, flowable oxide, tonen silazen, undoped silica glass, borosilica glass, phosphosilica glass, borophosphosilica glass, plasma enhanced tetra-ethyl orthosilicate, fluoridesilicate glass, carbon doped silicon oxide, or a combination thereof. For example, the fabrication technique of the interlayer dielectric layer 115 can include chemical vapor deposition, plasma enhanced chemical vapor deposition, or the like. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially planar surface for the following processing steps.

[0139] Referring to FIG. 8A plurality of conductive vias 109 can be formed in the ILD layer 115. The plurality of conductive vias 109 can be formed on the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401, respectively. In some embodiments, each of the conductive vias 109 can have a sloped profile. In some embodiments, the plurality of conductive vias 109 can be formed using a damascene method. Generally, in a damascene method, one or more dielectric materials, such as low-k dielectric materials (i.e., having a dielectric constant less than 4.0), are deposited and patterned to form vertical interconnects (i.e., vias) and horizontal interconnects (i.e., lines). Then, a plurality of conductive materials, such as copper-containing materials, and other materials, such as barrier layer materials, are damascened into the etch pattern to prevent the copper-containing materials from diffusing into the surrounding low-k dielectric. Any excess copper-containing materials and excess barrier layer materials outside the etch pattern are then removed.

[0140] Referring to FIG. 8 An ILD layer 117 can be formed on the ILD layer 115. In some embodiments, the ILD layer 117 can comprise the same material as the ILD layer 115, but is not limited thereto.

[0141] Referring to FIG. 8 An upper conductive layer 111 can be formed in the ILD layer 117. The upper conductive layer 111 can be formed on the plurality of conductive vias 109. The upper conductive layer 111 can be electrically coupled to the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 via the plurality of conductive vias 109. During a programming procedure, the upper conductive layer 111 can be electrically coupled to an external voltage. For example, the upper conductive layer 111 can comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. For example, the upper conductive layer 111 can be formed using a damascene process.

[0142] In some embodiments, the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 can be electrically coupled to different conductive layers and can be electrically coupled to different external voltages during a plurality of programming procedures.

[0143] Referring to FIG. 8A dielectric layer 121 can be formed on the dielectric layer 117. In some embodiments, the dielectric layer 121 can comprise the same material as the dielectric layer 117. In some embodiments, the dielectric layer 121 can be an etch stop layer, for example, and can comprise silicon nitride, silicon carbon nitride, or the like. For example, the fabrication technique of the dielectric layer 121 can comprise atomic layer deposition, chemical vapor deposition, or the like.

[0144] Referring to FIG. 8 The conductive plug 107 can be formed along the dielectric layer 121, the dielectric layer 117, the dielectric layer 115, and the isolation layer 105, and can be formed on the lower conductive layer 103. The conductive plug 107 can be electrically connected to the lower conductive layer 103. The conductive plug 107 can be electrically coupled to a bias or a ground potential. In some embodiments, the conductive plug 107 can have a sloped cross-sectional profile. For example, the conductive plug 107 can comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof.

[0145] Referring to FIG. 8 The first conductive layer 201, the second conductive layer 301, the third conductive layer 401, the isolation layer 105, and the lower conductive layer 103 together configure a programmable cell. The configuration of the first conductive layer 201 - the isolation layer 105 - the lower conductive layer 103, the configuration of the second conductive layer 301 - the isolation layer 105 - the lower conductive layer 103, and the configuration of the third conductive layer 401 - the isolation layer 105 - the lower conductive layer 103 can be considered as three capacitor-like structures (i.e., conductor-insulator-conductor structures).

[0146] For a capacitor-like structure having a plurality of n-type conductors, when a voltage greater than (i.e., having a greater magnitude than) the flat band voltage of the capacitor-like structure is applied, then a plurality of mobile carriers (electrons) can accumulate at the surface of the insulator. For a capacitor-like structure having a plurality of p-type conductors, when a voltage deeper than (i.e., having a smaller magnitude than) the flat band voltage of the capacitor-like structure is applied, then a plurality of mobile carriers (holes) can accumulate at the surface of the insulator. When the plurality of mobile carriers of a capacitor-like structure accumulates at the surface of the insulator, then the capacitor-like structure operates in an accumulation mode. When the band voltage of a capacitor-like structure is associated with the work function of the capacitor-like structure, and the work function of a capacitor-like structure is associated with the doping concentration of the capacitor-like structure, then the flat band voltage of a capacitor-like structure is associated with the doping concentration of the capacitor-like structure.

[0147] In one embodiment of the present disclosure, the lower conductive layer 103 comprises silicon doped with n-type dopants. The first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 comprise polysilicon doped with n-type dopants. The third doping concentration of the third conductive layer 401 can be greater than the second doping concentration of the second conductive layer 301. The second doping concentration of the second conductive layer 301 can be greater than the first doping concentration of the first conductive layer 201. In this embodiment, the first flatband voltage of the first conductive layer 201 is greater than the second flatband voltage of the second conductive layer 301, and the second flatband voltage of the second conductive layer 301 is greater than the third flatband voltage of the third conductive layer 401. For example, the first flatband voltage of the first conductive layer 201 is 4.0 volts, the second flatband voltage of the second conductive layer 301 is 3.0 volts, and the third flatband voltage of the third conductive layer 401 is 2.0 volts. When the flatband voltages of the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 are different, different voltages can be used to operate the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 in the accumulation mode, respectively.

[0148] In one programming procedure of the current embodiment, a programming voltage can be applied to the semiconductor element 1A through the upper conductive layer 111, and the conductive plug 107 can be electrically coupled to a ground potential. The programming voltage can apply pressure to the isolation layer 105. Thus, the isolation layer 105 can be broken to form a contiguous path connecting the lower conductive layer 103 and the first conductive layer 201, the second conductive layer 301, or the third conductive layer 401. By adjusting the value of the programming voltage, the number of contiguous paths formed can be controlled. That is, after the programming procedure, the resistance of the programmed cell can be fine-tuned by controlling the programming voltage.

[0149] For example, when the programming voltage is 2.5 volts, only the contiguous path of the third conductive layer 401 and the lower conductive layer 103 is formed. As another example, when the programming voltage is 3.5 volts, the contiguous path of the third conductive layer 401 and the lower conductive layer 103 and the contiguous path of the second conductive layer 301 and the lower conductive layer 103 are formed. As yet another example, when the programming voltage is 4.5 volts, all contiguous paths are formed.

[0150] In another embodiment of the present disclosure, the lower conductive layer 103 comprises silicon doped with p-type dopants. The first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 comprise polysilicon doped with p-type dopants. The third doping concentration of the third conductive layer 401 can be greater than the second doping concentration of the second conductive layer 301. The second doping concentration of the second conductive layer 301 can be greater than the first doping concentration of the first conductive layer 201. In such an embodiment, the first flatband voltage of the first conductive layer 201 is lower (e.g., closer to ground potential) than the second flatband voltage of the second conductive layer 301, and the second flatband voltage of the second conductive layer 301 is lower than the third flatband voltage of the third conductive layer 401. For example, the first flatband voltage of the first conductive layer 201 is -2.0 volts, the second flatband voltage of the second conductive layer 301 is -3.0 volts, and the third flatband voltage of the third conductive layer 401 is -4.0 volts. When the flatband voltages of the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 are different, different voltages can be used to operate the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401, respectively, in the accumulation mode.

[0151] An exemplary programming procedure can be as follows. When the programming voltage is -2.5 volts, only the continuous path of the third conductive layer 401 and the lower conductive layer 103 is formed. As another example, when the programming voltage is -3.5 volts, the continuous path of the third conductive layer 401 and the lower conductive layer 103 and the continuous path of the second conductive layer 301 and the lower conductive layer 103 are formed. As yet another example, when the programming voltage is -4.5 volts, all of the continuous paths are formed.

[0152] FIGS. 9-13 is a cross-sectional schematic view illustrating semiconductor elements 1B, 1C, 1D, 1E, 1F in some embodiments of the present disclosure.

[0153] Referring to FIG. 9 , the semiconductor element 1B can have a structure similar to that described in FIG. 8 . Elements in FIG. 9 that are the same as or similar to those in FIG. 8 have been designated by like element numbers, and repetitive descriptions thereof have been omitted. The semiconductor element 1B can include a well region 125. The well region 125 can be disposed in the substrate 101 and can surround the lower conductive layer 103. The well region 125 can have an electrical type opposite to that of the lower conductive layer 103. The well region 125 can provide additional electrical insulation for the lower conductive layer 103.

[0154] Referring to FIG. 10 , the semiconductor element 1C can have a structure similar to that described in FIG. 8 . Elements in FIG. 10 that are the same as or similar to those in FIG. 8The semiconductor element 1C can include a plurality of auxiliary layers 123. The plurality of auxiliary layers 123 can be respectively disposed on the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401. For example, the plurality of auxiliary layers 123 can include titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. The plurality of auxiliary layers 123 can have a thickness between about 2 nm and about 20 nm. The plurality of auxiliary layers 123 can respectively reduce contact resistance between the plurality of conductive vias 109 and the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401. In some embodiments, the plurality of auxiliary layers 123 can be respectively disposed on an upper surface of the first conductive layer 201, on an upper surface of the second conductive layer 301, and on an upper surface of the third conductive layer 401.

[0155] Referring to FIG. 11 , the semiconductor element 1D can have a structure similar to that described in FIG. 8 . In FIG. 11 , elements similar to or the same as those in FIG. 8 have been designated by like reference numerals, and repeated descriptions thereof have been omitted.

[0156] The semiconductor element 1D can include a plurality of gap spacers 113. The plurality of gap spacers 113 can be respectively disposed on sidewalls of the first conductive layer 201, on sidewalls of the second conductive layer 301, and on sidewalls of the third conductive layer 401. In some embodiments, for example, the plurality of gap spacers 113 can include silicon oxide, silicon nitride, silicon oxynitride, nitrided silicon oxide, the like, or a combination thereof. The plurality of gap spacers 113 can provide additional electrical insulation for the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401. In some embodiments, the plurality of gap spacers 113 can include a low-k dielectric material or a porous dielectric material. The plurality of gap spacers 113 including a low-k dielectric material or a porous dielectric material can reduce parasitic capacitance between the first conductive layer and the second conductive layer 301, and between the second conductive layer 301 and the third conductive layer 401.

[0157] Referring to FIG. 12 , the semiconductor element 1E can have a structure similar to that described in FIG. 8 . In FIG. 12 , elements similar to or the same as those in FIG. 8 have been designated by like reference numerals, and repeated descriptions thereof have been omitted. For example, the lower conductive layer 103 of the semiconductor element 1E can include a metal material. For example, the metal material can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, or a combination thereof.

[0158] Referring to FIG. 13 , the semiconductor device 1F can have a structure similar to that described in FIG. 8 . In FIG. 13 , elements identical or similar to those in FIG. 8 have been designated by like reference numerals, and repetitive description thereof has been omitted.

[0159] For example, the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 can include a metallic material, such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, platinum, or a combination thereof. The first conductive layer 201, the second conductive layer 301, and the third conductive layer 401 can include different materials so as to have different work functions. For example, the first conductive layer 201 can include aluminum and have a work function of +4.1 volts. The second conductive layer 301 can include copper and have a work function of +4.7 volts. The third conductive layer 401 can include platinum and have a work function of +6.4 volts. As with the different work functions of the first conductive layer 201, the second conductive layer 301, and the third conductive layer 401, different programming voltages can be required to program the first conductive layer 201, the second conductive layer 301, or the third conductive layer 401.

[0160] FIG. 14 is a flowchart illustrating a method 20 of fabricating a semiconductor device 1G according to another embodiment of the present disclosure. FIGS. 15-28 is a cross-sectional view illustrating a fabrication process of the semiconductor device 1G according to another embodiment of the present disclosure.

[0161] Referring to FIG. 14 and FIG. 15 , at step S21, a substrate 101 can be provided, a lower conductive layer 103 can be formed in the substrate 101, a plurality of pseudo-conductive layers 613 can be formed on the lower conductive layer 103, and a plurality of hard mask layers 615 can be formed on the plurality of pseudo-conductive layers 613.

[0162] Referring to FIG. 15 , the substrate 101 and the lower conductive layer 103 can be fabricated according to a procedure similar to that described in FIG. 2 . The plurality of pseudo-conductive layers 613 can be arranged to be spaced apart from each other. For example, the plurality of pseudo-conductive layers 613 can include amorphous silicon or polysilicon. For example, the plurality of hard mask layers 615 can include silicon nitride, silicon oxynitride, silicon oxynitride, or the like.

[0163] Referring to FIGS. 14-16 , at step S23, a plurality of gap spacers 113 can be formed on sidewalls of the plurality of pseudo-conductive layers 615, and an interlayer dielectric layer 115 can be formed to cover the plurality of gap spacers 113 and the plurality of hard mask layers 615.

[0164] Referring to FIG. 16 A layer of isolation material can be deposited to cover the plurality of dummy conductive layers 613 and the plurality of hard mask layers 615. An etching process, such as an anisotropic dry etching process, can then be performed to remove some portions of the layer of isolation material and simultaneously form the plurality of gap spacers 113. The fabrication technique of the ILD layer 115 can include a deposition process, such as chemical vapor deposition. A planarization process, such as chemical mechanical polishing, can be performed on the ILD layer 115 to provide a substantially planar surface for the subsequent processing steps.

[0165] Referring to FIG. 14 , FIG. 17 and FIG. 18 At step S25, the dummy conductive layers 613 are removed to form the first trench 701, the second trench 703, and the third trench 705 in the ILD layer 115 to expose some portions of the underlying conductive layer 103.

[0166] Referring to FIG. 17 A planarization process, such as chemical mechanical polishing, can be performed to remove some portions of the plurality of hard mask layers 615 and the plurality of gap spacers 113 to expose the plurality of dummy conductive layers 613.

[0167] Referring to FIG. 18 An etching process, such as an anisotropic dry etching process, can be performed to remove the plurality of dummy conductive layers 613 and simultaneously form the first trench 701, the second trench 703, and the third trench 705. Some portions of the upper surface of the underlying conductive layer 103 can be exposed via the first trench 701, the second trench 703, and the third trench 705.

[0168] Referring to FIG. 14 and FIGS. 19-27 At step S27, a first gate structure 200 can be formed in the first trench 701, a second gate structure 300 can be formed in the second trench 703, and a third gate structure 400 can be formed in the third trench 705.

[0169] Referring to FIG. 19 A layer of dielectric material 617 can be conformally formed on the intermediate semiconductor element as FIG. 18 described. For example, the dielectric material 617 can include silicon oxide, silicon nitride, hafnium oxide, silicon hafnium oxide, silicon hafnium oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, silicon zirconium oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or zinc lead niobate.

[0170] Referring to FIG. 20A first work function material 619 can be conformally formed on the dielectric material 617. For example, the first work function material 619 can include ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, titanium nitride, hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or combinations thereof. A mask layer 627 can be formed on the first work function material 619 to cover the third trench 705 and expose the second trench 703 and the first trench 701.

[0171] Referring to FIG. 21 An etch process can be performed to selectively remove the exposed portions of the first work function material 619. During the etch process, the etch rate ratio of the first work function material 619 to the dielectric material 617 can be between about 15: 1 and about 2: 1, or between about 10: 1 and about 3: 1. After the etch process, the mask layer 627 can be removed.

[0172] Referring to FIG. 22 A second work function material 621 can be conformally formed on the first work function material 619 and the dielectric material 617. The second work function material 621 can be different than the first work function material 619. For example, the second work function material 621 can include ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, titanium nitride, hafnium, zirconium, titanium, tantalum, aluminum, metal carbides, aluminides, or combinations thereof. A mask layer 629 can be formed on the second work function material 621 to cover the second trench 703 and expose the third trench 705 and the first trench 701.

[0173] Referring to FIG. 23 An etch process can be performed to selectively remove the exposed portions of the second work function material 621. During the etch process, the etch rate ratio of the second work function material 621 to the dielectric material 617 can be between about 15: 1 and about 2: 1, or between about 10: 1 and about 3: 1. During the etch process, the etch rate ratio of the second work function material 621 to the first work function material 619 can be between about 15: 1 and about 2: 1, or between about 10: 1 and about 3: 1. After the etch process, the mask layer 629 can be removed.

[0174] Referring to FIG. 24A third work function material 623 can be conformally formed on the first work function material 619, the second work function material 621, and the dielectric material 617. The third work function material 623 can be different from the first work function material 619 and the second work function material 621. For example, the third work function material 623 can include ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, titanium nitride, hafnium, zirconium, titanium, tantalum, aluminum, metal carbides, aluminides, or combinations thereof. A mask layer 631 can be formed on the third work function material 623 to cover the first trench 701 and expose the second trench 703 and the third trench 705.

[0175] Referring to FIG. 25 An etch process can be performed to selectively remove the exposed portions of the third work function material 623. During the etch process, the etch rate ratio of the third work function material 623 to the dielectric material 617 can be between about 15: 1 and about 2: 1, or between about 10: 1 and about 3: 1. During the etch process, the etch rate ratio of the third work function material 623 to the first work function material 619 can be between about 15: 1 and about 2: 1, or between about 10: 1 and about 3: 1. During the etch process, the etch rate ratio of the third work function material 623 to the second work function material 621 can be between about 15: 1 and about 2: 1, or between about 10: 1 and about 3: 1. After the etch process, the mask layer 631 can be removed.

[0176] Referring to FIG. 26 A fill material 625 can be formed to fill the first trench 701, the second trench 703, and the third trench 703. For example, the fill material 625 can include tungsten, aluminum, cobalt, ruthenium, gold, silver, titanium, platinum, the like, or combinations thereof. For example, the fill material 625 can be formed using chemical vapor deposition, physical vapor deposition, plating, thermal or e-beam evaporation, similar processes, or combinations thereof.

[0177] Referring to FIG. 27A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the ILD layer 115 is exposed. After the planarization process, the layer of dielectric material 617 can be converted into a first gate dielectric layer 203 in the first trench 701, into a second gate dielectric layer 303 in the second trench 703, and into a third gate dielectric layer 403 in the third trench 705. The layer of first work function material 619 can be converted into a third work function layer 405 in the third trench 705. The layer of second work function material 621 can be converted into a second work function layer 305 in the second trench 703. The layer of third work function material 623 can be converted into a first work function layer 205 in the first trench 701. The layer of fill material 625 can be converted into a first fill layer 207 in the first trench 701, into a second fill layer 307 in the second trench 703, and into a third fill layer 407 in the third trench 705. The thicknesses of the first gate dielectric layer 203, the second gate dielectric layer 303, and the third gate dielectric layer 403 can be the same.

[0178] Referring to FIG. 27 , the first gate dielectric layer 203, the first work function layer 205, the second gate dielectric layer 303, the second work function layer 305, the third gate dielectric layer 403, and the third work function layer 405 can have a U-shaped cross-sectional profile.

[0179] Referring to FIG. 27 , the first gate dielectric layer 203, the first work function layer 205, and the first fill layer 207 together configure a first gate structure 200. The second gate dielectric layer 303, the second work function layer 305, and the first fill layer 307 together configure a second gate structure 300. The third gate dielectric layer 403, the third work function layer 405, and the third fill layer 407 together configure a third gate structure 400. In some embodiments, the fabrication of the first gate structure 200, the second gate structure 300, and the third gate structure 400 can be easily integrated with the fabrication of the gates of the plurality of logic elements.

[0180] Referring to FIG. 14 and FIG. 28 , at step S29, a conductive plug 107 can be formed to electrically couple to the lower conductive layer 103, and an upper conductive layer 111 can be formed to electrically couple to the first gate structure 200, the second gate structure 300, and the third gate structure 400.

[0181] Referring to FIG. 28The interlayer dielectric layer 117 can be formed on the interlayer dielectric layer 115, and the interlayer dielectric layer 119 can be formed on the interlayer dielectric layer 117. For example, the plurality of conductive vias 109 and the upper conductive layer 111 can be formed in the interlayer dielectric layer 117 and the interlayer dielectric layer 119 by a damascene process. The upper conductive layer 111 can be electrically coupled to the first gate structure 200, the second gate structure 300, and the third gate structure 400 through the plurality of conductive vias 109. The interlayer dielectric layer 121 can be formed on the interlayer dielectric layer 119. The conductive plug 107 can be formed along the interlayer dielectric layers 115, 117, 119, 121, and on the lower conductive layer 103.

[0182] When the first work function layer 205, the second work function layer 305, and the third work function layer 405 comprise different work function materials, the first gate structure 200, the second gate structure 300, and the third gate structure 400 have different work functions. Accordingly, different programming voltages are needed to program the first gate structure 200, the second gate structure 300, or the third gate structure 400.

[0183] FIG. 29 and FIG. 30 are cross-sectional schematic views illustrating semiconductor devices 1H and 1I in accordance with some embodiments of the present disclosure. Reference is made to FIG. 29 The semiconductor device 1H can have a structure similar to that described in FIG. 28 The elements in FIG. 29 that are the same as or similar to those in FIG. 28 have been designated by like reference numerals, and repetitive description thereof has been omitted. The first gate structure 200 can further include a first wetting layer 209 and a first barrier layer 211. The second gate structure 300 can further include a second wetting layer 309 and a second barrier layer 311. The third gate structure 400 can further include a third wetting layer 409 and a third barrier layer 411.

[0184] The first wetting layer 208 can be disposed between the first work function layer 205 and the first fill layer 207. The second wetting layer 309 can be disposed between the second work function layer 305 and the second fill layer 307. The third wetting layer 409 can be disposed between the third work function layer 405 and the third fill layer 407. For example, the first wetting layer 209, the second wetting layer 309, and the third wetting layer 409 can comprise titanium, tantalum, nickel, or cobalt. The first wetting layer 209, the second wetting layer 309, and the third wetting layer 409 can facilitate bonding between layers and can facilitate uniform deposition of subsequent layers.

[0185] A first barrier layer 211 can be disposed between the first wetting layer 209 and the first fill layer 207. A second barrier layer 311 can be disposed between the second wetting layer 309 and the second fill layer 307. A third barrier layer 411 can be disposed between the third wetting layer 409 and the third fill layer 407. For example, the first barrier layer 211, the second barrier layer 311, and the third barrier layer 411 can include titanium nitride, tantalum nitride, or a combination thereof. The first barrier layer 211, the second barrier layer 311, and the third barrier layer can prevent subsequent deposition processes from degrading other layers of the semiconductor device 1H.

[0186] Referring to FIG. 30 , the semiconductor device 1I can have a structure similar to that described in FIG. 28 . The elements in FIG. 30 that are the same as or similar to those in FIG. 28 have been designated with like reference numerals, and repetitive descriptions thereof have been omitted.

[0187] Referring to FIG. 30 , the base 101, the lower conductive layer 103, and the isolation layer 105 can be fabricated in a manner similar to that described in FIG. 2 and FIG. 3 . The ILD layer 115 and the plurality of gap sub-layers 113 can be fabricated in a manner similar to that described in FIGS. 15-18 . The first work function layer 205, the first fill layer 207, the second work function layer 305, the second fill layer 307, the third work function layer 405, the third fill layer 407, the conductive plug 107, the plurality of conductive vias 109, the upper conductive layer 111, and the ILD layers 117, 119, 121 can be fabricated in a manner similar to that described in FIGS. 20-28 .

[0188] Referring to FIG. 30 , the first work function layer 205 and the first fill layer 207 together configure a first gate structure 200. The second work function layer 305 and the second fill layer 307 together configure a second gate structure 300. The third work function layer 405 and the third fill layer 407 together configure a third gate structure 400. When the first work function layer 205, the second work function layer 305, and the third work function layer 405 include different work function materials, the first gate structure 200, the second gate structure 300, and the third gate structure 400 have different work functions. Accordingly, different programming voltages can be needed to program the first gate structure 200, the second gate structure 300, or the third gate structure 400.

[0189] Due to the design of the semiconductor element 1A of the present disclosure, after a programming procedure, the resistance of the programmable cell can be fine-tuned by controlling the applied programming voltage. In addition, various programming voltages (e.g., -4.5 volts to +4.5 volts) can be selected and applied to program the programmable cell. In other words, the programmable cell can be designed to operate at various voltages in an integrated circuit. Furthermore, the programmable cell can be programmed by a relatively small (or weak) voltage (e.g., -2.5 volts to +2.5 volts). That is, the surface area used for a charge-pump circuit to generate the programming voltage can be reduced. Therefore, more surface area can be provided to other functional elements, such as logic functional elements.

[0190] While the present disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the techniques described above can be implemented in different methodologies or combinations thereof. Moreover, the language used in this disclosure has been presented in

[0191] Furthermore, the scope of the disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized according to the present disclosure. Accordingly, the appended claims include within their scope all existing and future embodiments of the processes, machines, manufacture, compositions of matter, means, methods and steps.

Claims

1. A semiconductor device, comprising: a substrate; a lower conductive layer disposed in the substrate; an isolation layer disposed on the substrate; a first conductive layer disposed on the isolation layer and over the lower conductive layer; a second conductive layer disposed on the isolation layer and over the lower conductive layer and spaced apart from the first conductive layer; a conductive plug electrically coupled to the lower conductive layer; and an upper conductive layer electrically coupled to the first conductive layer and the second conductive layer; wherein the first conductive layer has a first work function and the second conductive layer has a second work function different from the first work function; wherein the lower conductive layer, the isolation layer, the first conductive layer, and the second conductive layer together configure a programmable cell, wherein the first conductive layer and the second conductive layer comprise doped polysilicon, doped polysilicon germanium, or a combination thereof, and the first conductive layer and the second conductive layer have a same electrical type, wherein the lower conductive layer comprises doped silicon, doped germanium, doped silicon germanium, or a combination thereof, and the lower conductive layer has an electrical type that is the same as the first conductive layer and the second conductive layer, and further comprising a well region disposed in the substrate and surrounding the lower conductive layer, wherein the well region has an electrical type opposite to the lower conductive layer, the well region providing additional electrical isolation to the lower conductive layer.

2. The semiconductor device of claim 1, further comprising a plurality of assist layers covering the first conductive layer and the second conductive layer, wherein the plurality of assist layers comprise titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

3. The semiconductor device of claim 1, further comprising a plurality of gap spacers disposed on sidewalls of the first conductive layer and disposed on sidewalls of the second conductive layer.

4. The semiconductor device of claim 1, wherein the lower conductive layer comprises tungsten, aluminum, titanium, copper, or a combination thereof.

5. The semiconductor device of claim 1, wherein the first conductive layer and the second conductive layer comprise different materials, the first conductive layer comprising tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, platinum, or a combination thereof, and the second conductive layer comprising tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, platinum, or a combination thereof.

6. A semiconductor device, comprising: a substrate; an isolation layer disposed on the substrate; a lower conductive layer disposed in the substrate; a first gate structure comprising a first gate dielectric layer, a first work function layer, and a first fill layer, the first gate dielectric layer disposed on the lower conductive layer, the first work function layer disposed on the first gate dielectric layer, and the first fill layer disposed on the first work function layer, wherein the first work function layer has a first work function; a second gate structure comprising a second gate dielectric layer, a second work function layer, and a second fill layer, the second gate dielectric layer disposed on the lower conductive layer and spaced apart from the first gate dielectric layer, the second work function layer disposed on the second gate dielectric layer, and the second fill layer disposed on the second work function layer, wherein the second work function layer has a second work function different from the first work function. ​ a conductive plug electrically coupled to the lower conductive layer; and an upper conductive layer electrically coupled to the first gate structure and the second gate structure; wherein the lower conductive layer, the isolation layer, the first gate structure, and the second gate structure together configure a programmable cell, further comprising a well region disposed in the substrate and around the lower conductive layer, wherein the well region has an electrical type opposite to that of the lower conductive layer, the well region providing additional electrical insulation to the lower conductive layer.

7. The semiconductor element of claim 6, wherein the first gate dielectric layer and the second gate dielectric layer have the same thickness.

8. The semiconductor element of claim 7, further comprising a plurality of gap sub-regions disposed on both sides of the first gate structure and on both sides of the second gate structure.

9. The semiconductor element of claim 8, further comprising a first wetting layer disposed between the first work function layer and the first fill layer, wherein the first wetting layer comprises titanium, tantalum, nickel, or cobalt.

10. The semiconductor element of claim 9, further comprising a first barrier layer disposed between the first wetting layer and the first fill layer, wherein the first barrier layer comprises titanium nitride, tantalum nitride, or a combination thereof.

11. The semiconductor element of claim 6, wherein the first gate dielectric layer and the second gate dielectric layer have a U-shaped cross-sectional profile.

12. The semiconductor element of claim 6, wherein the lower conductive layer comprises doped silicon, doped germanium, doped silicon germanium, or a combination thereof.

13. The semiconductor element of claim 6, wherein the lower conductive layer comprises tungsten, aluminum, titanium, copper, or a combination thereof.

14. A semiconductor element, comprising: a substrate; a lower conductive layer disposed in the substrate; an isolation layer disposed on the substrate; a first gate structure disposed on the isolation layer and over the lower conductive layer, and comprising a first work function layer and a first fill layer, wherein the first work function layer has a first work function; a second gate structure disposed on the isolation layer, over the lower conductive layer, and spaced apart from the first gate structure, and comprising a second work function layer and a second fill layer, wherein the second work function layer has a second work function different from the first work function; a conductive plug electrically coupled to the lower conductive layer; and an upper conductive layer electrically coupled to the first gate structure and the second gate structure; wherein the lower conductive layer, the isolation layer, the first gate structure, and the second gate structure together configure a programmable cell, further comprising a well region disposed in the substrate and around the lower conductive layer, wherein the well region has an electrical type opposite to that of the lower conductive layer, the well region providing additional electrical insulation to the lower conductive layer.

15. A method of fabricating a semiconductor element, comprising: providing a substrate; forming a lower conductive layer in the substrate; forming an isolation layer on the substrate; forming a first conductive layer on the isolation layer and over the lower conductive layer, wherein the first conductive layer has a first work function; forming a second conductive layer on the isolation layer and above the lower conductive layer, and spaced apart from the first conductive layer, the second conductive layer having a second work function, the second work function being different from the first work function; wherein the lower conductive layer, the isolation layer, the first conductive layer, and the second conductive layer together configure a programmable cell, and further comprising forming a well region in the substrate and surrounding the lower conductive layer, wherein the well region has an electrical type opposite to that of the lower conductive layer, the well region providing additional electrical insulation to the lower conductive layer.

16. The method of claim 15, wherein the steps of forming the first conductive layer and forming the second conductive layer comprise: forming a first intermediate conductive layer and a second intermediate conductive layer on the isolation layer; forming a first masking layer to cover the second intermediate conductive layer and expose the first intermediate conductive layer; performing a first implantation process to convert the first intermediate conductive layer into the first conductive layer; removing the first masking layer; forming a second masking layer to cover the first conductive layer and expose the second intermediate conductive layer; performing a second implantation process to convert the second intermediate conductive layer into the second conductive layer; and removing the second masking layer; wherein the first implantation process and the second implantation process are performed with different doping concentrations.

17. The method of claim 16, wherein the lower conductive layer, the first conductive layer, and the second conductive layer have the same electrical type. ​

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