Image sensing device

Abstract

The present application relates to an image sensing device. An image sensing device includes: a semiconductor substrate; a photoelectric conversion region, which is supported by the semiconductor substrate and is configured to generate charge carriers from incident light and capture the charge carriers using a potential difference caused by a demodulation control signal applied to the photoelectric conversion region; and a circuit region, which is supported by the semiconductor substrate and is arranged adjacent to the photoelectric conversion region, the circuit region including a plurality of pixel transistors that generate and output pixel signals corresponding to the charge carriers captured by the photoelectric conversion region. The circuit region includes: a first well region, which is formed to have a first length in a first direction; and a second well region, which is formed below the first well region so that the lower end of the first well region contacts the upper end of the second well region, and is formed to have a second length shorter than the first length in the first direction.

Description

Technical Field

[0001] The techniques and implementations disclosed in this patent document generally relate to an image sensing device. Background Art

[0002] Image sensors are devices that capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the recent development of the automotive, medical, computer, and communication industries, the demand for high-performance image sensors is increasing in various fields such as smartphones, digital cameras, camcorders, personal communication systems (PCS), game consoles, IOT (Internet of Things), robots, surveillance cameras, medical micro cameras, etc. Summary of the invention

[0003] Embodiments of the disclosed technology relate to an image sensing device that can reduce power consumption while improving depth image characteristics.

[0004] According to an embodiment of the disclosed technology, an image sensing device may include: a semiconductor substrate; a photoelectric conversion region supported by the semiconductor substrate and configured to generate charge carriers from incident light and capture the charge carriers using a potential difference caused by a demodulation control signal applied to the photoelectric conversion region; and a circuit region supported by the semiconductor substrate and disposed adjacent to the photoelectric conversion region, the circuit region including a plurality of pixel transistors that generate and output pixel signals corresponding to the charge carriers captured by the photoelectric conversion region. The circuit region may include: a first well region formed to have a first length in a first direction; and a second well region formed below the first well region so that a lower end of the first well region contacts an upper end of the second well region, and the second well region is formed to have a second length shorter than the first length in the first direction.

[0005] According to an embodiment of the disclosed technology, an image sensing device may include: a substrate including a first region and a second region adjacent to the first region; a photoelectric conversion region formed in the substrate corresponding to the first region and including one or more demodulation points configured to receive a demodulation control signal and create an electric field and one or more detection nodes configured to collect photogenerated charge carriers; a circuit region including a circuit formed on the substrate corresponding to the second region to process the photogenerated charge carriers collected by the one or more detection nodes; a first well region doped with a first impurity and formed in the substrate corresponding to the second region below the circuit to have a first width and a first depth; and a second well region doped with a second impurity and formed in the substrate corresponding to the second region below the first well region to have a second depth and a second width from a bottom surface of the first well region.

[0006] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0008] Figure 2 Some implementations based on the disclosed technology are shown in Figure 1 A diagram of an example layout of unit pixels included in a pixel array is shown.

[0009] Figure 3 Some implementations based on the disclosed technology include Figure 2 A diagram of an example circuit of a tap and a pixel transistor included in a unit pixel is shown.

[0010] Figure 4A and Figure 4B is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line BB' is shown.

[0011] Figure 5A and Figure 5B The invention is to show the formation of some implementation methods based on the disclosed technology Figure 4A A cross-sectional view of an example of a method of forming a well structure in a circuit region is shown.

[0012] Fig. 6A and Figure 6B The invention is to show the formation of some implementation methods based on the disclosed technology Figure 4A A cross-sectional view of an example of another approach to well structure of a circuit region is shown. DETAILED DESCRIPTION

[0013] This patent document provides implementations and examples of image sensing devices, and the disclosed features can be implemented to achieve one or more advantages in more applications. Some implementations of the disclosed technology propose a design of an image sensing device that can reduce the power consumption required for sensing and improve depth characteristics.

[0014] Reference will now be made in detail to specific embodiments, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to represent the same or similar parts. In the following description, detailed descriptions of related known configurations or functions incorporated herein will be omitted to avoid obscuring the subject matter.

[0015] In order to acquire a three-dimensional (3D) image using an image sensor, color information of the 3D image and a distance (or depth) between a target object and the image sensor are required.

[0016] Methods for measuring depth information about a target object using one or more image sensors include triangulation methods and time of flight (TOF) methods. Among these depth measurement methods, the TOF method is widely used due to its wide range of applications, high processing speed and cost efficiency. In some implementations, the TOF method uses light emitted from a light source and light reflected from an object to measure the distance. Depending on whether the phase difference or round-trip time of light is used to determine the distance between a TOF sensor and an object, the TOF method can be classified into two different types: a direct method and an indirect method. The direct method can use the emitted light and the reflected light to calculate the round-trip time and use the round-trip time to measure the distance (i.e., depth) between the TOF sensor and the target object. The indirect method can use the phase difference to measure the distance between the TOF sensor and the target object. The direct method is used to measure a longer distance and is therefore widely used in automobiles. The indirect method is used to measure a shorter distance and is therefore used for game consoles or mobile cameras that are used at a shorter distance and require a faster processing speed. An indirect TOF sensor can be implemented at low cost using a simple circuit.

[0017] In some implementations, the indirect TOF sensor can utilize a current-assisted photon demodulator (CAPD) structure to detect electrons generated in the substrate using a hole current obtained by applying a voltage to the substrate, so that the CAPD structure can detect electrons more quickly. In addition, CAPD can detect electrons formed at a deeper depth in the substrate.

[0018] Figure 1 is a block diagram illustrating an example of an image sensing device ISD based on some implementations of the disclosed technology.

[0019] Reference Figure 1 , the image sensing device ISD may use an indirect time of flight (TOF) method to measure the distance between the image sensing device ISD and the target object 1. The TOF method based on some implementations may be a direct TOF method or an indirect TOF method. The indirect TOF method may measure the distance between the image sensing device ISD and the target object 1 by emitting modulated light to the target object 1, sensing light reflected from the target object 1, and calculating a phase difference between the modulated light and the reflected light.

[0020] The image sensing device ISD may include a light source 10 , a lens module 20 , a pixel array 30 , and a control block 40 .

[0021] The light source 10 may emit light toward the target object 1 upon receiving a modulated light signal (MLS) from the control block 40. The light source 10 may be a laser diode (LD) or a light emitting diode (LED) for emitting light having a specific wavelength band (e.g., near infrared (NIR) light, infrared (IR) light, or visible light), or may be any one of a near infrared laser (NIR), a point light source, a monochromatic light source combined with a white lamp or a monochromator, and a combination of other laser sources. For example, the light source 10 may emit infrared light having a wavelength of 800 nm to 1000 nm. Although as an example Figure 1 Only one light source 10 is shown, but a plurality of light sources may be arranged near the lens module 20 .

[0022] The lens module 20 may collect light reflected from the target object 1, and may allow the collected light to be focused on the pixel (PX) of the pixel array 30. For example, the lens module 20 may include a focusing lens having a surface formed of glass or plastic or another cylindrical optical element having a surface formed of glass or plastic. The lens module 20 may include a plurality of lenses arranged to focus light on an optical axis.

[0023] The pixel array 30 may include unit pixels (PX) arranged continuously in rows and columns into a two-dimensional (2D) matrix array. The unit pixels (PX) may be formed above a semiconductor substrate. Each unit pixel (PX) may convert incident light received through the lens module 20 into an electrical signal corresponding to the amount of incident light, and thus a pixel signal may be output using the electrical signal. In some implementations, the pixel signal may indicate the distance between the image sensing device ISD and the target object 1. For example, each unit pixel (PX) may be a current-assisted photon demodulator (CAPD) pixel that uses the difference between the potential levels of an electric field to capture photocharges generated in a semiconductor substrate by incident light. The following will be described from Figure 2 Initially, the structure and operation of each unit pixel (PX) will be described with reference to the accompanying drawings.

[0024] The control block 40 may emit light to the target object 1 by controlling the light source 10. Upon receiving reflected light from the target object 1, the control block 40 may process respective pixel signals corresponding to the light reflected from the target object 1 by operating the unit pixels (PX) of the pixel array 30, and measure the distance between the image sensing device ISD and the surface of the target object 1 based on the pixel signals.

[0025] The control block 40 may include a row driver 41 , a demodulation driver 42 , a light source driver 43 , a timing controller (T / C) 44 , and a readout circuit 45 .

[0026] In some implementations, the image sensing device ISD may include control circuits such as a row driver 41 and a demodulation driver 42 .

[0027] The control circuit may enable unit pixels (PX) of the pixel array 30 in response to a timing signal generated from the timing controller 44 .

[0028] The control circuit may generate a control signal for selecting and controlling at least one of the plurality of rows in the pixel array 30. In some implementations, the control signal may include a demodulation control signal for generating a pixel current in the substrate, a reset signal for controlling a reset transistor, a transmission signal for controlling transmission of photocharge accumulated in a detection node, a floating diffusion signal for providing additional electrostatic capacity at a high illumination level, and a selection signal for controlling a selection transistor. The pixel current may include a current for moving photocharge generated by the substrate to the detection node.

[0029] In this case, the row driver 41 may generate a reset signal, a transfer signal, a floating diffusion signal, and a selection signal, and the demodulation driver 42 may generate a demodulation control signal. In some implementations, the row driver 41 and the demodulation driver 42 may be separate elements. In other implementations, the row driver 41 and the demodulation driver 42 may be combined into a single element disposed on one side of the pixel array 30.

[0030] The light source driver 43 may generate a modulated light signal MLS for operating the light source 10 in response to a control signal from the timing controller 44. The modulated light signal MLS may be a signal modulated at a predetermined frequency.

[0031] The timing controller 44 may generate timing signals to control the row driver 41 , the demodulation driver 42 , the light source driver 43 , and the readout circuit 45 .

[0032] The readout circuit 45 may process the pixel signals received from the pixel array 30 based on the timing signal or other control signal provided by the timing controller 44, and may generate pixel data by converting the analog pixel signals into digital signals. To this end, the readout circuit 45 may include a correlated double sampler (CDS) circuit for performing correlated double sampling (CDS) on the pixel signals generated by the pixel array 30. In addition, the readout circuit 45 may include an analog-to-digital converter (ADC) for converting the output signal of the CDS circuit into a digital signal. In addition, the readout circuit 45 may include a buffer circuit that temporarily stores the pixel data generated from the analog-to-digital converter (ADC) and outputs the pixel data based on the timing signal or other control signal provided by the timing controller 44. In some implementations, the pixel array 30 includes a current-assisted photon demodulator (CAPD) pixel. Therefore, two column signal lines for transmitting pixel signals may be assigned to each column of the pixel array 30, and a circuit for processing pixel signals generated from each column line may correspond to each column line.

[0033] The light source 10 may emit light modulated at a predetermined frequency (i.e., modulated light) toward an object or scene (e.g., target object 1) captured by the image sensing device ISD. The image sensing device ISD may sense the modulated light (i.e., incident light) reflected from the target object 1 included in the scene, and thus may generate depth information of each unit pixel (PX). The time delay between the modulated light and the incident light is determined based on the distance between the image sensing device ISD and each target object 1. The time delay may be determined based on the phase difference between the signal generated by the image sensing device ISD and the modulated light signal MLS that controls the light source 10. An image processor (not shown) may calculate the phase difference generated in the output signal of the image sensing device ISD, and thus may generate a depth image including the depth information of each unit pixel (PX).

[0034] Figure 2 Some implementations based on the disclosed technology are shown in Figure 1 FIG. 2 is a schematic diagram of an exemplary layout of unit pixels included in the pixel array 30 shown.

[0035] Reference Figure 2 , the unit pixel PX can be Figure 1 As an example, Figure 2 Only one unit pixel PX is shown, and other pixels PX in the pixel array 30 may have the same structure and be arranged in the same manner as described above. Figure 2 The unit pixel PX shown operates in the same manner.

[0036] The unit pixel PX may include a photoelectric conversion region 100 and a circuit region 200 .

[0037] The photoelectric conversion region 100 may include a first tap TA (or a first demodulation point) and a second tap TB (or a second demodulation point) formed in a semiconductor substrate. Figure 2 The photoelectric conversion region 100 of the unit pixel PX is shown as including two taps TA and TB, but the unit pixel PX may include three or more taps. In some implementations, multiple taps may receive the same demodulation control signal. In other implementations, multiple taps may receive demodulation control signals with different phases and / or timings.

[0038] although Figure 2 The first tap TA and the second tap TB are shown to be arranged in the Y-axis direction (or column direction), but the first tap TA and the second tap TB may also be arranged in the X-axis direction (or row direction) or in a diagonal direction.

[0039] The first tap TA may include a first control node CNA and a first detection node DNA surrounding the first control node CNA. Figure 2As shown, the first control node CNA may have an octagonal shape, and the first detection node DNA is configured to surround the octagonal first control node CNA. In other implementations, the first control node CNA may have any shape that allows the first detection node DNA to surround the first control node CNA.

[0040] The annular structure constructed to surround the first control node CNA allows the first detection node DNA to have a larger inner surface facing the first control node CNA. In this way, the first detection node DNA can more easily capture the charge carriers moving along the pixel current formed by the first control node CNA. In other implementations, the first detection node DNA may not be formed in a single annular shape completely surrounding the first control node CNA, but may be formed in a manner that multiple elements separated from each other surround the first control node CNA.

[0041] The second tap TB may include a second control node CNB and a second detection node DNB surrounding the second control node CNB. The second control node CNB and the second detection node DNB may correspond to the first control node CNA and the first detection node DNA, respectively.

[0042] The first control node CNA and the second control node CNB and the first detection node DNA and the second detection node DNB may be formed in the substrate. For example, each of the first control node CNA and the second control node CNB may be a P-type impurity region, and each of the first detection node DNA and the second detection node DNB may be an N-type impurity region.

[0043] The first control node CNA and the first detection node DNA may be spaced apart from each other by a predetermined distance corresponding to the width of a device isolation layer (ISO), and the device isolation layer (ISO) is configured to physically isolate the first control node CNA from the first detection node DNA. In addition, the second control node CNB and the second detection node DNB may also be isolated from each other by the device isolation layer (ISO). The device isolation layer (ISO) may include a shallow trench isolation (STI) structure formed by filling a trench formed by etching a substrate to a predetermined depth with an insulating material.

[0044] The first tap TA and the second tap TB may also be spaced apart from each other by a device isolation layer (ISO).

[0045] The circuit region 200 may be disposed at one side of the photoelectric conversion region 100. The circuit region 200 may include a plurality of pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B for generating pixel signals corresponding to charge carriers captured by the detection nodes DNA and DNB.

[0046] The pixel transistors DX_A, SX_A, FDX_A, TX_A, and RX_A may generate pixel signals corresponding to charge carriers captured by the first detection node DNA and may output the pixel signals. The pixel transistors DX_A, SX_A, FDX_A, TX_A, and RX_A may be disposed near the first tap TA.

[0047] The pixel transistors DX_B, SX_B, FDX_B, TX_B, and RX_B may generate pixel signals corresponding to charge carriers captured by the second detection node DNB. The pixel transistors DX_B, SX_B, FDX_B, TX_B, and RX_B may be disposed near the second tap TB.

[0048] The pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B may be arranged in the circuit region 200. In one example, the circuit region 200 may be arranged in a direction (e.g., Figure 2 In this case, the pixel transistors DX_A, SX_A, FDX_A, TX_A and RX_A of the first tap TA and the pixel transistors DX_B, SX_B, FDX_B, TX_B and RX_B of the second tap TB can be as shown in FIG. Figure 2 A contact for applying a bias voltage VSS to the well region may be formed between the pixel transistors SX_A and FDX_A, and another contact for applying a bias voltage VSS to the well region may be formed between the pixel transistors SX_B and FDX_B. Here, the contact may include any type of structure that fills the gap with a conductive material.

[0049] Pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B may be formed in an active region ACT. The active region ACT may be isolated from the taps TA and TB by a device isolation layer (ISO). The active region ACT may be formed over the entire circuit region 200. For example, the active region ACT may be formed over the entire circuit region 200 in a line shape extending in the Y-axis direction. The width of each gate terminal of the pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B in the X direction may be narrower than the active region ACT.

[0050] In the circuit region 200, the well (e.g., P-well) region may be formed in such a manner that the width of the upper region of the well is different from the width of the lower region of the well. For example, the well (P-well) region may be formed in such a manner that the width of the well region formed below the active region ACT (i.e., the width in the X direction) is smaller than the width of the well region formed in the active region ACT.

[0051] Figure 3 Some implementations based on the disclosed technology are shown in Figure 2 A diagram of an example circuit of a unit pixel is shown. Figure 3 , the photoelectric conversion region 100 is shown along Figure 2 The cross-sectional view of the photoelectric conversion region is taken along the line AA'. The circuit region 200 shows a circuit diagram of a pixel transistor.

[0052] Reference Figure 3 , the first control node CNA may receive a first demodulation control signal (CSa) from the demodulation driver 42, and the second control node CNB may receive a second demodulation control signal (CSb) from the demodulation driver 42. The voltage difference between the first demodulation control signal (CSa) and the second demodulation control signal (CSb) may generate a pixel current (PC), which may be used to control the flow of charge carriers generated in the substrate by incident light. For example, when the first demodulation control signal (CSa) has a higher voltage than the second demodulation control signal (CSb), the pixel current (PC) may flow from the first control node CNA to the second control node CNB. Conversely, when the first demodulation control signal (CSa) has a lower voltage than the second demodulation control signal (CSb), the pixel current (PC) may flow from the second control node CNB to the first control node CNA.

[0053] Each of the first and second detection nodes DNA and DNB may capture charge carriers moving along the flow of the pixel current PC and may accumulate the captured charge carriers.

[0054] Photo charges may be captured in the photoelectric conversion region 100 during a first period and a second period following the first period.

[0055] In the first period, the light incident on the pixel PX may be converted into electron-hole pairs in the substrate. In some implementations, the photocharge may include these photogenerated electrons. In some implementations, the demodulation driver 42 may supply a first demodulation control signal (CSa) to the first control node CNA, and may supply a second demodulation control signal (CSb) to the second control node CNB. In one example, the first demodulation control signal (CSa) may have a voltage higher than the second demodulation control signal (CSb). Here, the voltage of the first demodulation control signal (CSa) may be defined as an active voltage or an enable voltage, and the voltage of the second demodulation control signal (CSb) may be defined as an inactive voltage or a deactivation voltage. For example, the voltage of the first demodulation control signal (CSa) may be set to 1.2V, and the voltage of the second demodulation control signal (CSb) may be 0V.

[0056] The voltage difference between the first demodulation control signal (CSa) and the second demodulation control signal (CSb) may create an electric field between the first control node CNA and the second control node CNB, so that the pixel current PC may flow from the first control node CNA to the second control node CNB. That is, holes in the substrate may move toward the second control node CNB, and electrons in the substrate may move toward the first control node CNA.

[0057] The electrons moving toward the first control node CNA may be captured by the first detection node DNA adjacent to the first control node CNA. Therefore, the electrons in the substrate may be used as charge carriers for detecting the intensity of incident light.

[0058] In the second period, the light incident on the pixel PX may be converted into electron-hole pairs. In some implementations, the demodulation driver 42 may supply a first demodulation control signal (CSa) to the first control node CNA, and may supply a second demodulation control signal (CSb) to the second control node CNB. In one example, the first demodulation control signal (CSa) may have a voltage lower than the second demodulation control signal (CSb). Here, the voltage of the first demodulation control signal (CSa) may be defined as an inactive voltage or a deactivated voltage, and the voltage of the second demodulation control signal (CSb) may be defined as an active voltage or an enabled voltage. For example, the voltage of the first demodulation control signal (CSa) may be 0V, and the voltage of the second demodulation control signal (CSb) may be set to 1.2V.

[0059] The voltage difference between the first demodulation control signal (CSa) and the second demodulation control signal (CSb) may create an electric field between the first control node CNA and the second control node CNB, and the pixel current PC may flow from the second control node CNB to the first control node CNA. That is, holes in the substrate may move toward the first control node CNA, and electrons in the substrate may move toward the second control node CNB.

[0060] The electrons moving toward the second control node CNB may be captured by the second detection node DNB adjacent to the second control node CNB. Thus, the electrons in the substrate may be used as charge carriers for detecting the intensity of incident light.

[0061] In other implementations, the order of the first time period and the second time period may be changed, so the first time period may follow the second time period.

[0062] The circuit area 200 may include a plurality of elements (pixel transistors) DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B, which are configured to convert the photocharge captured by the first detection node DNA and the second detection node DNB into an electrical signal. The circuit area 200 may also include an interconnect such as a metal wire, which is configured to carry electrical signals between the elements DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B. The control signals RST, TRG, FDG, and SEL may be supplied to the circuit area 200 from the row driver 41. In addition, the pixel voltage (Vpx) may be a power supply voltage (VDD).

[0063] Photocharges captured by the first detection node DNA may be converted into electrical signals as discussed below. The circuit region 200 may include a reset transistor RX_A, a transfer transistor TX_A, a first capacitor C1_A, a second capacitor C2_A, a floating diffusion transistor FDX_A, a drive transistor DX_A, and a select transistor SX_A.

[0064] The reset transistor RX_A may be enabled to enter an active state in response to a logic high level of a reset signal RST supplied to its gate electrode, so that the voltage of the floating diffusion node FD_A and the voltage of the first detection node DNA may be reset to a pixel voltage (Vpx) level. In addition, when the reset transistor RX_A is enabled (i.e., active state), the transfer transistor TX_A may also be enabled (i.e., active state) to reset the floating diffusion node FD_A.

[0065] The transfer transistor TX_A may be enabled (ie, active state) in response to a logic high level of a transfer signal TRG supplied to a gate electrode thereof, so that charges accumulated in the first detection node DNA may be transferred to the floating diffusion node FD_A.

[0066] The first capacitor C1_A may be coupled to the floating diffusion node FD_A so that the first capacitor C1_A may provide a predefined electrostatic capacity to the floating diffusion node FD_A. The second capacitor C2_A may be selectively coupled to the floating diffusion node FD_A based on the operation of the floating diffusion (FD) transistor FDX_A so that the second capacitor C2_A may provide an additional predefined electrostatic capacity to the floating diffusion node FD_A.

[0067] Each of the first capacitor C1_A and the second capacitor C2_A may include at least one of a metal-insulator-metal (MIM) capacitor, a metal-insulator-polysilicon (MIP) capacitor, a metal-oxide-semiconductor (MOS) capacitor, and a junction capacitor.

[0068] The floating diffusion transistor FDX_A may be enabled in response to a logic high level of a floating diffusion signal FDG supplied to a gate electrode thereof, so that the floating diffusion transistor FDX_A may couple the second capacitor C2_A to the floating diffusion node FD_A.

[0069] For example, when the intensity of the incident light satisfies a predetermined high illumination condition, the row driver 41 may turn on (or enable) the floating diffusion transistor FDX_A, so that the floating diffusion transistor FDX_A enters an active state and the floating diffusion node FD_A may be coupled to the second capacitor C2_A. As a result, when the incident light is at a high illumination level, the photocharge accumulated at the floating diffusion node FD_A increases, thereby achieving a high dynamic range (HDR).

[0070] On the other hand, when the incident light is at a relatively low illumination level, the row driver 41 may turn off (or deactivate) the floating diffusion transistor FDX_A so that the floating diffusion node FD_A may be isolated from the second capacitor C2_A.

[0071] In some other implementations, the floating diffusion transistor FDX_A and the second capacitor C2_A may be omitted, as desired.

[0072] The drain electrode of the driving transistor DX_A is coupled to the pixel voltage (Vpx) and the source electrode of the driving transistor DX_A is coupled to the vertical signal line SL_A through the selection transistor SX_A. The gate electrode of the driving transistor DX_A is coupled to the floating diffusion node FD_A, so that the driving transistor DX_A can operate as a source follower transistor for outputting a current (pixel signal) corresponding to the potential of the floating diffusion node FD_A.

[0073] The selection transistor SX_A may be enabled (ie, active state) in response to a logic high level of a selection signal SEL supplied to a gate electrode thereof, so that a pixel signal generated from the driving transistor DX_A may be output to the vertical signal line SL_A.

[0074] In order to process the photocharge captured by the second detection node DNB, the circuit area 200 may include a reset transistor RX_B, a transfer transistor TX_B, a first capacitor C1_B, a second capacitor C2_B, a floating diffusion transistor FDX_B, a drive transistor DX_B, and a selection transistor SX_B. The operation timing of the elements for processing the photocharge captured by the second detection node DNB is different from the operation timing of the elements for processing the photocharge captured by the first detection node DNA. However, the elements for processing the photocharge captured by the second detection node DNB may be similar to or the same as the elements for processing the photocharge captured by the first detection node DNA.

[0075] Pixel signals transmitted from the circuit area 200 to the vertical signal line SL_A and pixel signals transmitted from the circuit area 200 to the vertical signal line SL_B may be processed using a noise removal technique and an analog-to-digital converter (ADC) conversion process to convert the pixel signals into image data.

[0076] although Figure 3 Each of the reset signal RST, transfer signal TRG, floating diffusion signal FDG and selection signal SEL shown is supplied to the circuit area 200 through one signal line, but each of the reset signal RST, transfer signal TRG, floating diffusion signal FDG and selection signal SEL can be supplied to the circuit area 200 through multiple signal lines (for example, two signal lines), so that the elements for processing the photocharges captured by the first detection node DNA and other elements for processing the photocharges captured by the second detection node DNB can operate at different timings.

[0077] An image processor (not shown) may process image data acquired from the photocharge captured by the first detection node DNA and image data acquired from the photocharge captured by the second detection node DNB to generate a phase difference using the image data. The image processor may calculate depth information indicating the distance between the image sensor pixel and the target object 1 based on the phase difference corresponding to each pixel, and may generate a depth image including the depth information corresponding to each pixel.

[0078] Figure 4A is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line BB' is shown. Figure 4B is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line CC' is shown.

[0079] Reference Figure 4A and Figure 4BIn the photoelectric conversion region 100, the first control node CNA may include a P-type impurity region (eg, P - Area and P + For example, a P-type impurity region with a relatively low doping concentration (e.g., P - A P-type impurity region (eg, P + area) can be used in conjunction with the above P - The type impurity is implanted at the same position in the substrate 310 to a second depth less than the first depth. In this case, the first depth may be greater than the second depth.

[0080] The first detection node DNA may have N-type impurity regions (eg, N - Area and N + For example, an N-type impurity region with a relatively low doping concentration (e.g., N - region) may be implanted into the substrate 310 to a first depth, and an N-type impurity region (eg, N + area) can be used in conjunction with the above N - The P of the first control node CNA is implanted into the substrate 310 at the same position as the type impurity implantation position to a second depth less than the first depth. - The depth of the type impurity region may be greater than the N - type impurity region, thereby facilitating the flow of pixel current PC.

[0081] although Figure 4A Only the first tap TA is shown, but the second control node CNB and the second detection node DNB of the second tap TB may have the same structures as the first control node CNA and the first detection node DNA of the first tap TA, respectively.

[0082] In the circuit region 200 , the well region 320 may include an upper well region 320U and a lower well region 320D having different X-direction widths.

[0083] In some implementations, the upper well region 320U may be formed over the entire active area ACT. Impurity regions such as source / drain regions (S / D) of pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B may be formed in the upper well region 320U. The upper well region 320U may include a P-type (P - ) impurities.

[0084] The lower well region 320D may be formed below the active region ACT so that the lower well region 320D may contact the bottom surface of the upper well region 320U. For example, the lower well region 320D may be formed to protrude downward from the bottom surface of the upper well region 320U so that the top surface of the lower well region 320D contacts the bottom surface of the upper well region 320U. In some implementations, the depth of the lower well region 320D may be less than the depth of each of the control nodes CNA and CNB. The lower well region 320D may include a P-type (P-type) having the same doping concentration as the upper well region 320U. - ) impurities.

[0085] In addition, the width (length in the X direction) of the lower well region 320D may be smaller than the width of the upper well region 320U. For example, the lower well region 320D may be formed to extend in the Y direction, so that the Y direction length of the extended lower well region 320D is similar to or the same as the Y direction length of the upper well region 320U, and the width (length in the X direction) of the extended lower well region 320D is smaller than the width of the upper well region 320U. In some implementations, the Y direction length of each of the upper well region 320U and the lower well region 320D may be the same as the Y direction length of the circuit region 200 of the corresponding unit pixel.

[0086] In a conventional circuit region formed to include a pixel transistor, a region formed below the active region among the well regions may extend to a lower portion of the device isolation layer (ISO) in a manner that both sides of the region vertically overlap with the device isolation layer (ISO) of the photoelectric conversion region, and the region formed below the active region may also extend in a downward direction. However, in some implementations of the disclosed technology, when forming the well region 320 of the circuit region 200 including the pixel transistor, the width of the lower well region 320D formed below the active region ACT may be smaller than the width of the upper well region 320U, and the depth of the lower well region 320D may be smaller than the impurity region (P) of each of the control nodes CNA and CNB. - area) depth.

[0087] Since the lower well region 320D is formed to have a smaller width as described above, the well region 320 can be spaced farther from the control nodes CNA and CNB than in other cases where the lower well region 320D is formed to have a larger width. In addition, when the lower well region 320D is formed to have a smaller depth, the distance between the well region 320 and each of the control nodes CNA and CNB becomes longer. That is, as Figure 4A As shown, as the distance between the well region 320 and each of the control nodes CNA and CNB increases, the resistance between the well region 320 and each of the control nodes CNA and CNB also increases.

[0088] As described above, in some implementations, as the distance between the well region 320 and each of the control nodes CNA and CNB becomes longer, the resistance between the well region 320 and each of the control nodes CNA and CNB increases, so that the leakage of the current (pixel current) flowing from the control nodes CNA and CNB to the circuit region 200 is reduced, thereby reducing power consumption. In addition, as the leakage of the pixel current is reduced, the pixel current can be more concentrated in the photoelectric conversion region 100, thereby improving the depth characteristics.

[0089] However, if the well region 320 is formed to have a smaller width in the same manner as in the lower well region 320D, dark current may occur in a region (e.g., an edge region) where the well region is not formed in the active region. Therefore, in some implementations, the upper well region 320U may be completely formed in the active region ACT.

[0090] The lower well region 320D may be formed below the upper well region 320U in such a manner that the Y-direction central axis of the lower well region 320D may overlap the Y-direction central axis of the upper well region 320U. The width (length in the X-direction) of the lower well region 320D may be greater than the width of the source / drain regions (S / D) of the pixel transistors DX_A, SX_A, FDX_A, TX_A, RX_A, DX_B, SX_B, FDX_B, TX_B, and RX_B.

[0091] Figure 5A and Figure 5B Some implementations based on the disclosed technology are shown in Figure 4A The cross-sectional view of an example of a method for forming a well structure in a circuit region shown in FIG. Figure 5A and Figure 5B Only circuit area 200 is shown.

[0092] Reference Figure 5A , a mask pattern 410 for defining the circuit region 200 may be formed over the substrate 310. In some implementations, the mask pattern 410 may include a photoresist pattern.

[0093] Subsequently, the P-type (P - ) impurities are implanted into the upper portion of the substrate 310 to a first depth, thereby forming an upper well region 320U. In some implementations, such as Figure 4A As shown, the upper well region 320U may be formed to a predetermined depth corresponding to the depth of a device isolation layer (ISO) for isolating the active region ACT of the circuit region 200 from the taps TA and TB of the photoelectric conversion region 100 .

[0094] Reference Figure 5B, a mask pattern 420 for defining the lower well region 320D may be formed over the substrate 310 including the upper well region 320U. The mask pattern 420 may include a photoresist pattern.

[0095] Subsequently, the P-type (P - ) impurities are implanted into the lower portion of the upper well region 320U to a second depth, thereby forming a lower well region 320D. In some implementations, the second depth may be less than the impurity region (P - area) depth.

[0096] Thereafter, a device isolation layer (not shown) for isolating the active region ACT including the upper well region 320U from the taps TA and TB of the photoelectric conversion region 100 may be formed. In some implementations, the device isolation layer may be formed to have a shallow trench isolation (STI) structure.

[0097] Fig. 6A and Figure 6B Some implementations based on the disclosed technology are shown in Figure 4A A cross-sectional view of another example of a method for forming a well structure in a circuit region shown in FIG. Fig. 6A and Figure 6B Only circuit area 200 is shown.

[0098] Reference Fig. 6A , a mask pattern 420 for defining a lower well region 320D may be formed over the substrate 310 .

[0099] Subsequently, the P-type (P - ) impurities are implanted into the substrate 310 to a second depth from the top surface of the substrate 310, thereby forming impurity regions 320U1 and 320D. In some implementations, the second depth may be less than the impurity regions (P - area) depth.

[0100] although Fig. 6A The impurity regions 320U1 and 320D are illustrated as being different from each other, but the impurity regions 320U1 and 320D may be formed to have the same doping concentration.

[0101] Reference Figure 6B , a mask pattern 430 may be formed over the substrate 310 where the impurity regions 320U1 and 320D are formed. The mask pattern 430 may allow the remaining region other than the impurity regions 320U1 and 320D in the circuit region 200 to be exposed to the outside.

[0102] Subsequently, the P-type (P- ) impurity regions 320U2 are implanted into both sides of the impurity region 320U1 in the upper portion of the substrate 310, thereby forming the impurity regions 320U.

[0103] Thereafter, a device isolation layer (not shown) is formed to isolate the active region ACT including the upper well region 320U from the taps TA and TB of the photoelectric conversion region 100. In some implementations, the device isolation layer may be formed to have a shallow trench isolation (STI) structure.

[0104] As apparent from the above description, an image sensing device based on some implementations of the disclosed technology can reduce power consumption and improve depth image characteristics.

[0105] Although a number of exemplary embodiments have been described, it should be understood that numerous modifications to the disclosed embodiments and other embodiments are contemplated based on what is described and / or illustrated in this patent document.

[0106] CROSS-REFERENCE TO RELATED APPLICATIONS

[0107] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2021-0003960, filed on January 12, 2021, which is hereby incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: Semiconductor substrates; a photoelectric conversion region supported by the semiconductor substrate and generating charge carriers from incident light and capturing the charge carriers using a potential difference caused by a demodulation control signal applied to the photoelectric conversion region; as well as a circuit region supported by the semiconductor substrate and disposed adjacent to the photoelectric conversion region, the circuit region including a plurality of pixel transistors that generate and output pixel signals corresponding to the charge carriers captured by the photoelectric conversion region, Wherein, the circuit area includes: a first well region formed to have a first length in a first direction; and A second well region is formed below the first well region so that a lower end of the first well region contacts an upper end of the second well region, and the second well region is formed to have a second length shorter than the first length in the first direction, wherein the first direction is a direction from the circuit region to the photoelectric conversion region.

2. The image sensing device according to claim 1, wherein: The second length is longer than the length of the impurity regions of the plurality of pixel transistors in the first direction.

3. The image sensing device according to claim 1, wherein: Each of the first well region and the second well region extends in a second direction perpendicular to the first direction to have a third length longer than the first length.

4. The image sensing device according to claim 3, wherein: The third length is the same as a length of the circuit area in the second direction.

5. The image sensing device according to claim 1, wherein: The first well region and the second well region include first impurities having the same doping concentration.

6. The image sensing device according to claim 1, wherein: The first well region is formed entirely in an active region including the plurality of pixel transistors.

7. The image sensing device according to claim 6, wherein: A length of a gate electrode of each of the pixel transistors in the first direction is shorter than a length of the active region in the first direction.

8. The image sensing device according to claim 1, wherein: The photoelectric conversion region comprises: A plurality of taps controls movement of the charge carriers by generating a pixel current in the semiconductor substrate using the potential difference, and captures the charge carriers moved by the pixel current.

9. The image sensing device according to claim 8, wherein: The second well region is formed to have a smaller depth than the impurity region of each of the plurality of taps.

10. The image sensing device according to claim 8, wherein: The circuit area includes: An active region is formed to include the plurality of pixel transistors and is separated from the plurality of taps by a device isolation layer.

11. The image sensing device according to claim 10, wherein: The second well region is arranged not to vertically overlap the device isolation layer.

12. The image sensing device according to claim 8, wherein: The plurality of taps include: a first control node and a second control node, the first control node and the second control node being spaced apart from each other by a predetermined distance and generating the pixel current in the semiconductor substrate using the potential difference caused by the demodulated control signal; a first sense node formed around the first control node and capturing the charge carriers moving through the pixel current; and A second sensing node is formed around the second control node and captures the charge carriers moved by the pixel current.

13. The image sensing device according to claim 12, wherein: The first control node and the second control node include impurity regions doped with first impurities at different doping concentrations.

14. The image sensing device according to claim 12, wherein: The first sensing node and the second sensing node include impurity regions doped with second impurities at different doping concentrations.

15. An image sensing device, comprising: a substrate comprising a first region and a second region adjacent to the first region; a photoelectric conversion region formed in the substrate corresponding to the first region and comprising one or more demodulation points and one or more detection nodes, the one or more demodulation points receiving a demodulation control signal and creating an electric field, the one or more detection nodes collecting photogenerated charge carriers; a circuit region including circuitry formed on the substrate corresponding to the second region to process the photogenerated charge carriers collected by the one or more detection nodes; a first well region doped with a first impurity and formed in the substrate below the circuit corresponding to the second region to have a first width and a first depth, wherein the first width is a width in a first direction, and the first direction is a direction pointing from the circuit region to the photoelectric conversion region; and a second well region doped with a second impurity, the second well region being formed in the substrate below the first well region corresponding to the second region to have a second depth and a second width from a bottom surface of the first well region, Wherein, the first width is wider than the second width.

16. The image sensing device according to claim 15, wherein: The second depth is greater than the first depth.

17. The image sensing device according to claim 15, wherein: The second depth is less than the first depth.

18. The image sensing device according to claim 15, wherein: The first impurity is the same as the second impurity.

19. The image sensing device according to claim 15, wherein: The first well region has the same doping concentration as the second well region.

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