High voltage component and manufacturing method thereof

Abstract

The present invention proposes a high-voltage component and a method for manufacturing the same. The high-voltage component includes: a semiconductor layer, a well region, a base region, a gate, a source, and a drain. The base region has a second conductivity type, and the base region is formed in the semiconductor layer and connected to the well region in the channel direction. The gate is formed on the semiconductor layer, and part of the base region is located directly below the gate and connected to the gate to provide an inversion region for the high-voltage component during conduction operation. The source is located in the base region, the drain is located in a well region away from the base region, and part of the well region is located between the base region and the drain to separate the base region and the drain. The first concentration peak region of the impurity doping distribution of the base region is located directly below the source and contacts the source. The second conductivity type impurity concentration in the first concentration peak region is higher than that in other regions of the base region.

Description

Technical Field

[0001] The present invention relates to a high-voltage element and a manufacturing method thereof, and in particular to a high-voltage element capable of suppressing conduction of a parasitic transistor and a manufacturing method thereof. Background Art

[0002] Figure 1A and Figure 1B A top view and a cross-sectional view of a conventional high voltage device 100 are shown. A so-called high voltage device refers to a semiconductor device in which the voltage applied to the drain is higher than 3.3V during normal operation. Generally speaking, a drift region 12a (e.g., Figure 1B The drain 19 is separated from the body region 15, and the drift region 12a is in the channel direction (as shown in the dashed line range). Figure 1A and Figure 1B The length of the high voltage element 100 (indicated by the dotted arrow) is adjusted according to the operating voltage that the high voltage element 100 is subjected to during normal operation. Figure 1A and Figure 1B As shown, high-voltage device 100 includes a well region 12, a drift oxide region 14, a body region 15, a bulk electrode 16, a gate 17, a source 18, and a drain 19. Well region 12 is of N-type conductivity and is formed on substrate 11. Gate 17 partially covers drift oxide region 14. Bulk electrode 16 and body region 15 are of P-type conductivity. Source 18 and drain 19 are of N-type conductivity.

[0003] Generally, when manufacturing the high voltage component 100, a plurality of units are formed by mirror-image arrangement of the shared body region 15 and the body pole 16. Figure 1A and Figure 1B As shown, source 18' is mirror-symmetrical to source 18, gate 17' is mirror-symmetrical to gate 17, and source 18' is electrically connected to source 18 (not shown), gate 17' is electrically connected to gate 17 (not shown), and so on.

[0004] When the high-voltage device 100 is operating, holes in hot carriers generated by the high electric field are injected into the body region 15 through the body region 16. This hot carrier current flowing through the body region 15 increases the voltage drop within the body region 15, thereby turning on the parasitic NPN bipolar junction transistor (BJT) formed by the source 18, the body region 15, and the well region 12. This generates an extremely large on-state current, destroying the structure of the high-voltage device 100 and limiting the safe operation area (SOA). The definition of the SOA is well known to those skilled in the art and will not be elaborated on here.

[0005] In view of this, the present invention proposes a high-voltage device and a manufacturing method thereof, which can suppress the conduction of a parasitic transistor and increase the safe operating area when the high-voltage device is in operation. Summary of the Invention

[0006] In one aspect, the present invention provides a high-voltage device comprising: a semiconductor layer formed on a substrate; a well region having a first conductivity type, wherein the well region is formed in the semiconductor layer; a base region having a second conductivity type, wherein the base region is formed in the semiconductor layer and connected to the well region in a channel direction; a gate formed on the semiconductor layer, wherein a portion of the base region is located directly below the gate and connected to the gate to provide an inversion region for the high-voltage device in a conduction operation; and a source and a drain having the first conductivity type. Conductive type, wherein the source and the drain are formed below an upper surface of the semiconductor layer and connected to the upper surface, wherein the source and the drain are respectively located on both sides of the gate, the source is located in the base region, and the drain is located in the well region away from the base region, wherein a portion of the well region is located between the base region and the drain to separate the base region and the drain; wherein a first concentration peak region of the base region is located directly below the source and contacts the source; wherein the second conductive type impurity concentration of the first concentration peak region is higher than that of other regions of the base region.

[0007] In one embodiment, a second concentration peak region of the base region is located below the upper surface of the semiconductor layer and connected to the upper surface, wherein the second concentration peak region surrounds and connects to the source, and the second conductive type impurity concentration of the second concentration peak region is higher than that of other regions in the base region except the first concentration peak region.

[0008] In one embodiment, the base region further includes a first layer formed by a first process step, wherein the first process step simultaneously forms another first layer in another element in the semiconductor layer, and the depth of the first layer extending downward from the upper surface is greater than the source.

[0009] In one embodiment, the base region further includes a second layer formed by a second process step, wherein the second process step simultaneously forms another second layer in another element in the semiconductor layer, and the depth of the second layer extending downward from the upper surface is greater than that of the first layer.

[0010] In one embodiment, the high-voltage device further includes a buried layer, at least a portion of which is formed in the semiconductor layer, wherein the buried layer has the first conductivity type and is located directly below the base region and the well region.

[0011] In one embodiment, the high-voltage device further includes a drift oxide region formed above the semiconductor layer, wherein a portion of the gate is located directly above and connected to the drift oxide region.

[0012] In one embodiment, the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure, or a chemical vapor deposition (CVD) oxidation structure.

[0013] In one embodiment, the source electrode extends downward from the upper surface to a depth greater than the second concentration peak region.

[0014] In another aspect, the present invention provides a method for manufacturing a high-voltage device, comprising: forming a semiconductor layer on a substrate; forming a well region in the semiconductor layer, wherein the well region has a first conductivity type; forming a base region in the semiconductor layer, wherein the base region has a second conductivity type and is connected to the well region in a channel direction; forming a gate on the semiconductor layer, wherein a portion of the base region is located directly below the gate and is connected to the gate to provide an inversion region for the high-voltage device in a conduction operation; and forming a source and a drain on the semiconductor layer. A gate is provided below a top surface and the source and the drain are connected to the top surface, the source and the drain have a first conductivity type, wherein the source and the drain are respectively located on both sides of the gate, the source is located in the base region, and the drain is located in the well region away from the base region, wherein a portion of the well region is located between the base region and the drain to separate the base region and the drain; wherein a first concentration peak region of the base region is located directly below the source and contacts the source; wherein the second conductivity type impurity concentration of the first concentration peak region is higher than that of other regions of the base region.

[0015] In one embodiment, a second concentration peak region of the base region is located below the upper surface of the semiconductor layer and connected to the upper surface, wherein the second concentration peak region surrounds and connects to the source, and the second conductive type impurity concentration of the second concentration peak region is higher than that of other regions in the base region except the first concentration peak region.

[0016] In one embodiment, the base region further includes a first layer formed by a first process step, wherein the first process step simultaneously forms another first layer in another element in the semiconductor layer, and the depth of the first layer extending downward from the upper surface is greater than the source.

[0017] In one embodiment, the base region further includes a second layer formed by a second process step, wherein the second process step simultaneously forms another second layer in another element in the semiconductor layer, and the depth of the second layer extending downward from the upper surface is greater than that of the first layer.

[0018] In one embodiment, the high-voltage device manufacturing method further includes forming a buried layer, wherein at least a portion of the buried layer is formed in the semiconductor layer, the buried layer has the first conductivity type, and the buried layer is located directly below the base region and the well region.

[0019] In one embodiment, the high voltage device manufacturing method further includes forming a drift oxide region above the semiconductor layer, wherein a portion of the gate is located directly above and connected to the drift oxide region.

[0020] In one embodiment, the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure, or a chemical vapor deposition (CVD) oxidation structure.

[0021] In one embodiment, the source electrode extends downward from the upper surface to a depth greater than the second concentration peak region.

[0022] In one embodiment, the semiconductor layer is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm.

[0023] In one embodiment, the drift oxide region is a CVD oxide structure having a thickness of

[0024] In one embodiment, the high voltage device is a laterally diffused metal oxide semiconductor (LDMOS) device with a gate drive voltage of 3.3V and a gate oxide layer thickness of

[0025] In one embodiment, a low voltage device is formed on the substrate, and the channel length of the low voltage device is 0.18 μm.

[0026] In one embodiment, the first concentration peak region is formed by a self-aligned process step, wherein the self-aligned process step includes: etching a polysilicon layer to form a conductive layer of the gate; and using the conductive layer as a mask to form the first concentration peak region by an ion implantation process step.

[0027] An advantage of the present invention is that the present invention can prevent the parasitic bipolar junction transistor from being turned on, thereby suppressing the parasitic bipolar junction transistor.

[0028] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A and Figure 1B A schematic top view and a schematic cross-sectional view of a known high-voltage component are shown respectively.

[0030] Figure 2 FIG2 is a cross-sectional diagram showing a high voltage component according to an embodiment of the present invention.

[0031] Figure 3 FIG2 is a cross-sectional schematic diagram showing a high-voltage component according to another embodiment of the present invention.

[0032] Figures 4A-4K FIG. 4 is a schematic diagram showing a method for manufacturing a high-voltage device according to an embodiment of the present invention.

[0033] Figures 5A-5C 1 and 2 are schematic diagrams respectively showing an implementation step of forming the third layer 255 , the first concentration peak region 251 , and the second concentration peak region 252 .

[0034] Explanation of symbols in the figure

[0035] 100, 200, 300: high voltage components

[0036] 11, 21, 31: substrate

[0037] 12, 22, 32: well area

[0038] 12a, 22a, 32a: Drift zone

[0039] 13, 36: body pole

[0040] 14, 24, 34: drift oxidation area

[0041] 16, 35: Ontology area

[0042] 17, 17', 27, 27', 37, 37': gate

[0043] 18, 18', 28, 28', 38, 38': Source

[0044] 19, 29, 39: Drain

[0045] 21', 31': semiconductor layer

[0046] 21a, 31a: upper surface

[0047] 21b, 31b: lower surface

[0048] 23: buried layer

[0049] 25, 35: basal area

[0050] 25a, 35a: Reversing current channel

[0051] 251: First concentration peak area

[0052] 252: Second concentration peak area

[0053] 253: First floor

[0054] 254: Second Floor

[0055] 255: Third layer

[0056] 261, 281, 2511, 2521, 2531, 2541, 2551: Photoresist layer

[0057] 271, 271', 371, 371': dielectric layer

[0058] 272, 272', 372, 372': conductive layer

[0059] 273, 273', 373, 373': Interval layer

[0060] 282, 282': lightly doped region DETAILED DESCRIPTION

[0061] The foregoing and other technical aspects, features, and effects of the present invention will be more clearly understood in the following detailed description of preferred embodiments with reference to the accompanying drawings. The drawings herein are schematic, primarily intended to illustrate process steps and the hierarchical relationship between layers. Shapes, thicknesses, and widths are not drawn to scale.

[0062] Please refer to Figure 2 , which is a cross-sectional view of a high voltage component 200 according to an embodiment of the present invention. Figure 2As shown, the high-voltage device 200 includes: a substrate 21, a semiconductor layer 21', a well region 22, a drift oxide region 24, a bulk region 25, a bulk contact 26, a gate 27, a source 28, a drain 29, a first concentration peak region 251, a second concentration peak region 252, a first layer 253, a second layer 254, a third layer 255 and a buried layer 23. The first concentration peak region 251, the second concentration peak region 252, the first layer 253, the second layer 254 and the third layer 255 can constitute the bulk region 25. When the high-voltage device 200 is manufactured, a plurality of units are arranged in a mirror-image manner that shares the bulk region 25 and the bulk contact 26. Therefore, as shown in FIG. Figure 2 As shown, the source 28' is mirror-symmetrical to the source 28, the gate 27' is mirror-symmetrical to the gate 27, and so on. In a preferred embodiment, the high-voltage element 200 is as follows Figure 2 The LDMOS device is shown in FIG. 1 . In a preferred embodiment, the high voltage device 200 has a gate drive voltage of 3.3 V and a gate oxide layer thickness of 1.5 V.

[0063] The semiconductor layer 21' is formed on the substrate 21. The semiconductor layer 21' is formed on the substrate 21 in a vertical direction (eg Figure 2 , and the substrate 21 has an upper surface 21a and a lower surface 21b opposite to each other (indicated by the solid arrows in the figure, the same below). The substrate 21 is, for example, but not limited to, a P-type or N-type semiconductor silicon substrate. The semiconductor layer 21' is formed on the substrate 21, for example, by an epitaxial process, or a portion of the substrate 21 serves as the semiconductor layer 21'. The method for forming the semiconductor layer 21' is well known to those skilled in the art and will not be described in detail here. In a preferred embodiment, the semiconductor layer 21' is a P-type epitaxial silicon layer having a resistance of 45 Ohm-cm.

[0064] Please continue reading Figure 2 The drift oxide region 24 is formed on and connected to the upper surface 21a and is located in the drift region 22a (eg Figure 2 The gate 27 is located directly above the drift oxide region 24 and is connected to the drift oxide region 24. The drift oxide region 24 is not limited to the Figure 2The chemical vapor deposition (CVD) oxide structure shown may also be a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure. The steps for forming the LOCOS structure, STI structure, and CVD oxide structure are well known to those skilled in the art and will not be described in detail here. In a preferred embodiment, the drift oxide region 24 is a CVD oxide structure and has a thickness of

[0065] The well region 22 has a first conductivity type and is formed in the semiconductor layer 21'. In the vertical direction, the well region 22 is located below the upper surface 21a and is connected to the upper surface 21a. The base region 25 has a second conductivity type and is formed in the semiconductor layer 21'. In the vertical direction, the base region 25 is located below the upper surface 21a and is connected to the upper surface 21a. The base contact 26 is formed in the base region 25 and has a second conductivity type. It serves as an electrical contact of the base region 25. In the vertical direction, the base contact 26 is formed in the base region 25 below the upper surface 21a and is connected to the upper surface 21a. The base region 25 is formed in the semiconductor layer 21' and in a channel direction (such as Figure 2 The substrate 25 is connected to the well region 22 (indicated by the dashed arrow in the figure, the same below). A gate 27 is formed on the upper surface 21a of the semiconductor layer 21'. In the vertical direction, a portion of the base region 25 is located directly below the gate 27 and connected to the gate 27, thereby providing a reverse current channel 25a (also referred to as an inversion region) for the high-voltage device 200 during the on-state operation.

[0066] Please continue reading Figure 2 The source 28 and drain 29 have a first conductivity type. In the vertical direction, the source 28 and drain 29 are formed below and connected to the upper surface 21a. The source 28 and drain 29 are respectively located in the base region 25 below and outside the gate 27 in the channel direction and in the well region 22 away from the base region 25. A portion of the well region 22 is located between the base region 25 and the drain 29 to separate the base region 25 and the drain 29. In the channel direction, the drift region 22a is located between the drain 29 and the base region 25, in the well region 22 near the upper surface 21a, to serve as a drift current path for the high-voltage device 200 during the on-state operation. In one embodiment, the source 28 and 28' are electrically connected to the base contact 26 via a silicide metal layer (not shown).

[0067] Please refer to Figure 2As described above, the base region 25 includes a first peak concentration region 251, a second peak concentration region 252, a first layer 253, a second layer 254, and a third layer 255. The first peak concentration region 251 of the base region 25 is located directly below and contacts the source electrodes 28 and 28'. In one embodiment, the first peak concentration region 251 has a higher second conductivity type impurity concentration than other regions of the base region 25. The second peak concentration region 252 of the base region 25 is located below and connected to the upper surface 21a of the semiconductor layer 21' and is located in the upper portion of the base region 25. The second peak concentration region 252 surrounds and connects the source electrodes 28 and 28'. In one embodiment, the second peak concentration region 252 has a higher second conductivity type impurity concentration than other regions of the base region 25 except the first peak concentration region 251. In one embodiment, the depth to which the source electrode 28 extends downward from the upper surface 21a is greater than the depth to which the second peak concentration region 252 extends downward from the upper surface 21a.

[0068] The first layer 253 is located below and connected to the upper surface 21a of the semiconductor layer 21' and is formed in the first process step. The first process step also forms another first layer in another component in the semiconductor layer 21'. In other words, the first layer 253 can be formed simultaneously in the high-voltage component 200 and another component using the same lithography process step and the same ion implantation process step, without requiring additional manufacturing costs. In one embodiment, the depth to which the first layer 253 extends downward from the upper surface 21a is greater than the depth to which the source electrode 28 extends downward from the upper surface 21a.

[0069] like Figure 2 As shown, the second layer 254 is located below and connected to the upper surface 21a of the semiconductor layer 21' and is formed by the second process step. The second process step also forms another second layer in another component in the semiconductor layer 21'. In other words, the second layer 254 can be formed simultaneously in the high-voltage component 200 and another component using the same lithography process step and the same ion implantation process step, without requiring additional manufacturing costs. In one embodiment, the depth of the second layer 254 extending downward from the upper surface 21a is greater than the depth of the first layer 253 extending downward from the upper surface 21a.

[0070] In one embodiment, the base region 25 is composed of a first peak concentration region 251, a second peak concentration region 252, a first layer 253, a second layer 254, and a third layer 255. The buried layer 23 is formed in the semiconductor layer 21 ′ and has the first conductivity type. The buried layer 23 is located directly below the second layer 254 of the base region 25 and the well region 22.

[0071] In one embodiment, the first concentration peak region 251 is formed by a self-alignment process step, wherein the self-alignment process step includes: etching a polysilicon layer to form a conductive layer 272 of the gate 27; and using the conductive layer 272 as a mask to form the first concentration peak region 251 by an ion implantation process step.

[0072] In one embodiment, a low-voltage device is formed on substrate 21, and the channel length of the low-voltage device is 0.18 μm. In one embodiment, the metal processing steps of the low-voltage device are also 0.18 μm process steps, that is, the minimum metal wire (plug) width of the low-voltage device is 0.18 μm.

[0073] The present invention uses a first concentration peak region 251 (and a second concentration peak region 252) having a higher second conductivity type impurity concentration. When the high voltage element 200 is in operation, holes in hot carriers generated by the high electric field are injected into the base contact 26 via the base region 25. When this hot carrier current flows through the base region 25, the hot carrier current flows through the first concentration peak region 251 (and the second concentration peak region 252) having a higher second conductivity type impurity concentration. Compared to the prior art, the voltage drop within the base region 25 of the present invention is lower, which can prevent the parasitic bipolar junction transistor from turning on (insufficient base voltage), thereby inhibiting the parasitic bipolar junction transistor from turning on. The parasitic bipolar junction transistor is formed by a portion of the well region 22, a portion of the base region 25, a portion of the source 28, and a portion of the base contact 26, as shown in FIG. Figure 2 The solid line in the middle shows the NPNBJT circuit symbol.

[0074] It should be noted that the so-called inversion current channel 25a refers to the region where, when the high-voltage device 200 is turned on, an inversion layer is formed below the gate 27 due to the voltage applied to the gate 27, allowing the on-current to pass through. This region is located between the source 28 and the drift current channel. This is well known to those skilled in the art and will not be described in detail here. The same applies to other embodiments of the present invention.

[0075] It should be noted that the so-called drift current channel refers to the region where the high-voltage element 200 causes the conduction current to drift during conduction operation. This is well known to those skilled in the art and will not be described in detail here. The same applies to other embodiments of the present invention.

[0076] It should be noted that the upper surface 21a is not a completely flat surface, but refers to a surface of the semiconductor layer 21'. In one embodiment, the portion of the upper surface 21a where the drift oxide region 24 contacts the upper surface 21a may also have a recessed portion.

[0077] It should be noted that the gate 27 includes a dielectric layer 271 connected to the upper surface, a conductive layer 272 having conductivity, and a spacer layer 273 having electrical insulation properties, which is well known to those skilled in the art and will not be described in detail here.

[0078] It should be noted that the aforementioned "first conductivity type" and "second conductivity type" refer to the process of doping semiconductor component regions (such as, but not limited to, the well region, body region, source and drain regions) with impurities of different conductivity types in a high-voltage device, resulting in the semiconductor component regions becoming the first or second conductivity type (such as, but not limited to, the first conductivity type being N-type and the second conductivity type being P-type, or vice versa). The first conductivity type has an opposite electrical property to the second conductivity type.

[0079] It should also be noted that a so-called high-voltage device refers to a device in which, during normal operation, the voltage applied to the drain is higher than a specific voltage, such as 3.3V or 50V. Furthermore, the lateral distance between the body region 25 and the drain 29 (the length of the drift region 22a) is adjusted according to the operating voltage during normal operation, thereby enabling operation at the aforementioned higher specific voltage. This is well known to those skilled in the art and will not be further elaborated here.

[0080] Furthermore, it should be noted that the so-called low-voltage device refers to a device in which the voltage applied to the drain is lower than a specific voltage, such as 3.3V, during normal operation.

[0081] It is worth noting that one of the technical features of the present invention that is superior to the prior art is that: according to the present invention, Figure 2 Taking the illustrated embodiment as an example, when the high-voltage device 200 is in operation, hot carriers (such as, but not limited to, holes in an N-type high-voltage device) generated by a high electric field are injected through the base region 25 into the "hot carrier absorption channel" provided by the base contact 26 and absorbed. Compared to the prior art, the resistance of the "hot carrier absorption channel" of the present invention is relatively low. This is because the first concentration peak region 251 of the present invention is closer to the PN junction formed by the base region 25 and the well region 22, and the second conductivity type impurity concentration in the first concentration peak region 251 is higher than the second conductivity type impurity concentration in other portions of the base region 25. Therefore, when hot carriers flow through the "hot carrier absorption channel," the voltage drop caused by the hot carrier current in the base region 25 is low. This results in a low base voltage of the parasitic bipolar junction transistor formed by the base region 25, the source 28, and the well region 22, which is insufficient to turn on the parasitic bipolar junction transistor, thereby preventing the parasitic bipolar junction transistor from turning on when the high-voltage device 22 is in operation.

[0082] Figure 3 FIG. 1 is a cross-sectional view of a high voltage component 300 according to another embodiment of the present invention. Figure 2The difference between the embodiment of FIG1 and FIG2 is that, in this embodiment, the high voltage element 300 does not include the first layer and the second layer, and since there is no first layer and the second layer, the buried layer can also be omitted. The substrate 31, the semiconductor layer 31', the well region 32, the drift oxide region 34, the gates 37 and 37', the source 38 and 38', the drain 39, the first concentration peak region 351 and the second concentration peak region 352 of this embodiment correspond to the same Figure 2 The substrate 21, semiconductor layer 21', well region 22, drift oxide region 24, gates 27 and 27', sources 28 and 28', drain 29, first concentration peak region 251 and second concentration peak region 252 are omitted in detail.

[0083] In this embodiment, the body region 35 is used as a substrate region to provide a reverse current channel 35 a ; and the body pole 36 is used as an electrical contact of the body region 35 , that is, a substrate contact.

[0084] Please refer to Figures 4A-4K , which is a schematic diagram showing a method for manufacturing a high voltage component 200 according to an embodiment of the present invention. Figure 4A As shown, a substrate 21 is first provided. The substrate 21 is, for example but not limited to, a P-type or N-type semiconductor silicon substrate. In a preferred embodiment, the high voltage device 200 is a laterally diffused metal oxide semiconductor (LDMOS) device. In a preferred embodiment, the high voltage device 200 has a gate drive voltage of 3.3V and a gate oxide layer thickness of

[0085] Next, see Figure 4B , forming a buried layer 23 below the well region 22. In the vertical direction, the buried layer 23 is formed, for example, on both sides of the interface between the substrate 21 and the semiconductor layer 21', part of the buried layer 23 is located in the substrate 21, and part of the buried layer 23 is located in the semiconductor layer 21'. The buried layer 23 has a first conductivity type, for example but not limited to an ion implantation process step, the first conductivity type impurities are implanted into the substrate 21 in the form of accelerated ions, and after the semiconductor layer 21' is formed, the buried layer 23 is formed by thermal diffusion. Wherein, the semiconductor layer 21' is formed on the substrate 21, and the semiconductor layer 21' is vertically (such as Figure 4B 21 , and has an upper surface 21a and a lower surface 21b opposite to each other (indicated by the solid arrows in FIG. , the same applies hereinafter). A semiconductor layer 21' is formed on a substrate 21, for example, by epitaxy, or a portion of the substrate 21 serves as the semiconductor layer 21'. The method for forming the semiconductor layer 21' is well known to those skilled in the art and will not be described in detail here. In a preferred embodiment, the semiconductor layer 21' is a P-type epitaxial silicon layer having a resistance of 45 Ohm-cm.

[0086] Then, a well region 22 is formed in the semiconductor layer 21'. In the vertical direction, the well region 22 is located below and connected to the upper surface 21a. The well region 22 has a first conductivity type. For example, it can be formed by, but not limited to, ion implantation, in which first conductivity type impurities are introduced in the form of accelerated ions, such as Figure 4B As indicated by the dotted arrows, the semiconductor layer 21 ′ is implanted to form a well region 22 .

[0087] Next, see Figure 4C , forming a drift oxide region 24 on the upper surface 21a and connected to the upper surface 21a. The drift oxide region 24 is electrically insulated and is not limited to Figure 4C The chemical vapor deposition (CVD) oxidation structure shown may also be a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure. The drift oxide region 24 is located on the drift region 22a and is connected to the drift region 22a (see FIG. Figure 4F and Figure 2 In a preferred embodiment, the drift oxide region 24 is a CVD oxide structure and has a thickness of

[0088] Next, a base region 25 is formed in the semiconductor layer 21'. In one embodiment, forming the base region 25 may include forming a second layer 254, forming a first layer 253, forming a third layer 255, forming a first concentration peak region 251, and forming a second concentration peak region 252. In another embodiment, forming the base region 25 may include forming a third layer 255, forming a first concentration peak region 251, and forming a second concentration peak region 252. Figure 4D , forming a second layer 254 in the well region 22, and in the vertical direction, the second layer 254 is located below and connected to the upper surface 21a. The second layer 254 has a second conductivity type, and the steps of forming the second layer 254 include, for example but not limited to, using a photoresist layer 2541 formed by a lithography process as a mask to dope the second conductivity type impurities into the well region 22 to form the second layer 254. In this embodiment, the second conductivity type impurities can be introduced in the form of accelerated ions, such as, but not limited to, ion implantation. Figure 4D As indicated by the dotted arrow in the figure, the second layer 254 is implanted into the well region 22. The above process of forming the second layer 254 can also be used to simultaneously form another second layer in another device in the semiconductor layer 21'.

[0089] Afterwards, see Figure 4E, forming a first layer 253 in the second layer 254, and in the vertical direction, the first layer 253 is located below the upper surface 21a and connected to the upper surface 21a. The first layer 253 has a second conductivity type, and the step of forming the first layer 253 is, for example but not limited to, using the photoresist layer 2531 formed by the lithography process as a mask, doping the second conductivity type impurities into the second layer 254 to form the first layer 253. In this embodiment, the second conductivity type impurities can be introduced in the form of accelerated ions, such as, but not limited to, ion implantation. Figure 4E As indicated by the dashed arrows in the figure, the second layer 254 is implanted to form the first layer 253. The process for forming the first layer 253 can also be used to simultaneously form another first layer in another device within the semiconductor layer 21'. In one embodiment, the depth to which the first layer 253 extends downward from the upper surface 21a is greater than the depth to which the source electrode 28 extends downward from the upper surface 21a. In one embodiment, the depth to which the second layer 254 extends downward from the upper surface 21a is greater than the depth to which the first layer 253 extends downward from the upper surface 21a.

[0090] Next, see Figure 4F , forming a third layer 255 in the well region 22, and in the vertical direction, the third layer 255 is located below and connected to the upper surface 21a. The third layer 255 has the second conductivity type. The steps of forming the third layer 255 include, for example but not limited to, using the photoresist layer 2551 formed by the lithography process as a mask to dope the second conductivity type impurities into the well region 22 to form the third layer 255. In this embodiment, the second conductivity type impurities can be introduced in the form of accelerated ions, such as, but not limited to, ion implantation. Figure 4F As indicated by the straight dashed arrow in the middle, the third layer 255 is implanted into the well region 22 to form the third layer 255 .

[0091] Continue, see Figure 4G , forming a first concentration peak region 251 in the third layer 255. The first concentration peak region 251 is located in the lower portion of the third layer 255 and is located directly below and in contact with the source electrodes 28 and 28' (refer to Figure 2 and Figure 4I ). The first concentration peak region 251 has the second conductivity type. The step of forming the first concentration peak region 251 includes, for example but not limited to, using the photoresist layer 2511 formed by the lithography process as a mask to dope the second conductivity type impurities into the third layer 255 to form the first concentration peak region 251. In this embodiment, the second conductivity type impurities can be introduced into the third layer 255 in the form of accelerated ions, such as by, for example but not limited to, ion implantation. Figure 4G As indicated by the dotted arrows, the third layer 255 is implanted to form a first peak concentration region 251. In one embodiment, the second conductivity type impurity concentration in the first peak concentration region 251 is higher than that in other regions of the base region 25.

[0092] Afterwards, see Figure 4H , forming a second concentration peak region 252 in the third layer 255. The second concentration peak region 252 is located in the upper portion of the third layer 255, and is located below and connected to the upper surface 21a of the semiconductor layer 21', and the second concentration peak region 252 surrounds and connects to the source 28 and 28' (refer to Figure 2 and Figure 4I The second concentration peak region 252 has the second conductivity type. The step of forming the second concentration peak region 252 includes, for example but not limited to, using the photoresist layer 2521 formed by the lithography process as a mask to dope the second conductivity type impurities into the third layer 255 to form the second concentration peak region 252. In this embodiment, the second conductivity type impurities can be introduced into the third layer 255 in the form of accelerated ions, such as, but not limited to, ion implantation. Figure 4H As indicated by the dotted arrow in the figure, the third layer 255 is implanted to form a second peak concentration region 252. In one embodiment, the second peak concentration region 252 has a higher concentration of the second conductive type impurity than other regions in the base region 25 except the first peak concentration region 251. In one embodiment, the depth of the source 28 extending downward from the upper surface 21a is greater than the depth of the second peak concentration region 252 extending downward from the upper surface 21a (see Figure 4I ).

[0093] It should be noted that the photoresist layers 2511 , 2521 and 2551 can be shared. That is, in one embodiment, the photoresist layer 2551 can be used as the photoresist layers 2511 and 2521 to save process steps and reduce manufacturing costs.

[0094] Next, see Figure 4I , respectively forming the dielectric layers 271 and 271' of the gate electrodes 27 and 27', and the conductive layers 272 and 272' on the upper surface 21a of the semiconductor layer 21', and in the vertical direction (eg Figure 4I As indicated by the solid arrow in the figure, the same below), part of the base region 25 is located directly below the gates 27 and 27' and connected to the gates 27 and 27' to provide a reverse current channel 25a (also called a reverse region) for the high-voltage element 200 during the on-state operation.

[0095] Please continue reading Figure 4IFor example, after forming the dielectric layers 271 and 271' and the conductive layers 272 and 272' of the gate electrodes 27 and 27', lightly doped regions 282 and 282' are formed to provide a conduction channel under the spacer layers 273 and 273' when the high-voltage element 200 is in conduction operation; this is because when the high-voltage element 200 is in conduction operation, the second concentration peak region 252 of the base region 25 under the spacer layers 273 and 273' cannot form a reverse current channel. The method of forming the lightly doped regions 282 and 282' is, for example, to dope the first conductive type impurities into the second concentration peak region 252 of the base region 25 to form the lightly doped regions 282 and 282'. Among them, this embodiment can utilize, for example, but not limited to, ion implantation process steps to implant the first conductive type impurities in the form of accelerated ions, such as Figure 4I As indicated by the straight dotted arrows, the second concentration peak region 252 of the base region 25 is injected to form lightly doped regions 282 and 282'. Since the first conductivity type impurity concentration of the lightly doped regions 282 and 282' is much lower than the first conductivity type impurity concentration of the source electrodes 28 and 28' and the second conductivity type impurity concentration of the base contact 26, the lightly doped regions 282 and 282' can be ignored in the region where they overlap with the source electrodes 28 and 28' and the base contact 26, and will therefore be omitted in subsequent drawings. Figure 4I As shown, spacer layers 273 and 273 ′ are formed outside the sides of the conductive layers 272 and 272 ′, respectively, to form gates 27 and 27 ′.

[0096] Please continue reading Figure 4I .like Figure 4I As shown, in the vertical direction, the source 28 and 28 'and the drain 29 are formed below the upper surface 21a and connected to the upper surface 21a, and the source 28 and the drain 29 are respectively located in the base region 25 below the gate 27 in the channel direction and in the well region 22 away from the base region 25 side, and in the channel direction (as shown in FIG. Figure 4I (Indicated by the horizontal dotted arrow direction in the figure, the same below), the drift region 22a is located between the drain 29 and the base region 25, in the well region 22 close to the upper surface 21a, and is used as a drift current channel for the high-voltage element 200 in the conduction operation. The source 28 and 28' and the drain 29 have a first conductivity type, and the steps of forming the source 28 and 28' and the drain 29 include, for example but not limited to, using a photoresist layer 281 formed by a lithography process as a shield, and doping first conductivity type impurities into the base region 25 and the well region 22, respectively, to form the source 28 and 28' and the drain 29. Among them, this embodiment can use, for example but not limited to, an ion implantation process step to implant the first conductivity type impurities in the form of accelerated ions, such as Figure 4I As indicated by the vertical dashed arrows, the substrate region 25 and the well region 22 are implanted to form source electrodes 28 and 28 ′ and a drain electrode 29 .

[0097] Next, see Figure 4J ,like Figure 4J As shown, a base contact 26 is formed in the base region 25. The base contact 26 has a second conductivity type and serves as an electrical contact of the base region 25. In the vertical direction, the base contact 26 is formed below the upper surface 21a in the base region 25 and is connected to the upper surface 21a. The steps of forming the base contact 26 include, for example but not limited to, using a photoresist layer 261 formed by a lithography process as a mask to dope the second conductivity type impurities into the base region 25 to form the base contact 26. In this embodiment, the second conductivity type impurities can be introduced in the form of accelerated ions, such as by, for example but not limited to, ion implantation. Figure 4J As indicated by the straight dashed arrow in the figure, the substrate region 25 is implanted to form a substrate contact 26. The second conductivity type impurity concentration of the substrate contact 26 is higher than the second conductivity type impurity concentration of the substrate region 25. The second conductivity type impurity concentration of the substrate contact 26 is also lower than the first conductivity type impurity concentration of the source 28.

[0098] Next, see Figure 4K ,like Figure 4K As shown, the photoresist layer 261 is removed and a metal silicide layer (not shown) may be formed on the base contact 26 and the source electrodes 228 and 228 ′ to form the high voltage device 200 .

[0099] In one embodiment, a low-voltage device is formed on substrate 21, and the channel length of the low-voltage device is 0.18 μm. In one embodiment, the metal processing steps of the low-voltage device are also 0.18 μm process steps, that is, the minimum metal wire (plug) width of the low-voltage device is 0.18 μm.

[0100] Figures 5A-5C 2 is a schematic diagram showing an implementation step of forming the third layer 255, the first concentration peak region 251 and the second concentration peak region 252 in a method of manufacturing a high-voltage device 200 according to an embodiment of the present invention. Figures 4A-4E and Figure 4I-4K .

[0101] This embodiment and Figures 4A-4K The difference is that in this embodiment, the third layer 255, the first concentration peak region 251 and the second concentration peak region 252 are formed by a self-alignment process step, wherein the self-alignment process step includes: etching a polysilicon layer to form a conductive layer 272 of the gate 27; and using the conductive layer 272 as a shield, forming the third layer 255, the first concentration peak region 251 and the second concentration peak region 252 by an ion implantation process step.

[0102] like Figure 5A As shown, a dielectric layer 271 and a conductive layer 272 are formed for the gate 27. The dielectric layer 271 and the conductive layer 272 are formed by, for example, etching a silicon dioxide layer and a polysilicon layer respectively to form the dielectric layer 271 and the conductive layer 272. Then, the conductive layer 272 is used as a shield, and the gate 27 can also be formed as shown in FIG. Figure 5A As shown, a photoresist layer 2511 is added as a shield, and the second conductive type impurities are doped into the well region 22 to form a third layer 255. This embodiment can utilize, for example but not limited to, ion implantation process steps to implant the second conductive type impurities in the form of accelerated ions, such as Figure 4F As indicated by the diagonal dashed arrow, the second conductive type impurities are injected into the well region 22 to form the third layer 255. It should be noted that in order to form a portion of the third layer 255 below the gate 27, the direction of the accelerated ion incidence needs to be tilted at a predetermined angle relative to the normal to the well region 22, so that a portion of the second conductive type impurities are injected below the gate 27.

[0103] Continue, see Figure 5B , forming a first concentration peak region 251 in the third layer 255. The first concentration peak region 251 is located in the lower portion of the third layer 255 and is located directly below and in contact with the source electrodes 28 and 28' formed subsequently (refer to Figure 2 and Figure 4I The first concentration peak region 251 has the second conductivity type. The step of forming the first concentration peak region 251 includes, for example but not limited to, using the conductive layer 272 as a shield, or further adding a photoresist layer 2511 formed by a lithography process as a shield, doping the second conductivity type impurities into the third layer 255 to form the first concentration peak region 251. In this embodiment, the second conductivity type impurities can be introduced into the third layer 255 in the form of accelerated ions, such as by, for example but not limited to, ion implantation. Figure 5B As indicated by the diagonal dashed arrow in the figure, the second conductive type impurities are injected into the third layer 255 to form a first peak concentration region 251. In one embodiment, the concentration of the second conductive type impurities in the first peak concentration region 251 is higher than that in other regions of the base region 25. It should be noted that in order to form a portion of the first peak concentration region 251 below the gate 27, the direction of the accelerated ion incidence needs to be tilted at a predetermined angle with respect to the normal to the well region 22, so that a portion of the second conductive type impurities are injected below the gate 27.

[0104] Afterwards, see Figure 5C , forming a second concentration peak region 252 in the third layer 255. The second concentration peak region 252 is located in the upper portion of the third layer 255, and is located below and connected to the upper surface 21a of the semiconductor layer 21'. The second concentration peak region 252 surrounds and connects to the subsequently formed source electrodes 28 and 28' (refer to Figure 2 and Figure 4IThe second concentration peak region 252 has the second conductivity type. The step of forming the second concentration peak region 252 includes, for example but not limited to, using the conductive layer 272 as a shield, or further adding the photoresist layer 2511 formed by the lithography process as a shield, doping the second conductivity type impurities into the third layer 255 to form the second concentration peak region 252. In this embodiment, the second conductivity type impurities can be introduced into the third layer 255 in the form of accelerated ions, such as by, for example but not limited to, ion implantation. Figure 5C As indicated by the diagonal dashed arrow in the figure, the second conductive type impurities are injected into the third layer 255 to form a second peak concentration region 252. In one embodiment, the second peak concentration region 252 has a higher concentration of the second conductive type impurities than other regions of the base region 25 except the first peak concentration region 251. It should be noted that in order to form a portion of the second peak concentration region 252 below the gate 27 to form the reverse current channel 25a, it is necessary to tilt the incident direction of the accelerated ions at a predetermined angle with respect to the normal to the well region 22, so that a portion of the second conductive type impurities are injected below the gate 27 to form the reverse current channel 25a.

[0105] The present invention has been described above with respect to the preferred embodiments. The above description is only to make it easier for those skilled in the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. For example, other process steps or structures, such as deep well regions, can be added without affecting the main characteristics of the component; for example, lithography technology is not limited to mask technology, but can also include electron beam lithography technology. All of these can be derived by analogy based on the teachings of the present invention. In addition, the various embodiments described are not limited to individual applications, but can also be applied in combination, such as but not limited to the use of two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any embodiment of the present invention does not necessarily achieve all purposes or advantages, and therefore, any claim should not be limited to this.

Claims

1. A high voltage component, characterized in that: Include: a semiconductor layer formed on a substrate; a well region having a first conductivity type, wherein the well region is formed in the semiconductor layer; a base region having a second conductivity type, wherein the base region is formed in the semiconductor layer and connected to the well region in a channel direction; a gate formed on the semiconductor layer, wherein a portion of the base region is located directly below and connected to the gate to provide an inversion region of the high-voltage device in a conduction operation; a source and a drain having the first conductivity type, wherein the source and the drain are formed below and connected to an upper surface of the semiconductor layer, wherein the source and the drain are respectively located on either side of the gate, the source is located in the base region, and the drain is located in the well region away from the base region, wherein a portion of the well region is located between the base region and the drain to separate the base region and the drain; and a buried layer, at least a portion of which is formed in the semiconductor layer, wherein the buried layer has the first conductivity type and is located directly below the base region and the well region; Wherein, a first concentration peak region of the base region is located directly below the source electrode and contacts the source electrode; The second conductive type impurity concentration in the first concentration peak region is higher than that in other regions of the base region; wherein a second peak concentration region of the base region is located below and connected to the upper surface of the semiconductor layer, wherein the second peak concentration region surrounds and connects to the source, and the second conductivity type impurity concentration of the second peak concentration region is higher than that of other regions in the base region except the first peak concentration region; The base region further includes a first layer formed by a first process step, wherein the first process step simultaneously forms another first layer in another element in the semiconductor layer, and the depth of the first layer extending downward from the upper surface is greater than that of the source; The base region further includes a second layer formed by a second process step, wherein the second process step simultaneously forms another second layer in another element in the semiconductor layer, and the depth of the second layer extending downward from the upper surface is greater than that of the first layer.

2. The high voltage component according to claim 1, wherein: The invention also includes a drift oxide region formed above the semiconductor layer, wherein a portion of the gate is located directly above the drift oxide region and connected to the drift oxide region.

3. The high voltage component according to claim 2, wherein: The drift oxidation region includes a regional oxidation structure, a shallow trench insulation structure or a chemical vapor deposition oxidation structure.

4. The high voltage component according to claim 1, wherein: The depth of the source electrode extending downward from the upper surface is greater than the second concentration peak region.

5. The high voltage component according to claim 1, wherein: The semiconductor layer is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm.

6. The high voltage component according to claim 3, wherein: The drift oxidation region includes the chemical vapor deposition oxidation structure, and the chemical vapor deposition oxidation structure has a thickness of 7. The high voltage component according to claim 1, wherein: The high voltage component is a lateral diffused metal oxide semiconductor component with a gate drive voltage of 3.3V and a gate oxide layer thickness of 8. The high voltage component according to claim 7, wherein: A low voltage element is formed on the substrate, and a channel length of the low voltage element is 0.18 μm.

9. The high voltage component according to claim 1, wherein: The first concentration peak region is formed by a self-alignment process step, wherein the self-alignment process step includes: etching a polysilicon layer to form a conductive layer of the gate; and using the conductive layer as a shield to form the first concentration peak region by an ion implantation process step.

10. A method for manufacturing a high-voltage component, characterized in that: Include: forming a semiconductor layer on a substrate; forming a well region in the semiconductor layer, wherein the well region has a first conductivity type; forming a base region in the semiconductor layer, wherein the base region has a second conductivity type and is connected to the well region in a channel direction; forming a gate on the semiconductor layer, with a portion of the base region being located directly below and connected to the gate to provide an inversion region for the high-voltage device in a conduction operation; forming a source electrode and a drain electrode below an upper surface of the semiconductor layer and connecting the source electrode and the drain electrode to the upper surface, wherein the source electrode and the drain electrode have a first conductivity type, wherein the source electrode and the drain electrode are respectively located on either side of the gate electrode, the source electrode is located in the base region, and the drain electrode is located in the well region away from the base region, wherein a portion of the well region is located between the base region and the drain electrode to separate the base region and the drain electrode; and forming a buried layer, wherein at least a portion of the buried layer is formed in the semiconductor layer, the buried layer has the first conductivity type, and the buried layer is located directly below the base region and the well region; Wherein, a first concentration peak region of the base region is located directly below the source electrode and contacts the source electrode; The second conductive type impurity concentration in the first concentration peak region is higher than that in other regions of the base region; wherein a second peak concentration region of the base region is located below and connected to the upper surface of the semiconductor layer, wherein the second peak concentration region surrounds and connects to the source, and the second conductivity type impurity concentration of the second peak concentration region is higher than that of other regions in the base region except the first peak concentration region; The base region further includes a first layer formed by a first process step, wherein the first process step simultaneously forms another first layer in another element in the semiconductor layer, and the depth of the first layer extending downward from the upper surface is greater than that of the source; The base region further includes a second layer formed by a second process step, wherein the second process step simultaneously forms another second layer in another element in the semiconductor layer, and the depth of the second layer extending downward from the upper surface is greater than that of the first layer.

11. The method for manufacturing a high-voltage element according to claim 10, wherein: The method further includes forming a drift oxide region above the semiconductor layer, wherein a portion of the gate is located directly above the drift oxide region and connected to the drift oxide region.

12. The method for manufacturing a high-voltage element according to claim 11, wherein: The drift oxidation region includes a regional oxidation structure, a shallow trench insulation structure or a chemical vapor deposition oxidation structure.

13. The method for manufacturing a high-voltage component according to claim 10, wherein: The depth of the source electrode extending downward from the upper surface is greater than the second concentration peak region.

14. The method for manufacturing a high-voltage element according to claim 10, wherein: The semiconductor layer is a P-type epitaxial silicon layer and has a resistance of 45 Ohm-cm.

15. The method for manufacturing a high-voltage component according to claim 12, wherein: The drift oxidation region includes the chemical vapor deposition oxidation structure, and the chemical vapor deposition oxidation structure has a thickness of 16. The method for manufacturing a high-voltage component according to claim 10, wherein: The high voltage component is a lateral diffused metal oxide semiconductor component with a gate drive voltage of 3.3V and a gate oxide layer thickness of 17. The method for manufacturing a high-voltage component according to claim 16, wherein: The channel length of the LDMOS device is 0.18 μm.

18. The method for manufacturing a high-voltage component according to claim 10, wherein: The first concentration peak region is formed by a self-alignment process step, wherein the self-alignment process step includes: etching a polysilicon layer to form a conductive layer of the gate; and using the conductive layer as a shield to form the first concentration peak region by an ion implantation process step.

19. The method for manufacturing a high-voltage component according to claim 10, wherein: A low voltage element is formed on the substrate, and a channel length of the low voltage element is 0.18 μm.

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