Semiconductor light emitting device

Abstract

The semiconductor light-emitting device of the embodiment of the present application comprises a semiconductor substrate and a light-emitting layer. The light-emitting layer comprises a quantum well layer and a barrier layer alternately stacked on the semiconductor substrate. The quantum well layer comprises a first semiconductor mixed crystal having a lattice constant greater than that of the semiconductor substrate, and has a first strain amount which is the product of a first strain rate and its layer thickness. The barrier layer comprises a second mixed crystal having a lattice constant smaller than that of the semiconductor substrate, and has a second strain amount which is the product of a second strain rate and its layer thickness. The quantum well layer and the barrier layer are arranged in such a way that the first strain amount is greater than the second strain amount.

Description

[0001] Related Applications

[0002] This application claims the priority of Japanese Patent Application No. 2021-5297 (filing date: January 15, 2021) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor light emitting device. Background Art

[0004] Optical couplers that optically couple infrared elements and silicon photodiodes are now widely used. Such light-emitting elements are required to have high light-emitting efficiency. Summary of the invention

[0005] Embodiments provide a semiconductor light emitting device having improved light emitting efficiency.

[0006] The semiconductor light emitting device of the embodiment comprises a semiconductor substrate and a light emitting layer provided on the semiconductor substrate. The light emitting layer comprises a quantum well layer and a barrier layer alternately stacked in a first direction from the semiconductor substrate toward the light emitting layer. The quantum well layer comprises a first semiconductor mixed crystal having a lattice constant greater than that of the semiconductor substrate, has a first layer thickness in the first direction, and has a first strain amount, the first strain amount being the product of a first strain rate obtained by dividing the absolute value of the difference between the lattice spacing of the first semiconductor mixed crystal in the first direction and the lattice constant of the substrate by the lattice spacing of the first semiconductor mixed crystal and the first layer thickness. The barrier layer comprises a second semiconductor mixed crystal having a lattice constant smaller than that of the semiconductor substrate, has a second layer thickness in the first direction, and has a second strain amount, the second strain amount being the product of a second strain rate obtained by dividing the absolute value of the difference between the lattice spacing of the second semiconductor mixed crystal in the first direction and the lattice constant of the substrate by the lattice spacing of the second semiconductor mixed crystal and the second layer thickness. The quantum well layer and the barrier layer are provided so that the first strain amount is larger than the second strain amount. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 (a) and (b) are schematic cross-sectional views of semiconductor light emitting devices according to embodiments.

[0008] Figure 2 This is a graph showing the relationship between the lattice constant and the energy band gap of GaAs-based direct transition compound semiconductor materials.

[0009] Figure 3(a) to (c) are transmission electron microscope images (TEM images) and lattice spacing images of the light emitting layer according to the embodiment.

[0010] Figure 4 (a) and (b) are diagrams showing X-ray diffraction spectra of the light-emitting layer according to the embodiment.

[0011] Figure 5 This is a graph showing the relationship between the barrier layer thickness of the light-emitting layer and the position of the zero-order peak of X-ray diffraction according to the embodiment.

[0012] Figure 6 (a) and (b) are graphs showing the oxygen concentration contained in the epitaxial growth layer of the semiconductor light emitting device according to the embodiment.

[0013] Figure 7 It is a schematic cross-sectional view showing the structure of a semiconductor light emitting device according to an embodiment.

[0014] Figure 8 This is a graph showing the relationship between the light output of the semiconductor light emitting device according to the embodiment and the thickness of the barrier layer.

[0015] Fig. 9 It is a schematic cross-sectional view of a light-emitting layer showing a modification of the embodiment. DETAILED DESCRIPTION

[0016] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The same parts in the drawings are marked with the same symbols and their detailed description is appropriately omitted, and the different parts are described. In addition, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, etc. are not necessarily limited to the same as in reality. In addition, even when the same parts are represented, the mutual sizes or ratios are sometimes represented differently according to the drawings.

[0017] Figure 1 (a) and (b) are schematic cross-sectional views showing a semiconductor light emitting device 1 according to an embodiment. Figure 1 (a) shows the structure of a semiconductor layer epitaxially grown on an n-type GaAs substrate. Figure 1 (b) shows the structure of the light emitting layer. The semiconductor light emitting device 1 is an infrared diode (LED).

[0018] like Figure 1 As shown in (a), the semiconductor light emitting device 1 includes an n-type GaAs substrate (hereinafter referred to as GaAs substrate 101 ), an n-type cladding layer 102 , a light emitting layer 103 , a p-type cladding layer 104 , and a p-type contact layer 105 .

[0019] The n-type cladding layer 102 is provided on the GaAs substrate 101. The n-type cladding layer 102 includes, for example, Al 0.5 Ga0.5 As represents an AlGaAs mixed crystal.

[0020] The light emitting layer 103 is provided between the n-type cladding layer 102 and the p-type cladding layer 104. The light emitting layer 103 has a multi-quantum well structure (Multi-Quantum Well: MQW).

[0021] The p-type cladding layer 104 is provided on the light emitting layer 103. The p-type cladding layer 104 includes, for example, a composition of Al 0.5 Ga 0.5 As represents an AlGaAs mixed crystal.

[0022] The p-type contact layer 105 is provided on the p-type cladding layer 104. The p-type contact layer 105 is, for example, a GaAs layer. The p-type contact layer 105 is the outermost layer and is provided to form an electrode.

[0023] like Figure 1 As shown in (b), the light emitting layer 103 has an MQW structure and includes quantum well layers 103a and barrier layers 103b. The quantum well layers 103a and barrier layers 103b are alternately stacked, and the quantum well layers 103a are located between adjacent barrier layers 103b.

[0024] The quantum well layer 103a includes, for example, a composition of In 0.2 Ga 0.8 The barrier layer 103b includes, for example, an InGaAs mixed crystal having a composition formula of 0.9 P 0.1 Represents GaAsP mixed crystal.

[0025] The light emitting layer 103 includes, for example, four quantum well layers 103 a. The quantum well layer 103 a has a thickness of, for example, 5.8 nanometers (nm) and emits infrared light with a wavelength of 950 nm. Hereinafter, “thickness” refers to the thickness in the stacking direction from the GaAs substrate 101 to the p-type contact layer 105 .

[0026] Figure 2 This is a graph showing the relationship between the lattice constant and the energy band gap of GaAs-based direct transition compound semiconductor materials. Figure 2 The relationship between the lattice constant and the energy band gap corresponding to the respective compositions of the AlGaAs mixed crystal, the GaAsP mixed crystal, and the InGaAs mixed crystal is shown with GaAs as the center.

[0027] The composition formula In X Ga 1-XFor an InGaAs mixed crystal represented by As(0<X<1), as the In composition "X" increases, the energy band gap narrows and the lattice constant increases. The energy band gap of the InGaAs mixed crystal is narrower than that of GaAs. In addition, the lattice constant of the InGaAs mixed crystal is larger than that of GaAs.

[0028] For example, the InGaAs mixed crystal of the quantum well layer 103a has an In composition of X=0.2 and a lattice constant of 5.73 Å. , energy band gap 1.14 electron volts (eV).

[0029] The composition formula is GaAs 1-Y P Y For the GaAsP mixed crystal represented by (0<Y<1), as the P composition "Y" increases, the energy band gap becomes wider and the lattice constant becomes smaller. The energy band gap of the GaAsP mixed crystal is wider than the energy band gap of GaAs. In addition, the lattice constant of the GaAsP mixed crystal is smaller than the lattice constant of GaAs.

[0030] For example, the GaAsP mixed crystal of the barrier layer 103 b has a P composition of Y=0.1 and a lattice constant Energy band gap 1.51eV.

[0031] The composition formula is Al Z Ga 1-Z For AlGaAs mixed crystal represented by As(0<Z<1), the energy band gap widens as the Al composition "Z" increases. The energy band gap of AlGaAs mixed crystal is wider than that of GaAs. On the other hand, the change in the lattice constant of AlGaAs is small relative to the change in the Al composition "Z".

[0032] Figure 2 The InGaAs mixed crystal shown is now widely used as a light-emitting material for infrared elements. For example, it is a light-emitting material for a light-emitting diode (LED) constituting an optical coupler. The emission wavelength of the LED used for the optical coupler is adjusted to a wavelength region where the light sensitivity of the Si-based photodiode (PD) is high, such as around 1000 nm.

[0033] For example, in the case of the light-emitting layer 103 having the MQW structure, when an InGaAs mixed crystal is used in the quantum well layer 103a, the In composition X of the InGaAs mixed crystal is adjusted to a range of 0.15 to 0.2. The lattice constant of the InGaAs mixed crystal of such a composition is, for example, the closest to the lattice constant of GaAs among the compound semiconductor materials that can actually be used as an epitaxial growth substrate. Therefore, the light-emitting layer 103 is preferably formed on a GaAs substrate. In addition, the barrier layer 103b constituting the MQW and other constituent materials of the LED are also formed using compound semiconductor mixed crystals such as GaAsP and AlGaAs whose lattice constant is close to that of the GaAs substrate.

[0034] As one of the methods for producing these compound semiconductor mixed crystals, the metal organic chemical vapor deposition (MOCVD) method is used. In the MOCVD method, the GaAs substrate 101 is heated, and various raw materials for crystal growth, such as at least two of TMI (trimethylindium: (CH)3In), TMG (trimethylgallium: (CH)3Ga) and TMA (trimethylaluminum: (CH)3Al), and at least one of arsine (AsH3) and phosphine (PH3) are supplied to the substrate surface and thermally decomposed. In this way, the desired compound semiconductor mixed crystal can be deposited on the GaAs substrate 101. For example, while controlling the layer thickness of each compound semiconductor mixed crystal according to the supply amount and supply time of the raw materials, the deposition is carried out sequentially, thereby forming the basic structure of the LED (refer to Figure 1 ).

[0035] However, even if the lattice constant of the InGaAs mixed crystal is close to that of the GaAs substrate, it is not consistent, and there is a lattice mismatch between the two. Therefore, the lattice strain caused by the lattice mismatch accumulates in the deposition of the InGaAs mixed crystal, and increases with the thickness of the deposited layer. When the lattice strain in the deposited layer exceeds the critical point, the lattice relaxes and crystal defects are generated. Therefore, the luminescence characteristics of the light-emitting layer 103 are degraded.

[0036] In the embodiment, in order to prevent the degradation of the light emitting characteristics, a strain-compensated MQW structure is used for the light emitting layer 103. The strain-compensated MQW structure includes, for example, a quantum well layer 103a of InGaAs mixed crystal and a barrier layer 103b of GaAsP mixed crystal.

[0037] like Figure 2As shown in FIG. 1 , the GaAsP mixed crystal has a wider energy band gap than the InGaAs mixed crystal, and is therefore suitable as a material for the barrier layer 103b. In addition, the GaAsP mixed crystal has a lattice mismatch with respect to the GaAs substrate in the opposite direction to the InGaAs mixed crystal. By arranging such a GaAsP mixed crystal and an InGaAs mixed crystal adjacent to each other, the strain of the two caused by the lattice mismatch with respect to the GaAs substrate can be eliminated.

[0038] Generally, when forming such a strain-compensating MQW structure, the strain amount depending on the thickness of each of the quantum well layer 103a and the barrier layer 103b is balanced. The strain amount is determined by, for example, the lattice constant difference between the GaAs substrate and the compound semiconductor mixed crystal and the layer thickness of the compound semiconductor mixed crystal.

[0039] The composition X and thickness of the InGaAs mixed crystal in the quantum well layer 103a are set based on the emission wavelength of the light-emitting layer 103. In addition, the composition Y of the GaAsP mixed crystal in the barrier layer 103b is set in a manner that optimizes the carrier confinement effect of the quantum well layer 103a. Therefore, the strain amount at the quantum well layer 103a and the barrier layer 103b is controlled by the thickness of the barrier layer 103b. At this time, the thickness of the barrier layer 103b is set in a manner that falls within a range where lattice relaxation caused by excessive strain does not occur. In other words, the thickness of the barrier layer 103b is set within a range where the lattice of the light-emitting layer 103 undergoes elastic deformation.

[0040] In this way, even if the compound semiconductor mixed crystal has a large lattice strain relative to the GaAs substrate 101, by combining it with other compound semiconductor mixed crystals that compensate for the strain, it is possible to design an MQW structure that includes a strain that does not exceed the critical point of elastic deformation of the lattice, and the luminescence characteristics can be improved. However, this strain compensation structure is strictly designed and includes structural parameters with a narrow allowable range. Therefore, deviations from the design values ​​caused by unevenness and changes in the LED manufacturing process will cause changes and degradation in the luminescence characteristics. The semiconductor light-emitting device 1 of the embodiment has a structure that can solve this problem.

[0041] Example

[0042] The semiconductor light emitting device 1 includes a barrier layer 103b having a layer thickness d bar The strain-compensated MQW structure varies from 9.1nm, 20nm and 30nm.

[0043] Figure 3 (a) is a cross-sectional TEM image of the light-emitting layer 103 .

[0044] Figure 3(b) and (c) are heat maps showing the lattice spacing after visualization using Fast Fourier Transform Mapping (FFTM). Figure 3 The lattice spacing shown in (b) and (c) is determined by Figure 3 The light emitting layer 103 shown in this example has a layer thickness of d bar =30nm barrier layer 103b.

[0045] like Figure 3 As shown in (a), the light emitting layer 103 includes four quantum well layers 103a. The barrier layers 103b are arranged above and below each quantum well layer 103a. It can be seen that the boundary between the quantum well layer 103a and the barrier layer 103b is flat and no misfit dislocation occurs.

[0046] Figure 3 (b) shows the lattice spacing in the <002> direction. Figure 3 (c) shows the lattice spacing in the <220> direction. Figure 3 The "InGaAs" shown in (b) and (c) is the InGaAs of the quantum well layer 103a. 0.2 Ga 0.8 As mixed crystal, "GaAsP" is GaAs of the barrier layer 103b 0.9 P 0.1 In addition, “AlGaAs” is Al in the n-type cladding layer 102 and the p-type cladding layer 104. 0.5 Ga 0.5 As mixed crystal.

[0047] like Figure 3 As shown in (b), in the <002> direction, relative to Al 0.5 Ga 0.5 As mixed crystal lattice spacing, In 0.2 Ga 0.8 As mixed crystal has wide lattice spacing, GaAs 0.9 P 0.1 The lattice spacing of mixed crystals is narrow.

[0048] At once Figure 3 In the direction of <220> shown in (c), 0.2 Ga 0.8 As mixed crystal, GaAs 0.9 P 0.1 Mixed crystal and Al 0.5 Ga 0.5 The lattice spacing of As mixed crystals is regular and roughly constant. 0.5 Ga 0.5The As mixed crystal can be considered to be lattice-matched with GaAs. Therefore, the lattice spacing on the crystal plane perpendicular to the stacking direction of the quantum well layer 103 a and the barrier layer 103 b can be considered to be matched with the lattice spacing of the GaAs substrate 101 .

[0049] In contrast, the lattice spacing of the quantum well layer 103a and the barrier layer 103b in the stacking direction does not coincide with the lattice spacing of the GaAs substrate 101 (see Figure 3 (b)), the lattice spacing of the quantum well layer 103a in the stacking direction is wider than the lattice spacing of the GaAs substrate 101. In addition, the lattice spacing of the barrier layer 103b in the stacking direction is narrower than the lattice spacing of the GaAs substrate 101. That is, the lattice deformation of the quantum well layer 103a and the barrier layer 103b relative to the GaAs substrate 101 is in the opposite direction in the stacking direction, and they are stacked in a manner to compensate for the strain relative to the GaAs substrate 101.

[0050] Table 1 shows the In 0.2 Ga 0.8 As mixed crystal and GaAs of barrier layer 103b 0.9 P 0.1 Physical property values ​​of mixed crystals. The physical property values ​​of the ternary mixed crystals shown in the table are values ​​obtained by proportionally allocating the values ​​of the binary materials (InAs, GaAs, GaP) as the respective terminal compositions based on Vegard's law.

[0051] Table 1

[0052]

[0053] The relationship between the elastic constant and the lattice deformation amount of a compound semiconductor mixed crystal is expressed by the following equation.

[0054] Δa / a s =(C 11 / (C 11 +2×C 12 ))×(Δa ⊥ / a s )

[0055] Here, a s is the lattice constant of the GaAs substrate 101. Δa is the lattice constant of the compound semiconductor mixed crystal without lattice deformation and the lattice constant a of the GaAs substrate s The difference between ⊥ is the lattice spacing in the stacking direction of the compound semiconductor mixed crystal after lattice deformation and the lattice constant a of the GaAs substrate 101 s The difference. ij is the elastic stiffness constant.

[0056] The strain rate ε of the compound semiconductor mixed crystal with respect to the GaAs substrate is expressed as the lattice spacing a in the stacking direction of the compound semiconductor mixed crystal. ⊥ The lattice constant a of the GaAs substrate s The absolute value of the difference divided by a ⊥ The obtained value is defined by the following formula.

[0057] ε=|a ⊥ -a s | / a ⊥

[0058] The amount of strain in the stacking direction of the compound semiconductor crystal is represented by, for example, the product of the strain rate ε and the layer thickness. For example, if the strain rate at the quantum well layer 103a is ε well , with the strain rate at the barrier layer 103b being ε bar When , the balance of strain between the quantum well layer 103a and the barrier layer 103b is defined by the following equation.

[0059] ε well ×d well =ε bar ×d bar

[0060] Here, d well is the thickness of the quantum well layer 103a, d bar For example, in order to obtain a light emission wavelength of 950 nm, the thickness of the barrier layer 103b is 100 nm. 0.2 Ga 0.8 As mixed crystal layer thickness d well GaAs under strain balance when the thickness is 5.8nm 0.9 P 0.1 The thickness d of the mixed crystal (barrier layer 103b) bar Becomes to 22.8nm.

[0061] Figure 4 (a) and (b) show X-ray diffraction spectra of the light-emitting layer 103 . Figure 4 (b) Yes Figure 4 (a) is a diagram in which the horizontal axis of the X-ray diffraction spectrum shown is enlarged. Figure 4 (a) and (b) show the thickness d of the barrier layer 103b. bar The X-ray diffraction evaluation results were set to three structures of 9.1 nm, 20 nm, and 30 nm.

[0062] like Figure 4 As shown in (a), the X-ray diffraction spectrum includes the diffraction peaks of the GaAs substrate 101, the Al contained in the p-type cladding layer 102 and the n-type cladding layer 104, and the 0.5 Ga 0.5Diffraction peaks of As mixed crystals and multiple satellite peaks caused by MQW structure.

[0063] The satellite peaks have an interval (period) corresponding to the period of the MQW structure. For example, the period of the satellite peaks increases with the thickness d of the barrier layer 103b. bar Thickening and narrowing.

[0064] based on Figure 4 The period of the satellite peak in (a), In 0.2 Ga 0.8 As mixed crystal and GaAs 0.9 P 0.1 The lattice constant of the mixed crystal (see Table 1) can identify a zero-order peak among a plurality of satellite peaks. The zero-order peak corresponds to the average lattice spacing of the quantum well layer 103a and the barrier layer 103b.

[0065] Figure 4 The arrow in (b) shows the zero-order peak P0 of the diffraction spectrum. Figure 4 As shown in (b), the position of the zero-order peak P0 and the thickness d of each layer of the barrier layer 103b are bar Change accordingly.

[0066] Figure 5 is the thickness d of the barrier layer 103b bar The relationship between the position of the zero-order peak P0 and the Figure 4 The thickness of each barrier shown in (b) is d bar The position of the zero-order peak P0 at φ1 and the barrier layer thickness (calculated value) when the peak position of the GaAs substrate 101 coincides with the zero-order peak P0 are plotted.

[0067] like Figure 5 As shown in the figure, the diffraction peak of the GaAs substrate 101 is located at the layer thickness d of the barrier layer 103b. bar = 20nm when the zero-order peak position and layer thickness d bar = between the positions of the zero-order peaks at 30 nm.

[0068] When the zero-order peak of the MQW structure overlaps with the diffraction peak of the GaAs substrate 101 (relative angle: 0 sec), it can be said that the strain amount of the quantum well layer 103 a and the strain amount of the barrier layer 103 b are in a completely strain-compensated relationship.

[0069] The thickness d of the layer where the zero-order peak of the MQW structure overlaps with the diffraction peak of the GaAs substrate 101 ba For example, by Figure 5 The thickness of the connection barrier layer in bar = 20 nm plotted position and d bar =30nm plotted position line. Figure 5The thickness d at which the strain of the quantum well layer 103a and the strain of the barrier layer 103b are in a completely strain-compensated relationship is bar This value is consistent with the layer thickness d obtained from the strain balance condition. bar = 22.8nm is well consistent. Figure 5 The plotted position of the barrier layer thickness of 9.1 nm shown in FIG. 1 does not conform to the relationship of complete strain compensation, which indicates that the strain between the quantum well layer 103 a and the barrier layer 103 b is seriously unbalanced.

[0070] Figure 6 (a) and (b) are SIMS (Secondary Ion Mass Spectrometry) graphs showing the distribution of oxygen (O) doped into the n-type cladding layer 102 , the light emitting layer 103 , and the p-type cladding layer 104 . Figure 6 (b) is magnification Figure 6 The horizontal axis of (a) is a graph showing the oxygen distribution near the light-emitting layer 103 .

[0071] like Figure 6 As shown in (a), oxygen is doped into the n-type cladding layer 102 and the p-type cladding layer 104 at a higher concentration than that in the light emitting layer 103. Since the n-type cladding layer 102 and the p-type cladding layer 104 are Al containing aluminum (Al) having a high affinity for oxygen, 0.5 Ga 0.5 As mixed crystal, it is easy to be doped with oxygen atoms due to Al-O bonds during epitaxial growth. Under the growth conditions of the embodiment, the n-type cladding layer 102 and the p-type cladding layer 104 contain 3×10 16 ~5×10 16 cm -3 Concentration of oxygen.

[0072] like Figure 6 As shown in (b), the light-emitting layer 103 contains about 1×10 16 cm -3 The detection limit of oxygen in this SIMS measurement is 2.5×10 15 cm -3 , oxygen concentrations below this cannot be detected. Figure 6 The oxygen concentration of the light-emitting layer 103 shown in (b) is a value with significant difference.

[0073] Normally, the light emitting layer 103 is formed without doping oxygen that forms a non-radiative recombination center. In this embodiment, appropriate raw material supply conditions are set in consideration of the raw material consumption efficiency in epitaxial growth using the MOCVD method, and the growth conditions of the InGaAs mixed crystal are optimized, resulting in a lower growth temperature. Therefore, oxygen doping occurs in the light emitting layer 103.

[0074] Figure 7 It is a schematic cross-sectional view illustrating the structure of the semiconductor light emitting device 1 .

[0075] like Figure 7 As shown, the semiconductor light emitting device 1 includes a mesa-type light emitting body 110 , an n-side electrode 601 , and a p-side electrode 602 .

[0076] The mesa-type light emitter 110 is disposed on a GaAs substrate 101. The mesa-type light emitter 110 includes an n-type cladding layer 102, a light-emitting layer 103, a p-type cladding layer 104, and a p-type contact layer 105.

[0077] The n-side electrode 601 is provided on the surface of the GaAs substrate 101 and is electrically connected to the GaAs substrate 101. The n-side electrode 601 and the mesa-type light emitter 110 are arranged on the surface of the GaAs substrate 101.

[0078] The p-side electrode 602 is provided on the uppermost p-type contact layer 105 and is electrically connected to the p-type contact layer 105. The p-side electrode 602 is provided so as to reflect infrared light emitted from the light emitting layer 103 and propagate in the direction of the GaAs substrate 101.

[0079] The semiconductor light emitting device 1 is configured so that a current flows between the p-side electrode 602 and the n-side electrode 601 and infrared light generated by the recombination of electrons and holes injected into the light emitting layer 103 is radiated to the outside. The infrared light radiated from the light emitting layer 103 is emitted to the outside from the back side of the GaAs substrate 101.

[0080] Figure 8 is the relationship between the light output of the semiconductor light emitting device 1 and the thickness d of the barrier layer 103b. bar The horizontal axis is the layer thickness d bar The vertical axis represents light output, and the thickness d at which the strain of the quantum well layer 103a and the strain of the barrier layer 103b reach equilibrium is bar The light output at 40° is normalized.

[0081] Figure 8 The solid line shown in shows the light output of the semiconductor light emitting device 1. Figure 8 The dotted line in shows the light output of the semiconductor light emitting device of the comparative example. The semiconductor light emitting device of the comparative example has the same structure as the semiconductor light emitting device 1, but the oxygen concentration of the light emitting layer 103 is below the detection limit of the present SIMS measurement.

[0082] like Figure 8 As shown, for the semiconductor light emitting device of the comparative example, the layer thickness (dbar =22.8nm), the light output becomes the maximum. In contrast, for the semiconductor light emitting device 1, when the layer thickness of the barrier layer is bar The ratio is the layer thickness (d bar =22.8 nm), the light output becomes the maximum. In addition, the peak of the light output characteristic has a wider width than the peak of the light output characteristic of the semiconductor light emitting device of the comparative example.

[0083] Furthermore, the thickness d of the barrier layer 103b is bar When the thickness is less than 10 nm, a sharp drop in light output is observed. This is believed to be due to the X-ray diffraction evaluation results (see Figure 5 ) the strain in the MQW structure is seriously unbalanced, causing the luminescence properties to deteriorate.

[0084] according to Figure 8 It can be seen that, in the semiconductor light emitting device 1, for example, the thickness (d bar =22.8nm) 0.53 to 1.0 times the layer thickness d bar In other words, the thickness d of the barrier layer 103b is bar It is preferable to set the stacking direction strain rate ε in the quantum well layer 103a to well With layer thickness d well The product of the two divided by the stacking direction strain rate ε at the barrier layer 103b bar The obtained value is in the range of 0.53 to 1.0 times.

[0085] In addition, by changing the P composition "Y" of the GaAsP mixed crystal of the barrier layer 103b, the strain balance of the MQW structure can also be changed. For example, when the P composition "Y" is changed in the range of 0.053 to 0.1, the thickness d of the barrier layer 103b can be changed in the range of 0.53 to 1.0 times the value at which the strain amount reaches equilibrium. bar That is, by fixing the thickness of the barrier layer 103b at d bar =22.8 nm and setting the P composition “Y” of the GaAsP mixed crystal to a range of 0.053 to 0.1 can increase the light output of the semiconductor light emitting device 1 .

[0086] In the above-mentioned range of the layer thickness dbar at the barrier layer 103b and the range of the P composition "Y" of the GaAsP mixed crystal, the strain of the quantum well layer 103a and the strain of the barrier layer 103b cannot reach a balance, and the strain of the quantum well layer 103a is larger than the strain of the barrier layer 103b (ε well ×d well >ε bar ×d bar). In this way, the light output of the semiconductor light emitting device 1 is also affected by factors other than the balance of the strain amount (strain compensation) in the MQW structure.

[0087] Figure 8 The light output characteristics of the semiconductor light emitting device 1 and the semiconductor light emitting device of the comparative example show the influence of oxygen in the compound semiconductor mixed crystal. That is, the light emission characteristics change depending on the amount of oxygen doped in the light emitting layer 103.

[0088] It is known that the presence of oxygen in a compound semiconductor mixed crystal affects the hardness of the crystal. For example, it is believed that oxygen in the mixed crystal changes the elastic constant, thereby contributing to improving the light emission output in a range where the strain between the quantum well layer 103a and the barrier layer 103b is unbalanced.

[0089] On the other hand, oxygen in the crystal forms non-radiative centers. Therefore, the presence of a large amount of oxygen can deteriorate the luminescence properties. According to the inventors' in-depth experiments, when the oxygen concentration in the crystal exceeds 1×10 17 cm -3 When the light emission characteristics are degraded due to non-radiative recombination, the degradation becomes significant. Therefore, in order to increase the light output by oxygen in the crystal, it is desirable to control the oxygen concentration to 1×10 17 cm -3 the following.

[0090] The semiconductor light emitting device 1 of the embodiment can improve light output in a wider range than the allowable range of parameters for strain compensation based on the MQW structure, thereby suppressing the influence of variations and fluctuations in the manufacturing process of the semiconductor light emitting device 1 and achieving stable manufacturing.

[0091] Fig. 9 2 is a schematic cross-sectional view showing a light emitting layer 203 according to a modification of the embodiment. The light emitting layer 203 has an MQW structure including a quantum well layer 203a and a barrier layer 203b.

[0092] The quantum well layer 203a includes an InGaAs mixed crystal. The In composition "X" of the InGaAs mixed crystal is, for example, 0.2. The quantum well layer 203a has a layer thickness of, for example, 5.8 nanometers (nm), and emits infrared light with a wavelength of 950 nm.

[0093] The barrier layer 203b comprises a composition of Al Z Ga 1-Z As 1-Y P Y(0<Z<1, 0<Y<1). For the AlGaAsP mixed crystal in which Al is added to the GaAsP mixed crystal, the lattice constant will not be greatly changed compared with the GaAsP mixed crystal with the same P composition "Y", and the energy band gap can be widened. Therefore, it is possible to expand the energy band gap of the barrier layer 203b while maintaining the balance of the strain between the quantum well layer 203a and the barrier layer 203b. As a result, the carrier confinement effect of the quantum well layer 203a can be improved. Furthermore, by adding Al, it becomes easy to dope oxygen into the crystal. Therefore, it is easy to increase the oxygen concentration in the crystal and increase the light output. The barrier layer 203b, for example, contains a composition of Al 0.1 Ga 0.9 As 0.9 P 0.1 AlGaAsP mixed crystal represented by (Al composition Z=0.1, P composition Y=0.1).

[0094] have Fig. 9 The semiconductor light emitting device of the light emitting layer 203 is Figure 8 The range of barrier layer thickness shown has the same light output as the semiconductor light emitting device 1. In addition, the oxygen concentration in the light emitting layer 203 is 2.5×10 15 ~1.0×10 17 cm -3 range.

[0095] This embodiment is not limited to the above example. For example, GaAs 1-Y P Y Barrier layer 103b and Al Z Ga 1-Z As 1-Y P Y The P composition "Y" of the barrier layer 203b is determined by taking into account the strain balance with the InGaAs quantum well layers 103a and 203a and the range of oxygen concentration and the layer thickness d. bar Also, In X Ga 1-X The In composition "X" and the layer thickness of the As quantum well layers 103a and 203a are appropriately set, for example, within the range of a light emission wavelength of 900 nm to 1000 nm. Here, 900 nm is the absorption end wavelength of the GaAs substrate, and 1000 nm is the long wavelength end of the wavelength region in which the Si-based PD has light sensitivity. Furthermore, with respect to the InGaAs mixed crystal set in the quantum well layers 103a and 203a, the layer thickness d of the barrier layers 103b and 203b is set to bar The layer thickness d is set to balance the strain amount. bar The range is 0.53 to 1.0 times.

[0096] Several embodiments of the present invention have been described, but these embodiments are shown as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the present invention. These embodiments or their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor light emitting device comprising a semiconductor substrate and a light emitting layer provided on the semiconductor substrate, in, The light emitting layer includes quantum well layers and barrier layers alternately stacked in a first direction from the semiconductor substrate toward the light emitting layer. The quantum well layer includes a first semiconductor mixed crystal having a lattice constant greater than a lattice constant of the semiconductor substrate, and has a first layer thickness and a first strain amount in the first direction, the first strain amount being the product of the first layer thickness and the first strain rate, the first strain rate being the absolute value of the difference between the lattice spacing of the first semiconductor mixed crystal in the first direction and the lattice constant of the substrate divided by the lattice spacing of the first semiconductor mixed crystal, The barrier layer includes a second semiconductor mixed crystal having a lattice constant smaller than a lattice constant of the semiconductor substrate, and has a second layer thickness and a second strain amount in the first direction, the second strain amount being the product of the second layer thickness and a second strain rate, the second strain rate being the absolute value of the difference between the lattice spacing of the second semiconductor mixed crystal in the first direction and the lattice constant of the substrate divided by the lattice spacing of the second semiconductor mixed crystal, The quantum well layer and the barrier layer are provided so that the first strain amount is larger than the second strain amount.

2. The semiconductor light emitting device according to claim 1, wherein: The first semiconductor mixed crystal is composed of a composition formula In X Ga 1-X As represents an InGaAs mixed crystal with 0<X<1, The second semiconductor mixed crystal is composed of GaAs 1-Y P Y A GaAsP mixed crystal having a composition formula of Al and a composition formula of 0<Y<1 Z Ga 1-Z As 1-Y P Y It represents any one of the AlGaAsP mixed crystals with 0<Y<1, 0<Z<1.

3. The semiconductor light emitting device according to claim 1, wherein: The thickness of the barrier layer is in a range of 0.53 to 1.0 times a value obtained by dividing the first strain amount by the second strain rate.

4. The semiconductor light emitting device according to any one of claims 1 to 3, wherein: The first semiconductor mixed crystal and the second semiconductor mixed crystal contain oxygen.

5. The semiconductor light emitting device according to claim 4, wherein: The oxygen concentration is higher than 2.5×10 15 cm -3 and 1.0×10 17 cm -3 the following.

6. The semiconductor light emitting device according to claim 1, wherein: The quantum well layer includes the first semiconductor mixed crystal and the first layer thickness provided so that the wavelength of light emitted from the light emitting layer is longer than 900 nm and shorter than 1000 nm.

7. The semiconductor light emitting device according to claim 1, wherein: The semiconductor substrate transmits light emitted by the light emitting layer.

8. The semiconductor light emitting device according to claim 1, wherein: The semiconductor substrate is a GaAs substrate.

9. The semiconductor light emitting device according to claim 1, further comprising a first semiconductor layer of a first conductivity type provided on the semiconductor substrate and a second semiconductor layer of a second conductivity type provided on the light emitting layer, in, The first semiconductor layer includes a third semiconductor mixed crystal, which is provided between the semiconductor substrate and the light emitting layer and has a lattice constant larger than the lattice constant of the semiconductor substrate and smaller than the lattice constant of the first semiconductor mixed crystal of the light emitting layer, The light emitting layer is disposed between the first semiconductor layer and the second semiconductor layer.

10. The semiconductor light emitting device according to claim 9, wherein: The third semiconductor mixed crystal is an AlGaAs mixed crystal represented by a composition formula AlzGa1-zAs.

11. The semiconductor light emitting device according to claim 10, wherein: The second semiconductor layer includes an AlGaAs mixed crystal represented by a composition formula of AlzGa1-zAs.

12. The semiconductor light emitting device according to claim 8, wherein: The lattice spacing of the first semiconductor mixed crystal in the first direction is larger than the lattice constant of the semiconductor substrate, A lattice spacing of the first semiconductor mixed crystal in a second direction orthogonal to the first direction matches a lattice constant of the semiconductor substrate.

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