Receiver and data transmission system

Abstract

A receiver and data transmission system, the receiver comprises a decision feedback equalizer, a clock data recovery circuit and an eye diagram monitoring circuit; the eye diagram monitoring circuit is coupled with the clock data recovery circuit and the decision feedback equalizer respectively; the decision feedback equalizer is adapted to generate reference voltage scanning data; the clock recovery circuit is adapted to generate phase scanning data; the eye diagram monitoring module is adapted to determine corresponding eye diagram and output based on the reference voltage scanning data and the phase scanning data. The above scheme, the eye diagram monitoring circuit uses the clock data recovery circuit and the decision feedback equalizer to generate the scanning data required for determining the eye diagram, compared with setting a unique digital-to-analog converter, error comparator and data phase interpolator for the eye diagram monitoring circuit, the layout area can be reduced, and the power consumption can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuits, and in particular to a receiver and a data transmission system. BACKGROUND

[0002] An eye diagram is one of the important performance indicators in the physical layer test of high-speed serial communication, and is the core of analyzing the signal integrity of high-speed link. Eye height and eye width are usually used to measure the quality of the eye diagram. The greater the opening degree of the eye diagram in the vertical and horizontal directions, the better the quality of the signal.

[0003] In a wired communication system, high-speed serial data transmission in the channel will be affected by the signal reflection caused by the attenuation of high-frequency components of the signal by the channel and the discontinuity of the channel impedance, thereby degrading the quality of the received signal and increasing the bit error rate (BER).

[0004] However, the existing eye diagram monitoring circuit occupies a large layout area and has high power consumption. SUMMARY

[0005] The problem solved by the present application is to provide a receiver to save layout area and reduce power consumption.

[0006] To solve the above problems, the present application provides a receiver, comprising a decision feedback equalizer, a clock data recovery circuit and an eye diagram monitoring circuit; the eye diagram monitoring circuit is coupled with the clock data recovery circuit and the decision feedback equalizer respectively;

[0007] The decision feedback equalizer is adapted to generate reference voltage scan data.

[0008] The clock recovery circuit is adapted to generate phase scan data.

[0009] The eye diagram monitoring module is adapted to determine the corresponding eye diagram based on the reference voltage scan data and the phase scan data and output.

[0010] Optionally, the eye diagram includes an eye height and an eye width.

[0011] The eye diagram monitoring circuit is adapted to generate a reference voltage scan control signal when determining the eye height.

[0012] The decision feedback equalizer is adapted to, upon receiving the reference voltage scanning control signal, generate a first reference voltage signal that gradually changes within a preset reference voltage range, compare an input signal with the first reference voltage signal, and sample the comparison result between the input signal and the first reference voltage signal using a first data sampling clock signal to obtain a corresponding first error sampling signal; wherein a deviation between an edge input control code corresponding to the edge sampling clock signal and a data input control code corresponding to the data sampling clock signal is used as an input control code deviation, and the data input control code corresponding to the first data sampling clock signal is the same as the edge input control code corresponding to the edge sampling clock signal;

[0013] The clock data recovery circuit is adapted to compare the input signal with a preset first threshold value, and to sample the comparison result between the input signal and the first threshold value using the first data sampling clock signal to obtain a corresponding first data sampling signal;

[0014] The eye diagram monitoring circuit is adapted to compare the first error sampling signal with the first data sampling signal, and determine and output a corresponding eye diagram height based on the comparison result between the first error sampling signal and the first data sampling signal.

[0015] Optionally, the eye diagram monitoring circuit is adapted to generate an input control code deviation that gradually changes within a preset input control code deviation range when determining the eye diagram width;

[0016] The clock data recovery circuit is adapted to generate a corresponding second data sampling clock signal based on the input control code deviation data, and use the second data sampling clock signal to sample a comparison result of the input signal with the first threshold value to obtain a corresponding second data sampling signal;

[0017] The decision feedback equalizer is adapted to generate a preset second reference voltage signal, and use the second data sampling clock signal to sample an error comparison result between the input signal and the preset second reference voltage signal to obtain a corresponding second error sampling signal;

[0018] The eye pattern monitoring circuit is adapted to compare the second error sampling signal with the second data sampling signal, and determine and output the width of the eye pattern according to the comparison result between the second error sampling signal and the second data sampling signal.

[0019] Optionally, the decision feedback equalizer includes a digital-to-analog converter, an error comparator and a first deserializer; the eye diagram monitoring circuit includes an EOM module; the clock data recovery circuit includes a CDR logic module, a data phase interpolator, a data comparator and a second deserializer;

[0020] The EOM logic module is adapted to generate the reference voltage scan control signal when determining the eye height.

[0021] The digital-to-analog converter is adapted to generate the first reference voltage signal that gradually changes in the preset reference voltage range when receiving the reference voltage scan control signal.

[0022] The error comparator is adapted to compare the input signal with the first reference voltage signal under the triggering of the first data sampling clock signal to generate the corresponding first error comparison data.

[0023] The first deserializer is adapted to serialize and deserialize the first error comparison data to generate the first error sampling signal.

[0024] The CDR logic module is adapted to generate the first data input control code when determining the eye height.

[0025] The data phase interpolator is adapted to generate the corresponding first data sampling clock signal based on the first data input control code.

[0026] The data comparator is adapted to compare the input signal with the first threshold value under the triggering of the first data sampling clock signal to obtain the corresponding first data comparison result.

[0027] The second deserializer is adapted to serialize and deserialize the first data comparison result to generate the corresponding first data sampling signal.

[0028] The EOM logic module is adapted to compare the first error sampling signal with the first data sampling signal and determine the corresponding eye width and output according to the comparison result of the first error sampling signal and the first data sampling signal.

[0029] Optionally, the EOM logic module is further adapted to generate the corresponding control code offset control signal when determining the width of the eye.

[0030] The CDR logic module is further adapted to generate the input control code offset data that gradually changes in the preset input control code offset range based on the control code offset control signal.

[0031] The data phase interpolator is further adapted to generate the corresponding second data sampling clock signal based on the input control code offset data.

[0032] The data comparator is adapted to compare the input data with the first threshold value under the triggering of the second data sampling clock signal to obtain the corresponding second data comparison result.

[0033] The second deserializer is adapted to perform serial-parallel conversion on the second data comparison result to generate the second data sampling signal.

[0034] The digital-to-analog converter is further adapted to generate a preset second reference voltage signal when determining the width of the eye diagram.

[0035] The error comparator is further adapted to compare the input signal with the second reference voltage signal under the triggering of the second data sampling signal to obtain a corresponding second error comparison result.

[0036] The first deserializer is further adapted to perform serial-parallel conversion on the second error comparison result to generate a corresponding second error sampling signal.

[0037] The EOM logic module is further adapted to compare the second data sampling signal with the second error sampling signal, and determine the width of the eye diagram according to the comparison result of the second data sampling signal and the second error sampling signal and output.

[0038] Optionally, the data input control code offset range is determined by the data interpolator.

[0039] Optionally, the reference voltage range is determined by the digital-to-analog converter.

[0040] Optionally, the height of the eye diagram includes a height positive extreme value and a height negative extreme value, and the height positive extreme value and the height negative extreme value are symmetric or asymmetric along a center point of the eye diagram.

[0041] Optionally, the width of the eye diagram includes a right width extreme value and a left width extreme value, and the right width extreme value and the left width extreme value are symmetric or asymmetric along a center point of the eye diagram.

[0042] Correspondingly, the embodiment of the present application further provides a data transmission system, comprising the receiver as described in any one of the above.

[0043] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0044] A receiver implemented in the present invention includes a decision feedback equalizer, a clock data recovery circuit, and an eye pattern monitoring circuit. The eye pattern monitoring circuit is coupled to the clock data recovery circuit and the decision feedback equalizer, respectively. The decision feedback equalizer is adapted to generate reference voltage sweep data; the clock recovery circuit is adapted to generate phase sweep data; and the eye pattern monitoring module is adapted to determine and output a corresponding eye pattern based on the reference voltage sweep data and the phase sweep data. In this solution, the eye pattern monitoring circuit utilizes the clock data recovery circuit and the decision feedback equalizer to generate the sweep data required to determine the eye pattern. Compared to providing a dedicated digital-to-analog converter, error comparator, and data phase interpolator for the eye pattern monitoring circuit, this reduces layout area and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the structure of a receiver;

[0046] Figure 2 for Figure 1 A schematic diagram of the structure of the eye diagram monitoring module in the receiver shown;

[0047] Figure 3 A schematic structural diagram of a receiver in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0048] As can be seen from the background technology, the existing eye diagram monitoring circuit causes the serializer and deserializer link to have problems such as large circuit layout area and power consumption.

[0049] Generally speaking, a serializer / deserializer (SerDes) link is a transceiver integrated circuit that converts serial data to parallel data and vice versa. Figure 1 The receiver in the serializer and deserializer link typically includes a continuous time linear equalizer (CTLE) 11, a decision feedback equalizer (DFE) 12, a clock and data recovery (CDR) circuit 13, and an eye-opening monitor (EOM) circuit 14.

[0050] The continuous time linear equalizer 11 can be used to compensate for the attenuation of the channel, and the eye pattern generated by the eye pattern monitoring circuit 14 to represent the signal quality is monitored in real time to adjust the equalization coefficient of the continuous time linear equalizer 11; the decision feedback equalizer 12 is used to subtract a previous symbol from a current symbol to reduce or eliminate channel distortion such as intersymbol interference (ISI); the clock data recovery circuit 13 is used to provide a data sampling clock signal aligned with the input data; the eye pattern monitoring circuit 14 monitors the quality of the input signal to generate a corresponding eye pattern and feeds back to the continuous time linear equalizer 11 to adjust the equalization coefficient of the continuous time linear equalizer 11.

[0051] Referring to Figure 2 The eye pattern monitoring circuit 14 includes a digital-to-analog converter 141, an error comparator 142, and a data phase interpolator 143.

[0052] However, the unique digital-to-analog converter, error comparator, and data phase interpolator in the eye pattern monitoring circuit occupy a large area of the circuit layout and consume a large amount of power.

[0053] To solve the technical problem, the receiver provided by the embodiment of the present application comprises a decision feedback equalizer, a clock data recovery circuit, and an eye pattern monitoring circuit; the eye pattern monitoring circuit is coupled with the clock data recovery circuit and the decision feedback equalizer; the decision feedback equalizer is adapted to generate reference voltage scanning data; the clock data recovery circuit is adapted to generate phase scanning data; and the eye pattern monitoring circuit is adapted to determine a corresponding eye pattern based on the reference voltage scanning data and the phase scanning data and output the corresponding eye pattern.

[0054] In the receiver provided by the embodiment of the present application, the eye pattern monitoring circuit uses the clock data recovery circuit and the decision feedback equalizer to generate the scanning data required to determine the eye pattern, which can reduce the area of the circuit layout and reduce power consumption compared with the unique digital-to-analog converter, error comparator, and data phase interpolator provided for the eye pattern monitoring circuit.

[0055] Figure 3 The structure of the receiver in the embodiment of the present application is shown in a structural schematic diagram. Figure 3 The receiver 30 in the embodiment of the present application comprises a decision feedback equalizer 301, a clock data recovery circuit 302, and an eye pattern monitoring circuit 303.

[0056] In the embodiment of the present application, the eye pattern monitoring circuit 303 utilizes the corresponding scan comparison data generated by the decision feedback equalizer 301 and the clock data recovery circuit 302 to detect and determine the corresponding eye pattern. The eye pattern determined by the eye pattern monitoring circuit includes the height and width of the eye pattern. Specifically,

[0057] In determining the height of the eye pattern, the eye pattern monitoring circuit 303 can generate a reference voltage scan control signal. The decision feedback equalizer 301 can generate a first reference voltage signal that varies step by step within a preset reference voltage range upon receiving the reference voltage scan control signal, compare the input signal with the first reference voltage signal, and sample the comparison result between the input signal and the first reference voltage signal using a first data sampling clock signal to obtain a corresponding first error sampling signal. The deviation between the edge input control code corresponding to the edge sampling clock signal and the data input control code corresponding to the data sampling clock signal is used as the input control code deviation, and the data input control code corresponding to the first data sampling clock signal is the same as the edge input control code corresponding to the edge sampling clock signal. The clock data recovery circuit 302 can compare the input signal with a preset first threshold value and sample the comparison result between the input signal and the first threshold value using the first data sampling clock signal to obtain a corresponding first data sampling signal. The eye pattern monitoring circuit 303 can compare the first error sampling signal and the first data sampling signal and determine the corresponding eye pattern height and output according to the comparison result of the first error sampling signal and the first data sampling signal.

[0058] In determining the width of the eye pattern, the eye pattern monitoring circuit 303 can generate an input control code deviation that varies step by step within a preset input control code deviation range. The clock data recovery circuit 302 can generate a corresponding second data sampling clock signal based on the input control code deviation data and sample the comparison result between the input signal and the first threshold value using the second data sampling clock signal to obtain a corresponding second data sampling signal. The decision feedback equalizer 301 can generate a preset second reference voltage signal and sample the error comparison result between the input signal and the second reference voltage signal using the second data sampling clock signal to obtain a corresponding second error sampling signal. The eye pattern monitoring circuit 303 can compare the second error sampling signal and the second data sampling signal and determine the width of the eye pattern and output according to the comparison result of the second error sampling signal and the second data sampling signal.

[0059] Please continue to see Figure 3In an embodiment of the present application, the decision feedback equalizer 301 comprises a digital-to-analog converter 3011, an error comparator 3012, and a first deserializer 3013; the clock data recovery circuit 302 comprises a CDR logic module 3021, a data phase interpolator 3022, a data comparator 3023, and a second deserializer 3024; and the eye pattern monitoring circuit 303 comprises an EOM module 3031.

[0060] In a specific implementation, when determining the height of the eye pattern, the EOM logic module 3031 can generate a corresponding reference voltage scanning control signal; the digital-to-analog converter 3011 can generate a first reference voltage signal that gradually changes within a preset reference voltage range when receiving the reference voltage scanning control signal; the error comparator 3022 compares the input signal with the first reference voltage signal under the triggering of the first data sampling clock signal to generate corresponding first error comparison data; the first deserializer 3023 can perform serial-to-parallel conversion on the first error comparison data to generate the first error sampling signal; the CDR logic module 3021 can generate a first data input control code when determining the height of the eye pattern; the data phase interpolator 3022 can generate a corresponding first data sampling clock signal based on the first data input control code; the data comparator 3023 can compare the input signal with the first threshold under the triggering of the first data sampling clock signal to obtain a corresponding first data comparison result; the second deserializer 3024 can perform serial-to-parallel conversion on the first data comparison result to generate a corresponding first data sampling signal; and the EOM logic module 3031 can compare the first error sampling signal with the first data sampling signal and determine a corresponding eye pattern width according to the comparison result of the first error sampling signal and the first data sampling signal and output the same.

[0061] The eye pattern height comprises a height positive extreme value and a height negative extreme value, and specifically:

[0062] In the detection of the positive maximum value of the eye diagram, the EOM logic module 3031 can generate a first sub-reference voltage scan control signal; the digital-to-analog converter 3011 generates a first sub-reference voltage signal that gradually increases in a first sub-reference voltage range when receiving the first sub-reference voltage scan control signal; the error comparator 3012 can compare the input signal with the first sub-reference voltage signal under the trigger of the first data sampling clock signal, and generate corresponding first sub-error comparison data; the first deserializer 3023 can serialize the first sub-error comparison data, and generate corresponding first sub-error sampling signal; the CDR logic module 3021 can generate first sub-input control code offset data when determining the positive maximum value of the eye diagram; the data phase interpolator 3022 can generate corresponding first sub-data sampling clock signal based on the first sub-input control code offset data; the data comparator 3023 can compare the input signal with the first threshold under the trigger of the first sub-data sampling clock signal, and obtain corresponding first sub-data comparison result; the second deserializer 3024 can serialize the first sub-data comparison result, and generate corresponding first sub-data sampling signal; the EOM logic module 3031 compares the first sub-error sampling signal with the first sub-data sampling clock signal; when it is determined that the first sub-error sampling signal is the same as the first sub-data sampling clock signal, the corresponding first sub-voltage scan control signal is generated and sent to the digital-to-analog converter 3021, so that the digital-to-analog converter 3021 increases the next first sub-reference voltage signal by a preset first step on the basis of the current first sub-reference voltage signal, until the EOM logic module 3031 determines that the received first sub-error sampling signal is different from the first sub-data sampling signal. At this time, it indicates that the corresponding first sub-reference voltage signal has reached the positive maximum value of the eye diagram, and the EOM logic module 3031 outputs the voltage value of the corresponding first sub-reference voltage signal generated by the digital-to-analog converter 3021 as the positive maximum value of the eye diagram.

[0063] Taking the first sub-reference voltage range Vref1-Vref2 as an example, the first sub-reference voltage signal generated by the digital-to-analog converter 3011 is gradually increased from Vref1 to Vref2 by a preset first step size d1. Specifically, when performing the first comparison of detecting the high positive extreme value of the eye diagram, the first sub-reference voltage signal generated by the digital-to-analog converter 3011 is Vref1; when performing the second comparison of detecting the high positive extreme value of the eye diagram, the first sub-reference voltage signal generated by the digital-to-analog converter 3011 is (Vref1+d1); when performing the third comparison of detecting the high positive extreme value of the eye diagram, the first sub-reference voltage signal generated by the digital-to-analog converter 3011 is (Vref1+2*d1)…and so on, until the EOM logic module 304 determines that the received first sub-data sampling signal and the first sub-error sampling signal are different.

[0064] Similarly, when detecting the high negative value of the eye diagram, the EOM logic module 3031 can generate a second sub-reference voltage scan control signal; the digital-to-analog converter 3011 generates a second sub-reference voltage signal that gradually decreases in a second sub-reference voltage range when receiving the second sub-reference voltage scan control signal; the error comparator 3012 can compare the input signal with the first sub-reference voltage signal under the trigger of the second sub-data sampling clock signal, and generate a corresponding second sub-error comparison data; the first deserializer 3023 can serialize the second sub-error comparison data, and generate a corresponding second sub-error sampling signal; the CDR logic module 3021 can generate a second sub-data input control code when determining the high negative value of the eye diagram; the data phase interpolator 3022 can generate a corresponding second sub-data sampling clock signal based on the second sub-data input control code; the data comparator 3023 can compare the input signal with the first threshold value under the trigger of the second sub-data sampling clock signal, and obtain a corresponding second sub-data comparison result; the second deserializer 3024 can serialize the second sub-data comparison result, and generate a corresponding second sub-data sampling signal; the EOM logic module 3031 compares the second sub-error sampling signal with the second sub-data sampling signal; when it is determined that the second sub-error sampling signal is the same as the second sub-data sampling signal, a corresponding second sub-voltage scan control signal is generated and sent to the digital-to-analog converter 3021, so that the digital-to-analog converter 3021 generates a next second sub-reference voltage signal by reducing a preset second step from a current second sub-reference voltage signal until the EOM logic module 3031 determines that the received second sub-error sampling signal is different from the second sub-data sampling signal. At this time, it indicates that the corresponding second sub-reference voltage signal has reached the high negative value of the eye diagram, and the EOM logic module 3031 can output the voltage value of the corresponding second sub-reference voltage signal generated by the digital-to-analog converter 3021 as the high negative value of the eye diagram.

[0065] Taking the second sub-reference voltage range Vref3-Vref4 as an example, the second sub-reference voltage signal generated by the digital-to-analog converter 3021 is gradually decreased from Vref4 to Vref3 by a preset second step size d2. Specifically, in the first comparison for detecting the high negative value of the eye diagram, the second sub-reference voltage signal generated by the digital-to-analog converter 3021 is Vref4; in the second comparison for detecting the high negative value of the eye diagram, the second sub-reference voltage signal generated by the digital-to-analog converter 3021 is (Vref4-d2); in the third comparison for detecting the high negative value of the eye diagram, the second sub-reference voltage scanning analog signal generated by the digital-to-analog converter 3021 is (Vref4-2*d2)…and so on, until the EOM logic module 3031 determines that the received second sub-error sampling signal is different from the second sub-data sampling signal.

[0066] In the embodiment of the present application, the first sub-reference voltage range and the second sub-reference voltage range are determined by the digital-to-analog converter, and can be set according to actual needs by those skilled in the art, which is not limited herein.

[0067] It should be noted that, in the above process of determining the height of the eye diagram, the first sub-input control code offset data and the second sub-input control code offset data generated by the CDR logic module 3011 both make the edge input control code corresponding to the edge sampling clock signal and the data input control code corresponding to the data sampling clock signal have no deviation, that is, the edge input control code corresponding to the edge sampling clock signal is the same as the data input control code corresponding to the data sampling clock signal, and the first sub-data sampling clock signal and the second sub-data sampling clock signal are determined by the preset input clock initial phase and the corresponding input control code.

[0068] In a specific implementation, when detecting the width of the eye diagram, the EOM logic module 3031 can generate a corresponding control code offset control signal; the CDR logic module 3021 can generate input control code offset data that gradually changes within a preset input control code offset range based on the control code offset control signal; the data phase interpolator 3022 can generate a corresponding second data sampling clock signal based on the input control code offset data; the data comparator 3023 can compare the input data with the first threshold under the triggering of the second data sampling clock signal to obtain a corresponding second data comparison result; the second deserializer 3024 can perform serial-parallel conversion on the second data comparison result to generate the second data sampling signal; the digital-to-analog converter 3011 can generate a preset second reference voltage signal when the width of the eye diagram is determined; the error comparator 3012 can compare the input signal with the second reference voltage signal under the triggering of the second data sampling signal to obtain a corresponding second error comparison result; the first deserializer 3013 can perform serial-parallel conversion on the second error comparison result to generate a corresponding second error sampling signal; the EOM logic module 3031 can compare the second data sampling signal with the second error sampling signal and determine the width of the eye diagram according to the comparison result of the second data sampling signal and the second error sampling signal and output.

[0069] wherein the width of the eye diagram includes a right side width extreme value and a left side width extreme value, and specifically:

[0070] When the right side width extreme value of the eye diagram is detected, the EOM logic module 3031 can generate a corresponding first sub-control code offset control signal; the CDR logic module 3021 can generate first sub-input control code offset data that changes step by step within a preset first sub-input control code offset range based on the first sub-control code offset control signal; the data phase interpolator 3022 can generate a corresponding third sub-data sampling clock signal based on the first sub-input control code offset data; the data comparator 3023 can compare the input data with the first threshold under the triggering of the third sub-data sampling clock signal to obtain a corresponding third sub-data comparison result; the second deserializer 3024 can perform serial-parallel conversion on the third sub-data comparison result to generate a corresponding third sub-data sampling signal; the digital-to-analog converter 3011 can generate a corresponding second reference voltage signal when determining the width of the eye diagram; the error comparator 3012 can compare the input signal with the second reference voltage signal under the triggering of the third sub-data sampling signal to obtain a corresponding third sub-error comparison result; the first deserializer 3013 can perform serial-parallel conversion on the third sub-error comparison result to generate a corresponding third sub-error sampling signal; the EOM logic module 3031 can compare the received third sub-error sampling signal with the third sub-data sampling signal; when it is determined that the received third sub-error sampling signal is the same as the third sub-data sampling signal, the first sub-control code offset control signal is generated, so that the CDR logic module 3021 can increase the third step on the basis of the current first sub-data input control code to generate the next first sub-data input control code, until the third sub-data sampling signal received by the EOM logic module 3031 is different from the third sub-error sampling signal. At this time, it indicates that the corresponding right side width extreme value of the eye diagram has been reached, and the EOM logic module 3031 can output the phase of the corresponding third sub-data sampling clock signal as the right side width extreme value of the eye diagram.

[0071] Taking the first sub-input control code deviation range of Phase1~Phase2 as an example, the first sub-input control code offset data generated by the CDR logic module 3021 is gradually increased from Phase1 to Phase2 by a preset third step size p1. Specifically, when performing the first comparison of detecting the right side width extreme value of the eye diagram, the first sub-input control code offset data generated by the CDR logic module 3021 is Phase1; when performing the second comparison of detecting the height positive extreme value of the eye diagram, the first sub-input control code offset data generated by the CDR logic module 3021 is (Phase1+p1); when performing the third comparison of detecting the right side width extreme value of the eye diagram, the first sub-input control code offset data generated by the CDR logic module 3021 is (Phase1+2*p1)……and so on, until the EOM logic module 3031 determines that the received third sub-data sampling signal is different from the third sub-error sampling signal.

[0072] When the left width extreme value of the eye diagram is detected, the EOM logic module 3031 can generate a corresponding second sub-control code offset control signal; the CDR logic module 3021 can generate second sub-input control code offset data that gradually decreases within a preset second sub-input control code offset range based on the second sub-control code offset control signal; the data phase interpolator 3022 can generate a corresponding fourth sub-data sampling clock signal based on the second sub-input control code offset data; the data comparator 3023 can compare the input data with the first threshold under the triggering of the fourth sub-data sampling clock signal to obtain a corresponding fourth sub-data comparison result; the second deserializer 3024 can perform serial-parallel conversion on the fourth sub-data comparison result to generate the fourth sub-data sampling signal; the digital-to-analog converter 3011 can generate a corresponding preset second reference voltage signal when determining the width of the eye diagram; the error comparator 3012 can compare the input signal with the preset second reference voltage signal under the triggering of the fourth sub-data sampling signal to obtain a corresponding fourth sub-error comparison result; the first deserializer 3013 can perform serial-parallel conversion on the fourth sub-error comparison result to generate a corresponding fourth sub-error sampling signal; the EOM logic module 3031 can compare the received fourth sub-error sampling signal with the fourth sub-data sampling signal; when it is determined that the received fourth sub-error sampling signal is the same as the fourth sub-data sampling signal, the first sub-control code offset control signal is generated, so that the CDR logic module 3021 generates the next second sub-data input control code by subtracting the fourth step from the current first sub-data input control code until the EOM logic module 3031 determines that the received fourth sub-data sampling signal is different from the fourth sub-error sampling signal. At this time, it indicates that the corresponding left width extreme value of the eye diagram has been reached, and the EOM logic module 3031 can output the phase of the corresponding fourth sub-data sampling clock signal as the left width extreme value of the eye diagram.

[0073] Taking the second sub-input control code deviation range of Phase3~Phase4 as an example, the second sub-input control code offset data generated by the CDR logic module 3021 is gradually decreased from Phase4 to Phase3 by a preset fourth step length p4. Specifically, in the first comparison of detecting the left width extreme value of the eye diagram, the second sub-input control code offset data generated by the CDR logic module 3021 is Phase4; in the second comparison of detecting the left width extreme value of the eye diagram, the second sub-input control code offset data generated by the CDR logic module 3021 is (Phase4-p1); in the third comparison of detecting the left width extreme value of the eye diagram, the second sub-input control code offset data generated by the CDR logic module 3021 is (Phase4-2*p1)……and so on, until the EOM logic module determines that the received fourth sub-data sampling signal is different from the fourth sub-error sampling signal.

[0074] It should be noted that the values of the first sub-reference voltage range, the second sub-reference voltage range, the first input control code deviation range, the second input control code deviation, the first step length, the second step length, the third step length and the fourth step length can be set according to actual needs by those skilled in the art, which are not limited herein.

[0075] The eye diagram monitoring circuit in the embodiment of the present application does not need additional data phase interpolator, data comparator and error comparator to generate scanning comparison data for the EOM logic module, compared with the existing eye diagram monitoring circuit, the circuit layout area can be reduced, and the power consumption can be significantly reduced.

[0076] It should be noted that the eye diagram monitoring circuit in the embodiment of the present application, although sharing the data phase interpolator with the clock data recovery circuit, and sharing the digital-to-analog converter and the error comparator with the decision feedback equalization circuit, will not affect the data clock recovery circuit and the decision feedback equalizer, because:

[0077] The edge phase converter of the clock data recovery circuit is still controlled by the clock data recovery logic in the clock data recovery circuit, and the output of the data comparator is kept correct by limiting the change range of the data phase rotator in the eye opening region, so that the clock data recovery circuit can run in a closed loop, and its behavior is not affected by the data phase conversion during the operation of the eye diagram monitoring circuit.

[0078] Meanwhile, during the operation of the eye pattern monitoring circuit, the internal state machine of the decision feedback equalizer and its output tap coefficients remain unchanged, and only the source of the zero tap coefficient is switched from the internal state machine of the decision feedback equalizer to the EOM logic module, so that the digital-to-analog converter of the decision feedback equalizer can be used to generate reference voltage scanning data during the operation of the eye pattern monitoring circuit. After the operation of the EOM logic module is completed, the state machine of the decision feedback equalizer will again take control of the digital-to-analog converter.

[0079] Therefore, the eye pattern monitoring circuit in the embodiment of the present application can run in the background without affecting the operation of the clock data recovery circuit and the decision feedback equalizer, and can avoid the increase of the input signal load caused by the introduction of the additional error comparator, thereby obtaining a better signal-to-noise ratio.

[0080] In addition, the eye pattern monitoring circuit in the embodiment of the present application also includes some digital logic, including the same error code detection and accumulation logic as in the conventional EOM logic module, and separate control logic of the edge data phase interpolator and the data phase interpolator. In the conventional structure, the control of the edge data phase interpolator and the data phase interpolator is the same, and they output different phases by changing the order of the input phases. In the embodiment of the present application, the edge sampling phase generated by the edge phase interpolator in the clock data recovery circuit is still controlled by the conventional data clock recovery logic, and the data phase interpolator is controlled by the clock data recovery circuit to add the phase offset output by the EOM logic module to the edge sampling phase generated by the edge data phase interpolator, and by limiting the phase scanning region within the eye opening region detected by scanning the reference voltage, the operation of the data comparator can be avoided.

[0081] The above only describes the functions generated by the modules in the clock data recovery circuit and the decision feedback equalizer during the operation of the eye pattern monitoring circuit. Those skilled in the art can understand that the clock data recovery circuit and the decision feedback equalizer can also include other modules to realize corresponding clock data recovery and decision feedback equalization functions, which will not be described here.

[0082] Correspondingly, the embodiment of the present application also provides a data transmission system, which includes the receiver described above. Please refer to the detailed description in the foregoing part, which will not be described here.

[0083] In summary, the eye pattern monitoring circuit in the embodiment of the present application can reduce the layout area and reduce power consumption, because the eye pattern monitoring circuit shares the digital-to-analog converter with the feedback equalizer, and shares the data phase interpolator with the clock data recovery circuit, compared with setting a unique digital-to-analog converter, error comparator and data phase interpolator for the eye pattern monitoring circuit.

[0084] Although the present application has been disclosed with reference to the above examples, it is not intended to limit the present application. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and the scope of protection of the present application should be limited by the scope defined in the claims.

Claims

1. A receiver, characterized by The receiver comprises a decision feedback equalizer, a clock data recovery circuit and an eye diagram monitoring circuit; the eye diagram monitoring circuit is coupled with the clock data recovery circuit and the decision feedback equalizer respectively; The decision feedback equalizer comprises a digital-to-analog converter and an error comparator, and is adapted to generate reference voltage scanning data; The clock data recovery circuit comprises a data phase interpolator, and is adapted to generate phase scanning data; The eye diagram monitoring module shares the digital-to-analog converter and the error comparator with the decision feedback equalizer, and shares the data phase interpolator with the clock data recovery circuit, and is adapted to determine the height and width of the corresponding eye diagram based on the reference voltage scanning data generated by the decision feedback equalizer and the phase scanning data generated by the clock data recovery circuit.

2. The receiver of claim 1, wherein The eye diagram monitoring circuit is adapted to generate a reference voltage scanning control signal when determining the height of the eye diagram; the decision feedback equalizer is adapted to generate a first reference voltage signal which gradually changes in a preset reference voltage range when receiving the reference voltage scanning control signal, to compare the input signal with the first reference voltage signal, and to sample the comparison result between the input signal and the first reference voltage signal by using a first data sampling clock signal to obtain a corresponding first error sampling signal; wherein the deviation between the edge input control code corresponding to an edge sampling clock signal and the data input control code corresponding to the data sampling clock signal is taken as an input control code deviation, and the data input control code corresponding to the first data sampling clock signal is the same as the edge input control code corresponding to the edge sampling clock signal; The clock data recovery circuit is adapted to compare the input signal with a preset first threshold value, and to sample the comparison result between the input signal and the first threshold value by using the first data sampling clock signal to obtain a corresponding first data sampling signal; The eye diagram monitoring circuit is adapted to compare the first error sampling signal with the first data sampling signal, and to determine the corresponding eye diagram height and output according to the comparison result between the first error sampling signal and the first data sampling signal.

3. The receiver of claim 2, wherein The eye diagram monitoring circuit is adapted to generate an input control code deviation which gradually changes in a preset input control code deviation range when determining the width of the eye diagram; The clock data recovery circuit is adapted to generate a corresponding second data sampling clock signal based on the input control code deviation data, and to sample the comparison result between the input signal and the first threshold value by using the second data sampling clock signal to obtain a corresponding second data sampling signal; The decision feedback equalizer is adapted to generate a preset second reference voltage signal, and to sample the error comparison result between the input signal and the preset second reference voltage signal by using the second data sampling clock signal to obtain a corresponding second error sampling signal; The eye pattern monitoring circuit is adapted to compare the second error sampling signal with the second data sampling signal, and determine the width of the eye pattern and output according to the comparison result of the second error sampling signal and the second data sampling signal.

4. A receiver as claimed in claim 2 or 3, characterised in that, The decision feedback equalizer comprises a digital-to-analog converter, an error comparator and a first deserializer; the eye pattern monitoring circuit comprises an EOM module; the clock data recovery circuit comprises a CDR logic module, a data phase interpolator, a data comparator and a second deserializer; The EOM logic module is adapted to generate the reference voltage scanning control signal when determining the eye pattern height; The digital-to-analog converter is adapted to generate a first reference voltage signal which gradually changes in a preset reference voltage range when receiving the reference voltage scanning control signal; The error comparator is adapted to compare the input signal with the first reference voltage signal under the triggering of the first data sampling clock signal, and generate corresponding first error comparison data; The first deserializer is adapted to serialize the first error comparison data and generate the first error sampling signal; The CDR logic module is adapted to generate a first data input control code when determining the eye pattern height; The data phase interpolator is adapted to generate a corresponding first data sampling clock signal based on the first data input control code; The data comparator is adapted to compare the input signal with the first threshold value under the triggering of the first data sampling clock signal, and obtain a corresponding first data comparison result; The second deserializer is adapted to serialize the first data comparison result and generate the first data sampling signal; The EOM logic module is adapted to compare the first error sampling signal with the first data sampling signal, and determine the corresponding eye pattern height and output according to the comparison result of the first error sampling signal and the first data sampling signal.

5. The receiver of claim 4, wherein The EOM logic module is further adapted to generate a corresponding control code offset control signal when determining the width of the eye pattern; The CDR logic module is further adapted to generate input control code offset data which gradually changes in a preset input control code offset range based on the control code offset control signal; The data phase interpolator is further adapted to generate a corresponding second data sampling clock signal based on the input control code offset data; The data comparator is adapted to compare the input data with the first threshold value under the triggering of the second data sampling clock signal, and obtain a corresponding second data comparison result; The second deserializer is adapted to serialize the second data comparison result and generate the second data sampling signal; The digital-to-analog converter is further adapted to generate a preset second reference voltage signal when determining the width of the eye pattern; The error comparator is further adapted to compare the input signal with the second reference voltage signal under the triggering of the second data sampling signal, and obtain a corresponding second error comparison result; The first de-serializer is further adapted to serialize the second error comparison result to generate a corresponding second error sample signal; The EOM logic module is further adapted to compare the second data sample signal with the second error sample signal, and determine a width of the eye diagram and output according to a comparison result of the second data sample signal with the second error sample signal.

6. The receiver of claim 4, characterized in that The data input control code offset range is determined by the data interpolator.

7. The receiver of claim 4, characterized in that The reference voltage range is determined by the digital-to-analog converter.

8. The receiver of claim 2, wherein, The height of the eye diagram includes a height positive extreme value and a height negative extreme value, and the height positive extreme value and the height negative extreme value are symmetric or asymmetric along a center point of the eye diagram.

9. The receiver of claim 2, wherein, The width of the eye diagram includes a right width extreme value and a left width extreme value, and the right width extreme value and the left width extreme value are symmetric or asymmetric along the center point of the eye diagram.

10. A data transmission system, characterized by The receiver comprises any one of claims 1 to 9.

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