A test system, a test method and a test control device

Abstract

The present invention provides a test system, a test method and a test control device, which belong to the field of communication technology, wherein the test system comprises: a simulation terminal and a terminal consistency analyzer; the simulation terminal is connected to a device under test, and the simulation terminal is used to send a test signal; the terminal consistency analyzer is connected to the device under test, and the terminal consistency analyzer is used to receive the test signal forwarded by the device under test and decode and analyze the test signal. The present invention can truly simulate the signaling transmission process, improve the reliability of the test environment of the device under test, and can test the best capabilities of the device under test.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a test system, a test method and a test control device. Background Art

[0002] See also Figure 1 In existing analog system equipment, such as analog repeaters, uplink sensitivity tests are mainly performed by using a signal generator (or signal source) to generate a signal and input it into the device under test. The signal is then output to a spectrum analyzer through the device under test, and the receiving sensitivity of the device under test is obtained by detecting the error vector magnitude (EVM) of the received signal.

[0003] However, the signal generator and spectrum analyzer cannot truly simulate the signaling transmission process. In addition, the spectrum analyzer's calculation of EVM requires that the signal meet certain power requirements, that is, a larger power signal is required, while the uplink sensitivity to be tested is an extremely small power signal. The spectrum analyzer cannot calculate the corresponding EVM and cannot test the best capabilities of the device under test. Summary of the invention

[0004] In view of this, the present invention provides a test system, a test method and a test control device for solving the problem that the current test method for simulating the receiving sensitivity of a receiver cannot truly simulate the signaling transmission process and cannot test the best capability of the device.

[0005] In order to solve the above technical problems, in a first aspect, the present invention provides a test system, comprising: a simulation terminal and a terminal consistency analyzer;

[0006] The simulation terminal is connected to the device under test, and the simulation terminal is used to send a test signal;

[0007] The terminal consistency analyzer is connected to the device under test, and is used to receive the test signal forwarded by the device under test and perform decoding analysis on the test signal.

[0008] Optionally, the test system further includes: a combiner and a signal generator;

[0009] The combiner is arranged between the simulation terminal and the device under test;

[0010] The signal generator is connected to the combiner, and the signal generator is used to send an interference signal to the combiner;

[0011] The combiner is used to combine the test signal sent by the simulation terminal and the interference signal sent by the signal generator into one signal, and then forward it to the terminal consistency analyzer via the device under test.

[0012] In a second aspect, the present invention further provides a testing method, which is applied to any one of the testing systems described in the first aspect, and the method comprises:

[0013] Controlling the analog terminal to send a test signal at a first power;

[0014] Determine whether a first block error rate and / or a first cyclic redundancy check code check error rate obtained by a terminal consistency analyzer through decoding and analyzing the test signal forwarded by the device under test meets a preset condition;

[0015] If the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition, determining the sensitivity of the device under test;

[0016] If the first block error rate and / or the first cyclic redundancy check code check error rate does not meet the preset condition, adjust the first power of the simulation terminal until the first block error rate and / or the first cyclic redundancy check code check error rate meets the preset condition.

[0017] Optionally, if the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition, determining the sensitivity of the device under test includes:

[0018] Comparing the first power with a standard value, where the standard value is a predefined standard value of sensitivity of the device under test;

[0019] If the difference between the first power and the standard value is less than or equal to a first preset value, it is determined that the first power is the sensitivity of the device under test.

[0020] Optionally, before controlling the simulation terminal to send the test signal at the first power, the method further includes:

[0021] Starting the simulation terminal and the terminal consistency analyzer, and configuring cell parameters respectively;

[0022] It is determined that the simulated terminal has searched for a cell and completed cell synchronization.

[0023] Optionally, the cell parameters include at least one of bandwidth, transmit power, SSB subcarrier spacing, uplink and downlink frequency, SSB offset, physical layer parameters and protocol layer parameters.

[0024] Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the simulation terminal and the device under test; the signal generator is connected to the combiner, and the signal generator is used to send an interference signal to the combiner; the combiner is used to combine the test signal sent by the simulation terminal and the interference signal sent by the signal generator into one signal and then forward it to the terminal consistency analyzer via the device under test; the method further includes:

[0025] Controlling the analog terminal to send the test signal at a second power, where the second power is a predetermined power or a sum of a predetermined sensitivity standard value of the device under test and a preset backoff value;

[0026] Controlling the signal generator to output a first interference signal;

[0027] Determine whether a second block error rate obtained by the terminal consistency analyzer through decoding and analyzing the first synthetic signal forwarded by the device under test is less than or equal to a second preset value and / or whether a check error rate of a second cyclic redundancy check code is less than or equal to a third preset value; the first synthetic signal is obtained by synthesizing the test signal sent by the simulation terminal and the first interference signal sent by the signal generator by the combiner;

[0028] If the second block error rate is less than or equal to the second preset value and / or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value, determine that the blocking test passes;

[0029] Otherwise, the blocking test is determined to fail.

[0030] Optionally, the testing method further includes:

[0031] Controlling the signal generator to output a second interference signal, wherein the second interference signal is different from the first interference signal;

[0032] Determine whether a third block error rate obtained by the terminal consistency analyzer through decoding and analyzing the second synthetic signal forwarded by the device under test is less than or equal to a fourth preset value and / or whether a check error rate of a third cyclic redundancy check code is less than or equal to a fifth preset value; the second synthetic signal is obtained by synthesizing the test signal sent by the simulation terminal and the second interference signal sent by the signal generator by the combiner;

[0033] If the third block error rate is less than or equal to the fourth preset value and / or the check error rate of the third cyclic redundancy check code is less than or equal to the fifth preset value, it is determined that the blocking test passes;

[0034] Otherwise, the blocking test is determined to fail.

[0035] In a third aspect, the present invention further provides a test control device, which is applied to any one of the test systems described in the first aspect, and the test control device comprises:

[0036] A first simulation terminal control module, used to control the simulation terminal to send a test signal according to a first power;

[0037] A first judgment module is used to judge whether a first block error rate and / or a first cyclic redundancy check code check error rate obtained by a terminal consistency analyzer decoding and analyzing the test signal forwarded by the device under test meets a preset condition;

[0038] a sensitivity determination module, configured to determine the sensitivity of the device under test when the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition;

[0039] The first simulation terminal control module is also used to adjust the first power of the simulation terminal when the first block error rate and / or the check error rate of the first cyclic redundancy check code do not meet the preset conditions until the first block error rate and / or the check error rate of the first cyclic redundancy check code meet the preset conditions.

[0040] Optionally, the sensitivity determination module includes:

[0041] A comparing unit, configured to compare the first power with a standard value, wherein the standard value is a predefined standard value of sensitivity of the device under test;

[0042] A sensitivity determination unit is used to determine that the first power is the sensitivity of the device under test if the difference between the first power and the standard value is less than or equal to a first preset value.

[0043] Optionally, the test control device further includes:

[0044] A second simulated terminal control module, used to start the simulated terminal and configure cell parameters;

[0045] A first terminal consistency analyzer control module, used to start the terminal consistency analyzer and configure cell parameters;

[0046] The cell synchronization determination module is used to determine whether the simulated terminal has searched for a cell and completed cell synchronization.

[0047] Optionally, the cell parameters include at least one of bandwidth, transmit power, SSB subcarrier spacing, uplink and downlink frequency, SSB offset, physical layer parameters and protocol layer parameters.

[0048] Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the simulation terminal and the device under test; the signal generator is connected to the combiner, and the signal generator is used to send an interference signal to the combiner; the combiner is used to combine the test signal sent by the simulation terminal and the interference signal sent by the signal generator into one signal and then forward it to the terminal consistency analyzer via the device under test; the test control device also includes:

[0049] A third simulation terminal control module, used to control the simulation terminal to send the test signal according to a second power, where the second power is a predetermined power, or a predetermined sum of a sensitivity standard value of the device under test and a preset backoff value;

[0050] A signal generator control module, used to control the signal generator to output a first interference signal;

[0051] The second judgment module is used to judge whether the second block error rate obtained by the terminal consistency analyzer through decoding and analyzing the first synthetic signal forwarded by the device under test is less than or equal to the second preset value and / or whether the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value; the first synthetic signal is obtained by the combiner combining the test signal sent by the simulation terminal and the first interference signal sent by the signal generator;

[0052] The blocking determination module is used to determine that the blocking test passes when the second block error rate is less than or equal to the second preset value and / or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value; otherwise, determine that the blocking test fails.

[0053] Optionally, the signal generator control module is further used to control the signal generator to output a second interference signal, where the second interference signal is different from the first interference signal;

[0054] The second judgment module is further used to judge whether the third block error rate obtained by the terminal consistency analyzer decoding and analyzing the second synthetic signal forwarded by the device under test is less than or equal to the fourth preset value and / or whether the check error rate of the third cyclic redundancy check code is less than or equal to the fifth preset value; the second synthetic signal is obtained by the combiner synthesizing the test signal sent by the simulation terminal and the second interference signal sent by the signal generator;

[0055] The blocking determination module is further used to determine that the blocking test passes when the third block error rate is less than or equal to the fourth preset value and / or the check error rate of the third cyclic redundancy check code is less than or equal to the fifth preset value; otherwise, determine that the blocking test fails.

[0056] In a fourth aspect, the present invention further provides a test control device, comprising a memory, a processor, and a program stored in the memory and executable on the processor; when the processor executes the program, the steps in any one of the test methods provided in the second aspect are implemented.

[0057] In a fifth aspect, the present invention further provides a readable storage medium having a program stored thereon, which, when executed by a processor, implements the steps of any one of the test methods provided in the second aspect above.

[0058] The beneficial effects of the above technical solution of the present invention are as follows:

[0059] In the embodiment of the present invention, an analog terminal is used instead of a signal generator to send a test signal. The analog terminal is connected to the device under test, and the test signal is forwarded to a terminal consistency analyzer via the device under test. The terminal consistency analyzer then directly performs sensitivity measurement on the received signal. This can truly simulate the signaling transmission process, improve the reliability of the test environment of the device under test, and test the best capabilities of the device under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A schematic diagram of the receiving sensitivity of the device under test in the prior art test;

[0061] Figure 2 is a structural schematic diagram of a test system in an embodiment of the present invention;

[0062] Figure 3 is a schematic structural diagram of another test system in an embodiment of the present invention;

[0063] Figure 4 A flow chart of a testing method in an embodiment of the present invention;

[0064] Figure 5 is a structural schematic diagram of a test control device in an embodiment of the present invention;

[0065] Figure 6 It is a schematic diagram of the structure of another test control device in an embodiment of the present invention. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0067] See also Figure 2 , Figure 2 A structural diagram of a test system provided in Embodiment 1 of the present invention, the test system comprises: a simulation terminal 21 and a terminal consistency analyzer 22;

[0068] The simulation terminal 21 is connected to the device under test 23, and the simulation terminal 21 is used to send a test signal;

[0069] The device under test 23 is used to receive the test signal sent by the simulation terminal 21 and forward it to the terminal consistency analyzer 22;

[0070] The terminal consistency analyzer 22 is connected to the device under test 23 , and is used to receive the test signal forwarded by the device under test 23 and perform decoding analysis on the test signal.

[0071] It should be noted that at the beginning of the test, the simulated terminal 21 needs to complete the synchronization process with the terminal consistency analyzer 22 through the interaction of signaling information, that is, complete the process of the simulated terminal 21 accessing the terminal consistency analyzer 22. The specific process is similar to the process of the terminal accessing the base station, and will not be described in detail here.

[0072] In the embodiment of the present invention, the device under test 23 may be an analog system device, such as an analog repeater or other analog receivers. The test system may be used to test the receiving sensitivity of the device under test 23, or called uplink sensitivity.

[0073] In the embodiment of the present invention, an analog terminal 21 is used instead of a signal generator 25 to send a test signal. The analog terminal 21 is connected to a device under test 23. The test signal is forwarded to a terminal consistency analyzer 22 via the device under test 23. The terminal consistency analyzer 22 then directly performs sensitivity measurement on the received signal. This can truly simulate the signaling transmission process, improve the reliability of the test environment of the device under test 23, and test the best capabilities of the device under test 23.

[0074] Optional, such as Figure 3 As shown, the test system further includes: a combiner 24 and a signal generator 25;

[0075] The combiner 24 is arranged between the simulation terminal 21 and the device under test 23;

[0076] The signal generator 25 is connected to the combiner 24, and the signal generator 25 is used to send an interference signal to the combiner 24;

[0077] The combiner 24 is used to combine the test signal sent by the simulation terminal 21 and the interference signal sent by the signal generator 25 into one signal, and then forward it to the terminal consistency analyzer 22 via the device under test 23 .

[0078] Specifically, the connection process of the test system is that the input port of the device under test 23 is connected to the combiner 24, one end of the combiner 24 is connected to the transmitting port of the simulation terminal 21, and the other end is connected to the signal generator 25. The output port of the device under test 23 is connected to the receiving port of the terminal consistency analyzer 22.

[0079] The signal generator 25 may not work, that is, the signal generator 25 may not output an interference signal, and at this time, the combiner 24 only sends the test signal output by the analog terminal 21 to the device under test 23. For example, when performing a sensitivity test on the device under test 23, the signal generator 25 may not work.

[0080] The signal generator 25 may also be referred to as a signal source. The combiner 24 may be a broadband combiner.

[0081] Further optionally, the test system may further include a test control device for controlling the operation of the simulation terminal 21 and / or the signal generator 25 and controlling the test process. The test control device may be, for example, a processor, a controller, and the like.

[0082] See also Figure 4 , Figure 4 A flow chart of a testing method provided in Embodiment 2 of the present invention is provided. The method is applied to the testing system in Embodiment 1 above, and includes the following steps:

[0083] Step 41: Control the analog terminal to send a test signal at a first power;

[0084] Step 42: Determine whether a first block error rate (BLER) and / or a first cyclic redundancy check (CRC) check error rate obtained by decoding and analyzing the test signal forwarded by the device under test by the terminal consistency analyzer meets a preset condition;

[0085] That is to say, in the embodiment of the present application, only the block error rate of the test signal can be obtained, and it can be determined whether the block error rate meets the preset conditions, or only the check error rate of the CRC of the test signal can be obtained, and it can be determined whether the check error rate of the CRC meets the preset conditions, or both the block error rate of the test signal and the check error rate of the CRC of the test signal can be obtained, and it can be determined whether the block error rate meets the preset conditions and whether the check error rate of the CRC meets the preset conditions at the same time. Moreover, it should be conceivable for those skilled in the art that the specific preset conditions may be different in different scenarios, and the preset conditions that the block error rate needs to meet and the preset conditions that the check error rate of the CRC needs to meet may also be different.

[0086] For example, the preset condition that the block error rate needs to meet may be equal to the preset block error rate. For example, when the terminal consistency analyzer decodes and analyzes the received test signal and obtains a block error rate of 5%, it is determined that the preset condition is met.

[0087] In addition, the parameters that need to be determined may also be other parameters besides the block error rate and the CRC check error rate, which will not be listed in detail here.

[0088] Specifically, the test signal sent by the simulated terminal at the first power is forwarded to the terminal consistency analyzer via the device to be tested, and the terminal consistency analyzer decodes and analyzes the received test signal to obtain the block error rate.

[0089] Step 43: If the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition, determine the sensitivity of the device under test;

[0090] For example, the power of the test signal sent by the simulated terminal when the terminal consistency analyzer determines that the block error rate meets the preset condition can be used as the sensitivity of the device under test.

[0091] Step 44: If the first block error rate and / or the check error rate of the first cyclic redundancy check code does not meet the preset condition, adjust the first power of the simulated terminal until the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition.

[0092] For example, if the block error rate is lower than the preset block error rate, such as 2%, the output power of the simulated terminal sending the test signal is reduced; if the block error rate is higher than the preset block error rate, the output power of the simulated terminal sending the test signal is increased.

[0093] In the embodiment of the present invention, an analog terminal is used instead of a signal generator to send a test signal. The analog terminal is connected to the device under test, and the test signal is forwarded to a terminal consistency analyzer via the device under test. The terminal consistency analyzer then directly performs sensitivity measurement on the received signal. This can truly simulate the signaling transmission process, improve the reliability of the test environment of the device under test, and test the best capabilities of the device under test.

[0094] The above test method is illustrated below with examples.

[0095] Optionally, if the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition, determining the sensitivity of the device under test includes:

[0096] The first power is compared with a standard value, where the standard value is a predefined standard sensitivity value of the device under test; for example, corresponding standard sensitivity values ​​may be predefined for different types of devices in the test standard.

[0097] If the difference between the first power and the standard value is less than or equal to a first preset value, it is determined that the first power is the sensitivity of the device under test.

[0098] In other words, the sensitivity of the device under test must be close to the sensitivity standard value of the device of this type specified in the test standard in order to determine the sensitivity of the device under test.

[0099] Optionally, before controlling the simulation terminal to send the test signal at the first power, the method further includes:

[0100] Starting the simulation terminal and the terminal consistency analyzer, and configuring cell parameters respectively;

[0101] It is determined that the simulated terminal has searched for a cell and completed cell synchronization.

[0102] Specifically, the simulation terminal 21 can complete the synchronization process with the terminal consistency analyzer 22 through the interaction of signaling information, that is, complete the process of the simulation terminal 21 accessing the terminal consistency analyzer 22. The specific process is similar to the process of the terminal accessing the base station, which will not be described in detail here.

[0103] Further optionally, the cell parameters include at least one of bandwidth, transmit power, SSB subcarrier spacing, uplink and downlink frequency, SSB offset, physical layer parameters and protocol layer parameters.

[0104] Specifically, at the beginning of the test, it is necessary to open the simulation terminal and configure the cell parameters, such as bandwidth, transmit power, synchronization signal / physical broadcast channel signal block (SSB or SS / PBCH Block) subcarrier spacing, uplink and downlink frequency, SSB offset, etc.; it is also necessary to open the terminal consistency analyzer and configure the cell parameters, such as bandwidth, transmit power, SSB subcarrier spacing, uplink and downlink frequency, SSB offset, physical layer parameters, parameters of each protocol layer, etc. When the simulation terminal searches for the cell and the state is synchronized (SYNC), after the cell synchronization is completed, the terminal consistency analyzer is used to demodulate the test signal of the simulation terminal. At this time, the block error rate can be, for example, 1%.

[0105] That is, at the beginning of the test, the simulation terminal and the terminal consistency analyzer need to be turned on, and the relevant parameters (frequency, power, and related access configuration) need to be configured so that the terminal consistency analyzer can demodulate the uplink signal of the simulation terminal (ie, the test signal).

[0106] In addition, initial parameter configuration is required at the beginning of the test, powering on the device under test and setting the device under test to receive mode.

[0107] Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the simulation terminal and the device under test; the signal generator is connected to the combiner, and the signal generator is used to send an interference signal to the combiner; the combiner is used to combine the test signal sent by the simulation terminal and the interference signal sent by the signal generator into one signal and then forward it to the terminal consistency analyzer via the device under test; the method further includes:

[0108] Controlling the analog terminal to send the test signal at a second power, where the second power is a predetermined power or a sum of a predetermined sensitivity standard value of the device under test and a preset backoff value;

[0109] For example, the second power of the test signal sent by the analog terminal can be set according to the test standard, or the signal transmission power of the analog terminal can be adjusted to the sensitivity standard value + a preset back-off value. The back-off value is determined according to the test standard, for example, the back-off value is 6dB, and the back-off value can also be called a margin.

[0110] Controlling the signal generator to output a first interference signal;

[0111] Specifically, the signal generator is turned on and an interference signal is output, and the waveform, frequency and / or power of the interference signal are set according to the test specification.

[0112] Determine whether a second block error rate obtained by the terminal consistency analyzer through decoding and analyzing the first synthetic signal forwarded by the device under test is less than or equal to a second preset value and / or whether a check error rate of a second cyclic redundancy check code is less than or equal to a third preset value; the first synthetic signal is obtained by synthesizing the test signal sent by the simulation terminal and the first interference signal sent by the signal generator by the combiner;

[0113] The second preset value may be equal to the preset block error rate during the sensitivity test, for example, equal to 5%. The third preset value may be equal to or different from the second preset value.

[0114] If the second block error rate is less than or equal to the second preset value and / or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value, determine that the blocking test passes;

[0115] Specifically, the blocking test based on the first interference signal passes;

[0116] Otherwise, it is determined that the blocking test fails. Specifically, the blocking test based on the first interference signal fails.

[0117] The embodiment of the present invention can also perform a blocking test on the device to be tested.

[0118] Of course, at the beginning of the test, the test system connection process also needs to be completed. Specifically, the input port of the device under test is connected to the combiner, and the analog terminal and signal generator are connected at the same time. The signal generator is used to inject interference signals.

[0119] The embodiment of the present invention utilizes a simulation terminal and a terminal consistency analyzer to perform an uplink index test, where the uplink index includes uplink sensitivity and blocking.

[0120] Optionally, the method further includes:

[0121] Controlling the signal generator to output a second interference signal, where the second interference signal is different from the first interference signal; specifically, the first interference signal and the second interference signal may have different frequencies, different powers, and / or different signal formats;

[0122] The waveform, frequency and / or power of the second interference signal are set according to the test specification.

[0123] Determine whether the third block error rate obtained by the terminal consistency analyzer through decoding and analyzing the second synthetic signal forwarded by the device under test is less than or equal to the fourth preset value and / or whether the check error rate of the third cyclic redundancy check code is less than or equal to the fifth preset value; the second synthetic signal is obtained by the combiner combining the test signal sent by the simulation terminal and the second interference signal sent by the signal generator; wherein the fifth preset value is equal to or different from the fourth preset value.

[0124] Specifically, the terminal consistency analyzer receives the second synthetic signal forwarded by the device under test and decodes and analyzes it to obtain a block error rate.

[0125] If the third block error rate is less than or equal to the fourth preset value and / or the check error rate of the third cyclic redundancy check code is less than or equal to the fifth preset value, it is determined that the blocking test passes; specifically, the blocking test based on the second interference signal passes;

[0126] Otherwise, it is determined that the blocking test fails. Specifically, the blocking test based on the second interference signal fails.

[0127] That is to say, when performing a blocking test, different interference signals can be used to perform the test multiple times.

[0128] The embodiment of the present invention can directly measure the uplink receiving sensitivity of the device under test and other blocking tests through the terminal consistency analyzer, thereby improving the accuracy of the test.

[0129] See also Figure 5 , Figure 5 : is a schematic diagram of the structure of a test control device provided in Embodiment 3 of the present invention. The test control device 50 can be applied to any test system described in Embodiment 1 above, including:

[0130] A first simulated terminal control module 51, used to control the simulated terminal to send a test signal at a first power;

[0131] A first judgment module 52 is used to judge whether a first block error rate and / or a first cyclic redundancy check code check error rate obtained by a terminal consistency analyzer decoding and analyzing the test signal forwarded by the device under test meets a preset condition;

[0132] A sensitivity determination module 53, configured to determine the sensitivity of the device under test when the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition;

[0133] The first simulation terminal control module 51 is also used to adjust the first power of the simulation terminal when the first block error rate and / or the check error rate of the first cyclic redundancy check code do not meet the preset conditions until the first block error rate and / or the check error rate of the first cyclic redundancy check code meet the preset conditions.

[0134] In the embodiment of the present invention, an analog terminal is used instead of a signal generator to send a test signal. The analog terminal is connected to the device under test, and the test signal is forwarded to a terminal consistency analyzer via the device under test. The terminal consistency analyzer then directly performs sensitivity measurement on the received signal. This can truly simulate the signaling transmission process, improve the reliability of the test environment of the device under test, and test the best capabilities of the device under test.

[0135] Optionally, the sensitivity determination module 53 includes:

[0136] A comparing unit, configured to compare the first power with a standard value, wherein the standard value is a predefined standard value of sensitivity of the device under test;

[0137] A sensitivity determination unit is used to determine that the first power is the sensitivity of the device under test if the difference between the first power and the standard value is less than or equal to a first preset value.

[0138] Optionally, the test control device 50 further includes:

[0139] A second simulated terminal control module, used to start the simulated terminal and configure cell parameters;

[0140] A first terminal consistency analyzer control module, used to start the terminal consistency analyzer and configure cell parameters;

[0141] The cell synchronization determination module is used to determine whether the simulated terminal has searched for a cell and completed cell synchronization.

[0142] Optionally, the cell parameters include at least one of bandwidth, transmit power, SSB subcarrier spacing, uplink and downlink frequency, SSB offset, physical layer parameters and protocol layer parameters.

[0143] Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the simulation terminal and the device under test; the signal generator is connected to the combiner, and the signal generator is used to send an interference signal to the combiner; the combiner is used to combine the test signal sent by the simulation terminal and the interference signal sent by the signal generator into one signal and then forward it to the terminal consistency analyzer via the device under test; the test control device 50 also includes:

[0144] A third simulation terminal control module, used to control the simulation terminal to send the test signal according to a second power, where the second power is a predetermined power, or a predetermined sum of a sensitivity standard value of the device under test and a preset backoff value;

[0145] A signal generator control module, used to control the signal generator to output a first interference signal;

[0146] The second judgment module is used to judge whether the second block error rate obtained by the terminal consistency analyzer through decoding and analyzing the first synthetic signal forwarded by the device under test is less than or equal to the second preset value and / or whether the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value; the first synthetic signal is obtained by the combiner combining the test signal sent by the simulation terminal and the first interference signal sent by the signal generator;

[0147] The blocking determination module is used to determine that the blocking test passes when the second block error rate is less than or equal to the second preset value and / or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value; otherwise, determine that the blocking test fails.

[0148] Optionally, the signal generator control module is further used to control the signal generator to output a second interference signal, where the second interference signal is different from the first interference signal;

[0149] The second judgment module is further used to judge whether the third block error rate obtained by the terminal consistency analyzer decoding and analyzing the second synthetic signal forwarded by the device under test is less than or equal to the fourth preset value and / or whether the check error rate of the third cyclic redundancy check code is less than or equal to the fifth preset value; the second synthetic signal is obtained by the combiner synthesizing the test signal sent by the simulation terminal and the second interference signal sent by the signal generator;

[0150] The blocking determination module is further used to determine that the blocking test passes when the third block error rate is less than or equal to the fourth preset value and / or the check error rate of the third cyclic redundancy check code is less than or equal to the fifth preset value; otherwise, determine that the blocking test fails.

[0151] The embodiment of the present invention is a product embodiment corresponding to the above-mentioned method embodiment 2, so it will not be described in detail here. Please refer to the above-mentioned embodiment 2 for details.

[0152] See also Figure 6 , Figure 6: is a structural diagram of a test control device provided in Embodiment 4 of the present invention. The test control device 60 can be applied to any test system described in Embodiment 1 above. The test control device 60 includes a processor 61, a memory 62, and a program stored in the memory 62 and executable on the processor 61. When the processor 61 executes the program, the following steps are implemented:

[0153] Controlling the analog terminal to send a test signal at a first power;

[0154] Determine whether a first block error rate and / or a first cyclic redundancy check code check error rate obtained by a terminal consistency analyzer through decoding and analyzing the test signal forwarded by the device under test meets a preset condition;

[0155] If the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition, determining the sensitivity of the device under test;

[0156] If the first block error rate and / or the first cyclic redundancy check code check error rate does not meet the preset condition, adjust the first power of the simulation terminal until the first block error rate and / or the first cyclic redundancy check code check error rate meets the preset condition.

[0157] In the embodiment of the present invention, an analog terminal is used instead of a signal generator to send a test signal. The analog terminal is connected to the device under test, and the test signal is forwarded to a terminal consistency analyzer via the device under test. The terminal consistency analyzer then directly performs sensitivity measurement on the received signal. This can truly simulate the signaling transmission process, improve the reliability of the test environment of the device under test, and test the best capabilities of the device under test.

[0158] Optionally, the processor 61 may further implement the following steps when executing the program:

[0159] If the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition, determining the sensitivity of the device under test includes:

[0160] Comparing the first power with a standard value, where the standard value is a predefined standard value of sensitivity of the device under test;

[0161] If the difference between the first power and the standard value is less than or equal to a first preset value, it is determined that the first power is the sensitivity of the device under test.

[0162] Optionally, the processor 61 may further implement the following steps when executing the program:

[0163] Before controlling the simulation terminal to send the test signal according to the first power, the method further includes:

[0164] Starting the simulation terminal and the terminal consistency analyzer, and configuring cell parameters respectively;

[0165] It is determined that the simulated terminal has searched for a cell and completed cell synchronization.

[0166] Optionally, the cell parameters include at least one of bandwidth, transmit power, SSB subcarrier spacing, uplink and downlink frequency, SSB offset, physical layer parameters and protocol layer parameters.

[0167] Optionally, the test system further includes: a combiner and a signal generator; the combiner is arranged between the simulation terminal and the device under test; the signal generator is connected to the combiner, and the signal generator is used to send an interference signal to the combiner; the combiner is used to combine the test signal sent by the simulation terminal and the interference signal sent by the signal generator into one signal and then forward it to the terminal consistency analyzer via the device under test;

[0168] When the processor 61 executes the program, the following steps can also be implemented:

[0169] Controlling the analog terminal to send the test signal at a second power, where the second power is a predetermined power or a sum of a predetermined sensitivity standard value of the device under test and a preset backoff value;

[0170] Controlling the signal generator to output a first interference signal;

[0171] Determine whether a second block error rate obtained by the terminal consistency analyzer through decoding and analyzing the first synthetic signal forwarded by the device under test is less than or equal to a second preset value and / or whether a check error rate of a second cyclic redundancy check code is less than or equal to a third preset value; the first synthetic signal is obtained by synthesizing the test signal sent by the simulation terminal and the first interference signal sent by the signal generator by the combiner;

[0172] If the second block error rate is less than or equal to the second preset value and / or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value, determine that the blocking test passes;

[0173] Otherwise, the blocking test is determined to fail.

[0174] Optionally, the processor 61 may further implement the following steps when executing the program:

[0175] Controlling the signal generator to output a second interference signal, wherein the second interference signal is different from the first interference signal;

[0176] Determine whether a third block error rate obtained by the terminal consistency analyzer through decoding and analyzing the second synthetic signal forwarded by the device under test is less than or equal to a fourth preset value and / or whether a check error rate of a third cyclic redundancy check code is less than or equal to a fifth preset value; the second synthetic signal is obtained by synthesizing the test signal sent by the simulation terminal and the second interference signal sent by the signal generator by the combiner;

[0177] If the third block error rate is less than or equal to the fourth preset value and / or the check error rate of the third cyclic redundancy check code is less than or equal to the fifth preset value, it is determined that the blocking test passes;

[0178] Otherwise, the blocking test is determined to fail.

[0179] The specific working process of the embodiment of the present invention is consistent with that in the above method embodiment 2, so it will not be repeated here. Please refer to the description of the method steps in the above method embodiment 2 for details.

[0180] Embodiment 5 of the present invention provides a readable storage medium on which a program is stored, and when the program is executed by a processor, the steps in any one of the test methods in the above embodiment 2 are implemented. For details, please refer to the description of the method steps in the above corresponding embodiment.

[0181] The above-mentioned readable storage medium includes computer-readable storage medium. Computer-readable storage media include permanent and non-permanent, removable and non-removable media that can implement information storage by any method or technology. The information can be computer-readable instructions, data structures, program modules or other data. Examples of storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0182] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A testing method, characterized in that: Applied to a test system, the test system comprises: a simulation terminal and a terminal consistency analyzer; the simulation terminal is connected to the device under test, and the simulation terminal is used to send a test signal; the terminal consistency analyzer is connected to the device under test, and the terminal consistency analyzer is used to receive the test signal forwarded by the device under test and decode and analyze the test signal; wherein, at the beginning of the test, the simulation terminal and the terminal consistency analyzer complete the synchronization process through the interaction of signaling information; The method comprises: Controlling the analog terminal to send a test signal at a first power; Determine whether a first block error rate and / or a first cyclic redundancy check code check error rate obtained by a terminal consistency analyzer through decoding and analyzing the test signal forwarded by the device under test meets a preset condition; If the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition, determining the sensitivity of the device under test; If the first block error rate and / or the first cyclic redundancy check code check error rate does not meet the preset condition, adjust the first power of the simulation terminal until the first block error rate and / or the first cyclic redundancy check code check error rate meets the preset condition.

2. The method according to claim 1, characterized in that in, The test system also includes: a combiner and a signal generator; the combiner is arranged between the simulation terminal and the device under test; the signal generator is connected to the combiner, and the signal generator is used to send an interference signal to the combiner; the combiner is used to combine the test signal sent by the simulation terminal and the interference signal sent by the signal generator into one signal and then forward it to the terminal consistency analyzer via the device under test.

3. The method according to claim 1, characterized in that If the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition, determining the sensitivity of the device under test includes: Comparing the first power with a standard value, where the standard value is a predefined standard value of sensitivity of the device under test; If the difference between the first power and the standard value is less than or equal to a first preset value, it is determined that the first power is the sensitivity of the device under test.

4. The method according to claim 1, characterized in that: Before controlling the simulation terminal to send the test signal according to the first power, the method further includes: Starting the simulation terminal and the terminal consistency analyzer, and configuring cell parameters respectively; It is determined that the simulated terminal has searched for a cell and completed cell synchronization.

5. The method according to claim 4, characterized in that The cell parameters include at least one of bandwidth, transmit power, SSB subcarrier spacing, uplink and downlink frequency points, SSB offset, physical layer parameters and protocol layer parameters.

6. The method according to any one of claims 1 to 5, characterized in that The test system further includes: a combiner and a signal generator; the combiner is arranged between the simulation terminal and the device under test; the signal generator is connected to the combiner, and the signal generator is used to send an interference signal to the combiner; the combiner is used to combine the test signal sent by the simulation terminal and the interference signal sent by the signal generator into one signal and then forward it to the terminal consistency analyzer via the device under test; the method further includes: Controlling the analog terminal to send the test signal at a second power, where the second power is a predetermined power or a sum of a predetermined sensitivity standard value of the device under test and a preset backoff value; Controlling the signal generator to output a first interference signal; Determine whether a second block error rate obtained by the terminal consistency analyzer through decoding and analyzing the first synthetic signal forwarded by the device under test is less than or equal to a second preset value and / or whether a check error rate of a second cyclic redundancy check code is less than or equal to a third preset value; the first synthetic signal is obtained by synthesizing the test signal sent by the simulation terminal and the first interference signal sent by the signal generator by the combiner; If the second block error rate is less than or equal to the second preset value and / or the check error rate of the second cyclic redundancy check code is less than or equal to the third preset value, determine that the blocking test passes; Otherwise, the blocking test is determined to fail.

7. The method according to claim 6, characterized in that Also includes: Controlling the signal generator to output a second interference signal, wherein the second interference signal is different from the first interference signal; Determine whether a third block error rate obtained by the terminal consistency analyzer through decoding and analyzing the second synthetic signal forwarded by the device under test is less than or equal to a fourth preset value and / or whether a check error rate of a third cyclic redundancy check code is less than or equal to a fifth preset value; the second synthetic signal is obtained by synthesizing the test signal sent by the simulation terminal and the second interference signal sent by the signal generator by the combiner; If the third block error rate is less than or equal to the fourth preset value and / or the check error rate of the third cyclic redundancy check code is less than or equal to the fifth preset value, it is determined that the blocking test passes; Otherwise, the blocking test is determined to fail.

8. A test control device, characterized in that: Applied to a test system, the test system comprises: a simulation terminal and a terminal consistency analyzer; the simulation terminal is connected to the device under test, and the simulation terminal is used to send a test signal; the terminal consistency analyzer is connected to the device under test, and the terminal consistency analyzer is used to receive the test signal forwarded by the device under test and decode and analyze the test signal; wherein, at the beginning of the test, the simulation terminal and the terminal consistency analyzer complete the synchronization process through the interaction of signaling information; The test control device comprises: A first simulation terminal control module, used to control the simulation terminal to send a test signal according to a first power; A first judgment module is used to judge whether a first block error rate and / or a first cyclic redundancy check code check error rate obtained by a terminal consistency analyzer decoding and analyzing the test signal forwarded by the device under test meets a preset condition; a sensitivity determination module, configured to determine the sensitivity of the device under test when the first block error rate and / or the check error rate of the first cyclic redundancy check code meets the preset condition; The first simulation terminal control module is also used to adjust the first power of the simulation terminal when the first block error rate and / or the check error rate of the first cyclic redundancy check code do not meet the preset conditions until the first block error rate and / or the check error rate of the first cyclic redundancy check code meet the preset conditions.

9. A test control device, comprising a memory, a processor, and a program stored in the memory and executable on the processor; characterized in that: When the processor executes the program, the steps in the testing method according to any one of claims 1 to 7 are implemented.

10. A readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, the steps of the testing method according to any one of claims 1 to 7 are implemented.

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