Charge locking circuit and control system for qubit

Abstract

Systems and methods related to charge locking circuits and control systems for qubits are provided. A system for controlling qubit gates includes a first packaging device including a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a low temperature. The system also includes a second packaged device including a control circuit configured to operate at a low temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit includes a plurality of charge locking circuits configured to lock the charge of the first packaged device to the second packaged device. Wherein each charge locking circuit of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate.

Description

[0001] This application is a divisional application of the invention patent application with the international filing date of April 27, 2020, which entered the Chinese national phase on December 14, 2021, with Chinese national application number 202080043770.8, entitled "Charge-locked circuit and control system for qubits". Background Technology

[0002] Semiconductor-based integrated circuits used in electronic devices such as digital processors include digital circuits based on complementary metal-oxide-semiconductor (CMOS) technology. An additional approach to using CMOS-based processors and related components is to use devices based on superconducting logic. These devices can also be used to process quantum information, such as qubits. Summary of the Invention

[0003] In one aspect, this disclosure relates to a system for controlling qubit gates. The system may include a first encapsulation device including a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system may also include a second encapsulation device including control circuitry configured to operate at cryogenic temperatures, wherein the first encapsulation device is coupled to the second encapsulation device, and wherein the control circuitry includes a plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is coupled via interconnects to at least one of the plurality of qubit gates, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate.

[0004] In another aspect, this disclosure relates to a method for controlling a system of qubit gates, the system including a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures, and control circuitry is configured to operate at cryogenic temperatures, wherein the control circuitry includes a plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is coupled to at least one of the plurality of qubit gates via an interconnect, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate, and wherein each of the plurality of charge-locked circuits includes a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage quantity or a second voltage quantity, wherein the first voltage quantity is greater than the second voltage quantity. The method may include operating a first subset of the plurality of charge-locked circuits in capacitive mode, such that the voltage signal output to at least one qubit gate comprises a pulse signal having a first controlled amplitude, wherein the first controlled amplitude depends on the amount of the input voltage signal and each of the first and second voltage quantities. The method may also include operating a second subset of multiple charge-locked circuits in direct mode such that the voltage signal output to at least one qubit gate includes a signal having a second controlled amplitude, wherein the second controlled amplitude depends on the input voltage signal and only one of a first voltage quantity or a second voltage quantity.

[0005] In another aspect, this disclosure relates to a system for controlling qubit gates. The system may include a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system may also include control circuitry configured to operate at cryogenic temperatures, wherein the control circuitry includes a plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is coupled to at least one of the plurality of qubit gates via interconnects, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate, and wherein each of the plurality of charge-locked circuits includes an input terminal for receiving an input voltage signal and an output terminal for selectively providing a voltage signal to at least one qubit gate, and wherein the control circuitry further includes control logic configured to provide at least one control signal associated with each of the plurality of charge-locked circuits.

[0006] In another aspect, this disclosure relates to a system for controlling qubit gates. The system may include a first packaged device including a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system may also include a second packaged device including a control system configured to operate at cryogenic temperatures, wherein the first packaged device is coupled to the second packaged device. The control system may include a plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is coupled to at least one of the plurality of qubit gates via interconnects, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate. The control system may further include control circuitry including a finite state machine configured to provide at least one control signal to selectively enable at least one of the plurality of charge-locked circuits and selectively support providing at least one voltage signal to a selected charge-locked circuit among the plurality of charge-locked circuits.

[0007] In another aspect, this disclosure relates to a system for controlling qubit gates. The system may include a first packaged device including a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system may also include a second packaged device including a control system configured to operate at cryogenic temperatures, wherein the first packaged device is coupled to the second packaged device. The control system may include a plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is coupled to at least one of the plurality of qubit gates via interconnects, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate. The control system may further include control circuitry including control logic configured to provide at least one control signal to selectively enable at least one of the plurality of charge-locked circuits.

[0008] In another aspect, this disclosure relates to a system for controlling qubit gates. The system may include a first packaged device including a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system may also include a second packaged device including a control system configured to operate at cryogenic temperatures, wherein the first packaged device is coupled to the second packaged device. The control system may include a plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is coupled via interconnects to at least one of the plurality of qubit gates, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate. The control system may also include a digital-to-analog converter for generating at least one voltage signal. The control system may further include control circuitry including a finite state machine configured to provide at least one control signal to selectively enable at least one of the plurality of charge-locked circuits and selectively support providing at least one voltage signal to a selected charge-locked circuit among the plurality of charge-locked circuits.

[0009] This summary is provided to present a simplified description of the selection of concepts further described below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0010] This disclosure is illustrated by way of example and is not limited to the accompanying drawings, wherein the same reference numerals indicate similar elements. The elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

[0011] Figure 1 A system 100 for controlling qubits according to an example is shown;

[0012] Figure 2 A common substrate comprising a low-temperature CMOS control chip, a qubit chip, and a resonator chip, according to an example, is shown.

[0013] Figure 3 A block diagram of a control system associated with fast control multiplexing is shown, based on an example.

[0014] Figure 4 A plan view of a cryogenic CMOS control chip including a control system, according to an example, is shown.

[0015] Figure 5 A charge-locked fast-gated (CLFG) unit according to an example is shown;

[0016] Figure 6 It shows the relationship with Figure 5 Example waveform 600 associated with the operation of the CLFG unit;

[0017] Figure 7A and Figure 7B Various blocks associated with a cryogenic CMOS control chip 700 according to an example are shown;

[0018] Figure 8 A block diagram of charge locking and fast gating based on an example is shown;

[0019] Figure 9 An example of a fast gating circuit is shown;

[0020] Figure 10 A finite state machine for controlling the operation of a CLFG cell is shown according to an example.

[0021] Figure 11A and Figure 11B An example system is shown that can be used to generate an enable signal as part of an example cryogenic CMOS control chip;

[0022] Figure 12 A CLFG cell array based on an example is shown;

[0023] Figure 13 An example CLFG cell configured to operate in capacitor mode is shown according to an example;

[0024] Figure 14 An example CLFG cell configured to operate in dual modes, including capacitive mode and direct mode, is shown according to an example.

[0025] Figure 15 It shows the relationship with Figure 13 and Figure 14 Example waveforms associated with the signals of the CLFG unit shown;

[0026] Figure 16 Example waveforms associated with a simulation of a CLFG cell in capacitor mode are shown;

[0027] Figure 17 A first view and a second view of the active region of an example qubit device during a charge-locked test are shown.

[0028] Figure 18 A view showing the voltage and current variations associated with a quantum dot contact (QPC) according to an example;

[0029] Figure 19 Example waveforms corresponding to a cryogenic CMOS control chip are shown during testing of fast gating operations with quantum dots;

[0030] Figure 20 An example readout waveform corresponding to the readout signal through the quantum dot is shown during testing of a cryogenic CMOS control chip;

[0031] Figure 21 An example FDSOI digital device is shown;

[0032] Figure 22 An FDSOI simulation device based on an example is shown; and

[0033] Figure 23 A flowchart corresponding to a method associated with the system described in this disclosure is shown. Detailed Implementation

[0034] The examples described in this disclosure relate to a system for controlling qubit gates. Controlling a quantum device requires generating a large number of static and dynamic voltage signals, preferably at cryogenic temperatures tightly integrated with the quantum device, as used in this disclosure. The term "(multiple) cryogenic temperatures" refers to any temperature equal to or less than 300 Kelvin. This is a significant challenge, given that cryogenic environments severely limit the power consumption of any active electronic device. Furthermore, a large number of voltage signals also need to be coupled to the qubit gates in the quantum computing device. This is because potentially thousands of leads need to be connected to voltage sources to drive the qubit gates in the quantum computing device. Moreover, qubits are conventionally controlled using room-temperature pulse generators, which must generate large signals that decay in a cryostat. The power required to overcome this decay, as well as the power required to drive the cable impedance, is an obstacle to scaling quantum computers.

[0035] The examples described in this disclosure relate to cryogenic control circuitry and architectures for quantum computing devices. The control architecture includes an integrated circuit control chip containing cryogenic control circuitry tightly integrated with the qubit plane. As an example, the control chip can be wire-bonded or flip-chip mounted to the qubit plane. Additionally, the control chip stores charge on capacitors (including interconnect capacitors) to generate bias voltages. A single digital-to-analog converter can be used to set the charge on each capacitor, which remains cryogenic for extended periods due to the extremely low leakage paths at these temperatures. Charge refresh can be cyclically performed on timescales commensurate with qubit operation. The challenge associated with decaying generated heat is addressed by deploying “charge shuffling” circuitry—moving charge between capacitors to generate voltage pulses. Capacitance is minimized through tight integration between the cryogenic CMOS control chip and the qubit plane. This tight integration (e.g., via chip stacking packaging methods) significantly reduces capacitance, thereby impacting power dissipation.

[0036] In one example, the low-temperature CMOS control chip can be implemented using a fully depleted semiconductor-on-insulator (FDSOI) process. In one example, an FDSOI-based device may include an undoped gate channel, an ultrathin body, source, drain, and an ultrathin buried oxide (BOX) beneath the gate, along with complete dielectric isolation from adjacent devices. Capacitors for charge storage are implemented using on-chip devices. The back-gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address cooling-related effects. The control chip includes circuit blocks partitioned into domains that impart a common back-gate bias. Example domains with individual biases include circuit blocks for n-type devices, circuit blocks for p-type devices, circuit blocks for analog devices, and circuit blocks for digital devices. In some examples, different back-gate biases are provided for transistors with different aspect ratios.

[0037] A qubit plane can include topological computing gates that operate at approximately 20 milliklvin (~20 mK). Quantum computing devices can process quantum information, such as qubits. Qubits can be implemented using a variety of physical systems, including photons, electrons, Josephson junctions, quantum dots, or heterostructures. Multiple quantum states can be encoded as spin direction, another side of the spin, charge, energy, or an excitation level that is part of the qubit, or a topological phase of a superconducting material. Example qubits can operate based on low-frequency DC signals (e.g., bias current) or high-frequency radio frequency signals (e.g., 10 GHz signals), or a combination of both. In some examples, microwave signals can be used to control the states of superconducting devices, including, for example, qubits. Some implementations of qubit gates may require high-frequency microwave signals.

[0038] Figure 1A system 100 for controlling qubits is illustrated according to an example. In this example, system 100 may include multiple energy levels, each of which can be configured to operate at different temperatures. Therefore, system 100 may include energy levels 110, 130, and 150. Energy level 110 may include components configured to operate at room temperature (e.g., ambient temperature) or between 4 Kelvin and room temperature. Energy level 130 may include components configured to operate at 300 Kelvin or below and up to 4 Kelvin. Energy level 150 may include components configured to operate at 20 millikelvin (mK) or approximately 20 millikelvin (mK). Energy level 110 may include a microcontroller 112 (or microprocessor), a digital-to-analog converter (DAC) 114, a signal generator 116, and a measurement device 118. Microcontroller 112 may generate control signals configured to control the qubits and other aspects of system 100. DAC 114 can receive digital control signals from microcontroller 112 (or from other components) and convert these signals into analog form. The analog signals can then be transmitted to other energy levels as needed. Signal generator 116 may include a microwave signal generator and other clock signal generators as required. Measurement device 118 may include instruments such as a spectrum analyzer.

[0039] Continue to refer to Figure 1 Level 130 may include components configured to interconnect level 110 and level 150 in a manner that reduces heat load and allows efficient connectivity between components at room temperature and components at 20 milliklvin (mK). Therefore, in this example, level 130 may include component 132, interconnect 134, interconnect 136, and interconnect 138. In one example, component 132 may be implemented as a high electron mobility transistor (HEMT) low-noise amplifier. Interconnects 134, 136, and 138 may be implemented as cables comprising conductors such as niobium and copper. The conductors may be insulated within the interconnects using a suitable dielectric material such as polyimide.

[0040] Still refer to Figure 1Energy level 150 may include coupler 152, readout multiplexing 154, fast control multiplexing 156, and qubit 160. Coupler 152 can couple signals from a signal generator (e.g., signal generator 116) to readout multiplexing 154. Coupler 152 can also direct any reflected signals to component 132. Readout multiplexing 154 and fast control multiplexing 156 can be implemented on a single control chip (sometimes called a cryogenic control CMOS chip). In one example, readout multiplexing 154 can be implemented using a superconducting material, such as niobium on an inert substrate (e.g., sapphire). The readout multiplexing 154 chip can contain multiple inductor, capacitor, and resistor elements of suitable size to form a group of resonators. At low temperatures, the resonator circuitry exhibits superconductivity and produces resonators with a high quality factor. This can provide an efficient, low-loss frequency multiplexing mechanism. In one example, a low-temperature CMOS control chip (e.g., an ASIC manufactured using semiconductor technologies such as CMOS) can be mounted on the same substrate as the qubit (e.g., qubit 160) and can be configured to operate at the same low temperature as the qubit (e.g., 20 mK).

[0041] Figure 2 A common substrate 200 comprising a cryogenic CMOS control chip 210, a qubit chip 250, and a resonator chip 280, according to an example, is shown. The cryogenic CMOS control chip 210 may be coupled to contact pads (e.g., contact pads 222 and 224) via wire bonding (e.g., wire bonds 212 and 214). The cryogenic CMOS control chip 210 may also be coupled to contact pads (e.g., contact pads 226 and 228) via wire bonding (e.g., wire bonds 216 and 218). The cryogenic CMOS control chip 210 may also be coupled to other contacts (e.g., contacts 234 and 236) via wire bonding (e.g., wire bonds 230 and 232). The qubit chip 250 may be coupled to contact pads (e.g., contact pads 256 and 258) via wire bonding (e.g., wire bonds 252 and 254). The qubit chip 250 can be coupled to the resonator chip 280 via wire bonding (e.g., wire bonds 260 and 262). The resonator chip 280 can be coupled to contacts (e.g., contacts 290 and 292) via wire bonding (e.g., wire bonds 282 and 284). Although not in Figure 2As shown, however, to mitigate unnecessary heating in quantum devices, the chip packaging arrangement can also include thermal management by bonding each chip to individual gold-plated copper pillars that are in parallel thermal contact with the mixing chamber energy levels of the dilution refrigerator. While this example illustrates tight integration between the control chip and the qubits via wire bonding, other techniques can also be used. As an example, the control chip can be flip-chip bonded to a substrate containing qubits. Alternatively, stacked packaging, system-in-package, or other multi-chip assemblies can also be used.

[0042] In this example, the cryogenic CMOS control chip can be implemented using 28nm-FDSOI technology, an inherently low-power, low-leakage CMOS platform suitable for cryogenic operation. The transistors in FDSOI can provide the utility of configuring back-gate bias to offset threshold voltage variations with temperature. This example platform offers both high (1.8V) and low (1V) voltage cells and also allows for individual back-gate control of n-type and p-type transistors or entire circuit blocks, a useful aspect of mixed-signal circuit design, such as the example control system.

[0043] Figure 3 A block diagram of a control system 300 associated with a fast control multiplexer 156, according to an example, is shown. The control system 300 can be used to control the behavior of a charge latching and fast gate (CLFG) unit 360 incorporated as part of a control chip. The control system 300 may include a serial peripheral interface (SPI) interface 310, a waveform memory 320, a voltage-controlled oscillator (VCO) 330, and a clock selection multiplexer (C... SEL )340 and finite state machine 350. As shown, three different voltage levels can be coupled to the cell, including V HOLD V HIGH and V LOW C SEL 340 is used to select the clock signal provided to the finite state machine. Additional details about the finite state machine and related registers will be provided later.

[0044] In one example, the control system 300 can be implemented as part of a cryogenic CMOS control chip. Figure 4 A plan view of a cryogenic CMOS control chip 400 according to an example is shown, including a control system 420 (similar to...). Figure 1The control system 300. The cryogenic CMOS control chip 400 may include digital and analog blocks. In this example, the cryogenic CMOS control chip 400 may include a charge-locked and fast-gated (CLFG) unit and components corresponding to the control system 420. In this example, the cryogenic CMOS control chip 400 may include logic 410 and the CLFG unit. In one example, logic 410 may include a series of coupled digital logic circuits that provide chip communication, waveform memory, and autonomous operation via two FSMs. Logic 410 may include the control system 420, which may include an oscillator 422, a finite state machine(s) FSM(s) and an SPI interface (e.g., an FSM+SPI interface) 424, and a memory 426. Oscillator 422 may be implemented as a ring oscillator and frequency divider with configurable length. Additional details about the FSMs will be provided later. Memory 426 may be configured as a 128-bit register that allows arbitrary pulse patterns to be stored. Tiled along the left and bottom edges of the chip are likely repeating blocks of analog circuitry “CLFG” that generate the static and dynamic voltages required to control the qubits. CLFG cells may include cells 432, 434, 436, and 438. In the examples described here, although the CLFG cells are implemented on a single die, they can be formed on multiple dies packaged together or otherwise interconnected. Although Figure 4 A plan view of a low-temperature CMOS control chip 400 is shown; the chip can have different plan views. Additionally, although... Figure 4 A number of components are shown arranged in a certain way, but the cryogenic CMOS control chip 400 may include additional or fewer components arranged differently.

[0045] Figure 5 A CLFG unit 500 according to an example is shown. The CLFG unit 500 can be configured to lock charge and provide a voltage output. Each CLFG unit 500 can correspond to any one of N units. The CLFG unit 500 can include two parts: one for coupling the quiescent voltage to the output terminal (labeled GATE). <n>Part 510 and the part for applying dynamic voltage (based on voltage V) HIGH or voltage V LOW A portion 550 of the CLFG unit 500 may include a switch 512 that is responsive to a signal G. The voltage in the signal G is coupled to the output terminal. LOCK,N And operation. This signal can be provided under the control of an appropriate finite state machine or another type of control logic or instruction. When switch 512 is closed, voltage V HOLD It can be coupled to the label C PULSE,N One plate of the capacitor, representing the on-chip capacitor. A portion 550 of the CLFG unit 500 may also include switches 552 and 554. The CLFG unit 500 may also include an inverter 556. The CLFG unit 500 can be configured such that only one of these switches (switch 552 and switch 554) is closed at some point. In this example, it is labeled as... GFG,N The signal can control switch 552, and an inverted version of the signal (e.g., inverted by inverter 556) can control switch 554. Thus, at a certain time, the voltage V... HIGH or voltage V LOW It can be coupled to the symbol C via one of the two switches. PULSE,N The second plate of the capacitor represents the on-chip capacitance.

[0046] Continue to refer to Figure 5 C P This is likely due to the sum of parasitic capacitances generated by the wiring in the low-temperature CMOS control chip and the qubit chips(s), as well as the leads (or other interconnections) used to interconnect the two. The cell can first be configured via an on-chip finite state machine (FSM) that connects an external voltage source to the input terminals of the CLFG cell 500 (in... Figure 5 (marked as IN), thereby raising its potential to V. HOLD In this example, a single channel of the room-temperature digital-to-analog converter (DAC) can be used as a source, and the FSM sequentially switches each CLFG cell to contact that bias voltage, thereby energizing the capacitor and then locking it at the high-impedance output to generate the charge needed for the quiescent voltage. The circuit includes an on-chip capacitor C. PULSE and parasitic capacitance C P This includes contributions from bonding pads, bonding leads, and gate interconnects on the qubit chip. After charging, switch 512 is turned on by the FSM (e.g., by deactivating G). LOCK,N A signal is generated that causes the charge on the capacitor and the qubit gate to float. This locked charge remains even when the CLFG cell 500 is removed, thus establishing a static voltage that can be used to configure the offset bias of the qubit device. Although Figure 5 A number of components are shown arranged in a certain way, but the CLFG unit 500 may include additional or fewer components arranged differently.

[0047] Figure 6 Example waveform 600 associated with the operation of CLFG cell 500 is shown. For dynamic control, voltage pulses are needed to rapidly change the gate potential and energy state of the qubits. Generating such pulses remotely from the qubit plane requires a large amount of energy because the generator must drive the cable impedance, even if the power is not dissipated at the end of the open line. Alternatively, fairly large voltage pulses can be generated with very little energy by redistributing local charge in a circuit with small capacitance. In this example, this concept is used to implement the dynamic operation of CLFG cell 500. Under the control of the second FSM, the cell is selected for pulses, and a preloaded pulse pattern stored in the register memory is applied to switch G. FG .

[0048] Switches 552 and 554 are used to switch between two voltage sources V HIGH and V LOW Between toggling capacitor C PULSE The lower electrode is controlled in a manner similar to that of the chip. These sources can be external to the chip or derived from locally pre-charged capacitors. With C PULSE The potential of the lower plate switches to V LOW or V HIGH Charge is induced onto the top plate, thereby changing the output voltage V relative to the ground reference. OUT .

[0049] In this example, the amplitude of the pulse is determined by ΔV PULSE =(C PULSE / (C P +C PULSE ))(V HIGH -V LOW The value is given, and the power dissipation P is given. PULSE Given the total capacitance, pulse frequency f, and voltages at both levels, P PULSE =((C P ×C PULSE ) / (C P +C PULSE ))(V HIGH –V LOW ) 2 f. Because C P and C PULSE They are (pF) chip-level capacitors, so they require very little power to charge.

[0050] Figure 7A and Figure 7B Various blocks associated with a cryogenic CMOS control chip 700 according to an example are shown. As previously explained, the cryogenic CMOS control chip 700 may include analog and digital components. In this example, the cryogenic CMOS control chip may include an analog-to-digital converter (ADC) buffer 702, an ADC 704, an ADC SRAM 706, and an ADC control 708. The cryogenic CMOS control chip 700 may also include a clock driver 710, a waveform generator 720, and a reference and bias generator 722. These components may be coupled via various buses. Each bus may include at least one signal line. Figure 7A and Figure 7B As shown, the cryogenic CMOS control chip 700 can receive various external signals, including clock signals, various voltages, and control signals. Some clock signals are generated and received externally via pins associated with the control chip.

[0051] Continue to refer to Figure 7A The cryogenic CMOS control chip 700 may also include a main control and register 730 and various miscellaneous blocks 740. The main control and register 730 may include a Serial Peripheral Interface (SPI) that allows communication with an external processor. The miscellaneous blocks 740 may include a Sample & Hold (S&H) block 742, a comparator 744, and a Radio Frequency (RF) Multiplexer (MUX) 746. The RF MUX 746 allows selection between two RF signals (RFIN1 and RFIN2). In this example, there is an Advanced Peripheral Block Clock (APBCLK) input for the main control and register 730 and a separate APBCLK input pin for the charge latch and fast gating block 750. Figure 7B As shown, for the charge-locked and fast-gated 750, it is also possible to switch to a local oscillator (e.g., VCO 754). The local oscillator can also be down-divided via the configuration register. The SPI clock (SCLK) comes from the SPI master. In this example, there is a clock ratio requirement between APBCLK and SCLK from the SPI master. In one example, APBCLK must be >= 4 * SCLK. To ensure correct timing, clock domain crossover (CDC) logic is placed between SCLK and APBCLK, and another CDC logic is placed between APBCLK and the divider oscillator clock.

[0052] Figure 7B A diagram illustrating some aspects of a charge-locked and fast-gated (CLG) 750 is shown. The CLFG 750 may include a master control and register 752, a voltage-controlled oscillator (VCO) 754, and a CLFG cell array 760. The control and register 752 may include an SPI interface. The control and register 752 may include register read / write blocks, which may in turn be coupled to a register file. The VCO 754 may be configured to provide an additional clock signal for use with some aspects of the CLFG 750. The CLFG cell array 760 may include CLFG cells 762 and 764, each CLFG cell being similar to... Figure 5 The CLFG unit 500.

[0053] Figure 8 A block diagram of a charge-locked and fast-gated (CLFG) 800 according to an example is shown. The CLFG 800 may include an SPI interface 810 coupled to a register read / write interface 820 via a bus (e.g., APB), which in turn may be coupled to a register 830 (e.g., the register may be included as part of a register file). The CLFG 800 may also include a finite state machine 840, which may be configured to receive inputs from registers and provide output signals to a CLFG cell array 880, which may in turn provide voltages to quantum bits. The CLFG 800 may also include an oscillator 850, a frequency divider (FDIV) 860, and a multiplexer 870. The multiplexer 870 may receive the APB clock as one input and the frequency divider output as another input. Thus, in this example, the finite state machine is able to copy either the APBCLK clock or a clock signal from a local oscillator. The clock control module can be used to divide the local oscillator clock into integer values ​​from 1 to 255, and the multiplexer 870 can be used to allow switching between APBCLK and the divided oscillator clock. The divided clock has no duty cycle requirement. The clock output of the clock control module is called XCLK, and it is used for timing the finite state machine.

[0054] Table 1 below lists some signals and their descriptions for the low-temperature CMOS control chip.

[0055]

[0056] Table 1

[0057] Table 2 lists some of the registers associated with the cryogenic CMOS control chip. Since the descriptions of most registers are self-evident, only a few registers and their functions are described to explain the operation of the cryogenic CMOS control chip.

[0058]

[0059]

[0060]

[0061]

[0062]

[0063] Table 2

[0064] While Table 2 shows some registers and their arrangement, additional or fewer registers may be used. Furthermore, the information presented in the table can be passed to the cryogenic CMOS control chip via modes other than registers. As an example, special instructions can be used to encode the information contained in the registers. The architecture enabled by the registers described in Table 2 assumes 32 charge-locked fast-gated (CLFG) cells. In this example, each CLFG cell can be DC charged independently and can be rapidly pulsed according to a waveform stored in the FGSR register. In this implementation, 128 bits can be stored in four 32-bit registers (e.g., registers FGSR0-3), and any charge-locked fast-gated cell can be rapidly pulsed according to the bit patterns stored in these registers. The bit patterns can be continuously repeated or played once under the control of the FSM. This implementation is suitable for two-stage pulses; however, it can be extended to multi-stage pulses. In this example architecture, the REG_CTL1 register described in Table 2 contains information used by a started finite state machine to initiate and complete cell charging. As an example, bit 8 of this register controls when the counter selected by FGSR is enabled, and increments every clock cycle of the XCLK clock until it reaches 127, at which point the counter toggles. As another example, bits 4 and 5 of the REG_CTL1 register control whether a complete DC charge sequence occurs across all 32 cells, or whether a selective DC charge sequence occurs only on a subset of the 32 cells.

[0065] Figure 9 An example of a fast gating circuit 900 is shown. As previously described, as part of Table 2, four 32-bit registers can control the output of the fast gating circuit 900. The fast gating circuit 900 may include a counter 910 and a multiplexer 920, which can be coupled to receive the output of the counter 910 as an input and receive the corresponding register REG_CTL. <3> The value is used as another input. The fast gate circuit 910 may also include an AND gate 930, a multiplexer 940, and a gate 950, which can be used as... Figure 9 They are coupled to each other as shown. These logic elements can also receive... Figure 9 The signal is shown. Counter 910 selects the bit position of the 128-bit value to output on the CL_FG terminal. In this example, this is a 128:1 multiplexer. Each clock cycle (e.g., corresponding to...) Figure 9 When the clock XCLK is shown, counter 910 is incremented by 1. Counter 910 wraps back to 0 and continues counting. The value of the bit stored in REG_CTL[8] enables counter 910. Therefore, in this example, when REG_CTL[8] = 0, the counter remains at 0 and does not increment. If the charge-locked state machine is not idle, then the fast-gated output CL_FG is 0. In this case, the counter continues to increment as long as REG_CTL[8] = 1.

[0066] Continue to refer to Figure 9 In one example, the programming sequence for updating the 128-bit FGSR and starting a new fast gating sequence is as follows: (1) clear REG_CTL1[8] to keep the counter at 0, or set REG_CTL1[1] to stop XCLK, (2) write the new value to the four 32-bit FGSR registers, and (3) set REG_CTL1[8] to allow the counter to increment, or clear REG_CTL1[1] to restore XCLK. In one example, the FG output can also be overwritten. When REG_CTL1[2] = 1, the CL_FG output is equal to REG_CTL1[3]. Although Figure 9 A fast gating circuit 900 with a certain number of components arranged in a certain way is shown, but the fast gating circuit 900 may include additional or fewer components with different arrangements. Additionally, other signals may be used to provide additional or fewer controls.

[0067] Figure 10 A finite state machine 1000 according to an example is shown. In this example, finite state machine 1000 includes two finite state machines: FSM A and FSM B. Each of the finite state machines is configured for DC charging of CLFG cells (e.g., CLFG cell 500). FSM A corresponds to a finite state machine that is configured to charge only those CLFG cells that are enabled according to the bits in the CL_EN register simultaneously. FSM B corresponds to a finite state machine that is configured to charge all CLFG cells in the CLFG array (e.g., all 32 cells in a CLFG array with 32 cells) sequentially. In this example, bit values ​​stored in registers (e.g., bits 4 and 5 of the 32-bit register REG_CTL1 corresponding to the field BEGIN_CHRG described in Table 2) determine which of the two finite state machines is active. In this example, FSM A is activated when the BEGIN_CHRG field transitions from 00 to 01; alternatively, FSM B is activated when the BEGIN_CHRG field transitions from 00 to 10. The output signals from FSM A and FSM B are provided as the CHRG signal, which is coupled to one of the inputs of multiplexer 1002. Other inputs of multiplexer 1002 include those stored in REG_CTL. <6> The bit values ​​in the table are described in Table 2. The output of multiplexer 1002 is a global DC charge signal and is labeled CL_CHRG. The value of the 7th bit (e.g., REG_CTL) <7> Determine whether the outputs of FSM A and FSM B are provided as a DC charge signal, or whether the DC charge signal is selected by the user as the value of bit 6 of the REG_CTL register described in Table 2.

[0068] Continue to refer to Figure 10 Upon startup, FSM A begins in the IdleA0 state and transitions to the countdown A state. As part of this transition, FSM A maintains the CHRG signal and begins a countdown to DC charge the enabled CLFG cells. Throughout the operation of FSM A, the CL_EN value remains the same as previously specified by the user. In this example, when the local enable signal of a specific CLFG cell is high (e.g., CL_EN), the value remains the same. When = 1), the i-th CLFG cell is enabled. Therefore, by gating the CHRG signal, the local enable signal ensures that the CLFG cell is charged only when it is able to charge. After charging is complete, FSM A enters the idle state IdleA1. Table 3 below shows the FSM A's... Figure 10 The document provides example correspondences between transitions / states and example values ​​for bits and other signals.

[0069]

[0070] Table 3

[0071] Still refer to Figure 10 During startup, FSM B enters the START_CHRG state, and assuming there are 32 CLFG units, when CL_EN... <32> Charging of the 32nd CLFG cell begins when bit START_CHRG is set to 1 and each of the other enable bits is set to 0. As part of this process, FSM B enters Countdown B state and counts down the clock cycles (e.g., DCSR clock cycles) required for the sequential charging of the CLFG cells. Except in the START_CHRG state and Countdown B state, the CL_EN value remains the same as previously specified by the user throughout the operation of FSM B. <31> When bit 32 is set to 1 and the remaining enable bits are set to 0, DC charging of the 32nd CLFG cell is complete, and DC charging of the 31st CLFG cell begins. In this example, these steps are repeated until all 32 CLFG cells are charged. Then, FSM B transitions to an idle state (e.g., IdleB1 state). Table 4 below shows the FSM B's... Figure 10 The document provides example correspondences between transitions / states and example values ​​for bits and other signals.

[0072]

[0073] Table 4

[0074] Although Figure 10 A specific finite state machine is shown that operates in a certain way, but other state machines can also be used. Although Tables 3 and 4 show the specific bits and signals and their corresponding values ​​for two finite state machines, other bits and signals and their corresponding values ​​can also be used. Furthermore, the functionality associated with the state machine can be implemented using other logic or instructions.

[0075] Figure 11A and Figure 11B An example system 1100 is shown, which can be used to generate an enable signal as part of an example cryogenic CMOS control chip. A previously described FSM can be used to interface with system 1100, which can be used to generate the enable signal used to select the charging CLFG cell. This example also assumes that 1024 CLFG cells (arranged in a grid comprising 32 rows and 32 columns) need to be controlled. System 1100 may include a host logic and clock section 1110, a row decoder 1120, and a column decoder 1130. The host logic and clock section 1110 may include circuitry and logic configured to store and interpret instructions or commands in a manner similar to a memory controller. The row decoder 1120 may be configured to receive row addresses from the host logic and clock section 1110 and maintain labels labeled R0 to R10. 31 One or more signals. Column decoder 1130 can be configured to receive column addresses from host logic and clock section 1110 and maintain markers from C0 to C10. 31 and D0 to D 31 One or more signals.

[0076] Now refer to Figure 11B System 1100 may also include a bus system to couple signals generated by row decoder 1120 and column decoder 1130 to circuit 1140. Circuit 1140 may be configured to generate a signal labeled OUT at its output terminal. I,FG The signal can be coupled to qubit gate 1160. Circuit 1140 is an example implementation of the "direct mode" of a CLFG cell similar to that described earlier. Therefore, in this example, when the corresponding row (R J ) signals and corresponding columns (C I When the (D) signal is high and the drive line (D) signal is high or low, circuit 1160 can be connected to the voltage bus V. LFG or V HFG Circuit 1140 can also be implemented as a CLFG cell array (e.g., as shown in the image). Figure 5 (As shown and previously described). Although Figure 11 shows the system 1100 as having some components arranged in a certain way, it is possible to have more or fewer components arranged differently.

[0077] Figure 12 A CLFG cell array 1200 according to an example is shown. As an example, the CLFG cell array 1200 may correspond to the CLFG cell array 760 of Figure 7 and may be included as part of a low-temperature CMOS control chip. In this example, the CLFG cell array 1200 may include 32 CLFG cells (e.g., CLFG cells 1210, 1220, 1230, 1240, and 1250). Each of these CLFG cells can be configured to generate one OUTCL signal in the OUTCL signal, which can be used to provide control or other types of voltage to the quantum bits. Each CLFG cell can receive signals labeled CL_FG, CL_CHRG, VICL, VHFG, and VLFG. These signals will be relative to... Figure 13 and Figure 14 A more detailed description is provided. Additionally, some of these signals have previously been described as part of a description associated with the cryogenic CMOS control chip. Each CLFG unit can also receive an enable signal (e.g., CL_EN). <0> CL_EN <1> CL_EN <2> CL_EN <30> or CL_EN <31> ,like Figure 12 (As shown). The enable signal can allow selective or sequential DC charging, as previously indicated relative to... Figure 10 The finite state machine description in the text explains this. Figure 12 Each CLFG cell shown may also include an electrostatic discharge (ESD) circuitry system, including ESD circuits 1212, 1222, 1232, 1242, and 1252. CLFG cells may operate in capacitive mode only or in dual modes, including capacitive and direct modes. As an example, a CLFG cell array 1200 may consist of 32 CLFG cells—16 CLFG cells configured to operate in capacitive mode and 16 CLFG cells configured to operate in direct mode. In one example, half of each type of CLFG cell may also contain custom-designed analog pads with reduced ESD protection to further minimize leakage through standard pad structures. Although Figure 12 The CLFG cell array 1200 is shown as having some components arranged in a certain way, but it is possible to have more or fewer components arranged differently.

[0078] Figure 13 An example of a CLFG unit 1300 configured to operate in capacitor mode is shown. Unless otherwise indicated, Figure 13 The signal cited in the text has a similarity to the earlier one. Figures 5 to 7B and the same meaning described in Tables 1 and 2. CLFG unit 1300 is consistent with... Figure 5 The CLFG unit 500 is configured in a similar manner. The CLFG unit 1300 is configured to lock charge and provides a voltage output at the output terminal (OUT) associated with the CLFG unit. Each CLFG unit 1300 can correspond to any one of N units. The dynamic voltage (based on the voltage via the VHFG terminal) is... Figure 5 V is referred to as V in Chinese. HIGH The voltage received or via the VLFG terminal (in) Figure 5 V is referred to as V in Chinese. LOW One of the received voltages can be coupled to the output terminal. The CLFG unit 1300 may include components responsive to the signal CL_EN. <n>Switch 1312 is operated by a signal. This signal can be provided under the control of a suitable finite state machine or another type of control logic, such as relative to... Figure 10 Described. When switch 1312 is closed, the voltage received via the input terminal (IN) on signal line VICL (in Figure 5 V is referred to as V in Chinese. HOLD ) can be coupled to denoted as C PULSE,N One plate of the capacitor represents the on-chip capacitance. The CLFG unit 1300 may also include switches 1314 and 1316. The CLFG unit 1300 may also include an inverter 1318. The CLFG unit 1300 can be configured such that only one of these switches is closed at a certain time. In this example, it is labeled CL_EN. <n>The signal can control switch 1314, and an inverted version of the signal (e.g., inverted by inverter 1318) can control switch 1316. Thus, at a certain time, the voltage V... HIGH or voltage V LOW It can be coupled to the symbol C via one of the two switches. PULSE,N The second plate of the capacitor represents the on-chip capacitor. The CLFG unit 1300 may also include an ESD 1320 coupled to the output terminal (OUT). The CLFG unit 1300 operates only in capacitor mode because the output voltage supplied to the qubit gate is via... Figure 13 The capacitor arrangement shown is provided. Although Figure 13 A number of components are shown arranged in a certain way, but CLFG unit 1300 may include additional or fewer components arranged differently. As an example, CLFG unit 1300 may not include ESD 1320.

[0079] Figure 14 An example of a CLFG unit 1400 configured to operate in dual modes (including capacitor mode and direct mode) is shown. Unless otherwise indicated, Figure 14 The signal cited in the text has a similarity to the earlier one. Figures 5 to 7B And the same meaning described in Tables 1 and 2. The CLFG unit 1400 is configured to lock charge and provides a voltage output at the output terminal (OUT) associated with the CLFG unit. Each CLFG unit 1400 can correspond to any one of N units. In capacitor mode (enabled by maintenance of a signal marked CL_MODE maintained via switch 1414), the dynamic voltage (based on the voltage output via the VHFG terminal (at...) Figure 5 V is referred to as V in Chinese. HIGH The voltage received or via the VLFG terminal (in) Figure 5 V is referred to as V in Chinese. LOW One of the received voltages can be coupled to the output terminal. The CLFG unit 1400 may include components responsive to CL_EN. <n>Switch 1416 is operated by a signal. This signal can be provided under the control of a suitable finite state machine or another type of control logic, such as relative to... Figure 10 Described. When switch 1416 is closed, the voltage received via the input terminal (IN) on signal line VICL (in Figure 5 V is referred to as V in Chinese. HOLD ) can be coupled to denoted as C PULSE,N One plate of the capacitor, representing the on-chip capacitance. The CLFG unit 1400 may also include switches 1416 and 1418. The CLFG unit 1400 may also include an inverter 1420. The CLFG unit 1400 can be configured such that only one of these switches (1416 and 1418) is closed at some point. In this example, it is labeled CL_EN. <n>The signal can control switch 1416, and an inverted version of the signal (e.g., inverted by inverter 1420) can control switch 1418. Thus, at a certain time, the voltage V... HIGH or voltage V LOW It can be coupled to the symbol C via one of the two switches. PULSE,N The second plate of the capacitor represents the on-chip capacitor. When the CL_MODE signal is maintained, the CLFG unit 1400 operates in capacitor mode because the output voltage supplied to the qubit gate is via... Figure 14 The capacitor arrangement shown is provided.

[0080] Continue to refer to Figure 14 When the CL_MODE signal is deactivated, the CLFG unit 1400 can operate in direct mode. Therefore, when the CL_MODE signal is deactivated, switch 1434 closes and depends on CL_EN. <n>The signal state indicates that switch 1436 or switch 1438 is closed. Therefore, at a certain time, the voltage V... HIGH or voltage V LOW It can be coupled to the same terminal via one of the two switches, V IN Voltage is coupled to this terminal via the input terminal (IN). The CLFG unit 1400 may also include an ESD 1450 coupled to the output terminal (OUT). Although Figure 14 A number of components are shown arranged in a certain way, but CLFG unit 1400 may include additional or fewer components in a different arrangement. As an example, CLFG unit 1400 may not include ESD 1450.

[0081] In the cases of CLFG cells 1300 and 1400, the low leakage at low temperatures ensures that the capacitors do not require frequent refreshes once they are charged. Each CLFG cell in the CLFG cell can receive voltage from a single DAC. Using a technique similar to that used in rasterized displays, a single DAC voltage can be used to charge all CLFG cells (e.g., the 32 CLFG cells in the previously described example). Thus, in this example, the DAC voltage is supplied to the capacitors via a switch in the path between the DAC voltage line and the capacitors; after the capacitors are charged, the switch is opened, and the DAC voltage is used to charge the next capacitor in a cyclic manner. By using a shared DAC, the number of input / output lines between the control chip (including the CLFG cell array) and the room-temperature electronics is significantly reduced. As previously described, the interconnect between the low-temperature CMOS control chip and the qubit plane is formed using wire bonding, flip-chip bonding, or other low-impedance interconnect techniques.

[0082] Figure 15 Example waveform 1500 associated with signals from CLFG cells 1300 and 1400 is shown. In this example, each CLFG cell in CLFG cells 1300 and 1400 is shown as operating with respect to a clock labeled XCLK. The CL_CHRG signal is maintained for a period of time based on a clock cycle (or another indicator) specified in a control register (e.g., REG_DCSR) associated with the cryogenic CMOS control chip. The CL_FG control signal is used for charge rinsing. For CLFG cells 1300 and 1400, whenever this control signal is high, the voltage at the OUTCL terminal is VICL+V. HIGH Voltage and V LOW The voltage difference is pulsed. Whenever the CL_FG control signal is low, both CLFG units 1300 and 1400 operate in DC mode, causing the output voltage (represented by the waveform labeled OUTCL in DC mode) to be maintained at the voltage to which the capacitor was initially charged (e.g., via the CL_CHRG signal), and it may dissipate over time without refresh. The waveform labeled OUTCL in capacitor mode shows the output signal of CLFG unit 1300. The same waveform also shows the output of CLFG unit 1400 operating in capacitor mode. The waveform labeled OUTCL in direct mode shows the output signal of CLFG unit 1400 operating in direct mode. Each of these modes is pulsed relative to the earlier... Figure 13 and 14 explain.

[0083] Continue to refer to Figure 15 In capacitor mode, the fast gating operation cycle of the CLFG 1400 consists of a DC charge of the storage capacitor, followed by a series of pulses. In one example, the DC charge period is determined by the REG_DCSR value. The duration and number of pulses are determined by the contents of the CL_FGSR register (explained earlier), which is set to 128 bits. In this example, the contents of this register are read one bit at a time (e.g., by a waveform generator) and applied as a control signal labeled: CL_FG. When using direct drive mode, fast gating consists of a series of pulses, where the output is directly connected to VLFG or VHFG. In direct drive mode, the charging cycle still exists and behaves the same as a "0" value on CL_FGSR. Each of these modes is relative to the previously explained... Figure 13 and 14 explain.

[0084] Figure 16 Example waveform 1600 is shown associated with an simulation of the CLFG cell 1400 in capacitor mode. The waveform labeled OUTCL represents the simulated output signal of the CLFG cell 1400 when operating in capacitor mode. The waveform labeled CL_EN corresponds to the enable signal, which is used to enable the CLFG cell to charge. The CL_CHRG signal is used to charge the capacitor (or capacitors) associated with the CLFG cell. As explained earlier, the CL_CHRG signal is maintained for a period of time based on a clock cycle (or another indicator) specified in a control register (e.g., REG_DCSR) associated with the cryogenic CMOS control chip. For the CLFG cell 1400, whenever the CL_FG control signal is high, the voltage at the OUTCL terminal is VICL+V. HIGH Voltage and V LOW The voltage difference is pulsed. The VICL voltage corresponds to the voltage at the input terminal of the CLFG unit, which can be received from the DAC (as explained earlier). V HIGH The voltage is received via the VHFG terminal, and the waveform is... Figure 16 It is also marked as VHFG. V LOW The voltage is received via the VLFG terminal, and the waveform is... Figure 16 It is also marked as VLFG.

[0085] Continue to refer to Figure 16 Section 1602 of the OUTCL waveform shows the locking of a DC voltage (e.g., 1.8 volts) in the CLFG cell. Section 1604 of the OUTCL waveform shows fast gating of the voltage to generate pulses that can be used as control signals for qubits. Section 1606 shows the locked DC voltage restored after pulse generation. Section 1608 shows the voltage at the OUTCL terminals when the locked DC voltage is not refreshed or restored. Section 1610 shows a locked DC voltage level (e.g., 0.6 volts) that differs from the locked voltage level in section 1602. Section 1612 shows fast gating of the voltage to generate pulses of different amplitudes, which can also be used to control qubits or other such devices. Although Figure 16 The OUTCL waveform is shown as having rectangular pulses, but the pulses can have different shapes. Although Figure 16 The OUTCL waveform is shown as having two different amplitudes; the amplitude of the OUTCL waveform may also vary. Similarly, the pulse frequency of the OUTCL waveform can also be controlled via the previously described low-temperature CMOS control chip. Additionally, the OUTCL waveform can be used to modulate high-frequency signals, such as micro-beam modulation, to generate control signals for qubit gates or other types of qubit devices.

[0086] Figure 17 A first view 1710 and a second view 1750 of the active region of an example qubit device 1700 during a charge-locked test are shown. The qubit device 1700 can be a gallium arsenide (GaAs)-based quantum dot device. In this example, as shown in views 1710 and 1750, multiple signals can be used to control the quantum dots. A previously described low-temperature CMOS control chip can be used to generate any control signals using either capacitive or direct modes associated with the previously described CLFG cell. Signals used to control the qubits may include a left wall (LW) signal, a left plunger (LP) signal, a center wall (CW) signal, a right plunger (RP) signal, and a right wall (RW) signal. Additional signals associated with the quantum dot 1730 in the sensing qubit gate may include a sensing dot top gate (SD). T ), sensing point plunger (SD) P ) and sensor dot bottom grid (SD B In this example, as shown in view 1710, the potentials of control signals LW, LP, CW, RP, and RW can be locked using five CLFG units based on a programmed finite state machine. Although Figure 17 A qubit device 1700 with certain control signals is shown; other types of qubit devices with other control signals can also withstand voltages generated by the previously described cryogenic CMOS control chip.

[0087] Figure 18 View 1800 shows the voltage and current variations associated with a quantum dot contact (QPC) according to an example. Graph 1810 shows the QPC current variation over time. Graph 1820 shows the QPC current variation as a function of the left wall voltage variation. Graph 1830 shows the holding voltage variation of a cryogenic CMOS control chip over time.

[0088] Figure 19 Example waveform 1900 is shown corresponding to a cryogenic CMOS control chip during testing of fast gating operation with quantum dots. Example waveform 1910 corresponds to the readout signal when fast gating is performed at 140 kHz. Example waveform 1920 corresponds to the readout signal when fast gating is performed at 1.26 MHz. Example waveform 1930 corresponds to the readout signal when fast gating is performed at 2.45 MHz. The frequency can be changed using a frequency divider. The waveforms do not share a common time scale. Although Figure 19 The specific duty cycle and amplitude of the voltage pulse associated with the waveform are shown, and these can be changed by a cryogenic CMOS control chip. This advantageously eliminates the need to control the qubit gate from a room-temperature device.

[0089] Controlling qubit gates from room temperature would require attenuating voltage pulses generated at room temperature, resulting in significant heat dissipation from these pulses. Furthermore, instead of a room-temperature voltage signal to handle the load of a meter (or longer) of cable (e.g., a 50-ohm transmission line with a capacitance greater than 200 pF for capacitive loads), the cryogenic CMOS control chip only needs to handle the capacitance of the flip-chip bond and the very short interconnect between the control chip and the qubit gates. This capacitance can be as low as 0.1 pF. This allows the cryogenic CMOS control chip to control the state of thousands of qubits without requiring substantial heat dissipation. Additionally, the power consumption from fast gating is minimal, allowing the control chip to efficiently manage potentially thousands of qubits. Regarding the power requirements for controlling qubits, in one example, assuming the readout clock frequency is set to 1 MHz and the qubit interconnect has a capacitance of 1 pF, the power consumption for 1000 qubit gates for a 0.1 volt pulse is 10 μW. Assuming each qubit has 10 gates, 1mW of power can be used to control 10,000 qubits at a clock frequency of 1MHz or 1,000 qubits at a clock frequency of 10MHz.

[0090] Figure 20 An example readout waveform 2000 corresponding to the readout signal through the quantum dot is shown during testing of a cryogenic CMOS control chip. When the CLFG cell voltage V... HIGH and V LOW Used to generate pulses for controlling quantum dots and sensing point plungers (SD) P Waveform 2000 is generated as the voltage on the gate is scanned. Waveform 2010 shows V HIGH The voltage change, and waveform 2020 shows V LOW Voltage variation. Waveform 2030 shows the pulse applied to the CLFG cell.

[0091] As previously described, in one example, a low-temperature CMOS control chip can be implemented using a fully depleted semiconductor-on-insulator (FDSOI) process. In one example, an FDSOI-based device may include an undoped gate channel, an ultrathin body, a source, a drain, and an ultrathin buried oxide (BOX) beneath the gate, as well as complete dielectric isolation from adjacent devices. As previously described, FDSOI-based devices may include digital and analog devices (e.g., transistors or other devices). Figure 21 An FDSOI digital device 2100 according to an example is shown. The FDSOI digital device 2100 may include a substrate 2102. In this example, the substrate 2102 may be a silicon-on-insulator (SOI) substrate. A deep n-well 2104 may be formed in the substrate 2102 by doping the substrate with an n-type dopant. Additional wells may be formed in the substrate 2102 and the deep n-well 2104. As an example, a p-well 2106 and an n-well 2108 may be formed. Next, transistor devices 2120 and 2130 may be formed using multiple photolithography steps. In this example, transistor device 2120 is a p-type transistor having a gate channel 2122 formed over block 2126. Transistor device 2120 may also include p+ type source / drain regions and contacts S and D with the source / drain. In this example, transistor device 2130 is an n-type transistor having a gate channel 2132 formed over block 2136. Transistor device 2130 may also include n+ type source / drain regions and contacts S and D with respect to the source / drain. Capacitors for charge storage are implemented using this transistor device. Various types of devices and regions can be isolated using shallow trench isolation (STI) regions, which are formed using a dielectric. Example STI regions formed in FDSOI digital device 2100 include STI 2150, STI 2152, STI 2154, STI 2156, STI 2158, and STI 2160.

[0092] Continue to refer to Figure 21 The back gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address cooling-related effects. Therefore, in this example, the FDSOI digital device 2100 includes a N-type device... BG Terminal back grid bias and via P for p-type devices BG Terminal back gate bias. In this example, although the FDSOI digital device 2100 includes the ability to change the back gate bias of the n-type and p-type devices, the back gate voltage of the n-type device is not allowed to be lower than the back gate voltage of the p-type device.

[0093] Still refer to Figure 21 The back-gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address the effects associated with chip cooling in cryogenic environments. The transistor devices and associated control circuitry are designed so that, using back-gate bias control, the threshold voltage of the transistor device can be tuned despite significant variations in the operating temperature of the transistor device. Cryo CMOS control chips can include circuit blocks partitioned into domains that impart a common back-gate bias. Example domains with individual biases include circuit blocks for n-type devices, circuit blocks for p-type devices, circuit blocks for analog devices, and circuit blocks for digital devices. In some examples, different back-gate biases are provided for transistors with different aspect ratios. Although Figure 21 An FDSOI digital device 2100 is shown, comprising a number and type of wells. The FDSOI digital device 2100 may include additional or fewer other types of wells. Additionally, the transistor device may be planar or non-planar (e.g., a FinFET device).

[0094] Figure 22 An example FDSOI analog device 2200 is shown. Unlike the FDSOI digital device 2100, the FDSOI analog device 2200 includes independent back-gate bias control, wherein the back-gate voltage of the p-type device can be boosted to voltage V. DD The above is independent of the back gate voltage of the n-type transistor. The FDSOI analog device 2200 may include a substrate 2202. In this example, the substrate 2202 may be a silicon-on-insulator (SOI) substrate. A deep n-well 2204 can be formed in the substrate 2202 by doping the substrate with an n-type dopant. A p-well 2206 can be formed in the deep n-well 2204, and an n-well 2208 can be formed in the substrate 2202. Next, transistor devices 2220 and 2230 can be formed using multiple photolithography steps. In this example, transistor device 2220 is a p-type transistor with a gate channel 2222 formed over block 2226. Transistor device 2220 may also include p+ type source / drain regions and contacts S and D with the source / drain. In this example, transistor device 2230 is an n-type transistor with a gate channel 2232 formed over block 2236. The transistor device 2230 may also include n+ type source / drain regions and contacts S and D with respect to the source / drain. Various types of devices and regions can be isolated using shallow trench isolation (STI) regions, which are formed using a dielectric. Example STI regions formed in the FDSOI analog device 2200 include STI 2250, STI 2252, STI 2254, STI 2256, STI 2258, STI 2260, STI 2262, and STI 2164.

[0095] Continue to refer to Figure 22 The back gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address cooling-related effects. Therefore, in this example, the FDSOI analog device 2200 includes a N-type device... BG Terminal back grid bias and via P for p-type devices BG Back gate bias of the terminals. In this example, unlike the FDSOI digital device 2100, the FDSOI analog device 2200 includes independent back gate bias control, wherein the back gate voltage of the p-type device can be boosted to voltage V. DD The above is independent of the back gate voltage of n-type devices.

[0096] Still refer to Figure 22 The back-gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address the effects associated with chip cooling in low-temperature environments. The transistor devices and associated control circuitry are designed so that, using back-gate bias control, the threshold voltage of the transistor device can be tuned despite significant variations in the transistor's operating temperature. In some examples, different back-gate biases are provided for transistors with different aspect ratios. Although Figure 22 An FDSOI analog device 2200 is shown, comprising a number and type of wells. The FDSOI analog device 2200 may include additional or fewer other types of wells. Additionally, the transistor device may be planar or non-planar (e.g., a FinFET device).

[0097] In an example cryogenic CMOS control chip, the FDSOI digital device 2100 can be used as part of a circuit block that only requires the difference between the low and high voltage values ​​and does not involve intermediate values. Because the FDSOI digital device 2100 occupies less area than the FDSOI analog device 2200, it is advantageous to use it in most circuits, provided they are not overly sensitive. In one example, only the FDSOI analog device 2200 is fabricated, allowing for independent back-gate bias control for n-type and p-type devices, as well as independent back-gate bias control based on the aspect ratio of these devices. As previously described, the cryogenic CMOS control chip can be partitioned into domains, such that each domain includes multiple transistor devices but shares a common back-gate bias. In one example, there may be eight domains based on the combination of n-type and p-type devices and the different aspect ratios associated with each type of device.

[0098] Figure 23 A flowchart 2300 corresponding to a method associated with the system described in this disclosure is shown. In one example, a system for controlling qubit gates may include a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. As an example, the quantum device may correspond to... Figure 1 The system may also include qubit 160. It may further include control circuitry configured to operate at cryogenic temperatures, and wherein the control circuitry includes a plurality of charge-locked circuits. As an example, the control circuitry may correspond to the circuitry included in a previously described cryogenic CMOS control chip. Each of the plurality of charge-locked circuits may be coupled via an interconnect to at least one of the plurality of qubit gates, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate, wherein each of the plurality of charge-locked circuits includes a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage quantity or a second voltage quantity, wherein the first voltage quantity is greater than the second voltage quantity. As an example, the charge-locked circuitry may be included as part of a CLFG unit 360. Each charge-locked circuitry may correspond to any of the previously described CLFG units 500, 1300, or 1400.

[0099] Step 2310 may include operating a first subset of a plurality of charge-locked circuits in capacitive mode such that the voltage signal output to at least one qubit gate includes a pulse signal having a first controlled amplitude, wherein the first controlled amplitude depends on the amount of the input voltage signal and each of a first voltage amount and a second voltage amount. In one example, this step may be associated with the operation of CLFG unit 1300. As previously described, CLFG unit 1300 may include components responsive to CL_EN <n>Switch 1312 is operated by a signal. This signal can be provided under the control of a suitable finite state machine or another type of logic, such as relative to... Figure 10 Described. When switch 1312 is closed, the voltage received via the input terminal (IN) on signal line VICL (in Figure 5 V is referred to as V in Chinese. HOLD ) can be coupled to denoted as C PULSE,N One plate of the capacitor represents the on-chip capacitance. The CLFG unit 1300 may also include switches 1314 and 1316. The CLFG unit 1300 may also include an inverter 1318. The CLFG unit 1300 can be configured such that only one of these switches is closed at a certain time. In this example, it is labeled CL_EN. <n>The signal can control switch 1314, and an inverted version of the signal (e.g., inverted by inverter 1318) can control switch 1316. Thus, at a certain time, the voltage V... HIGH or voltage V LOW It can be coupled to the symbol C via one of the two switches. PULSE,N The second plate of the capacitor represents the on-chip capacitance.

[0100] Step 2320 may include operating a second subset of the multiple charge-locked circuits in direct mode such that the voltage signal output to at least one qubit gate includes a signal with a second controlled amplitude, wherein the second controlled amplitude depends on the input voltage signal and only one of a first voltage quantity or a second voltage quantity. In one example, this step may relate to the operation of CLFG unit 1400. As previously described, CLFG unit 1400 can operate in direct mode when the CL_MODE signal is deactivated. Therefore, when the CL_MODE signal is deactivated, switch 1434 is closed and depends on CL_EN. <n>The signal state indicates that switch 1436 or switch 1438 is closed. Therefore, at a certain time, the voltage V... HIGH or voltage V LOW It can be coupled to the same terminal via one of the two switches, V IN Voltage is coupled to this terminal via the input terminal (IN).

[0101] In summary, in one aspect, this disclosure relates to a system for controlling qubit gates. The system may include a first packaging device comprising a quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system may also include a second packaging device including control circuitry configured to operate at cryogenic temperatures, wherein the first packaging device is coupled to the second packaging device, and wherein the control circuitry includes a plurality of charge-locking circuits, each of the plurality of charge-locking circuits being coupled via interconnects to at least one of the plurality of qubit gates, such that each of the plurality of charge-locking circuits is configured to provide a voltage signal to at least one qubit gate.

[0102] Each of the multiple charge-locked circuits may include an input terminal for receiving an input voltage signal and an output terminal for selectively providing a voltage signal to at least one qubit gate. Each charge-locked circuit may also include a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage quantity or a second voltage quantity, wherein the first voltage quantity is greater than the second voltage quantity.

[0103] Each of the multiple charge-locked circuits can be configured to generate a voltage signal as a pulse signal with a controlled amplitude, wherein the controlled amplitude depends at least on a first voltage quantity and a second voltage quantity. At least a subset of the multiple charge-locked circuits can be configured to operate in either a direct mode or a capacitor mode. Each charge-locked circuit in the at least subset of the multiple charge-locked circuits may include a capacitor having a first terminal for receiving an input voltage signal and a second terminal for selectively receiving either a first voltage quantity or a second voltage quantity, wherein the first voltage quantity is greater than the second voltage quantity. The capacitor may not be charged during direct mode. The capacitor may be charged during capacitor mode.

[0104] Each charge-locked circuit in a plurality of charge-locked circuits may include a plurality of transistor devices, and each transistor in at least a subset of the plurality of transistors may include a back-gate bias terminal. The back-gate bias terminal may be configured to receive a voltage to change a threshold voltage associated with the respective transistor. The control circuitry may also include control logic configured to control at least one control signal associated with each of the plurality of charge-locked circuits.

[0105] In another aspect, this disclosure relates to a method for controlling a system of qubit gates, the system including a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures, and control circuitry is configured to operate at cryogenic temperatures, wherein the control circuitry includes a plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is coupled to at least one of the plurality of qubit gates via an interconnect, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate, and wherein each of the plurality of charge-locked circuits includes a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage quantity or a second voltage quantity, wherein the first voltage quantity is greater than the second voltage quantity. The method may include operating a first subset of the plurality of charge-locked circuits in capacitive mode, such that the voltage signal output to at least one qubit gate comprises a pulse signal having a first controlled amplitude, wherein the first controlled amplitude depends on the amount of the input voltage signal and each of the first and second voltage quantities. The method may also include operating a second subset of multiple charge-locked circuits in direct mode such that the voltage signal output to at least one qubit gate includes a signal having a second controlled amplitude, wherein the second controlled amplitude depends on the input voltage signal and only one of a first voltage quantity or a second voltage quantity.

[0106] The control circuitry may further include control logic configured to control at least one control signal associated with each of the plurality of charge-locked circuits. Each charge-locked circuit may include a plurality of transistor devices, and each transistor in at least a subset of the plurality of transistors includes a back-gate bias terminal. The back-gate bias terminal may be configured to receive a voltage to change a threshold voltage associated with the corresponding transistor.

[0107] In another aspect, this disclosure relates to a system for controlling qubit gates. The system may include a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system may also include control circuitry configured to operate at cryogenic temperatures, wherein the control circuitry includes a plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is coupled to at least one of the plurality of qubit gates via interconnects, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate, and wherein each of the plurality of charge-locked circuits includes an input terminal for receiving an input voltage signal and an output terminal for selectively providing a voltage signal to at least one qubit gate, and wherein the control circuitry further includes control logic configured to provide at least one control signal associated with each of the plurality of charge-locked circuits.

[0108] Each of the multiple charge-locked circuits may further include a capacitor having a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage quantity or a second voltage quantity, wherein the first voltage quantity is greater than the second voltage quantity, and wherein each of the multiple charge-locked circuits is configured to generate a voltage signal as a pulse signal with a controlled amplitude, wherein the controlled amplitude depends at least on the first voltage quantity and the second voltage quantity.

[0109] At least a subset of multiple charge-locked circuits can be configured to operate in either a direct mode or a capacitor mode, and each charge-locked circuit in the at least subset of the multiple charge-locked circuits includes a capacitor having a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, wherein the first voltage amount is greater than the second voltage amount. The capacitor may not be charged during direct mode. The capacitor may be charged during capacitor mode.

[0110] It should be understood that the methods, modules, and components described herein are merely exemplary. For example, but not limited to, illustrative types of devices may include field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chips (SoCs), complex programmable logic devices (CPLDs), etc.

[0111] Furthermore, in an abstract yet still explicit sense, any arrangement of components that achieves the same functionality is effectively "associated" so that the desired functionality is realized. Therefore, any two components combined in this paper to achieve a specific functionality can be considered "associated" with each other so that the desired functionality is realized, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered "operably connected" or "coupled" with each other to achieve the desired functionality.

[0112] Furthermore, those skilled in the art will recognize that the boundaries between the functionalities of the above-described operations are merely illustrative. The functionality of multiple operations can be combined into a single operation, and / or the functionality of a single operation can be distributed across additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be varied in various other embodiments.

[0113] While specific examples are provided in this disclosure, various modifications and alterations can be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure. Any benefits, advantages, or solutions to problems described herein with reference to specific examples are not intended to be construed as key, essential, or fundamental features or elements of any or all claims.

[0114] Furthermore, the term "a" or "an" as used herein is defined as one or more. Moreover, the use of introductory phrases such as "at least one" and "one or more" in claims should not be construed as meaning that introducing another claim element with the indefinite article "a" or "an" limits any particular claim containing such an introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" along with indefinite articles (such as "a" or "an"). The same applies to the use of definite articles.

[0115] Unless otherwise specified, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of such elements.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A controller for a qubit gate, comprising: A plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is configured to provide a voltage signal to at least one qubit gate, wherein each of the plurality of charge-locked circuits includes an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to at least one qubit gate, wherein each of the plurality of charge-locked circuits further includes a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage quantity or a second voltage quantity, wherein the first voltage quantity is greater than the second voltage quantity.

2. The controller of claim 1, wherein each of the plurality of charge-locked circuits is configured to generate the voltage signal as a pulse signal with a controlled amplitude, wherein the controlled amplitude depends at least on the first voltage quantity and the second voltage quantity.

3. The controller of claim 1, wherein at least a subset of the plurality of charge-locking circuits is configured to operate in either direct mode or capacitor mode.

4. The controller of claim 3, wherein the capacitor is not charged during the direct mode.

5. The controller of claim 3, wherein the capacitor is charged during the capacitor mode.

6. The controller of claim 1, wherein each of the plurality of charge-locking circuits further comprises a switch for selectively coupling an input voltage signal received via the input terminal to a first terminal of the capacitor.

7. The controller of claim 1, wherein each of the plurality of charge-locking circuits comprises a plurality of transistor devices, and each transistor in at least a subset of the plurality of transistor devices comprises a back-gate bias terminal.

8. The controller of claim 7, wherein the back gate bias terminal is configured to receive a voltage to change the threshold voltage associated with the corresponding transistor.

9. A method for controlling a qubit gate configured to operate at cryogenic temperatures, wherein a controller for controlling the qubit gate includes a plurality of charge-locked circuits, wherein each of the plurality of charge-locked circuits is configurable to provide a voltage signal to at least one qubit gate, and wherein each of the plurality of charge-locked circuits includes a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage quantity or a second voltage quantity, wherein the first voltage quantity is greater than the second voltage quantity, the method comprising: Operating a first subset of the plurality of charge-locked circuits in capacitive mode, such that the voltage signal output to at least one qubit gate includes a pulse signal having a first controlled amplitude, wherein the first controlled amplitude depends on the amount of the input voltage signal and each of the first voltage amount and the second voltage amount; as well as A second subset of the plurality of charge-locked circuits is operated in direct mode such that the voltage signal output to at least one qubit gate includes a signal having a second controlled amplitude, wherein the second controlled amplitude depends on the input voltage signal and only one of the first voltage quantity or the second voltage quantity.

10. The method of claim 9, wherein the controller further comprises control logic configured to control at least one control signal associated with each of the plurality of charge-locking circuits.

11. The method of claim 9, wherein each of the plurality of charge-locked circuits comprises a plurality of transistor devices, and each transistor in at least a subset of the plurality of transistor devices comprises a back-gate bias terminal.

12. The method of claim 11, wherein the back gate bias terminal is configured to receive a voltage to change the threshold voltage associated with the corresponding transistor.

13. A controller for a qubit gate, comprising: A control circuit configured to operate at low temperatures, wherein the control circuit includes a plurality of charge-locked circuits, each of the plurality of charge-locked circuits being configured to provide a voltage signal to at least one qubit gate, each of the plurality of charge-locked circuits including an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to the at least one qubit gate, and wherein the control circuit further includes control logic configured to provide at least one control signal associated with each of the plurality of charge-locked circuits, and wherein each of the plurality of charge-locked circuits further includes a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage quantity or a second voltage quantity, wherein the first voltage quantity is greater than the second voltage quantity.

14. The controller of claim 13, wherein each of the plurality of charge-locked circuits is configured to generate the voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on the first voltage quantity and the second voltage quantity.

15. The controller of claim 13, wherein at least a subset of the plurality of charge-locking circuits is configured to operate in one of a direct mode or a capacitor mode.

16. The controller of claim 14, wherein the capacitor is not charged during the direct mode.

17. The controller of claim 14, wherein the capacitor is charged during the capacitor mode.

18. The controller of claim 13, wherein each of the plurality of charge-locking circuits further comprises a switch for selectively coupling an input voltage signal received via the input terminal to a first terminal of the capacitor.

19. The controller of claim 13, wherein each of the plurality of charge-locking circuits comprises a plurality of devices formed using a fully depleted semiconductor-on-insulator (FDSOI) process, and wherein each of the plurality of devices comprises a back gate bias terminal.

20. The controller of claim 19, wherein the back gate bias terminal is configured to receive a voltage to change a threshold voltage associated with a corresponding device among the plurality of devices formed using the fully depleted semiconductor-on-insulator process.

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