Charge locking circuit and control system for a qubit

Abstract

Systems and methods related to charge locking circuits and control systems for qubits are provided. A system for controlling qubit gates includes a first packaging device including a quantum device, the quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system further includes a second packaging device including a control circuit configured to operate at cryogenic temperatures, wherein the first packaging device is coupled to the second packaging device, and wherein the control circuit includes a plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate.

Description

BACKGROUND

[0001] Semiconductor-based integrated circuits used in electronic devices such as digital processors include digital circuits based on complementary metal-oxide-semiconductor (CMOS) technology. An additional approach to using processors and related components based on CMOS technology is to use superconducting logic-based devices. Superconducting logic-based devices can also be used to process quantum information, such as qubits. SUMMARY

[0002] In one aspect, the present disclosure relates to a system for controlling qubit gates. The system can include a first package device including a quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system can also include a second package device including a control circuit configured to operate at cryogenic temperatures, wherein the first package device is coupled to the second package device, and wherein the control circuit includes a plurality of charge-locked circuits, wherein each charge-locked circuit of the plurality of charge-locked circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locked circuit of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate.

[0003] In another aspect, the present disclosure relates to a method in a system for controlling qubit gates, the system including a quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures, and a control circuit configured to operate at cryogenic temperatures, and wherein the control circuit includes a plurality of charge-locked circuits, wherein each charge-locked circuit of the plurality of charge-locked circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locked circuit of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate, and wherein each charge-locked circuit of the plurality of charge-locked circuits includes a first terminal to receive an input voltage signal and a second terminal to selectively receive a first voltage amount or a second voltage amount, and wherein the first voltage amount is greater than the second voltage amount. The method can include operating a first subset of the plurality of charge-locked circuits in a capacitive mode, such that the voltage signal output to the at least one qubit gate includes a pulse signal having a first controlled amplitude, wherein the first controlled amplitude depends on an amount of the input voltage signal and each of the first voltage amount and the second voltage amount. The method can also include operating a second subset of the plurality of charge-locked circuits in a direct mode, such that the voltage signal output to the at least one qubit gate includes a signal having a second controlled amplitude, wherein the second controlled amplitude depends on the input voltage signal and only one of the first voltage amount or the second voltage amount.

[0004] In yet another aspect, the present disclosure relates to a system for controlling qubit gates. The system can include a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. The system can also include a control circuit configured to operate at cryogenic temperatures, where the control circuit includes a plurality of charge-locked circuits, where each charge-locked circuit of the plurality of charge-locked circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locked circuit of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate, and where each charge-locked circuit of the plurality of charge-locked circuits includes an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to the at least one qubit gate, and where the control circuit further includes control logic configured to provide at least one control signal associated with each charge-locked circuit of the plurality of charge-locked circuits.

[0005] In yet another aspect, the present disclosure relates to a system for controlling qubit gates. The system can include a first package device including a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. The system can also include a second package device including a control system configured to operate at cryogenic temperatures, where the first package device is coupled to the second package device. The control system can include a plurality of charge-locked circuits, where each charge-locked circuit of the plurality of charge-locked circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locked circuit of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate. The control system can also include a control circuit including a finite state machine configured to provide at least one control signal to selectively enable at least one charge-locked circuit of the plurality of charge-locked circuits and to selectively support providing the at least one voltage signal to a selected one of the plurality of charge-locked circuits.

[0006] In another aspect, the present disclosure relates to a system for controlling qubit gates. The system can include a first packaging device including a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. The system can also include a second packaging device including a control system configured to operate at cryogenic temperatures, where the first packaging device is coupled to the second packaging device. The control system can include a plurality of charge-locked circuits, where each of the plurality of charge-locked circuits is coupled to at least one of the plurality of qubit gates via an interconnect, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate. The control system can also include a control circuit including control logic configured to provide at least one control signal to selectively enable at least one of the plurality of charge-locked circuits.

[0007] In another aspect, the present disclosure relates to a system for controlling qubit gates. The system can include a first packaging device including a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. The system can also include a second packaging device including a control system configured to operate at cryogenic temperatures, where the first packaging device is coupled to the second packaging device. The control system can include a plurality of charge-locked circuits, where each of the plurality of charge-locked circuits is coupled to at least one of the plurality of qubit gates via an interconnect, such that each of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate. The control system can also include a digital-to-analog converter to generate at least one voltage signal. The control system can also include a control circuit including a finite state machine configured to provide at least one control signal to selectively enable at least one of the plurality of charge-locked circuits and to selectively support providing the at least one voltage signal to a selected one of the plurality of charge-locked circuits.

[0008] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the DETAILED DESCRIPTION. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0009] The present disclosure is illustrated by way of example and not by way of limitation in the appended drawings, wherein like reference numerals refer to similar elements. The elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0010] Figure 1 A system 100 for controlling qubits according to one example is shown;

[0011] Figure 2 A common substrate including a low temperature CMOS control chip, a qubit chip, and a resonator chip is shown in accordance with one example;

[0012] Figure 3 A block diagram of a control system associated with fast control multiplexing is shown in accordance with one example;

[0013] Figure 4 A plan view of a low temperature CMOS control chip including a control system is shown in accordance with one example;

[0014] Figure 5 A charge lock fast gate (CLFG) cell is shown in accordance with one example;

[0015] Figure 6 Example waveforms 600 associated with operation of a CLFG cell of Figure 5

[0016] Figure 7A and Figure 7B Various blocks associated with a low temperature CMOS control chip 700 are shown in accordance with one example;

[0017] Figure 8 A block diagram of charge lock and fast gate is shown in accordance with one example;

[0018] Figure 9 An example of a fast gate circuit is shown;

[0019] Figure 10 A finite state machine for controlling operation of a CLFG cell is shown in accordance with one example;

[0020] Figure 11A and Figure 11B An example system that can be used to generate an enable signal as part of an example low temperature CMOS control chip is shown;

[0021] Figure 12 A CLFG cell array is shown in accordance with one example;

[0022] Figure 13 An example CLFG cell configured to operate in a capacitance mode is shown in accordance with one example;

[0023] Figure 14 An example CLFG cell configured to operate in a dual mode including a capacitance mode and a direct mode is shown in accordance with one example;

[0024] Figure 15 Example waveforms associated with Figure 13 and Figure 14 ​Example waveforms associated with signals of the CLFG cell shown;

[0025] Figure 16 Example waveforms associated with simulations of the CLFG cell in the capacitive mode are shown;

[0026] Figure 17 A first view and a second view of an active area of an example qubit device during a charge lock test are shown;

[0027] Figure 18 A view of changes in voltage and current associated with a quantum point contact (QPC) according to one example is shown;

[0028] Figure 19 Example waveforms corresponding to a cryogenic CMOS control chip during testing of fast gating operations with quantum dots are shown;

[0029] Figure 20 Example readout waveforms corresponding to readout signals through quantum dots during testing of a cryogenic CMOS control chip are shown;

[0030] Figure 21 An FDSOI digital device according to one example is shown;

[0031] Figure 22 An FDSOI analog device according to one example is shown; and

[0032] Figure 23 A flowchart corresponding to a method associated with the systems described in the present disclosure is shown. DETAILED DESCRIPTION

[0033] Examples described in the present disclosure relate to a system for controlling qubit gates. Controlling a quantum device requires the generation of a large number of static and dynamic voltage signals, preferably at cryogenic temperatures that are tightly integrated with the quantum device. As used in the present disclosure, the term “cryogenic” refers to any temperature equal to or less than 300 Kelvin. This is a significant challenge given that the low temperature environment strongly limits the power dissipation of any active electronic device. In addition, a large number of voltage signals also need to be coupled to the qubit gates in the quantum computing device. This is because potentially thousands of leads need to be connected to voltage sources to drive the qubit gates in the quantum computing device. Moreover, conventionally, qubits have been controlled with room temperature pulse generators that must generate large signals that are attenuated in the cryostat. The power required to overcome this attenuation, as well as the power required to drive the cable impedance, is an obstacle to scaling quantum computers.

[0034] Examples described in this disclosure relate to cryogenic control circuitry and architecture for quantum computing devices. The control architecture includes an integrated circuit control chip containing cryogenic control circuitry tightly integrated with a qubit plane. As an example, the control chip can be wire-bonded or flip-chip mounted to the qubit plane. Additionally, the control chip stores charge on capacitors (including interconnect capacitance) to generate bias voltages. A single digital-to-analog converter can be used to set the charge on each capacitor, which will hold for a long time at cryogenic temperatures due to extremely low leakage paths at these temperatures. Refresh of the charge can be cycled on a time scale commensurate with qubit operations. By deploying a "charge shuffling" circuit - moving charge between capacitors to generate voltage pulses - the challenge associated with generating heat that decays is addressed. Via tight integration between the cryogenic CMOS control chip and the qubit plane, capacitance is minimized as much as possible. This tight integration (e.g., via a chip stack package approach) can significantly reduce capacitance, which in turn impacts dissipated power.

[0035] In one example, the cryogenic CMOS control chip can be implemented using a fully depleted semiconductor-on-insulator (FDSOI) process. In one example, a device based on the FDSOI process can include an undoped gate channel, an ultra-thin body, an ultra-thin buried oxide (BOX) under the source, drain, and gate, and full dielectric isolation from adjacent devices. Capacitors for charge storage are implemented using on-chip devices. The back gate or body bias of each transistor device can be used to dynamically configure threshold voltages to address effects associated with cooling. The control chip includes circuit blocks partitioned into domains that are given a common back gate bias. Example domains with separate biasing include circuit blocks for n-type devices, circuit blocks for p-type devices, circuit blocks for analog devices, and circuit blocks for digital devices. In some examples, different back gate biases are provided for transistors with different aspect ratios.

[0036] The qubit plane can include topological computing gates that can operate at about 20 millikelvin (~20 mK). The quantum computing device can process quantum information, such as qubits. Qubits can be implemented using a variety of physical systems, including photons, electrons, Josephson junctions, quantum dots, or heterostructures. The quantum state(s) can be encoded as a spin direction, another aspect of spin, charge, energy, or an excited energy level that is part of a qubit or a topological phase of a superconductor. Example qubits can operate based on low frequency DC signals (e.g., bias currents) or high frequency radio frequency signals (e.g., 10 GHz signals) or a combination of both. In certain examples, microwave signals can be used to control superconducting devices, including, for example, the state of a quantum bit (qubit). Certain implementations of quantum bit (qubit) gates can require high frequency microwave signals.

[0037] Figure 1A system 100 for controlling qubits is shown, according to one example. In this example, the system 100 can include multiple energy levels, each of which can be configured to operate at different temperatures. Thus, the system 100 can include energy levels 110, 130, and 150. The energy level 110 can include components configured to operate at room temperature (e.g., ambient temperature) or between 4 Kelvin and room temperature. The energy level 130 can include components configured to operate at 300 Kelvin or below 300 Kelvin and up to 4 Kelvin. The energy level 150 can include components configured to operate at or around 20 milli-Kelvin (mK). The energy level 110 can include a microcontroller 112 (or microprocessor), a digital-to-analog converter (DAC) 114, a signal generator 116, and a measurement device 118. The microcontroller 112 can generate control signals configured to control qubits and other aspects of the system 100. The DAC 114 can receive digital control signals from the microcontroller 112 (or from other components) and convert these signals to analog form. The analog signals can then be transmitted to other energy levels as needed. The signal generator 116 can include a microwave signal generator and other clock signal generators, as needed. The measurement device 118 can include instrumentation, such as a spectrum analyzer.

[0038] Continuing to refer to Figure 1 , the energy level 130 can include components configured to interconnect the energy level 110 with the energy level 150 in a manner that reduces thermal loading and allows for efficient connectivity between components at room temperature and components at 20 milli-Kelvin (mK). Thus, in this example, the energy level 130 can include a component 132, interconnections 134, 136, and 138. In one example, the component 132 can be implemented as a high electron mobility transistor(s) (HEMT(s)) low noise amplifier. The interconnections 134, 136, and 138 can be implemented as cables including conductors such as niobium and copper. The conductors can be insulated within the interconnections using appropriate dielectric materials such as polyimide.

[0039] Still referring to Figure 1, the energy level 150 can include a coupler 152, a readout multiplex 154, a fast control multiplex 156, and a qubit 160. The coupler 152 can couple signals from a signal generator (e.g., the signal generator 116) to the readout multiplex 154. The coupler 152 can also direct any reflected signals to the assembly 132. The readout multiplex 154 and the fast control multiplex 156 can be implemented on a single control chip (sometimes referred to as a cryogenic control CMOS chip). In one example, the readout multiplex 154 can be implemented using a superconducting material, such as niobium on an inert substrate, such as sapphire. The readout multiplex 154 chip can contain a number of inductance, capacitance, and resistance elements of suitable size to form a resonator(s) bank. At cryogenic temperatures, the resonator circuit exhibits superconductivity and produces a resonator with a high quality factor. This can provide an efficient, low-loss frequency multiplexing mechanism. In one example, the cryogenic CMOS control chip (e.g., an ASIC manufactured using a semiconductor technology such as CMOS) can be mounted on the same substrate as the qubit (e.g., the qubit 160) and can be configured to operate at the same cryogenic temperature as the qubit (e.g., 20 mK).

[0040] Figure 2 A common substrate 200 including a cryogenic CMOS control chip 210, a qubit chip 250, and a resonator chip 280 is shown, according to one example. The cryogenic CMOS control chip 210 can be coupled to contact pads (e.g., contact pads 222 and 224) via wirebonds (e.g., wirebonds 212 and 214). The cryogenic CMOS control chip 210 can also be coupled to contact pads (e.g., contact pads 226 and 228) via wirebonds (e.g., wirebonds 216 and 218). The cryogenic CMOS control chip 210 can also be coupled to other contacts (e.g., contacts 234 and 236) via wirebonds (e.g., wirebonds 230 and 232). The qubit chip 250 can be coupled to contact pads (e.g., contact pads 256 and 258) via wirebonds (e.g., wirebonds 252 and 254). The qubit chip 250 can be coupled to the resonator chip 280 via wirebonds (e.g., wirebonds 260 and 262). The resonator chip 280 can be coupled to contacts (e.g., contacts 290 and 292) via wirebonds (e.g., wirebonds 282 and 284). Although not shown in FIG. 2, the qubit chip 250 can also be coupled to the cryogenic CMOS control chip 210 via wirebonds. Figure 2The chip package arrangement can also include thermal management by adhering each chip to individual gold plated copper posts that are in parallel thermal contact with the dilution refrigerator's mixing chamber level, as shown in FIG. 6, but to mitigate unnecessary heating of the quantum device. While this example shows tight integration between the control chip and the qubits via wirebonds, other techniques can be used. As an example, the control chip can be flip chip bonded to the substrate with the qubits. Alternatively, a package on package, system in package, or other multi-chip assembly can be used.

[0041] In this example, the low temperature CMOS control chip can be implemented in 28 nm-FDSOI technology, which is an inherently low power, low leakage CMOS platform suitable for low temperature operation. Transistors in FDSOI can provide the utility of configuring a back gate bias to counteract threshold voltage variation with temperature. This example platform provides both high (1.8V) and low (1V) voltage cells, and also allows for separate back gate control of n-type and p-type transistors or entire circuit blocks, which is a useful aspect in mixed signal circuit design, such as the example control system.

[0042] Figure 3 A block diagram of a control system 300 associated with the fast control multiplexer 156 is shown, according to one example. The control system 300 can be used to control the behavior of a charge locking and fast gating (CLFG) cell 360 incorporated as part of a control chip. The control system 300 can include a serial peripheral interface (SPI) interface 310, a waveform memory 320, a voltage controlled oscillator (VCO) 330, a clock selection multiplexer (C SEL ) 340, and a finite state machine 350. As shown, three different voltage levels can be coupled to the cell, including V HOLD , V HIGH , and V LOW . The C SEL 340 is used to select the clock signal provided to the finite state machine. Additional details regarding the finite state machine and related registers are provided later.

[0043] In one example, the control system 300 can be implemented as part of a low temperature CMOS control chip. Figure 4 A plan view of a low temperature CMOS control chip 400 is shown, according to one example, including a control system 420 (similar to the control system 300 of FIG. 3) and a plurality of control channels 410. The control channels 410 can be used to control the behavior of a plurality of qubits 430, such as the qubits 130 of FIG. 1. Figure 1control system 300). The cryogenic CMOS control chip 400 can include digital and analog blocks. In this example, the cryogenic CMOS control chip 400 can include charge-locked and fast-gated (CLFG) cells and components corresponding to the control system 420. In this example, the cryogenic CMOS control chip 400 can include logic 410 and CLFG cells. In one example, the logic 410 can include a series of coupled digital logic circuits that provide communication, waveform memory, and autonomous operation of the chip via two FSMs. The logic 410 can include a control system 420 that can include an oscillator 422, finite state machine(s) FSM, and SPI interface (e.g., FSM + SPI interface) 424, and memory 426. The oscillator 422 can be implemented as a ring oscillator with configurable length and frequency divider. Additional details regarding the FSMs are provided later. The memory 426 can be configured as a 128-bit register that allows an arbitrary pulse pattern to be stored. Along the left and bottom edges of the chip are tiled possibly repeating analog circuit blocks “CLFG” that generate the static and dynamic voltages required to control the qubits. The CLFG cells can include cells 432, 434, 436, and 438. In the example described here, while the CLFG cells are implemented on a single die, they can be formed on multiple dies that are packaged together or otherwise interconnected. While Figure 4 A certain plan view of the cryogenic CMOS control chip 400 is shown, which can have different plan views. In addition, while a certain number of components are shown arranged in a certain way, the cryogenic CMOS control chip 400 can include additional or fewer components arranged differently. Figure 4 A certain plan view of the cryogenic CMOS control chip 400 is shown, which can have different plan views. In addition, while a certain number of components are shown arranged in a certain way, the cryogenic CMOS control chip 400 can include additional or fewer components arranged differently.

[0044] Figure 5 A CLFG cell 500 according to one example is shown. The CLFG cell 500 can be configured to lock charge and provide a voltage output. Each CLFG cell 500 can correspond to any one of the N number of cells. The CLFG cell 500 can include two parts: a static voltage coupling to an output terminal (labeled GATE <n>) and a portion 510 for coupling a dynamic voltage (based on a voltage V HIGH or one of the voltages V LOW ) to an output terminal, a portion 550. The portion 510 of the CLFG unit 500 can include a switch 512 that can operate in response to a signal G LOCK,N . This signal can be provided under control of an appropriate finite state machine or another type of control logic or instructions. When the switch 512 is closed, the voltage V HOLD can be coupled to one plate of a capacitor labeled C PULSE,N , which represents an on-chip capacitor. The portion 550 of the CLFG unit 500 can also include a switch 552 and a switch 554. The CLFG unit 500 can also include an inverter 556. The CLFG unit 500 can be configured so that only one of these switches (the switch 552 and the switch 554) is closed at a time. In this example, a signal labeled G GFG,N can control the switch 552, and an inverted version of this signal (e.g., inverted by the inverter 556) can control the switch 554. In this way, at a time, the voltage V HIGH or the voltage V LOW can be coupled to a second plate of the capacitor labeled C PULSE,N , which represents an on-chip capacitor, via one of the two switches.

[0045] With continued reference to Figure 5 , C P may be the sum of parasitic capacitances due to wiring in the low-temperature CMOS control chip and the quantum bit chip(s) and leads (or other interconnections) used to interconnect the two. The unit can first be selected for configuration by an on-chip finite state machine (FSM) that connects an external voltage source to an input terminal (labeled IN in Figure 5 ) of the CLFG unit 500, raising its potential to V HOLD . In this example, a single channel of a room-temperature digital-to-analog converter (DAC) can be used as the source, and the FSM switches each CLFG unit in turn into contact with this bias, energizing the capacitor and then locking in the charge needed to generate a static voltage at the high-impedance output. This circuit contains an on-chip capacitor C PULSE and a parasitic capacitance C P , which includes contributions from the bond pads, bond leads, and gate interconnections on the quantum bit chip. After charging, the switch 512 is opened by the FSM (e.g., by deasserting the G LOCK,N signal), floating the charge on the capacitor and the quantum bit gate. This locked-in charge is maintained even when the CLFG unit 500 is deasserted, establishing a static voltage that can be used to configure the offset bias of the quantum bit device. Although Figure 5 A number of components are shown arranged in a certain way, but the CLFG unit 500 may include additional or fewer components arranged differently.

[0046] Figure 6 Example waveform 600 associated with the operation of CLFG cell 500 is shown. For dynamic control, voltage pulses are needed to rapidly change the gate potential and energy state of the qubits. Generating such pulses remotely from the qubit plane requires a large amount of energy because the generator must drive the cable impedance, even if the power is not dissipated at the end of the open line. Alternatively, fairly large voltage pulses can be generated with very little energy by redistributing local charge in a circuit with small capacitance. In this example, this concept is used to implement the dynamic operation of CLFG cell 500. Under the control of the second FSM, the cell is selected for pulses, and a preloaded pulse pattern stored in the register memory is applied to switch G. FG .

[0047] Switches 552 and 554 are used to switch between two voltage sources V. HIGH and V LOW Between toggling capacitor C PULSE The lower electrode is controlled in a manner similar to that of the chip. These sources can be external to the chip or derived from locally pre-charged capacitors. With C PULSE The potential of the lower plate switches to V LOW or V HIGH Charge is induced onto the top plate, thereby changing the output voltage V relative to the ground reference. OUT .

[0048] In this example, the amplitude of the pulse is determined by ΔV PULSE =(C PULSE / (C P +C PULSE ))(V HIGH -V LOW The value is given, and the power dissipation P is given. PULSE Given the total capacitance, pulse frequency f, and voltages at both levels, P PULSE =((C P *C PULSE ) / (C P +C PULSE ))(V HIGH -V LOW ) 2 f. Because C P and C PULSE They are (pF) chip-level capacitors, so they require very little power to charge.

[0049] Figure 7A and Figure 7B Various blocks associated with the low temperature CMOS control chip 700 are shown, according to one example. As explained earlier, the low temperature CMOS control chip 700 can include analog and digital components. In this example, the low temperature CMOS control chip can include an analog-to-digital converter (ADC) buffer 702, ADC 704, ADC SRAM 706, and ADC control 708. The low temperature CMOS control chip 700 can also include a clock driver 710, a waveform generator 720, and a reference and bias generator 722. These components can be coupled via various buses. Each bus can include at least one signal line. As Figure 7A and Figure 7B shown, the low temperature CMOS control chip 700 can receive various external signals, including clock signals, various voltages, and control signals. As shown, some clocks are generated and received externally via pins associated with the control chip.

[0050] With continued reference to Figure 7A , the low temperature CMOS control chip 700 can also include master control and registers 730 and various miscellaneous blocks 740. The master control and registers 730 can include a serial peripheral interface (SPI), which can allow for communication with an external processor. The miscellaneous blocks 740 can include a sample and hold (S&H) block 742, a comparator 744, and a radio frequency (RF) multiplexer (MUX) 746. The RF MUX 746 can allow for selection between two radio frequency signals (RFIN1 and RFIN2). In this example, there is a high-level peripheral block clock (APBCLK) input for the master control and registers 730 and a separate APBCLK input pin for the charge lock and fast gate block 750. As Figure 7B shown, for the charge lock and fast gate 750, it is also possible to switch to a local oscillator (e.g., VCO 754). The local oscillator can also be divided down by a configuration register. The SPI clock (SCLK) is from the SPI host. In this example, there is a clock ratio requirement between the APBCLK and SCLK from the SPI host. In one example, the APBCLK must >= 4 * SCLK. To ensure proper timing, clock domain crossing (CDC) logic is placed between the SCLK and the APBCLK, and another CDC logic is placed between the APBCLK and the divided oscillator clock.

[0051] Figure 7B A diagram showing some aspects of a charge locking and fast gating 750. The charge locking and fast gating 750 can include a control and register 752, a voltage controlled oscillator (VCO) 754, and a CLFG cell array 760. The control and register 752 can include an SPI interface. The control and register 752 can include a register read / write block, which in turn can be coupled to a register file. The VCO 754 can be configured to provide another clock signal for use with some aspects of the charge locking and fast gating 750. The CLFG cell array 760 can include CLFG cells 762 and 764, each of which can be similar to the CLFG cell 500 of Figure 5

[0052] Figure 8 A block diagram of a charge locking and fast gating (CLFG) 800 according to one example is shown. The CLFG 800 can include an SPI interface 810, which is coupled to a register read / write interface 820 via a bus (e.g., APB), which in turn can be coupled to registers 830 (e.g., the registers can be included as part of a register file). The CLFG 800 can also include a finite state machine 840, which can be configured to receive input from the registers and provide an output signal to a CLFG cell array 880, which in turn can provide a voltage to a qubit. The CLFG 800 can also include an oscillator 850, a frequency divider (FDIV) 860, and a multiplexer 870. The multiplexer 870 can receive the APB clock as one input and the frequency divider output as the other input. In this way, in this example, the finite state machine is able to copy the APBCLK or the clock signal from the local oscillator. A clock control module can be used to divide down the local oscillator clock from an integer value of 1 to 255, and the multiplexer 870 can be used to allow switching between the APBCLK and the divided down oscillator clock. The divided down clock has no duty cycle requirement. The clock output of the clock control module is referred to as XCLK, and it is used to clock the finite state machine.

[0053] Table 1 below lists some signals of the cryogenic CMOS control chip and their descriptions.

[0054]

[0055] Table 1

[0056] Table 2 lists some registers associated with the cryogenic CMOS control chip. Since the description of most of the registers is self-explanatory, only some of the registers and their functionality are described to explain the operation of the cryogenic CMOS control chip.

[0057] ​

[0058]

[0059]

[0060]

[0061]

[0062]

[0063] Table 2

[0064] While Table 2 shows certain registers and their arrangement, additional or fewer registers can be used. Additionally, the information presented in the table can be communicated to the cryogenic CMOS control chip via other modalities other than registers. As an example, special instructions can be used to encode the information contained in the registers. The architecture enabled by the registers described in Table 2 assumes 32 charge-locked fast gate (CLFG) cells. In this example, each CLFG cell can be independently DC charged and pulsed according to a waveform stored in the FGSR registers. In this implementation, 128 bits can be stored in four 32-bit registers (e.g., registers FGSR0-3), and any charge-locked fast gate cell can be pulsed according to the bit pattern stored in these registers. The bit pattern can be repeated continuously or played once under the control of a FSM. This implementation is suitable for two-level pulses, however it can be extended to multi-level pulses. In this example architecture, the REG_CTL1 register described in Table 2 includes information used by the enabled finite state machine to initiate and complete cell charging. As an example, bit 8 of this register controls when the counter for FGSR selection is enabled, and is incremented every clock cycle of the XCLK clock until it reaches 127, at which point the counter rolls over. As another example, bits 4 and 5 of the REG_CTL1 register control whether all 32 cells are presented with a full DC charge sequence, or whether a selective DC charge sequence is presented on only a subset of the 32 cells.

[0065] Figure 9 An example of a fast gate circuit 900 is shown. As described earlier, as part of Table 2, four 32-bit registers can control the output of the fast gate circuit 900. The fast gate circuit 900 can include a counter 910, a multiplexer 920, which can be coupled to receive the output of the counter 910 as one input, and to receive the value corresponding to the register REG_CTL<3> as another input. The fast gate circuit 910 can also include an AND gate 930, a multiplexer 940, and a gate 950, which can be coupled as shown. Figure 9 are shown coupled to one another. These logic elements can also receive Figure 9 The counter 910 selects the bit position of the 128-bit value to output on the CL_FG terminal. In this example, this is a 128-to-1 multiplexer. The counter 910 is incremented by one every clock cycle (e.g., corresponding to the clock XCLK shown). The counter 910 wraps around to 0 and continues counting. The value of the bit stored in REG_CTL[8] enables the counter 910. Thus, in this example, when REG_CTL[8] = 0, the counter remains at 0 and does not increment. If the charge lock state machine is not idle, then the fast gate output CL_FG is 0. In this case, the counter continues to increment as long as REG_CTL[8] = 1. Figure 9 The counter 910 selects the bit position of the 128-bit value to output on the CL_FG terminal. In this example, this is a 128-to-1 multiplexer. The counter 910 is incremented by one every clock cycle (e.g., corresponding to the clock XCLK shown). The counter 910 wraps around to 0 and continues counting. The value of the bit stored in REG_CTL[8] enables the counter 910. Thus, in this example, when REG_CTL[8] = 0, the counter remains at 0 and does not increment. If the charge lock state machine is not idle, then the fast gate output CL_FG is 0. In this case, the counter continues to increment as long as REG_CTL[8] = 1.

[0066] With continued reference to Figure 9 In one example, the sequence to update the 128-bit FGSR and start a new fast gate sequence is as follows: (1) clear REG_CTL1[8] to hold the counter at 0, or set REG_CTL1[1] to stop XCLK, (2) write new values into the four 32-bit FGSR registers, and (3) set REG_CTL1[8] to allow the counter to increment, or clear REG_CTL1[1] to resume XCLK. In one example, the FG output can also be overridden. When REG_CTL1[2] = 1, the CL_FG output equals REG_CTL1[3]. Although Figure 9 The fast gate circuit 900 is shown with a certain number of components arranged in a certain way, but the fast gate circuit 900 can include additional or fewer components arranged differently. In addition, other signals can be used to provide additional or fewer controls.

[0067] Figure 10 A finite state machine 1000 is shown according to one example. In this example, the finite state machine 1000 includes two finite state machines: FSM A and FSM B. Each of the finite state machines is configured for DC charging of CLFG cells (e.g., CLFG cells 500). FSM A corresponds to a finite state machine that is configured to charge only those CLFG cells that are enabled according to bits in a CL_EN register concurrently. FSM B corresponds to a finite state machine that is configured to sequentially charge all CLFG cells in a CLFG array (e.g., all 32 cells in a CLFG array having 32 cells). In this example, the bit values stored in a register (e.g., bits 4 and 5 of a 32-bit register REG_CTL1 corresponding to the field BEGIN_CHRG described in Table 2) determine which of the two finite state machines is active. In this example, FSM A is initiated when the BEGIN_CHRG field transitions from 00 to 01; alternatively, FSM B is initiated when the BEGIN_CHRG field transitions from 00 to 10. The output signals from FSM A and FSM B are provided as a CHRG signal that is coupled to one of the inputs of a multiplexer 1002. The other inputs of the multiplexer 1002 include the bit values stored in REG_CTL<6> (described in Table 2). The output of the multiplexer 1002 is a global DC charge signal, and is labeled CL_CHRG. The value of bit 7 (e.g., REG_CTL<7>) determines whether the output of FSM A and FSM B is provided as the DC charge signal, or whether the DC charge signal is selected by the user as the value of bit 6 of the REG_CTL register described in Table 2.

[0068] With continued reference to Figure 10 At initiation, FSM A begins in the IdleA0 state, and transitions to the countdownA state. As part of this transition, FSM A asserts the CHRG signal and begins a countdown to DC charge the CLFG cells that have been enabled. The CL_EN value remains the same as previously specified by the user throughout the operation of FSM A. In this example, when the local enable signal for a particular CLFG cell is high (e.g., CL_EN = 1), the ith CLFG cell is enabled. Thus, by gating the CHRG signal, the local enable signal ensures that the CLFG cell is only charged when it can be charged. After the charge is complete, FSM A enters an idle state, IdleAl. Table 3 below shows the states of FSM A Figure 10 Example correspondence between transitions / states referenced in the text and example values of bits and other signals.

[0069]

[0070] Table 3

[0071] Still referring to Figure 10 At start-up, FSM B enters a START_CHRG state, and assuming there are 32 CLFG cells, when the CL_EN<32> bit is set to 1 and each of the other enable bits is set to 0, charging of the 32nd CLFG cell begins. As part of this process, FSM B enters a countdown B state and counts down the number of clock cycles (e.g., DCSR clock cycles) needed for the sequential charging of the CLFG cells. Except in the states START_CHRG and countdown B, the CL_EN value remains the same as previously specified by the user throughout the operation of FSM B. When the CL_EN<31> bit is set to 1 and the remaining enable bits are set to 0, the DC charging of the 32nd CLFG cell is complete and the DC charging of the 31st CLFG cell begins. In this example, these steps are repeated until all 32 CLFG cells are charged. Then, FSM B transitions to an idle state (e.g., IdleBl state). Table 4 below shows the states of FSM B Figure 10 Example correspondence between transitions / states referenced in the text and example values of bits and other signals.

[0072]

[0073] Table 4

[0074] Although Figure 10 Although specific finite state machines are shown operating in a certain manner, other state machines can be used. Although Tables 3 and 4 refer to specific bits and signals and corresponding values for two finite state machines, other bits and signals and corresponding values can be used. In addition, the functionality associated with the state machines can be implemented using other logic or instructions.

[0075] Figure 11A and Figure 11B An example system 1100 is shown that can be used to generate enable signals as part of an example low temperature CMOS control chip. The FSM described earlier can be used to interface with the system 1100, which can be used to generate enable signals that are used to select a charged CLFG cell. This example also assumes that there are 1024 CLFG cells (arranged in a grid comprising 32 rows and 32 columns) that need to be controlled. The system 1100 can include a host logic and clock portion 1110, a row decoder 1120, and a column decoder 1130. The host logic and clock portion 1110 can include circuitry and logic configured to store and interpret instructions or commands in a manner similar to a memory controller. The row decoder 1120 can be configured to receive row addresses from the host logic and clock portion 1110 and to maintain one or more signals labeled R0 through R31. The column decoder 1130 can be configured to receive column addresses from the host logic and clock portion 1110 and to maintain one or more signals labeled C0 through C31 and D0 through D31. 31 31 31

[0076] Referring now to Figure 11B , the system 1100 can also include a bus system to couple the signals generated by the row decoder 1120 and the column decoder 1130 to circuitry 1140. The circuitry 1140 can be configured to generate a signal labeled OUT I,FG at its output terminals. This signal can be coupled to a qubit gate 1160. The circuitry 1140 is an example implementation of the "direct mode" of the CLFG cell described earlier. Thus, in this example, when the respective row (R J ) signal and the respective column (C I ) signal are high and the line (D) signal is high or low, respectively, the circuit 1160 can be connected to the voltage bus V LFG or V HFG . The circuitry 1140 can also be implemented as an array of CLFG cells (e.g., as shown in Figure 5 and described earlier). Although FIG. 11 shows the system 1100 with certain components arranged in a certain manner, there can be more or fewer components arranged differently.

[0077] Figure 12 ​​​A CLFG cell array 1200 according to one example is shown. As an example, the CLFG cell array 1200 can correspond to the CLFG cell array 760 of FIG. 7, and can be included as part of a cryogenic CMOS control chip. In this example, the CLFG cell array 1200 can include 32 CLFG cells (e.g., CLFG cells 1210, 1220, 1230, 1240, and 1250). Each of these CLFG cells can be configured to generate one of the OUTCL signals, which can be used to provide control or other types of voltages to a qubit. Each CLFG cell can receive signals labeled CL_FG, CL_CHRG, VICL, VHF G, and VLFG. These signals will be described in more detail with respect to Figure 13 and Figure 14 Additionally, some of these signals have also been described earlier as part of the description associated with a cryogenic CMOS control chip. Each CLFG cell can also receive an enable signal (e.g., CL_EN<0>, CL_EN<1>, CL_EN<2>, CL_EN<30>, or CL_EN<31>, as shown in Figure 12 The enable signals can allow for selective or sequential DC charging, as explained earlier with respect to the finite state machine in Figure 10 Figure 12 Each of the CLFG cells shown can also include electrostatic discharge (ESD) circuitry, including ESD circuits 1212, 1222, 1232, 1242, and 1252. The CLFG cells can operate in either a capacitive mode only or in a dual mode, including a capacitive mode and a direct mode. As an example, the CLFG cell array 1200 can consist of 32 CLFG cells— 16 CLFG cells configured to operate in a capacitive mode and 16 CLFG cells configured to operate in a direct mode. In one example, half of each type of CLFG cell can also contain custom analog pads with reduced ESD protection to further minimize leakage through standard pad structures. Although Figure 12 The CLFG cell array 1200 is shown with certain components arranged in a certain way, but there can be more or fewer components arranged differently.

[0078] Figure 13 An example of a CLFG cell 1300 configured to operate in a capacitive mode according to one example is shown. Unless otherwise indicated, the signals referenced in Figure 13 have the same meaning as described earlier with respect to Figure 5 to Figure 7B and Tables 1 and 2. The CLFG cell 1300 is arranged in the same way as Figure 5 ​configured in a similar manner as the CLFG cells 500. The CLFG cells 1300 are configured to lock charge and provide a voltage output at an output terminal (OUT) associated with the CLFG cell. Each CLFG cell 1300 can correspond to any one of the N number of cells. A dynamic voltage (based on one of a voltage received via a VHFG terminal (referred to as V Figure 5 in HIGH ) or a voltage received via a VLFG terminal (referred to as V Figure 5 in LOW )) can be coupled to the output terminal. The CLFG cells 1300 can include a signal CL_EN <n>The CLFG unit 1300 can also include a switch 1312 that is operable in response to a signal. The signal can be provided under control of an appropriate finite state machine or another type of control logic, as described with respect to Figure 10 FIG. 4. When the switch 1312 is closed, a voltage received via an input terminal (IN) on the signal line VICL (referred to in Figure 5 as V HOLD ) can be coupled to one plate of a capacitor labeled C PULSE,N , which represents an on-chip capacitor. The CLFG unit 1300 can also include a switch 1314 and a switch 1316. The CLFG unit 1300 can also include an inverter 1318. The CLFG unit 1300 can be configured such that only one of these switches is closed at a time. In this example, the switch labeled CL_EN <n>The signal can control switch 1314, and an inverted version of the signal (e.g., inverted by inverter 1318) can control switch 1316. Thus, at a certain time, the voltage V... HIGH or voltage V LOW It can be coupled to the symbol C via one of the two switches. PULSE,N The second plate of the capacitor represents the on-chip capacitor. The CLFG unit 1300 may also include an ESD 1320 coupled to the output terminal (OUT). The CLFG unit 1300 operates only in capacitor mode because the output voltage supplied to the qubit gate is via... Figure 13 The capacitor arrangement shown is provided. Although Figure 13 A number of components are shown arranged in a certain way, but CLFG unit 1300 may include additional or fewer components arranged differently. As an example, CLFG unit 1300 may not include ESD 1320.

[0079] Figure 14 An example of a CLFG unit 1400 configured to operate in dual modes (including capacitor mode and direct mode) is shown. Unless otherwise indicated, Figure 14 The signal cited in the text has a similarity to the earlier one. Figure 5 to Figure 7B And the same meaning described in Tables 1 and 2. The CLFG unit 1400 is configured to lock charge and provides a voltage output at the output terminal (OUT) associated with the CLFG unit. Each CLFG unit 1400 can correspond to any one of N units. In capacitor mode (enabled by maintenance of a signal marked CL_MODE maintained via switch 1414), the dynamic voltage (based on the voltage output via the VHFG terminal (at...) Figure 5 V is referred to as V in Chinese. HIGH The voltage received or via the VLFG terminal (in) Figure 5 V is referred to as V in Chinese. LOW One of the received voltages can be coupled to the output terminal. The CLFG unit 1400 may include components responsive to CL_EN. <n>The CLFG unit 1400 can also include a switch 1416 that is operable in response to a signal. The signal can be provided under control of an appropriate finite state machine or another type of control logic, as described with respect to Figure 10 FIG. 4. When the switch 1416 is closed, a voltage received via the input terminal (IN) on the signal line VICL (referred to in Figure 5 as V HOLD ) can be coupled to one plate of a capacitor labeled C PULSE,N , which represents an on-chip capacitor. The CLFG unit 1400 can also include a switch 1416 and a switch 1418. The CLFG unit 1400 can also include an inverter 1420. The CLFG unit 1400 can be configured such that only one of these switches (1416 and 1418) is closed at a time. In this example, the switch labeled CL_EN <n>The signal can control switch 1416, and an inverted version of the signal (e.g., inverted by inverter 1420) can control switch 1418. In this way, at some time, voltage V HIGH or voltage V LOW may be coupled to the second plate of the capacitor labeled C PULSE,N , which represents an on-chip capacitor. When the CL_MODE signal is asserted, the CLFG unit 1400 operates in the capacitive mode because the output voltage supplied to the qubit gate is provided via the capacitive arrangement shown. Figure 14

[0080] With continued reference to Figure 14 , when the CL_MODE signal is de-asserted, the CLFG unit 1400 can operate in the direct mode. Thus, when the CL_MODE signal is de-asserted, switch 1434 is closed and depending on the CL_EN <n>The state of the signal, either switch 1436 or switch 1438 is closed. Thus, at some time, the voltage V HIGH or the voltage V LOW may be coupled to the same terminal, V IN via one of the two switches. The voltage is coupled to this terminal via the input terminal (IN). The CLFG unit 1400 can also include an ESD 1450 coupled to the output terminal (OUT). Although Figure 14 A certain number of components are shown arranged in a certain way, but the CLFG unit 1400 can include additional or fewer components arranged differently. As an example, the CLFG unit 1400 can not include the ESD 1450.

[0081] In the case of the CLFG unit 1300 and the CLFG unit 1400, once the capacitors are charged, the low leakage in the low temperature environment ensures that they need to be refreshed less frequently. Each of the CLFG units can receive the voltage from a single DAC. Using a technique similar to a rasterized display, the single DAC voltage can be used to charge all of the CLFG units (e.g., 32 CLFG units in the example described earlier). Thus, in this example, the DAC voltage is provided to the capacitors by closing the switches in the path between the DAC voltage line and the capacitors; after the capacitors are charged, the switches are opened, and the DAC voltage is used to charge the next capacitor in a round-robin fashion. By using a shared DAC, the number of input / output lines between the control chip (including the array of CLFG units) and the room temperature electronics is significantly reduced. As described earlier, the interconnect between the low temperature CMOS control chip and the plane of qubits is formed using wirebonds, flip-chip bonds, or other low impedance interconnect technology.

[0082] Figure 15 An example waveform 1500 associated with the signals of the CLFG unit 1300 and the CLFG unit 1400 is shown. In this example, each of the CLFG units 1300 and 1400 is shown operating with respect to a clock labeled XCLK. The CL_CHRG signal is maintained for a period of time based on a clock period (or another indicator) specified in a control register (e.g., REG_DCSR) associated with the low temperature CMOS control chip. The CL_FG control signal is used for charge shuffling. For both the CLFG unit 1300 and the CLFG unit 1400, whenever this control signal is high, the voltage at the OUTCL terminal is VICL+V HIGH The voltage is V LOW pulses between the differences. Whenever the CL_FG control signal is low, both the CLFG unit 1300 and the CLFG unit 1400 are operating in DC mode, such that the output voltage (represented by the waveform labeled OUTCL in the DC mode) is held at the voltage to which the capacitor was initially charged (e.g., by the CL_CHRG signal), and it can dissipate over time without refresh. The waveform labeled OUTCL in the capacitor mode shows the output signal of the CLFG unit 1300. This same waveform also shows the output of the CLFG unit 1400 when operating in capacitor mode. The waveform labeled OUTCL in the direct mode shows the output signal of the CLFG unit 1400 when operating in direct mode. Each of these modes is explained earlier with respect to Figure 13 and 14 explained.

[0083] With continued reference to Figure 15 The fast gate operation cycle using the CLFG 1400 in capacitor mode includes a DC charge of the storage capacitor, followed by a series of pulses. In one example, the DC charge period is determined by the REG_DCSR value. The period and number of pulses is determined by the contents of the CL_FGSR register (explained earlier) which is set to 128 bits. In this example, the contents of this register are read one bit at a time (e.g., by the waveform generator), and applied as the control signal labeled: CL_FG. When using the direct drive mode, the fast gate consists of a series of pulses where the output is directly connected to either VLFG or VHFG. In the direct drive mode, the charge cycle still exists, and behaves the same as a "0" value on the CL_FGSR. Each of these modes is explained earlier with respect to Figure 13 and 14 explained.

[0084] Figure 16 An example waveform 1600 associated with a simulation of the CLFG unit 1400 in capacitor mode is shown. The waveform labeled OUTCL represents the simulated output signal of the CLFG unit 1400 when operating in capacitor mode. The waveform labeled CL_EN corresponds to the enable signal, which is used to enable the CLFG unit to charge. The CL_CHRG signal is used to charge the capacitor (or capacitors) associated with the CLFG unit. As explained earlier, the CL_CHRG signal is maintained for a period of time based on a clock period (or another metric) specified in a control register (e.g., REG_DCSR) associated with the low temperature CMOS control chip. For the CLFG unit 1400, whenever the CL_FG control signal is high, the voltage at the OUTCL terminal is at VICL+V HIGH the voltage is at VICL+V LOW The voltage difference is pulsed. The VICL voltage corresponds to the voltage at the input terminal of the CLFG unit, which can be received from the DAC (as explained earlier). V HIGH The voltage is received via the VHFG terminal, and the waveform is... Figure 16 It is also marked as VHFG. V LOW The voltage is received via the VLFG terminal, and the waveform is... Figure 16 It is also marked as VLFG.

[0085] Continue to refer to Figure 16 Section 1602 of the OUTCL waveform shows the locking of a DC voltage (e.g., 1.8 volts) in the CLFG cell. Section 1604 of the OUTCL waveform shows fast gating of the voltage to generate pulses that can be used as control signals for qubits. Section 1606 shows the locked DC voltage restored after pulse generation. Section 1608 shows the voltage at the OUTCL terminals when the locked DC voltage is not refreshed or restored. Section 1610 shows a locked DC voltage level (e.g., 0.6 volts) that differs from the locked voltage level in section 1602. Section 1612 shows fast gating of the voltage to generate pulses of different amplitudes, which can also be used to control qubits or other such devices. Although Figure 16 The OUTCL waveform is shown as having rectangular pulses, but the pulses can have different shapes. Although Figure 16 The OUTCL waveform is shown as having two different amplitudes; the amplitude of the OUTCL waveform may also vary. Similarly, the pulse frequency of the OUTCL waveform can also be controlled via the previously described low-temperature CMOS control chip. Additionally, the OUTCL waveform can be used to modulate high-frequency signals, such as micro-beam modulation, to generate control signals for qubit gates or other types of qubit devices.

[0086] Figure 17 A first view 1710 and a second view 1750 of the active region of an example qubit device 1700 during a charge-locked test are shown. The qubit device 1700 can be a gallium arsenide (GaAs)-based quantum dot device. In this example, as shown in views 1710 and 1750, multiple signals can be used to control the quantum dots. A previously described low-temperature CMOS control chip can be used to generate any control signals using either capacitive or direct modes associated with the previously described CLFG cell. Signals used to control the qubits may include a left wall (LW) signal, a left plunger (LP) signal, a center wall (CW) signal, a right plunger (RP) signal, and a right wall (RW) signal. Additional signals associated with the quantum dot 1730 in the sensing qubit gate may include a sensing dot top gate (SD). T ), sensing point plunger (SD) P ) and a sensing dot bottom gate (SD B ) In this example, as shown in view 1710, the potentials of control signals LW, LP, CW, RP, and RW can be latched using five CLFG units based on a programmed finite state machine. While Figure 17 The qubit device 1700 is shown with certain control signals, other types of qubit devices with other control signals can also be subject to voltages generated by the low temperature CMOS control chip described earlier.

[0087] Figure 18 A view 1800 is shown of voltage and current changes associated with a quantum dot point (QPC) according to one example. Plot 1810 shows QPC current changes over time. Plot 1820 shows QPC current changes as a function of left wall voltage changes. Plot 1830 shows low temperature CMOS control chip hold voltage changes over time.

[0088] Figure 19 Example waveforms 1900 corresponding to a low temperature CMOS control chip during testing of fast gating operations with quantum dots are shown. Example waveform 1910 corresponds to a readout signal when fast gating is performed at 140 KHz. Example waveform 1920 corresponds to a readout signal when fast gating is performed at 1.26 MHz. Example waveform 1930 corresponds to a readout signal when fast gating is performed at 2.45 MHz. The frequencies can be changed using a frequency divider. The waveforms do not share a common time scale. While Figure 19 The particular duty cycles and amplitudes of the voltage pulses associated with the waveforms can be changed by the low temperature CMOS control chip. This advantageously eliminates the need to control qubit gates from room temperature devices.

[0089] From room temperature controlled qubit gates will require attenuation of the voltage pulses generated at room temperature, resulting in a need to dissipate a large amount of heat from the room temperature voltage pulses. Additionally, instead of needing a voltage signal from room temperature to handle the load of a meter long (or longer) cable (e.g., a 50 ohm transmission line greater than 200 pF as a capacitive load), the cryogenic CMOS control chip only needs to handle the capacitance of the flip chip bond and the very short interconnect between the control chip and the qubit gate. This capacitance can be as low as 0.1 pF. This allows the cryogenic CMOS control chip to control the state of thousands of qubits without needing to dissipate a large amount of heat. Additionally, the power consumption from the fast gating is small, so it allows the control chip to efficiently manage potentially thousands of qubits. In terms of power requirements for controlling qubits, in one example, assuming the readout clock frequency is set to 1 MHz, the qubit interconnect has a capacitance of 1 pF, then the power consumption for 1000 qubit gates for a 0.1 volt pulse is 10 μW. Assuming 10 gates per qubit, 1 mW of power can be used to control 10,000 qubits at a 1 MHz clock frequency or 1000 qubits at a 10 MHz clock frequency.

[0090] Figure 20 An example readout waveform 2000 corresponding to a readout signal through a quantum dot is shown during testing of a cryogenic CMOS control chip. When the CLFG cell voltage V HIGH and V LOW are used to generate pulses for controlling the quantum dot and the voltage on the sensor dot plunger (SD P ) gate is scanned, the waveform 2000 is generated. The waveform 2010 shows the change in V HIGH voltage, and the waveform 2020 shows the change in V LOW voltage. The waveform 2030 shows the pulses applied to the CLFG cell.

[0091] As described earlier, in one example, the cryogenic CMOS control chip can be implemented using a fully depleted silicon-on-insulator (FDSOI) process. In one example, a device based on the FDSOI process can include an un-doped gate channel, an ultra-thin body, an ultra-thin buried oxide (BOX) under the source, drain, and gate, and full dielectric isolation from adjacent devices. As described earlier, a device based on the FDSOI process can include digital and analog devices (e.g., transistors or other devices). Figure 21 An FDSOI digital device 2100 is shown, according to one example. The FDSOI digital device 2100 can include a substrate 2102. In this example, the substrate 2102 can be a silicon-on-insulator (SOI) substrate. By doping the substrate with n-type dopants, a deep n-well 2104 can be formed in the substrate 2102. Additional wells can be formed in the substrate 2102 and the deep n-well 2104. As examples, a p-well 2106 and an n-well 2108 can be formed. Next, using multiple photolithography steps, transistor devices 2120 and 2130 can be formed. In this example, the transistor device 2120 is a p-type transistor, with a gate channel 2122 formed over a block 2126. The transistor device 2120 can also include p+ source / drain regions, as well as contacts S and D to the source / drain. In this example, the transistor device 2130 is an n-type transistor, with a gate channel 2132 formed over a block 2136. The transistor device 2130 can also include n+ source / drain regions, as well as contacts S and D to the source / drain. Capacitors for charge storage are implemented using such transistor devices. Various types of devices and regions can be isolated using shallow trench isolation (STI) regions, which are formed using a dielectric. Example STI regions formed in the FDSOI digital device 2100 include STI 2150, 2152, 2154, 2156, 2158, and 2160.

[0092] Continuing to refer to Figure 21 , the back gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to account for effects associated with cooling. Thus, in this example, the FDSOI digital device 2100 includes a back gate bias via an N BG terminal for n-type devices and a back gate bias via a P BG terminal for p-type devices. In this example, while the FDSOI digital device 2100 includes the ability to change the back gate bias of n-type and p-type devices, the back gate voltage of n-type devices is not allowed to go lower than the back gate voltage of p-type devices.

[0093] Still referring to Figure 21 The back gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to address effects associated with cooling of the chip in low temperature environments. The transistor devices and associated control circuitry are designed such that the threshold voltage of the transistor devices can be tuned despite large changes in the operating temperature of the transistor devices using back gate bias control. The low temperature CMOS control chip can include circuit blocks zoned into domains that are given a common back gate bias. Example domains with separate biasing include circuit blocks for n-type devices, circuit blocks for p-type devices, circuit blocks for analog devices, and circuit blocks for digital devices. In some examples, different back gate biases are provided for transistors with different aspect ratios. While Figure 21 The FDSOI digital device 2100 is shown including a number and type of wells, the FDSOI digital device 2100 can include additional or fewer other types of wells. Additionally, the transistor devices can be planar or non-planar (e.g., FinFET devices).

[0094] Figure 22 An FDSOI analog device 2200 is shown according to one example. Unlike the FDSOI digital device 2100, the FDSOI analog device 2200 includes independent back gate bias control, where the back gate voltage of the p-type devices can be raised to a voltage V DD above, independent of the back gate voltage of the n-type transistors. The FDSOI analog device 2200 can include a substrate 2202. In this example, the substrate 2202 can be a silicon-on-insulator (SOI) substrate. A deep n-well 2204 can be formed in the substrate 2202 by doping the substrate with n-type dopants. A p-well 2206 can be formed in the deep n-well 2204, and an n-well 2208 can be formed in the substrate 2202. Next, using a number of photolithography steps, transistor devices 2220 and transistor devices 2230 can be formed. In this example, the transistor device 2220 is a p-type transistor with a gate channel 2222 formed above a block 2226. The transistor device 2220 can also include p+ type source / drain regions and contacts S and D to the source / drain. In this example, the transistor device 2230 is an n-type transistor with a gate channel 2232 formed above a block 2236. The transistor device 2230 can also include n+ type source / drain regions and contacts S and D to the source / drain. Various types of devices and regions can be isolated using shallow trench isolation (STI) regions, which are formed using a dielectric. Example STI regions formed in the FDSOI analog device 2200 include STI 2250, STI 2252, STI 2254, STI 2256, STI 2258, STI 2260, STI 2262, and STI 2164.

[0095] With continued reference to Figure 22 , the back gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to account for the effects associated with cooling. Thus, in this example, the FDSOI analog device 2200 includes a back gate bias via an N BG terminal for n-type devices and a back gate bias via a P BG terminal for p-type devices. In this example, unlike the FDSOI digital device 2100, the FDSOI analog device 2200 includes independent back gate bias control, where the back gate voltage for p-type devices can be raised to a voltage V DD above, independent of the back gate voltage for n-type devices.

[0096] With continued reference to Figure 22 , the back gate or body bias of each transistor device can be used to dynamically configure the threshold voltage to account for the effects associated with cooling of the chip in a low temperature environment. The transistor devices and related control circuitry are designed such that, using back gate bias control, the threshold voltage of the transistor devices can be tuned despite large changes in the operating temperature of the transistor devices. In some examples, different back gate biases are provided for transistor devices having different aspect ratios. While Figure 22 While the FDSOI analog device 2200 is shown including a certain number and type of wells, the FDSOI analog device 2200 can include additional or fewer other types of wells. Additionally, the transistor devices can be planar or non-planar (e.g., FinFET devices).

[0097] In one example low temperature CMOS control chip, the FDSOI digital device 2100 can be used as part of a circuit block that only requires the difference between the low and high values of voltage and does not involve intermediate values. Because the FDSOI digital device 2100 takes up less area than the FDSOI analog device 2200, it is advantageous to use it for most circuits, as long as they are not too sensitive. In one example, only the FDSOI analog device 2200 is fabricated, such that there is independent back gate bias control for n-type and p-type devices as well as independent back gate bias control based on the aspect ratio of the devices. As described earlier, the low temperature CMOS control chip can be zoned into domains, such that each domain includes multiple transistor devices, but shares a common back gate bias. In one example, there can be eight domains based on the combination of n-type and p-type devices and the different aspect ratios associated with each type of device.

[0098] Figure 23 A flowchart 2300 is shown that corresponds to a method associated with the systems described in this disclosure. In one example, a system for controlling a qubit gate can include a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at cryogenic temperatures. As an example, the quantum device can correspond to the qubit 160 of Figure 1 The system can also include a control circuit configured to operate at cryogenic temperatures, and where the control circuit includes a plurality of charge-locked circuits. As an example, the control circuit can correspond to the circuits included in the cryogenic CMOS control chip described earlier. Each charge-locked circuit of the plurality of charge-locked circuits can be coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locked circuit of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate, where each charge-locked circuit of the plurality of charge-locked circuits includes a first terminal to receive an input voltage signal and a second terminal to selectively receive a first voltage amount or a second voltage amount, where the first voltage amount is greater than the second voltage amount. As an example, the charge-locked circuits can be included as part of the CLFG unit 360. Each charge-locked circuit can correspond to any of the CLFG units 500, 1300, or 1400 described earlier.

[0099] Step 2310 can include operating the first subset of the plurality of charge-locked circuits in a capacitance mode such that the voltage signal output to the at least one qubit gate includes a pulse signal having a first controlled amplitude, where the first controlled amplitude depends on an amount of the input voltage signal and each of the first voltage amount and the second voltage amount. In one example, this step can relate to the operation of the CLFG unit 1300. As described earlier, the CLFG unit 1300 can include a CLFG unit 1300 that can respond to the CL_EN <n>Switch 1312 is operated by a signal. This signal can be provided under the control of a suitable finite state machine or another type of logic, such as relative to... Figure 10 Described. When switch 1312 is closed, the voltage received via the input terminal (IN) on signal line VICL (in Figure 5 V is referred to as V in Chinese. HOLD ) can be coupled to denoted as C PULSE,N One plate of the capacitor represents the on-chip capacitance. The CLFG unit 1300 may also include switches 1314 and 1316. The CLFG unit 1300 may also include an inverter 1318. The CLFG unit 1300 can be configured such that only one of these switches is closed at a certain time. In this example, it is labeled CL_EN. <n>The signal can control switch 1314, and an inverted version of the signal (e.g., inverted by inverter 1318) can control switch 1316. In this way, at some time, voltage V HIGH or voltage V LOW may be coupled to the second plate of the capacitor labeled C PULSE,N , which represents an on-chip capacitor, via one of the two switches.

[0100] Step 2320 can include operating the second subset of the plurality of charge-locked circuits in a direct mode such that the voltage signal output to the at least one qubit gate includes a signal having a second controlled amplitude, where the second controlled amplitude depends on the input voltage signal and only one of the first voltage quantity or the second voltage quantity. In one example, this step can be related to the operation of CLFG unit 1400. As described earlier, CLFG unit 1400 can operate in the direct mode when the CL_MODE signal is negated. Thus, when the CL_MODE signal is negated, switch 1434 is closed and the voltage signal output to the at least one qubit gate depends on CL_EN <n>The state of the signal, either switch 1436 or switch 1438 is closed. Thus, at some time, the voltage V HIGH or the voltage V LOW may be coupled to the same terminal, V IN the voltage is coupled to the terminal via the input terminal (IN).

[0101] In summary, in one aspect, the present disclosure relates to a system for controlling qubit gates. The system can include a first packaging device comprising a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system can further include a second packaging device comprising a control circuit configured to operate at cryogenic temperatures, wherein the first packaging device is coupled to the second packaging device, and wherein the control circuit comprises a plurality of charge-locked circuits, wherein each charge-locked circuit of the plurality of charge-locked circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locked circuit of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate.

[0102] Each charge-locked circuit of the plurality of charge-locked circuits can include an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to the at least one qubit gate. Each charge-locked circuit of the plurality of charge-locked circuits can further include a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, wherein the first voltage amount is greater than the second voltage amount.

[0103] Each charge-locked circuit of the plurality of charge-locked circuits can be configured to generate the voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on the first voltage amount and the second voltage amount. At least a subset of the plurality of charge-locked circuits can be configured to operate in one of a direct mode or a capacitive mode. Each charge-locked circuit of the at least a subset of the plurality of charge-locked circuits can include a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving the first voltage amount or the second voltage amount, wherein the first voltage amount is greater than the second voltage amount. The capacitor can not be charged during the direct mode. The capacitor can be charged during the capacitive mode.

[0104] Each charge-locking circuit of the plurality of charge-locking circuits can include a plurality of transistor devices, and each transistor of at least a subset of the plurality of transistors can include a back-gate bias terminal. The back-gate bias terminal can be configured to receive a voltage to change a threshold voltage associated with the respective transistor. The control circuit can further include control logic configured to control at least one control signal associated with each charge-locking circuit of the plurality of charge-locking circuits.

[0105] In another aspect, the disclosure relates to a method for use in a system for controlling qubit gates, the system comprising a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures, and a control circuit configured to operate at cryogenic temperatures, and wherein the control circuit comprises a plurality of charge-locking circuits, wherein each charge-locking circuit of the plurality of charge-locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locking circuit of the plurality of charge-locking circuits is configured to provide a voltage signal to the at least one qubit gate, and wherein each charge-locking circuit of the plurality of charge-locking circuits comprises a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, and wherein the first voltage amount is greater than the second voltage amount. The method can comprise operating a first subset of the plurality of charge-locking circuits in a capacitive mode, such that the voltage signal output to the at least one qubit gate comprises a pulsed signal having a first controlled amplitude, wherein the first controlled amplitude depends on an amount of the input voltage signal and each of the first voltage amount and the second voltage amount. The method can further comprise operating a second subset of the plurality of charge-locking circuits in a direct mode, such that the voltage signal output to the at least one qubit gate comprises a signal having a second controlled amplitude, wherein the second controlled amplitude depends on the input voltage signal and only one of the first voltage amount or the second voltage amount.

[0106] The control circuit can further include control logic configured to control at least one control signal associated with each charge-locking circuit of the plurality of charge-locking circuits. Each charge-locking circuit of the plurality of charge-locking circuits can include a plurality of transistor devices, and each transistor of at least a subset of the plurality of transistors includes a back-gate bias terminal. The back-gate bias terminal can be configured to receive a voltage to change a threshold voltage associated with the respective transistor.

[0107] In yet another aspect, the present disclosure relates to a system for controlling qubit gates. The system can include a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system can further include a control circuit configured to operate at cryogenic temperatures, wherein the control circuit comprises a plurality of charge-locked circuits, wherein each charge-locked circuit of the plurality of charge-locked circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locked circuit of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate, and wherein each charge-locked circuit of the plurality of charge-locked circuits comprises an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to the at least one qubit gate, and wherein the control circuit further comprises control logic configured to provide at least one control signal associated with each charge-locked circuit of the plurality of charge-locked circuits.

[0108] Each charge-locked circuit of the plurality of charge-locked circuits can further comprise a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, wherein the first voltage amount is greater than the second voltage amount, and wherein each charge-locked circuit of the plurality of charge-locked circuits is configured to generate the voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on the first voltage amount and the second voltage amount.

[0109] At least a subset of the plurality of charge-locked circuits can be configured to operate in one of a direct mode or a capacitive mode, and wherein each charge-locked circuit of the at least a subset of the plurality of charge-locked circuits comprises a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, wherein the first voltage amount is greater than the second voltage amount. The capacitor can not be charged during the direct mode. The capacitor can be charged during the capacitive mode.

[0110] It is to be understood that the methods, modules, and components depicted herein are merely examples. For example, but not by way of limitation, illustrative types of devices can include field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SOCs), complex programmable logic devices (CPLDs), etc.

[0111] Also, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, a

[0112] Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations can be combined into a single operation, and / or the functionality of a single operation can be distributed in additional operations. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be altered in various other embodiments.

[0113] Although the present disclosure provides specific examples, various modifications and changes can be made therein without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative manner and not a restrictive one, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems that are described herein as associated with specific examples are not intended to be limiting unless expressly stated as such. The specification and appended drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

[0114] Furthermore, as used herein the terms "a" or "one" are defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that the invention encompasses more than one of the claimed elements unless the language specifically states otherwise. The same holds true for the use of definite articles. Unless specifically stated otherwise, the term "comprising" encompasses the presence of stalement(s) or element(s) of a claim; the terms "including," "comprising," and "having" are intended to be open-ended and mean that there can be additional elements other than the listed elements.

[0115] Unless otherwise specified, the terms "first" and "second" are used arbitrarily to distinguish between elements of the same type. Thus, these terms are not necessarily intended to indicate a time or other priority.< / n> < / n> < / n> < / n> ​< / n> < / n> < / n> < / n> < / n>

Claims

1. A system for controlling qubit gates, comprising: a first packaging device comprising a quantum device, the quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at a cryogenic temperature; and a second packaging device comprising a control circuit configured to operate at the cryogenic temperature, wherein the first packaging device is coupled to the second packaging device, and wherein the control circuit comprises a plurality of charge-locked circuits, wherein each charge-locked circuit of the plurality of charge-locked circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locked circuit of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate, wherein each charge-locked circuit of the plurality of charge-locked circuits comprises an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to the at least one qubit gate, and wherein each charge-locked circuit of the plurality of charge-locked circuits further comprises a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, wherein the first voltage amount is greater than the second voltage amount.

2. The system of claim 1, wherein each charge-locked circuit of the plurality of charge-locked circuits is configured to generate the voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on the first voltage amount and the second voltage amount.

3. The system of claim 1, wherein at least a subset of the plurality of charge-locked circuits is configured to operate in one of a direct mode or a capacitive mode.

4. The system of claim 3, wherein each charge-locked circuit of the at least a subset of the plurality of charge-locked circuits comprises a capacitor having a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, wherein the first voltage amount is greater than the second voltage amount.

5. The system of claim 4, wherein the capacitor is not charged during the direct mode.

6. The system of claim 4, wherein the capacitor is charged during the capacitive mode.

7. The system of claim 1, wherein each charge-locked circuit of the plurality of charge-locked circuits comprises a plurality of transistor devices, and wherein each transistor of at least a subset of the plurality of transistors comprises a back-gate bias terminal.

8. The system of claim 7, wherein the back-gate bias terminal is configured to receive a voltage to change a threshold voltage associated with the respective transistor.

9. The system of claim 1, wherein the control circuit further comprises control logic configured to control at least one control signal associated with each charge-locked circuit of the plurality of charge-locked circuits.

10. The system of claim 1, wherein each charge-locking circuit of the plurality of charge- locking circuits further comprises a switch for selectively coupling an input voltage signal received via the input terminal to a first terminal of the capacitor.

11. A method for use in a system for controlling qubit gates, the system comprising a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at a cryogenic temperature, and a control circuit is configured to operate at the cryogenic temperature, and wherein the control circuit comprises a plurality of charge-locking circuits, wherein each charge-locking circuit of the plurality of charge-locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locking circuit of the plurality of charge-locking circuits is configured to provide a voltage signal to the at least one qubit gate, and wherein each charge-locking circuit of the plurality of charge-locking circuits comprises a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, and wherein the first voltage amount is greater than the second voltage amount, the method comprising: operating a first subset of the plurality of charge-locking circuits in a capacitive mode, such that the voltage signal output to the at least one qubit gate comprises a pulsed signal having a first controlled amplitude, wherein the first controlled amplitude depends on an amount of the input voltage signal and each of the first voltage amount and the second voltage amount; and operating a second subset of the plurality of charge-locking circuits in a direct mode, such that the voltage signal output to the at least one qubit gate comprises a signal having a second controlled amplitude, wherein the second controlled amplitude depends on the input voltage signal and only one of the first voltage amount or the second voltage amount.

12. The method of claim 11, wherein the control circuit further comprises control logic configured to control at least one control signal associated with each charge-locking circuit of the plurality of charge-locking circuits.

13. The method of claim 11, wherein each charge-locking circuit of the plurality of charge- locking circuits comprises a plurality of transistor devices, and wherein each transistor of at least a subset of the plurality of transistors comprises a back-gate bias terminal.

14. The method of claim 13, wherein the back-gate bias terminal is configured to receive a voltage to change a threshold voltage associated with the respective transistor.

15. A system for controlling qubit gates, comprising: a quantum device comprising a plurality of qubit gates, wherein the quantum device is configured to operate at a cryogenic temperature; and a control circuit configured to operate at the low temperature, and wherein the control circuit comprises a plurality of charge-locked circuits, wherein each charge-locked circuit of the plurality of charge-locked circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge-locked circuit of the plurality of charge-locked circuits is configured to provide a voltage signal to the at least one qubit gate, and wherein each charge-locked circuit of the plurality of charge-locked circuits comprises an input terminal for receiving an input voltage signal and an output terminal for selectively providing the voltage signal to the at least one qubit gate, and wherein the control circuit further comprises control logic configured to provide at least one control signal associated with each charge-locked circuit of the plurality of charge-locked circuits, wherein each charge-locked circuit of the plurality of charge-locked circuits further comprises a capacitor having a first terminal for receiving the input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, wherein the first voltage amount is greater than the second voltage amount.

16. The system of claim 15, wherein each charge-locked circuit of the plurality of charge-locked circuits is configured to generate the voltage signal as a pulse signal having a controlled amplitude, wherein the controlled amplitude depends at least on the first voltage amount and the second voltage amount.

17. The system of claim 15, wherein at least a subset of the plurality of charge-locked circuits is configured to operate in one of a direct mode or a capacitive mode, and wherein each charge-locked circuit of the at least a subset of the plurality of charge-locked circuits comprises a capacitor having a first terminal for receiving an input voltage signal and a second terminal for selectively receiving a first voltage amount or a second voltage amount, wherein the first voltage amount is greater than the second voltage amount.

18. The system of claim 17, wherein the capacitor is not charged during the direct mode.

19. The system of claim 17, wherein the capacitor is charged during the capacitive mode.

20. The system of claim 15, wherein each charge-locked circuit of the plurality of charge-locked circuits further comprises a switch for selectively coupling an input voltage signal received via the input terminal to the first terminal of the capacitor.

Images