Semiconductor die including silicon nitride stress compensation regions and methods of manufacturing the same

Abstract

A method of forming a semiconductor structure includes forming a first semiconductor device over a first substrate, forming a first dielectric material layer over the first semiconductor device, forming vertical recesses in the first dielectric material layer such that each of the vertical recesses extends vertically from a topmost surface of the first dielectric material layer toward the first substrate, forming a portion of silicon nitride material in each of the vertical recesses, and locally irradiating a second subset of the portions of silicon nitride material with a laser beam. A first subset of the portions of silicon nitride material that are not irradiated with the laser beam includes first portions of silicon nitride material that impart a tensile stress to a respective surrounding material portion, and the second subset of the portions of silicon nitride material that are irradiated with the laser beam includes second portions of silicon nitride material that impart a compressive stress to a respective surrounding material portion.

Description

[0001] Related Applications

[0002] This patent application claims the benefit of priority to U.S. Nonprovisional Patent Application Serial No. 16 / 806,087, filed March 2, 2020, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of semiconductor devices, and more specifically to silicon nitride stress compensation regions for reducing warpage of semiconductor dies and methods of manufacturing the same. BACKGROUND

[0004] Three-dimensional memory devices including three-dimensional vertical NAND strings with one bit per cell are disclosed in T. Endoh et al., “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. SUMMARY

[0005] According to one aspect of the present disclosure, a semiconductor structure is provided that includes a first semiconductor die. The first semiconductor die includes a first substrate, a first semiconductor device located above the first substrate, a first dielectric material layer located above the first semiconductor device, a first silicon nitride material portion embedded within an upper portion of the first dielectric material layer and imparting a tensile stress to a respective surrounding material portion, and a second silicon nitride material portion embedded within the upper portion of the first dielectric material layer and imparting a compressive stress to a respective surrounding material portion.

[0006] According to another aspect of the present disclosure, a method of forming a semiconductor structure includes forming a first semiconductor device over a first substrate; forming a first dielectric material layer over the first semiconductor device; forming vertical recesses in the first dielectric material layer such that each of the vertical recesses extends vertically from a topmost surface of the first dielectric material layer toward the first substrate; forming portions of silicon nitride material in each of the vertical recesses; and locally irradiating a second subset of the portions of silicon nitride material with a laser beam. A first subset of the portions of silicon nitride material that are not irradiated with the laser beam includes first portions of silicon nitride material that impart a tensile stress to respective surrounding material portions, and the second subset of the portions of silicon nitride material that are irradiated with the laser beam includes second portions of silicon nitride material that impart a compressive stress to respective surrounding material portions. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1A is a top-down view of a first exemplary structure including a first semiconductor die after forming a first dielectric material layer according to the first embodiment of the present disclosure.

[0008] FIG. 1B and 1C is a different magnified view of a vertical cross-sectional view taken along vertical plane B-B’ of the first exemplary structure of FIG. 1A

[0009] FIG. 2A is a top-down view of the first exemplary structure after forming vertical recesses according to the first embodiment of the present disclosure.

[0010] FIG. 2B is a vertical cross-sectional view taken along vertical plane B-B’ of the first exemplary structure of FIG. 2A

[0011] FIG. 3A is a top-down view of the first exemplary structure after forming a compressive stress silicon nitride material layer according to the first embodiment of the present disclosure.

[0012] FIG. 3B is a vertical cross-sectional view taken along vertical plane B-B’ of the first exemplary structure of FIG. 3A

[0013] FIG. 4A is a top-down view of the first exemplary structure after forming a compressive stress silicon nitride material strip according to the first embodiment of the present disclosure.

[0014] FIG. 4B is a vertical cross-sectional view taken along vertical plane B-B’ of the first exemplary structure of FIG. 4A

[0015] FIG. 5A ​​​​is a top-down view of the first exemplary structure after converting a subset of the compressively stressed silicon nitride material strips to tensilely stressed silicon nitride material strips according to the first embodiment of the present disclosure.

[0016] FIG. 5B is a vertical cross-sectional view taken along vertical plane B-B’ of the first exemplary structure. FIG. 5A

[0017] FIG. 6A is a top-down view of the first exemplary structure after forming first bonding pads according to the first embodiment of the present disclosure.

[0018] FIG. 6B is a vertical cross-sectional view taken along vertical plane B-B’ of the first exemplary structure. FIG. 6A

[0019] FIG. 7A is a top-down view of a second semiconductor die according to the first embodiment of the present disclosure.

[0020] FIG. 7B and 7C is a vertical cross-sectional view taken along vertical plane B-B’ of the second semiconductor die structure. FIG. 7A

[0021] FIG. 8A is a top-down view of the first exemplary structure after forming a bonded assembly of the first semiconductor die and the second semiconductor die according to the first embodiment of the present disclosure.

[0022] FIG. 8B is a vertical cross-sectional view taken along vertical plane B-B’ of the first exemplary structure. FIG. 8A

[0023] FIG. 9A is a top-down view of a second exemplary structure including a first semiconductor die after forming lower-level bonding pads embedded in a first lower-level dielectric material layer according to the second embodiment of the present disclosure.

[0024] FIG. 9B is a vertical cross-sectional view taken along vertical plane B-B’ of the second exemplary structure. FIG. 9A

[0025] FIG. 10A is a top-down view of the second exemplary structure after forming a first upper-level dielectric material layer according to the second embodiment of the present disclosure.

[0026] FIG. 10B is a vertical cross-sectional view taken along vertical plane B-B’ of the second exemplary structure. FIG. 10A ​​​​​​

[0027] FIG. 11A is a top-down view of the second exemplary structure after forming vertical recesses according to the second embodiment of the disclosure.

[0028] FIG. 11B is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 11A

[0029] FIG. 12A is a top-down view of the second exemplary structure after forming a layer of compressively stressed silicon nitride material according to the second embodiment of the disclosure.

[0030] FIG. 12B is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 12A

[0031] FIG. 13A is a top-down view of the second exemplary structure after forming compressively stressed silicon nitride material strips and compressively stressed silicon nitride material pillars according to the second embodiment of the disclosure.

[0032] FIG. 13B is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 13A

[0033] FIG. 14A is a top-down view of the second exemplary structure after converting a subset of the compressively stressed silicon nitride material strips to tensile stressed silicon nitride material strips and converting a subset of the compressively stressed silicon nitride material pillars to tensile stressed silicon nitride material pillars according to the second embodiment of the disclosure.

[0034] FIG. 14B is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 14A

[0035] FIG. 15A is a top-down view of the second exemplary structure after forming first bonding pads according to the second embodiment of the disclosure.

[0036] FIG. 15B is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 15A

[0037] FIG. 16A is a top-down view of the second exemplary structure after forming cavities in the recessed regions by vertically recessing portions of the first upper-level dielectric material layer according to the second embodiment of the disclosure.

[0038] FIG. 16B is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 15A ​​​​​a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of

[0039] FIG. 17A is a top-down view of a second semiconductor die according to the second embodiment of the present disclosure.

[0040] FIG. 17B is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 18A

[0041] FIG. 18B is a top-down view of a second exemplary structure according to the second embodiment of the present disclosure after forming a bonded assembly of the first semiconductor die and the second semiconductor die.

[0042] FIG. 18A is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 19A

[0043] FIG. 19B is a top-down view of an alternative embodiment of the second exemplary structure according to the second embodiment of the present disclosure after forming a bonded assembly of the first semiconductor die and a plurality of second semiconductor dies.

[0044] FIG. 19A is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 20A

[0045] FIG. 20B is a top-down view of another alternative embodiment of the second exemplary structure according to the second embodiment of the present disclosure after forming a bonded assembly of the first semiconductor die and a plurality of second semiconductor dies.

[0046] FIG. 20A is a vertical cross-sectional view taken along vertical plane B-B' of the second exemplary structure of FIG. 1A to FIG. 1C DETAILED DESCRIPTION

[0047] As described above, embodiments of the present disclosure relate to silicon nitride stress compensation regions for reducing warpage of semiconductor dies, such as semiconductor dies in bonded assemblies, and methods of manufacturing the same, aspects of which are described in detail.

[0048] ​​​​The drawings are not drawn to scale. Where a single instance of an element is illustrated in the drawings, multiple instances of this element can be repeated unless explicitly described or otherwise clearly indicated otherwise. Numerical designators such as“first,”“second,” and“third” are merely used to identify like elements and different numerical designators can be employed throughout the specification and claims of this disclosure. Like designators refer to like elements or features throughout the figures. Elements having the same designator are assumed to have the same composition and the same function unless otherwise stated. “Contact” between elements means direct contact between elements that provides an edge or surface shared by the elements, unless otherwise stated. As used herein, a first element positioned“on” a second element can be positioned on an outer side of a surface of the second element or on an inner side of the second element. As used herein, a first element is“directly” positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein,“prototype” structure or“in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0049] As used herein,“layer” refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of uniform or non-uniform thickness that is less than the thickness of a continuous structure. For example, a layer can be positioned between any pair of horizontal planes between or at the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, thereabove, and / or therebelow.

[0050] As used herein, first and second surfaces are“vertically coincident” with one another if the second surface is above or below the first surface and if there is a vertical plane or substantially vertical plane that includes the first and second surfaces. A substantially vertical plane is a plane that extends linearly in a direction that is angled less than 5 degrees from a vertical direction. A vertical plane or substantially vertical plane is straight along a vertical direction or substantially vertical direction and can or can not include a curvature along a direction perpendicular to the vertical direction or substantially vertical direction.

[0051] As used herein,“memory level” or“memory array level” refers to a level corresponding to a general region between a first horizontal plane including a topmost surface of an array of memory elements (i.e., a plane parallel to a top surface of a substrate) and a second horizontal plane including a bottommost surface of the array of memory elements. As used herein,“through-penetration stack” element refers to an element that extends vertically through a memory level.

[0052] As used herein, a "semiconductor material" refers to a material having an electrical conductivity in the range from 1.0 x 10 -5 S / m to 1.0 x 10 5 S / m. As used herein, a "semiconductor material" refers to a material having an electrical conductivity in the range from 1.0 x 10 -5 S / m to 1.0 S / m in the absence of electrical dopants therein, and capable of producing a doped material having an electrical conductivity in the range from 1.0 S / m to 1.0 x 10 5 S / m upon suitable doping with electrical dopants. As used herein, an "electrical dopant" refers to a p-type dopant that adds holes to a valence band within a band structure or an n-type dopant that adds electrons to a conduction band within a band structure. As used herein, an "electrically conductive material" refers to a material having an electrical conductivity greater than 1.0 x 10 5 S / m. As used herein, an "insulator material" or "dielectric material" refers to a material having an electrical conductivity less than 1.0 x 10 -5 S / m. As used herein, a "heavily doped semiconductor material" refers to a semiconductor material that is doped with electrical dopants at a sufficiently high atomic concentration to become an electrically conductive material (i.e., having an electrical conductivity greater than 1.0 x 10 5 S / m) when formed as a crystalline material or in the case of being converted into a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material that includes electrical dopants (i.e., p-type dopants and / or n-type dopants) at a concentration in the range from 1.0 x 10 -5 S / m to 1.0 x 10 5 S / m. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or electrically conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or electrically conductive, depending on the atomic concentration of electrical dopants therein. As used herein, a "metallic material" refers to an electrically conductive material that includes at least one metallic element therein. All electrical conductivity measurements are made at standard conditions.

[0053] A monolithic three-dimensional memory array is a memory array formed over a single substrate, such as a semiconductor wafer, without intervening substrates, of multiple levels of memory. The term “monolithic” refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled “Three-dimensional Structure Memory,” a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and stacking the memory levels vertically. The substrates can be thinned or removed from the memory levels prior to joining, but since the memory levels are initially formed over separate substrates, such a memory is not a true monolithic three-dimensional memory array. The substrates can include integrated circuits fabricated thereon, such as driver circuits for the memory devices.

[0054] Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be fabricated with the various embodiments described herein. The monolithic three-dimensional NAND strings are positioned in a monolithic three-dimensional NAND string array located over a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located over another memory cell in a second device level of the three-dimensional NAND string array.

[0055] In general, a semiconductor package (or “package”) refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package can include one or more semiconductor chips (or “chips”) that are through-bonded, for example, by flip-chip bonding or another chip-to-chip bonding. A package or chip can include a single semiconductor die (or “die”) or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands concurrently as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there can be some limitations. In the case where a die is a memory die (i.e., a die that includes memory elements), a concurrent read operation, a concurrent write operation, or a concurrent erase operation can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or “blocks”), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. Pages are also the smallest units that can be selected for read operations.

[0056] Reference FIG. 2AFIG. 1 shows a first exemplary structure including a first semiconductor die 100’. The first semiconductor die 100’ includes a first substrate 109 including a first semiconductor material, a first semiconductor device 120 formed on a top surface of the first substrate 109, a first dielectric material layer 140 formed over the first semiconductor device 120 and embedding a first metal interconnect structure 130 therein. While the present disclosure is described with illustration of a single first semiconductor die 100’, it is to be understood that multiple first semiconductor dies 100’ can be formed simultaneously on a single semiconductor wafer, with the first substrate 109 laterally extending across the area of the multiple first semiconductor dies 100’.

[0057] The first substrate 109 can be a semiconductor substrate, and can include a bulk semiconductor wafer or as a semiconductor-on-insulator (SOI) wafer. For example, a commercial single-crystal silicon wafer or a silicon-on-insulator substrate including a single-crystal top semiconductor layer can be used as the first substrate 109.

[0058] The first semiconductor device 120 can include any semiconductor device known in the art. In an illustrative example, the first semiconductor device 120 can include an array of three-dimensional memory elements within a three-dimensional NAND memory device or a three-dimensional NOR memory device. In this case, the first semiconductor device 120 can include an alternating stack (32, 46) of insulating layers 32 and conductive layers (e.g., word lines) 46, and a two-dimensional array of memory opening fill structures 58 formed therein. Each memory opening fill structure can include a vertical semiconductor channel extending vertically between a source region and a drain region, and a vertical stack of memory elements provided at levels of the conductive layers, which can function as word lines. A source line 50 can be provided in contact with the source regions of the memory opening fill structures 58. Bit lines 60 can be electrically connected to respective subsets of the drain regions of the memory opening fill structures 58. One or more dielectric layers 70 can be formed around each vertical alternating stack (32, 46) to provide electrical isolation between adjacent vertical alternating stacks (32, 46).

[0059] The first dielectric material layer 140 includes an interconnect level dielectric material such as an undoped silicate glass, a doped silicate glass, an organosilicate glass, a porous dielectric material, and / or a dielectric metal oxide. The first dielectric material layer 140 embeds the first metal interconnect structure 130. The first metal interconnect structure 130 provides electrical interconnects between various nodes of the first semiconductor device 120 and can include interconnect paths for the first bonding pads to be subsequently formed. For example, the first metal interconnect structure 130 can include metal lines, metal pads, or metal via structures disposed in the area of the first bonding pads to be subsequently formed and vertically recessed from the topmost surface of the first dielectric material layer 140. The vertical distance between the topmost surface of the first dielectric material layer 140 and the top surface of the first substrate 109 can be in the range of 1 to 60 microns, such as 2 to 30 microns, although smaller and larger vertical distances can also be employed.

[0060] The first semiconductor device 120 can include stress components, which can include compressive stress or tensile stress. For example, metal plates, metal lines (e.g., word lines 46), metal wall structures, dielectric plates, and dielectric wall structures can be present in the first semiconductor device 120. Such stress components cause local distortions due to stresses (i.e., strains) that cause the first semiconductor die 100’ to warp. As a result, the topmost surface of the first dielectric material layer 140 can have a topography variation, i.e., a local variation in height and local tensile and / or compressive stresses.

[0061] Referring to FIG. 2B and FIG. 3A A photoresist layer (not shown) can be applied over the top surface of the first dielectric material layer 140. The photoresist layer can be lithographically patterned to form elongated openings. For example, if the first semiconductor die 100’ has a rectangular horizontal cross-sectional shape, the longitudinal direction of the elongated openings can be parallel to the straight sides of the rectangular perimeter of the first semiconductor die 100’, extending along the straight sides and / or laterally in the middle of the first semiconductor die 100’. The length of each elongated opening through the photoresist layer can be in the range of 0.1% to 99.9%, such as 1% to 99% and / or 5% to 90%, of the length of the straight sides of the first semiconductor die 100’. In one embodiment, at least one elongated opening through the photoresist layer can have a length in the range of 50% to 90% of the length of the straight sides of the first semiconductor die 100’.

[0062] According to one aspect of the disclosure, the elongated openings in the photoresist layer can include first elongated openings laterally extending along a first horizontal direction hd1 parallel to straight edges of the first semiconductor die 100', and second elongated openings laterally extending along a second horizontal direction hd2 perpendicular to the first horizontal direction hd2 and parallel to another straight edge of the first semiconductor die 100'. Typically, the elongated openings can be arranged to define at least one bond pad region free of elongated openings. In this case, each bond pad region can be laterally surrounded by a respective subset of the elongated openings. In one embodiment, the elongated openings can have respective rectangular horizontal cross-sectional shapes. A width of each elongated opening can be in a range from 0.5 microns to 10 microns, such as 1 micron to 5 microns.

[0063] An etching process can be performed to transfer the pattern of elongated openings through the upper portion of the first dielectric material layer 140. In one embodiment, an anisotropic etching process can be performed to etch unmasked portions of the first dielectric material layer 140 under the elongated openings in the photoresist layer. The photoresist layer can serve as an etch mask for the anisotropic etching process. A vertical recess is formed in each volume from which material of the first dielectric material layer 140 is removed. Each of the vertical recesses extends vertically from a topmost surface of the first dielectric material layer 140 toward the first substrate 109. The vertical recesses are referred to herein as line cavities 181. The line cavities 181 can have vertical or substantially vertical sidewalls, and can have a depth in a range from 10% to 99%, such as 20% to 60% and / or 30% to 50% of a thickness of the first dielectric material layer 140. For example, the line cavities 181 can have a depth in a range from 0.5 microns to 5 microns. In one embodiment, at least one of the line cavities 181 and / or each of the line cavities 181 can have a respective uniform vertical cross-sectional shape along a vertical plane perpendicular to a respective longitudinal direction.

[0064] In an alternative embodiment, an isotropic etching process can be performed to etch unmasked portions of the first dielectric material layer 140 under the elongated openings in the photoresist layer. The photoresist layer can serve as an etch mask for the isotropic etching process. The vertical recesses (i.e., line cavities 181) formed thereby can have concave sidewalls with undercut beneath the photoresist layer. In this case, a depth of each line cavity 181 can be approximately the same as a lateral undercut distance. Each line cavity 181 can have a depth in a range from 10% to 99%, such as 20% to 60% and / or 30% to 50% of a thickness of the first dielectric material layer 140. For example, the line cavities 181 can have a depth in a range from 0.5 microns to 5 microns. The photoresist layer can be subsequently removed, e.g., by ashing.

[0065] Reference is made to FIG. 3B andFIG. 4A Compressive stress silicon nitride material can be deposited in the cavity 181 and deposited above the top surface of the first dielectric material layer 140 to form a compressive stress silicon nitride layer 180. The compressive stress silicon nitride material can be deposited at approximately 300°C using a mixture of silane, ammonia, and hydrogen source gases via plasma-enhanced chemical vapor deposition (PECVD), allowing hydrogen atoms to be incorporated into the deposited silicon nitride material. The hydrogen atoms incorporated into the silicon nitride material can subject the deposited silicon nitride material to compressive stress and apply tensile stress to the surrounding area. For example, Hasegawa et al. used active hydrogen to deposit amorphous SiN... x Effects of active hydrogen on the stress relaxation of amorphous SiN x A method for depositing a compressive stress silicon nitride material is disclosed in J Appl Phys 75,1493 (1994), the disclosure of which is incorporated herein by reference. In this compressive stress silicon nitride material, the ratio of silicon atoms to nitrogen atoms is approximately 3:4. In other words, the compressive stress silicon nitride material can be stoichiometric except for the addition of hydrogen atoms. The level of tensile stress that can be applied to adjacent material portions of the compressive stress silicon nitride material can range from 0.5 GPa to 3.0 GPa. The thickness of the deposited compressive stress silicon nitride material can be selected to fill the entire volume of each cavity 181. Therefore, the thickness of the horizontally extended portion of the compressive stress silicon nitride layer 180 can range from 0.5 micrometers to 5 micrometers, such as 1 micrometer to 2.5 micrometers, although smaller and larger thicknesses are also possible.

[0066] refer to FIG. 4B and FIG. 5A The horizontal extension of the compressive stress silicon nitride layer 180 covering the top surface of the first dielectric material layer 140 can be removed without removing a portion of the compressive stress silicon nitride layer 180 filling the line cavity 181. For example, an isotropic etching process (such as a wet etching process using hot phosphoric acid) can be performed to etch back the horizontal extension of the compressive stress silicon nitride layer 180 covering the horizontal plane including the top surface of the first dielectric material layer 140. Alternatively or additionally, a chemical mechanical planarization process can be used to remove all or part of the horizontal extension of the compressive stress silicon nitride layer 180 covering the horizontal plane including the top surface of the first dielectric material layer 140.

[0067] Each remaining portion of the compressively stressed silicon nitride layer 180 that fills a respective one of the line cavities 181 constitutes a compressively stressed silicon nitride material strip 182. Each compressively stressed silicon nitride material strip 182 can extend laterally along a respective longitudinal direction, which can be the first horizontal direction hd1 or the second horizontal direction hd2. Each compressively stressed silicon nitride material strip 182 is a portion of silicon nitride material that includes silicon nitride material that applies a tensile stress to a respective adjacent material portion. In cases where a chemical mechanical planarization process is employed to remove portions of the compressively stressed silicon nitride layer 180 that cover a horizontal plane including a top surface of the first dielectric material layer 140, a top surface of the compressively stressed silicon nitride material strip 182 can lie within the horizontal plane including the top surface of the first dielectric material layer 140.

[0068] Local distortions (i.e., local strains) or local stresses in the first semiconductor die 100’ can be known or measured. For example, the local strains or stresses can be calculated or determined experimentally from the same test die and then stored in a database. Alternatively, the local strains can be measured, for example, by measuring a lateral distance between a pair of marks (not shown) present in or on a subset of the first metal interconnect structures embedded in or on the first dielectric material layer 140. In one embodiment, the marks can include alignment marks or overlay measurement marks. In this case, the local distortions (i.e., distortions) in the first semiconductor die can be determined by comparing the measured distance between the pair of marks or the pair of first metal interconnect structures to a nominal distance based on a design layout of the first semiconductor die 100’.

[0069] In one embodiment, the first semiconductor die 100’ can be in tensile stress along one horizontal direction (e.g., a word line or bit line direction) and in compressive stress along a perpendicular horizontal direction (e.g., a bit line or word line direction). Without the addition of the silicon nitride counter stress regions, these opposite stresses can cause the first semiconductor die 100’ to bend into a saddle shape, where the first and second parallel edges of the first semiconductor die 100’ bend upward along the word line direction, and where the third and fourth parallel edges (which are orthogonal to the first and second edges) bend downward along the bit line direction.

[0070] Reference FIG. 5B and FIG. 5AThe first silicon nitride stressor regions under compressive stress are located in a first region of the first semiconductor die 100' under tensile stress to reduce or prevent compressive strain in the first region. The second silicon nitride stressor regions under tensile stress are located in a second region of the first semiconductor die 100' under compressive stress to reduce or prevent tensile strain in the second region. The first silicon nitride stressor regions can comprise compressive stress silicon nitride material strips 182, and the second silicon nitride stressor regions can comprise tensile stress silicon nitride material strips 184.

[0071] The tensile stress silicon nitride material strips 184 can be formed by laser annealing a subset of the compressive stress silicon nitride material strips 182 to outgas hydrogen from these strips. The reduction in hydrogen concentration converts the compressive stress silicon nitride material strips 182 to tensile stress silicon nitride material strips 184. After laser annealing, the remaining compressive stress silicon nitride material strips 182 that are not irradiated with the laser beam are referred to herein as first silicon nitride material strips 182 that impart tensile stress to the respective surrounding material portions of the first semiconductor die 100'. The tensile stress silicon nitride material strips 184 are referred to herein as second silicon nitride material strips 184 that impart compressive stress to the respective surrounding material portions of the first semiconductor die 100'.

[0072] A subset of the compressive stress silicon nitride material strips 182 to be converted to the second silicon nitride material strips 184 by laser irradiation can be selected for each first semiconductor die 100' based on measured local strain or based on stored local stresses or strains in a database. In one embodiment, the first silicon nitride material strips 182 can extend orthogonally to the second silicon nitride material strips 184 if the regions of the first semiconductor die 100' of the same stress type are orthogonal to each other. The first silicon nitride material strips 182 can extend parallel to each other along the first and second parallel edges of the first semiconductor die 100'. The second silicon nitride material strips 184 can extend parallel to each other along the third and first parallel edges of the first semiconductor die 100'. Optionally, one or more of the first or second silicon nitride material strips can also be located in the middle portion of the first semiconductor die 100', as shown in FIG. 1C. The third and fourth edges of the first semiconductor die 100' can be orthogonal to the first and second edges. The second silicon nitride material strips 184 can be orthogonal to the first silicon nitride material strips 182. FIG. 6A

[0073] ​The peak temperature of the compressively stressed silicon nitride material strips 182 during the laser irradiation can be in a range from 600 degrees Celsius to 1,100 degrees Celsius. The intensity and duration of the laser beam can be selected to provide a target annealing temperature in each irradiated region to cause a sufficient amount of hydrogen gas to outgas to convert the stress state of the silicon nitride from a compressive state to a tensile state. In one embodiment, the absolute magnitude of the tensile stress in the second silicon nitride material strips 184 after the laser irradiation process can be in a range from 0.1 GPa to 0.6 GPa, and the absolute magnitude of the compressive stress in the first silicon nitride material strips 182 can be in a range from 1 GPa to 3 GPa.

[0074] Referring to FIG. 6B and FIG. 5A A photoresist layer (not shown) can be applied over the first dielectric material layer 140, the first silicon nitride material strips 182, and the second silicon nitride material strips 184, and can be lithographically patterned to form an array of openings. Each opening can have a circular shape, a polygonal shape, or a rounded polygonal shape, i.e., a polygonal shape modified to replace the corners with rounded corners. An anisotropic etch process can be performed to transfer the pattern of the array of openings through the upper portion of the first dielectric material layer 140. An array of pad cavities can be formed in regions not masked by the photoresist layer. The top surface of an underlying metal interconnect structure, such as a metal pad, a metal line, or a metal via structure, can be physically exposed at the bottom of each pad cavity. The photoresist layer can be subsequently removed, e.g., by ashing.

[0075] At least one metal material can be deposited in the array of pad cavities. The at least one metal material can include, for example, a metal nitride material, such as TiN, TaN, or WN, and a metal fill material, such as Cu or a copper-containing alloy. Excess portions of the at least one metal material can be removed from above the horizontal plane including the top surface of the first dielectric material layer 140 by a planarization process. For example, a chemical-mechanical planarization process can be employed to remove portions of the at least one metal material that cover the horizontal plane including the top surface of the first dielectric material layer 140. The remaining portions of the at least one metal material that fill the array of pad cavities constitute the first bonding pads 168.

[0076] The first bonding pads 168 are formed in the first dielectric material layer 140. The top surface of the first bonding pads 168 can be formed within a horizontal plane including the topmost surface of the first dielectric material layer 140. The first bonding pads 168 can be formed in regions in which there are no silicon nitride material strips (182, 184). As FIG. 5B and FIG. 5A As provided by the processing steps of FIGS. 1A-1C, the first bonding pads 168 are formed after locally annealing a subset of the compressively stressed silicon nitride material strips 182 with laser irradiation.

[0077] In one embodiment, at least one of the silicon nitride material strips (182, 184) can have a lateral dimension that is greater than a maximum lateral dimension of each of the first bonding pads 168, and can have a depth that is greater than a vertical thickness of the first bonding pads 168. For example, at least one and / or each of the silicon nitride material strips (182, 184) can have a lateral dimension that is greater than 100 microns, and a maximum lateral dimension of each of the first bonding pads 168 can be less than 100 microns. In one embodiment, the first bonding pads 168 can have a first pitch along a first horizontal direction hd1 and a second pitch along a second horizontal direction hd2, and at least one and / or each of the silicon nitride material strips (182, 184) can have a lateral dimension that is greater than the first pitch and greater than the second pitch. Further, at least one and / or each of the silicon nitride material strips (182, 184) can have a vertical thickness in a range from 0.5 microns to 5 microns, and the first bonding pads 168 can have a thickness that is less than the vertical thickness of the silicon nitride material strips (182, 184). For example, the thickness of the first bonding pads 168 can be in a range from 0.3 microns to 3 microns.

[0078] Generally, the first silicon nitride material strip 182 and the second silicon nitride material strip 184 can be positioned in any manner that reduces the overall strain and distortion of the first semiconductor die 100’. In some cases, aligning the longitudinal direction of the first silicon nitride material strip 182 along one horizontal direction and the longitudinal direction of the second silicon nitride material strip 184 along another horizontal direction can be advantageous to reduce the overall distortion of the first semiconductor die 100’. Such cases can occur if the principal stress component of the first semiconductor device 120 (such as the word line 46) is arranged along the same horizontal direction. In one embodiment, the first silicon nitride material strip 182 can extend laterally along a first longitudinal direction (such as the first horizontal direction hd1), and the second silicon nitride material strip 184 can extend laterally along a second longitudinal direction (such as the second horizontal direction hd2) that is different from (e.g., perpendicular to) the first longitudinal direction.

[0079] Generally, the first bonding pads 168 can be embedded in an upper portion of the first dielectric material layer 140. In one embodiment, the first bonding pads 168 can be embedded in an upper portion of the first dielectric material layer 140, and the first silicon nitride material strip 182 can be embedded in a lower portion of the first dielectric material layer 140. In one embodiment, the first bonding pads 168 can be embedded in an upper portion of the first dielectric material layer 140, and the second silicon nitride material strip 184 can be embedded in a lower portion of the first dielectric material layer 140. FIG. 5B and FIG. 7A to FIG. 7CThe reduction in warpage of the first semiconductor die 100' in the processing steps provides a more planar top surface of the first dielectric material layer 140, and thus provides the formation of the first bonding pads 168 having a higher planarity in the upper portion of the first dielectric material layer 140. The top surfaces of the first bonding pads 168 are in a horizontal plane that includes the top surface of the first dielectric material layer 140. The top surfaces of the first silicon nitride material strips 182 and the second silicon nitride material strips 184 can be within the horizontal plane that includes the top surface of the first dielectric material layer 140.

[0080] Referring to FIG. 7C , a second semiconductor die 200' is shown that is configured to be bonded to the first semiconductor die 100'. The second semiconductor die 200' includes a second substrate 209, second semiconductor devices 220 located on the second substrate 209, a second dielectric material layer 240 located on the second semiconductor devices 220 and embedded in second metal interconnect structures 230 (as shown in FIG. 8A ), and second bonding pads 268 embedded in the second dielectric material layer 240. The top surfaces of the second bonding pads 268 can be physically exposed within a horizontal plane that includes the top surface of the second dielectric material layer 240. The pattern of the second bonding pads 268 can be a mirror image pattern of the pattern of the first bonding pads 168 of the first semiconductor die 100'. The materials of the second substrate 209, the second dielectric material layer 240, the second metal interconnect structures 230, and the second bonding pads 268 can be the same as the materials of the respective first substrate 109, the first dielectric material layer 140, the first metal interconnect structures 130, and the first bonding pads 168.

[0081] In one embodiment, the first semiconductor devices 120 in the first semiconductor die 100' can include an array of three-dimensional memory elements, and the second semiconductor devices 220 in the second semiconductor die 200' can include peripheral (e.g., driver) circuitry configured to control the operation of the array of three-dimensional memory elements in the first semiconductor die 100'. The second semiconductor devices 220 can include field effect transistors in a CMOS configuration. In general, the first semiconductor devices 120 and the second semiconductor devices 220 can be selected to provide complementary functionality such that the bonded assembly of the first semiconductor die 100' and the second semiconductor die 200' provides enhanced functionality or full functionality that is not provided by the first semiconductor die 100' alone or the second semiconductor die 200' alone.

[0082] Referring to FIG. 8B and FIG. 5AThe second semiconductor die 200' can be configured to face the first semiconductor die 100', such that each second bonding pad 268 faces a corresponding first bonding pad among the first bonding pads 168. Metal-to-metal bonding can be induced between each mating pair of the first bonding pads 168 and the second bonding pads 268 to bond the first bonding pad 168 to the second bonding pad 268. For example, an annealing process can be performed in a temperature range of 200 degrees Celsius to 400 degrees Celsius. Optionally, dielectric-to-dielectric bonding, such as oxide-to-oxide bonding, can be induced between the first dielectric material layer 140 and the second dielectric material layer 240. In this case, the annealing temperature can be in the range of 250 degrees Celsius to 500 degrees Celsius. A bonding assembly 1000' of the first semiconductor die 100' and the second semiconductor die 200' can be formed. FIG. 5B and FIG. 5A In the processing steps, stress is locally adjusted by selectively converting a subset of compressive stress silicon nitride material strips 182 into tensile stress silicon nitride material strips 184, thereby reducing warpage and distortion of the first semiconductor die 100'.

[0083] In particular, if the first semiconductor device 120 includes a tall structure (such as a three-dimensional memory element array) with a height greater than 5 micrometers, then local stress conditioning processes can be effective. FIG. 5B and FIG. 9A The localized stress-adjusting treatment reduces the vertical and lateral displacement of the first mating pad 168 from its ideal position and provides enhanced periodicity and regularity to the first mating pad 168. Therefore, it facilitates alignment and engagement between the first mating pad 168 and the second mating pad 268, and the engagement assembly 1000' can have a solid-bonding structure between the mating pairs of the first mating pad 168 and the second mating pad 268. Although multiple first and second dielectric material layers (140, 240) have been described above, it should be noted that a single dielectric material layer 140 and a single second dielectric material layer 240 can be used alternatively.

[0084] See FIG. 9B and FIG. 1A This illustrates a second exemplary structure including a first semiconductor die 100 according to a second embodiment of the present disclosure. The first semiconductor die 100 of the second embodiment can be derived from the first semiconductor die 100' of the first embodiment by forming only one or more lower layers of a first dielectric material layer 140. A lower subset of the first dielectric material layer 140 includes a first lower-level dielectric material layer 140A, which is a set of lower-level dielectric material layers within the first dielectric material layer 140. The first lower-level dielectric material layer 140A is embedded... FIG. 1B and FIG. 9Aa subset of the first metal interconnect structures 130 that are located within a set of lower-tier dielectric material layers within the first dielectric material layer 140. In other words, in the second implementation FIG. 9B and FIG. 1B of the processing steps of the second implementation, only a lower subset of the first dielectric material layer 140 and a subset of the first metal interconnect structures 130 that are located below a horizontal plane of the middle region of the first dielectric material layer 140 are formed. FIG. 1C and FIG. 1B of the processing steps of the second implementation, only a lower subset of the first dielectric material layer 140 and a subset of the first metal interconnect structures 130 that are located below a horizontal plane of the middle region of the first dielectric material layer 140 are formed.

[0085] For example, FIG. 1C and FIG. 10A At least one array of metal interconnect structures (such as a metal pad, a metal line, or a metal via structure) can be formed within the first lower-tier dielectric material layer 140A. In one implementation, a plurality of arrays of metal interconnect structures can be formed within the first lower-tier dielectric material layer 140A.

[0086] A photoresist layer can be applied over a top surface of the first lower-tier dielectric material layer 140A, and can be lithographically patterned to form at least one array of openings therethrough. Each of the openings through the photoresist layer can be formed over a respective one of the underlying metal interconnect structures 130 embedded in the first lower-tier dielectric material layer 140A. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through an upper portion of the first lower-tier dielectric material layer 140A. At least one array of pad cavities is formed in the upper portion of the first lower-tier dielectric material layer 140A. The photoresist layer can be removed, e.g., by ashing.

[0087] At least one metal material can be deposited in the array of pad cavities. The at least one metal material can include, e.g., a metal nitride material (such as TiN, TaN, or WN) and a metal fill material (such as Cu or a copper-containing alloy). Excess portions of the at least one metal material can be removed from above a horizontal plane including a top surface of the first lower-tier dielectric material layer 140A by a planarization process. For example, a chemical-mechanical planarization process can be employed to remove portions of the at least one metal material that cover the horizontal plane including the top surface of the first lower-tier dielectric material layer 140A. The remaining portions of the at least one metal material that fill the array of pad cavities constitute lower-tier bonding pads 166. Each of the lower-tier bonding pads 166 can contact a respective metal interconnect structure 130 embedded in the first lower-tier dielectric material layer 140A, and can be electrically connected to a respective node of the first semiconductor device 120, or to a respective metal interconnect structure that will subsequently be connected to a respective set of additional metal interconnect structures to be subsequently formed.

[0088] Referring toFIG. 10B and FIG. 11A An additional dielectric material layer can be formed over the first lower-tier dielectric material layer 140A. The additional dielectric material layer is referred to herein as a first upper-tier dielectric material layer 140B. The combination of the first lower-tier dielectric material layer 140A and the first upper-tier dielectric material layer 140B constitutes the first dielectric material layer 140. The first upper-tier dielectric material layer 140B can embed the remaining first metal interconnect structures 130 in regions that do not cover the lower-tier bond pads 166. The lower-tier bond pads 166 are covered by the first upper-tier dielectric material layer 140B and become buried bond pads.

[0089] Referring to FIG. 11B and FIG. 12A A photoresist layer (not shown) can be applied over the top surface of the first dielectric material layer 140. The photoresist layer can be lithographically patterned to form elongated openings extending laterally along the straight sides of the first semiconductor die 100 and to form local openings. For example, if the first semiconductor die 100 has a rectangular horizontal cross-sectional shape, the longitudinal direction of the elongated openings can be parallel to the straight sides of the rectangular perimeter of the first semiconductor die 100. The length of each elongated opening through the photoresist layer can be in the range of 0.1% to 99.9%, such as 1% to 99% and / or 5% to 90%, of the length of the straight sides of the first semiconductor die 100. In one embodiment, at least one elongated opening through the photoresist layer can have a length in the range of 50% to 90% of the length of the straight sides of the first semiconductor die 100. The horizontal cross-sectional shape of each local opening can be a polygonal shape, a circular shape, an elliptical shape, or a shape of any two-dimensional curved shape having a closed perimeter. In one embodiment, at least a subset of the local openings can have a rectangular horizontal cross-sectional shape. The largest lateral dimension of the local openings can be less than 10%, such as less than 5%, for example 0.1% to 3%, of the largest lateral dimension of the first semiconductor die 100. The elongated openings and the local openings in the photoresist layer are formed in regions that do not cover the lower-tier bond pads 166.

[0090] According to one aspect of the disclosure, the elongated openings in the photoresist layer can include first elongated openings laterally extending along a first horizontal direction hd1 parallel to a straight edge of the first semiconductor die 100, and second elongated openings laterally extending along a second horizontal direction hd2 perpendicular to the first horizontal direction hd2 and parallel to another straight edge of the first semiconductor die 100'. In one embodiment, the local openings can include rectangular openings having a length-to-width ratio in a range of 1 : 1 to 3: 1. Generally, the elongated openings and the local openings can be arranged to define at least one bond pad region that is free of the elongated openings, the local openings, and the underlying lower-level bond pads 166. In one embodiment, the elongated openings can have respective rectangular horizontal cross-sectional shapes having a length-to-width ratio in a range of 3: 1 to 10,000: 1. The width of each elongated opening can be in a range of 0.5 microns to 10 microns, such as 1 micron to 5 microns. In the case that the local openings have rectangular shapes, the sides of the rectangular shapes of the local openings can be in a range of 0.5 microns to 30 microns, such as 1 micron to 10 microns.

[0091] An etching process can be performed to transfer the pattern of openings through the upper portion of the first dielectric material layer 140. An anisotropic or isotropic etching process can be performed to etch unmasked portions of the first dielectric material layer 140 below the openings in the photoresist layer. The photoresist layer can serve as an etch mask for the anisotropic etching process. A vertical recess is formed within each volume from which material of the first dielectric material layer 140 is removed. Each of the vertical recesses extends vertically from a topmost surface of the first dielectric material layer 140 toward the first substrate 109. The vertical recesses below the elongated openings are referred to herein as line cavities 181, as in the first embodiment. The vertical recesses below the local openings are referred to herein as pillar cavities 191. The line cavities 181 and the pillar cavities 191 can have vertical or substantially vertical sidewalls, and can have a depth in a range of 10% to 99%, such as 20% to 60% and / or 30% to 50% of a thickness of the first dielectric material layer 140. For example, the depth of the line cavities 181 and the pillar cavities 191 can be in a range of 0.5 microns to 5 microns. In one embodiment, at least one of the line cavities 181 and / or each of the line cavities 181 can have a respective uniform vertical cross-sectional shape along a vertical plane perpendicular to the respective longitudinal direction. If an isotropic etching process is used, the line cavities 181 and the pillar cavities 191 can have concave sidewalls with undercut below the photoresist layer. The photoresist layer can be subsequently removed, e.g., by ashing.

[0092] Referring to FIG. 12B and FIG. 13AThe compressively stressed silicon nitride material can be deposited in the line cavities 181 and the column cavities 191 and over the top surface of the first dielectric material layer 140 to form a compressively stressed silicon nitride layer 180. The compressively stressed silicon nitride material can be deposited using a plasma-enhanced chemical vapor deposition (PECVD) process in which hydrogen atoms are incorporated into the deposited silicon nitride material. The compressively stressed silicon nitride layer 180 in the second exemplary structure can have the same material composition and physical properties as the compressively stressed silicon nitride layer 180 in the first exemplary structure, and can be formed using the same deposition method as in the first embodiment.

[0093] Referring to FIG. 13B and FIG. 14A The horizontally extending portions of the compressively stressed silicon nitride layer 180 that cover the top surface of the first dielectric material layer 140 can be removed without removing portions of the compressively stressed silicon nitride layer 180 that fill the line cavities 181 and the column cavities 191. For example, an isotropic etching process, such as a wet etching process using hot phosphoric acid, can be performed to etch back the horizontally extending portions of the compressively stressed silicon nitride layer 180 that cover the horizontal plane including the top surface of the first dielectric material layer 140. Alternatively or additionally, a chemical mechanical planarization process can be employed to remove all or a portion of the horizontally extending portions of the compressively stressed silicon nitride layer 180 that cover the horizontal plane including the top surface of the first dielectric material layer 140.

[0094] Each remaining portion of the compressively stressed silicon nitride layer 180 that fills a respective one of the line cavities 181 constitutes a compressively stressed silicon nitride material strip 182. Each compressively stressed silicon nitride material strip 182 can extend laterally along a respective longitudinal direction, which can be the first horizontal direction hd1 or the second horizontal direction hd2. Each compressively stressed silicon nitride material strip 182 is a portion of silicon nitride material that includes silicon nitride material under compressive stress that applies tensile stress to a respective adjacent material portion. In the case that a chemical mechanical planarization process is employed to remove portions of the compressively stressed silicon nitride layer 180 that cover the horizontal plane including the top surface of the first dielectric material layer 140, a top surface of the compressively stressed silicon nitride material strip 182 can lie within the horizontal plane including the top surface of the first dielectric material layer 140.

[0095] Each remaining portion of the compressively stressed silicon nitride layer 180 that fills a respective one of the column cavities 191 constitutes a compressively stressed silicon nitride material column 192. Each compressively stressed silicon nitride material column 192 can have a polygonal horizontal cross-sectional shape or a generally curvilinear horizontal cross-sectional shape. Each compressively stressed silicon nitride material column 192 is a portion of silicon nitride material that is under compressive stress that exerts tensile stress to a respective adjacent material portion. In cases where a chemical mechanical planarization process is employed to remove portions of the compressively stressed silicon nitride layer 180 that overlie a horizontal plane comprising a top surface of the first dielectric material layer 140, a top surface of the compressively stressed silicon nitride material column 192 can lie within the horizontal plane comprising the top surface of the first dielectric material layer 140. In one embodiment, a set of compressively stressed silicon nitride material columns 192 can be disposed along a periphery of a region comprising a respective underlying array of bond pads 166.

[0096] Reference is made to FIG. 14B and FIG. 15A As in the first embodiment, a subset of the compressively stressed silicon nitride material strips 182 and the compressively stressed silicon nitride material columns 192 can be locally annealed with laser radiation. A first subset of the compressively stressed silicon nitride material strips 182 that are not irradiated with the laser beam comprises first silicon nitride material strips 182 that are under compressive stress and exert tensile stress to respective surrounding material portions, and a second subset of the compressively stressed silicon nitride material strips 182 that are irradiated with the laser beam comprises second silicon nitride material strips 184 that are under tensile stress and exert compressive stress to respective surrounding material portions. In other words, the first subset of the compressively stressed silicon nitride material strips 182 that are not irradiated with the laser beam is hereinafter referred to as first silicon nitride material strips 182, and the second subset of the compressively stressed silicon nitride material strips 182 that are irradiated with the laser beam is hereinafter referred to as second silicon nitride material strips 184.

[0097] A first subset of the compressively stressed silicon nitride material columns 192 that are not irradiated with the laser beam comprises first silicon nitride material columns 192 that are under compressive stress and exert tensile stress to respective surrounding material portions, and a second subset of the compressively stressed silicon nitride material columns 192 that are irradiated with the laser beam comprises second silicon nitride material columns 194 that are under tensile stress and exert compressive stress to respective surrounding material portions. In other words, the first subset of the compressively stressed silicon nitride material columns 192 that are not irradiated with the laser beam is hereinafter referred to as first silicon nitride material columns 192, and the second subset of the compressively stressed silicon nitride material columns 192 that are irradiated with the laser beam is hereinafter referred to as second silicon nitride material columns 194.

[0098] As in the first embodiment, a subset of the compressive-stress silicon nitride material strips 182 to be converted into the second silicon nitride material strips 184 by laser irradiation and a subset of the compressive-stress silicon nitride material pillars 192 to be converted into the second silicon nitride material pillars 194 by laser irradiation can be selected for each first semiconductor die 100.

[0099] Generally, the first silicon nitride material strips 182, the second silicon nitride material strips 184, the first silicon nitride material pillars 192, and the second silicon nitride material pillars 194 can be positioned in any manner that reduces the overall strain and distortion of the first semiconductor die 100. In some cases, aligning the longitudinal direction of the first silicon nitride material strips 182 along one horizontal direction and aligning the longitudinal direction of the second silicon nitride material strips 184 along another horizontal direction can facilitate reducing the overall distortion of the first semiconductor die 100. Such cases can occur if the principal stress components of the first semiconductor device 120 (such as the word lines 46) are arranged along the same horizontal direction. In one embodiment, the first silicon nitride material strips 182 can extend laterally along a first longitudinal direction (such as a first horizontal direction hd1), and the second silicon nitride material strips 184 can extend laterally along a second longitudinal direction (such as a second horizontal direction hd2) that is different from (e.g., orthogonal to) the first longitudinal direction.

[0100] In one embodiment, the first silicon nitride material pillars 192 and the second silicon nitride material pillars 194 can be arranged along a periphery of a region including the lower-level bonding pads 166. The first silicon nitride material pillars 192 and the second silicon nitride material pillars 194 can be located outside the region of the lower-level bonding pads 166. Sidewalls of the first silicon nitride material pillars 192 and the second silicon nitride material pillars 194 can be aligned with a periphery of a respective region including a respective array of the lower-level bonding pads 166.

[0101] Reference is made to FIG. 15B and FIG. 16AAn optional photoresist layer (not shown) can be applied over the first dielectric material layer 140, the first silicon nitride material strips 182, the second silicon nitride material strips 184, the first silicon nitride material pillars 192, and the second silicon nitride material pillars 194, and can be lithographically patterned to form an optional array of openings. Each opening can have a polygonal shape or a rounded polygonal shape, i.e., a polygonal shape modified to replace a corner with a rounded corner. The openings can be formed in regions that do not cover any of the first silicon nitride material strips 182, the second silicon nitride material strips 184, the first silicon nitride material pillars 192, the second silicon nitride material pillars 194, and the underlying level bonding pads 166, which are buried bonding pads. An anisotropic etch process can be performed to transfer the pattern of the array of openings through the upper portion of the first dielectric material layer 140. An optional array of pad cavities can be formed in the regions that are not masked by the photoresist layer. A top surface of an underlying metal interconnect structure, such as a metal pad, a metal line, or a metal via structure, can be physically exposed at the bottom of each pad cavity. The photoresist layer can be subsequently removed, e.g., by ashing.

[0102] At least one metal material can be optionally deposited in the array of pad cavities. The at least one metal material can include, for example, a metal nitride material, such as TiN, TaN, or WN, and a metal fill material, such as Cu or a copper-containing alloy. Excess portions of the at least one metal material can be removed from above the level plane that includes the top surface of the first dielectric material layer 140 by a planarization process. For example, a chemical-mechanical planarization process can be employed to remove portions of the at least one metal material that cover the level plane that includes the top surface of the first dielectric material layer 140. The remaining portions of the at least one metal material that fill the array of pad cavities constitute the optional first bonding pads 168. In an alternative implementation, if a second semiconductor die to be bonded to the first semiconductor die 100 does not extend to a peripheral region of the first semiconductor die 100 in which the first bonding pads 168 are located, then the first bonding pads 168 can be omitted. FIG. 13A

[0103] Thus, the first bonding pads 168 are omitted or are located in the upper portion of the first dielectric material layer 140. The underlying level bonding pads 166 are vertically recessed from the top surface of the first dielectric material layer 140 and from the first bonding pads 168, if present. The underlying level bonding pads 166 are covered by the first upper level dielectric material layer 140B, which includes the upper portion of the first dielectric material layer 140. The top surface of the first bonding pads 168, if present, can be formed within a level plane that includes the topmost surface of the first dielectric material layer 140. The first bonding pads 168 can be formed in regions in which there are no silicon nitride material strips (182, 184) and silicon nitride material pillars (192, 194). The first bonding pads 168 can be formed by a laser irradiation process, as described above. FIG. 13B and​FIG. 14A After locally annealing the subset of the silicon nitride material strips 182 and the subset of the silicon nitride material pillars 192 provided in the processing steps of the first semiconductor die 100', an optional first bonding pad 168 is formed.

[0104] Generally, the first bonding pad 168 can be embedded in an upper portion of the first dielectric material layer 140. In FIG. 14B and FIG. 16A The reduction of the deformation of the first semiconductor die 100' in the processing steps of the first semiconductor die 100' provides a more planar topmost surface of the first dielectric material layer 140, and thus enables forming the first bonding pad 168 in the upper portion of the first dielectric material layer 140 with a higher planarity. A top surface of the first bonding pad 168 lies in a horizontal plane comprising a top surface of the first dielectric material layer 140. Top surfaces of the first silicon nitride material strips 182, the second silicon nitride material strips 184, the first silicon nitride material pillars 192, and the second silicon nitride material pillars 194 can be within the horizontal plane comprising the top surface of the first dielectric material layer 140.

[0105] With reference to FIG. 16B and FIG. 16A A photoresist layer can be applied over the first dielectric material layer 140, and can be lithographically patterned to form at least one opening therethrough. Each opening in the photoresist layer can be formed in a region covering an array of underlying bonding pads 166, which are buried bonding pads. An etching process can be performed to remove unmasked portions of the first dielectric material layer 140 that are located under the openings in the photoresist layer. The etching process can be an anisotropic etching process, such as a reactive ion etching process, and / or can be an isotropic etching process, such as a wet etching process. The duration of the etching process can be selected such that portions 140B of the first dielectric material layer 140 covering each array of underlying bonding pads 166 are removed by the etching process, and physically expose top surfaces of the underlying bonding pads 166. The underlying bonding pads 166 are vertically recessed relative to the first bonding pad 168, if present. Thus, the underlying bonding pads 166 are referred to hereinafter as recessed bonding pads.

[0106] A void laterally surrounded by an upper portion of the first dielectric material layer 140 exists above each array of lower-tier bond pads 166. Each region comprising a void over a respective array of lower-tier bond pads 166 (i.e., an array of recessed bond pads) is referred to herein as a dimple region 167. As used herein, a dimple region refers to a recessed region having a lateral dimension of at least 1 mm along two perpendicular horizontal directions, such as the first horizontal direction hd1 and the second horizontal direction hd2. A depth of each dimple region 167 can be at least a height difference between a horizontal plane comprising a top surface of the first dielectric material layer 140 (and a top surface of the first bond pads 168, if present) and a horizontal plane comprising a top surface of the lower-tier bond pads 166, and less than a height difference between a horizontal plane comprising a top surface of the first dielectric material layer 140 (and a top surface of the first bond pads 168, if present) and a horizontal plane comprising a bottom surface of the lower-tier bond pads 166. In general, a dimple region 167 can be formed by vertically recessing a portion of the first upper-tier dielectric material layer 140B that overlies an array of lower-tier bond pads 166. A top surface of a buried bond pad (i.e., a lower-tier bond pad 166 as covered by the first dielectric material layer 140) is physically exposed beneath each dimple region 167, and the buried bond pad becomes a recessed bond pad (i.e., a lower-tier bond pad 166 having a physically exposed top surface).

[0107] In one embodiment, sidewalls of at least one of the silicon nitride material pillars (192, 194) and the silicon nitride material strips (182, 184) can be physically exposed to the dimple region 167. In one embodiment, at least one of a first silicon nitride material portion (such as the first silicon nitride material pillar 192 and the first silicon nitride material strip 182) that generates tensile stress and a second silicon nitride material portion (such as the second silicon nitride material pillar 194 and the second silicon nitride material strip 184) that generates compressive stress can have sidewalls that are physically exposed to a cavity of the dimple region 167.

[0108] In one embodiment, the cavity of a recess region 167 is laterally bounded by four sidewalls, one of the first silicon nitride material portions (such as the first silicon nitride material posts 192 and / or the first silicon nitride material strips 182) is physically exposed at one of the four sidewalls, and one of the second silicon nitride material portions (such as the second silicon nitride material posts 194 and / or the second silicon nitride material strips 184) is physically exposed at another of the four sidewalls. In this configuration, a combination of a directional compressive stress and a directional tensile stress can be applied orthogonally about the recess region 167 to compensate for a directional local distortion of the first semiconductor die 100. For example, in one recess region 167, one of the first silicon nitride material posts 192 or the second silicon nitride material posts 194 is exposed to a first sidewall and a second sidewall extending in a first horizontal direction hd1, and the other of the first silicon nitride material posts 192 or the second silicon nitride material posts 194 is exposed to a third sidewall and a fourth sidewall extending in a second horizontal direction hd2.

[0109] In one embodiment, the first semiconductor die 100 can include a plurality of recess regions 167 in which respective recessed horizontal surfaces of the first dielectric material layer 140 are vertically recessed from a horizontal plane including a top surface of the first bonding pad 168. In FIG. 16A In some of the illustrated recess regions 167A, 167D, the first silicon nitride material posts 192 are exposed to a first sidewall and a second sidewall extending in a first horizontal direction hd1, and the second silicon nitride material posts 194 are exposed to a third sidewall and a fourth sidewall extending in a second horizontal direction hd2. FIG. 17A In other of the illustrated recess regions 167B, 167C, the second silicon nitride material posts 194 are exposed to a first sidewall and a second sidewall extending in a first horizontal direction hd1, and the first silicon nitride material posts 192 are exposed to a third sidewall and a fourth sidewall extending in a second horizontal direction hd2.

[0110] Reference is made to FIG. 17B and FIG. 18AFIG. 2B shows a second semiconductor die 200 configured to be bonded to the first semiconductor die 100. The second semiconductor die 200 includes a second substrate 209, second semiconductor devices 220 on the second substrate 209, a second dielectric material layer 240 on the second semiconductor devices 220 and embedded with a subset of second metal interconnect structures 230. The second dielectric material layer 240 can include a second lower-level dielectric material layer embedded with the subset of second metal interconnect structures 230 and proximate to the second substrate 209. Optional second bonding pads 268 can be formed in an upper portion of the second lower-level dielectric material layer. The second bonding pads 268 can be electrically connected to respective nodes of the second semiconductor devices 220. The pattern of the second bonding pads 268, if present, can be a mirror image of the pattern of the first bonding pads 168, if present, of the first semiconductor die 100.

[0111] Subsequently, a second upper-level dielectric material layer can be formed over the second lower-level dielectric material layer and the second bonding pads 268. The second upper-level dielectric material layer and the second lower-level dielectric material layer collectively constitute the second dielectric material layer 240. The second upper-level dielectric material layer can be embedded with another subset of the second metal interconnect structures 230. Additional bonding pads can be formed in an upper portion of the second upper-level dielectric material layer. The additional bonding pads are formed above the second bonding pads 268 and are referred to herein as raised bonding pads 266. The pattern of the raised bonding pads 266 can be a mirror image of the pattern of the lower-level bonding pads 166 (i.e., recessed bonding pads) of the first semiconductor die 100. The height difference between the top surfaces of the second bonding pads 268 and the raised bonding pads 266 in the second semiconductor die 200 can be the same as the height difference between the top surface of the first bonding pads 168 and the lower-level bonding pads 166 (i.e., recessed bonding pads) in the first semiconductor die 100.

[0112] The portions of the second dielectric material layer 240 within the regions of the mirror image of the regions of the un-recessed surface of the first semiconductor die 100 can be vertically recessed by an etching process. A patterned photoresist layer can be employed to define the regions that are to be vertically recessed during the etching process. The etching process can include an anisotropic etching process, such as a reactive ion etching process, or an isotropic etching process, such as a wet etching process. The regions of the un-recessed surface of the first semiconductor die 100 include all regions of the first semiconductor die 100 except for the regions of the recessed regions 167. In other words, the regions of the un-recessed surface of the first semiconductor die 100 include the regions of the topmost surface of the first dielectric material layer 140 and the regions of the silicon nitride material portions (182, 184, 192, 194). Accordingly, in a subsequent bonding process, the regions of the second dielectric material layer 240 that face the regions of the topmost surface of the first dielectric material layer 140 and the regions of the silicon nitride material portions (182, 184, 192, 194) of the first semiconductor die 100 are vertically recessed.

[0113] In one embodiment, the first semiconductor devices 120 in the first semiconductor die 100’ can include an array of three-dimensional memory elements, and the second semiconductor devices 220 in the second semiconductor die 200’ can include peripheral circuitry configured to control operation of the array of three-dimensional memory elements in the first semiconductor die 100’. In general, the first semiconductor devices 120 and the second semiconductor devices 220 can be selected to provide complementary functionality, such that the bonded assembly of the first semiconductor die 100 and the second semiconductor die 200 provides enhanced functionality or full functionality that is not provided by the first semiconductor die 100 alone or the second semiconductor die 200 alone.

[0114] Each un-recessed portion of the second dielectric material layer 240 constitutes a mesa portion that protrudes upward from the second substrate 209. The horizontal cross-sectional shape of each mesa portion of the second semiconductor die 200 can be the same as or smaller than the horizontal cross-sectional shape of the corresponding recessed region 167 into which the mesa portion is to be subsequently inserted. The raised bonding pads 266 are located at planar surfaces of the mesa portions. In general, each mesa portion in the second dielectric material layer 240 can be formed by recessing a respective peripheral portion of the second dielectric material layer 240 around the mesa portion. The patterned photoresist layer can be subsequently removed, for example, by ashing.

[0115] REFERENCE FIG. 18B AND FIG. 14AThe second semiconductor die 200 can be disposed over the first semiconductor die 100 such that each second bonding pad 268, if present, faces a respective one of the first bonding pads 168, if present, and each raised bonding pad 266 faces a respective one of the recessed bonding pads (i.e., lower-level bonding pads 166). The second semiconductor die 200 can be bonded to the first semiconductor die 100 with a mesa portion of the second semiconductor die 200 located within a respective pocket region 167 of the first semiconductor die 100.

[0116] An induced metal-to-metal bonding can be performed to bond each mating pair of the first bonding pads 168 and the second bonding pads 268 and each mating pair of the recessed bonding pads (i.e., lower-level bonding pads 166) and the raised bonding pads 266. For example, an annealing process can be performed in a temperature range of 150 degrees Celsius to 400 degrees Celsius. Optionally, a dielectric-to-dielectric bonding such as oxide-to-oxide bonding can be induced between the first dielectric material layer 140 and the second dielectric material layer 240. In this case, the annealing temperature can be in a range of 250 degrees Celsius to 500 degrees Celsius. A bonded assembly 1000 of the first semiconductor die 100 and the second semiconductor die 200 can be formed. FIG. 14B and FIG. 19A In the processing steps of FIGS. 1 1 A and 1 1 B, local adjustment of stress can be performed by selectively converting a subset of the compressively stressed silicon nitride material strips 182 to tensile stressed silicon nitride material strips 184 and by converting a subset of the compressively stressed silicon nitride material posts 192 to tensile stressed silicon nitride material posts 194, thereby reducing warpage and distortion of the first semiconductor die 100.

[0117] In one embodiment, the first semiconductor die 100 can include at least one pocket region 167 in which a recessed horizontal surface of the first dielectric material layer 140 is vertically recessed from a horizontal bonding interface between the first bonding pads 168 and the second bonding pads 268 to provide a cavity in the pocket region 167, and the second semiconductor die 200 includes at least one mesa portion that protrudes away from the second substrate 209 and at least partially fills the cavity in the pocket region 167. The first semiconductor die 100 can include a recessed bonding pad (i.e., lower-level bonding pad 166) at the recessed horizontal surface, and the second semiconductor die 200 includes a raised bonding pad 266 at a planar surface of the mesa portion and bonded to a respective one of the recessed bonding pads.

[0118] In one embodiment, the first semiconductor die 100 includes a plurality of recessed regions 167 in which a respective recessed horizontal surface of the first dielectric material layer 140 is vertically recessed from a horizontal bonding interface between the first bonding pads 168 and the second bonding pads 268 toward the first substrate 109 to provide a plurality of cavities located in the respective recessed regions 167, and the second semiconductor die 200 can include a plurality of mesa portions that protrude away from the second substrate 209 and at least partially fill respective ones of the plurality of cavities in the respective recessed regions 167.

[0119] Referring to FIG. 19B and FIG. 18A , an alternative embodiment of the second exemplary structure after forming the bonded assembly of the first semiconductor die 100 and the plurality of second semiconductor dies 200 is shown in accordance with a second embodiment of the present disclosure. In the alternative embodiment, FIG. 18B and FIG. 20A the second semiconductor dies 200 in the structure of

[0120] In one embodiment, the first semiconductor die 100 includes a plurality of recessed regions 167 in which a respective recessed horizontal surface of the first dielectric material layer 140 is vertically recessed from a horizontal bonding interface between the first bonding pads 168 and the second bonding pads 268 toward the first substrate 109 to provide a plurality of cavities located in the respective recessed regions 167, and the second semiconductor die 200 can include a plurality of mesa portions that protrude away from the second substrate 209 and at least partially fill respective ones of the plurality of cavities in the respective recessed regions 167.

[0121] In the alternative embodiment, a plurality of first semiconductor dies 100 can be bonded to a single second semiconductor die 200. In other words, the first and second semiconductor dies are interchangeable in terms of which die includes the recessed regions and which die includes the mesa portions. Likewise, the silicon nitride strips and / or pillars under compression and / or tension stress can be used in the first semiconductor die 100, the second semiconductor die 200, or both the first and second semiconductor dies.

[0122] Referring to FIG. 20B andFIG. 19A FIG. 3 shows another alternative embodiment of the second exemplary structure after forming the bonded assembly of the first semiconductor die 100 and the plurality of second semiconductor dies 200 according to the second embodiment of the present disclosure. In this alternative embodiment, FIG. 19B and ​ The second semiconductor dies 200 in the structure of FIG. 3 only include the mesa portions. In other words, the recessed portions in the second dielectric material layer 240 and the second bonding pads 268 are omitted in the second semiconductor dies 200. Likewise, the first bonding pads 168 in the first semiconductor die 100 can also be omitted.

[0123] The combination of the recessed regions 167 and the mesa portions can reduce the overall thickness of the bonded assembly. The first substrate 109 and the second substrate 209 can be thinned from the backside, for example, by grinding, polishing, anisotropic etching processes, and / or isotropic etching processes to thin the bonded assembly. The overall thickness of the bonded assembly after thinning the first substrate 109 and the second substrate 209 can be in the range of 30 microns to 100 microns.

[0124] The various embodiments of the present disclosure can be used to provide local stress compensation and reduce warpage and distortion of each first semiconductor die 100. The arrangement of compressive stress elements, such as the compressive stress silicon nitride material strips 182 and the compressive stress silicon nitride material pillars 192, and tensile stress elements, such as the tensile stress silicon nitride material strips 184 and the tensile stress silicon nitride material pillars 194, can be used to compensate for the distortion introduced to the top surface of the first dielectric material layer 140 due to the stress generated by the elements within the first semiconductor device 120. The flatness of the bonding surface of the first semiconductor die 100, such as the top surface of the first dielectric material layer 140 or the bottom recessed 167 surface, can be improved by using the complementary stress compensation elements in the first semiconductor die 100. Furthermore, the stress compensation elements of the embodiments of the present disclosure remain within the bonded assembly. Thus, the stress compensation elements remain in the operational semiconductor chip and provide enhanced reliability to the bonding surface through stress compensation.

[0125] While specific embodiments are mentioned herein, it is understood that the present disclosure is not limited thereto. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. Such equivalents are considered to be within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not alternatives to each other. Unless explicitly stated otherwise, the word "comprising" or "including" envisages all embodiments in which the word "consisting essentially of or the word "consisting of is substituted for the word "comprising" or "including". Embodiments are shown in the present disclosure using specific structures and / or configurations, it is understood that the present disclosure can be practiced in any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise deemed impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A semiconductor structure comprising a first semiconductor die, wherein the first semiconductor die comprises: a first substrate; a first semiconductor device, wherein the first semiconductor device is an array of three-dimensional memory elements, the first semiconductor device being located above the first substrate; a first dielectric material layer, the first dielectric material layer being located above the first semiconductor device; a first silicon nitride material portion, the first silicon nitride material portion being embedded within an upper portion of the first dielectric material layer and imparting tensile stress to respective surrounding material portions; and a second silicon nitride material portion, the second silicon nitride material portion being embedded within the upper portion of the first dielectric material layer and imparting compressive stress to respective surrounding material portions; wherein the semiconductor structure further comprises a first bonding pad embedded in the upper portion of the first dielectric material layer; wherein the first silicon nitride material portion comprises a strip extending laterally along a first horizontal direction; wherein the second silicon nitride material portion comprises a strip extending laterally along a second horizontal direction different from the first horizontal direction; wherein a top surface of the first silicon nitride material portion and a top surface of the second silicon nitride material portion are within a horizontal plane comprising a top surface of the first dielectric material layer; and wherein a top surface of the first bonding pad is located in the horizontal plane comprising the top surface of the first dielectric material layer.

2. The semiconductor structure of claim 1, wherein the first silicon nitride material portion has a higher hydrogen concentration than the second silicon nitride material portion.

3. The semiconductor structure of claim 1, wherein: at least one of the first silicon nitride material portion and the second silicon nitride material portion has a lateral dimension greater than a maximum lateral dimension of each of the first bonding pads; and each of the first silicon nitride material portion and the second silicon nitride material portion has a depth greater than a vertical thickness of the first bonding pads.

4. The semiconductor structure of claim 1, further comprising a second semiconductor die, the second semiconductor die comprising: a second substrate; a second semiconductor device, the second semiconductor device being located above the second substrate; a second dielectric material layer, the second dielectric material layer being located above the second semiconductor device; and a second bonding pad, the second bonding pad being embedded in the second dielectric material layer and bonded to a respective one of the first bonding pads.

5. The semiconductor structure of claim 4, wherein the second semiconductor die further comprises: a third silicon nitride material portion, the third silicon nitride material portion being embedded within an upper portion of the second dielectric material layer and imparting tensile stress to respective surrounding material portions; and a fourth silicon nitride material portion, the fourth silicon nitride material portion being embedded within the upper portion of the second dielectric material layer and imparting compressive stress to respective surrounding material portions.

6. The semiconductor structure of claim 4, wherein: the first semiconductor die includes a recessed land pad at the recessed horizontal surface; and the second semiconductor die includes a raised land pad at a planar surface of the mesa portion and bonded to a respective one of the recessed land pads.

7. The semiconductor structure of claim 6, wherein: the first semiconductor die includes a recessed land pad at the recessed horizontal surface; and the second semiconductor die includes a raised land pad at a planar surface of the mesa portion and bonded to a respective one of the recessed land pads.

8. The semiconductor structure of claim 6, wherein: the cavity of the recessed region is laterally defined by four sidewalls; one of the first silicon nitride material portions is physically exposed at one of the four sidewalls; and one of the second silicon nitride material portions is physically exposed at another one of the four sidewalls.

9. The semiconductor structure of claim 4, wherein: the first semiconductor die includes a plurality of recessed regions, with respective recessed horizontal surfaces of the first dielectric material layer vertically recessed from a horizontal bonding interface between the first and second bonding pads toward the first substrate to provide a plurality of cavities; the second semiconductor die includes a mesa portion that protrudes away from the second substrate and at least partially fills one of the plurality of cavities; and an additional semiconductor die is bonded to the first semiconductor die at a respective one of the recessed horizontal surfaces of the first dielectric material layer in a cavity other than the cavity present in the second semiconductor die.

10. The semiconductor structure of claim 1, further comprising a plurality of second semiconductor dies each including a second substrate, a second semiconductor device above the second substrate, a second dielectric material layer above the second semiconductor device, and a second bonding pad embedded in the second dielectric material layer; wherein: the first semiconductor die further includes a recessed region in each of which a recessed horizontal surface of the first dielectric material layer is vertically recessed to provide a cavity, and a recessed first bonding pad at the recessed horizontal surface; the plurality of second semiconductor dies are in respective ones of the recessed regions in the first semiconductor die; and the second bonding pads are bonded to respective ones of the recessed first bonding pads.

11. The semiconductor structure of claim 10, wherein: the first silicon nitride material portions include both first silicon nitride strips and first silicon nitride pillars; and the second silicon nitride material portions include both second silicon nitride strips and second silicon nitride pillars.

12. A method of forming a semiconductor structure, comprising: forming a first semiconductor device over a first substrate; forming a first dielectric material layer over the first semiconductor device, wherein the first semiconductor device is an array of three-dimensional memory elements; forming vertical recesses in the first dielectric material layer, wherein each of the vertical recesses extends vertically from a topmost surface of the first dielectric material layer toward the first substrate; forming portions of silicon nitride material in each of the vertical recesses; and locally irradiating a second subset of the portions of silicon nitride material with a laser beam, wherein a first subset of the portions of silicon nitride material that are not irradiated with the laser beam comprises first portions of silicon nitride material that impart a tensile stress to respective surrounding material portions, and the second subset of the portions of silicon nitride material that are irradiated with the laser beam comprises second portions of silicon nitride material that impart a compressive stress to respective surrounding material portions; the method further comprising forming first bonding pads in the first dielectric material layer, wherein top surfaces of the first bonding pads are formed within a horizontal plane that includes the topmost surface of the first dielectric material layer; wherein the first portions of silicon nitride material comprise strips that extend laterally along a first horizontal direction; wherein the second portions of silicon nitride material comprise strips that extend laterally along a second horizontal direction that is different from the first horizontal direction; wherein top surfaces of the first portions of silicon nitride material and the second portions of silicon nitride material are within a horizontal plane that includes the topmost surface of the first dielectric material layer.

13. The method of claim 12, wherein: locally irradiating the second subset of the portions of silicon nitride material with the laser beam releases hydrogen gas from the second portions of silicon nitride material; and the first portions of silicon nitride material have a higher hydrogen concentration than the second portions of silicon nitride material.

14. The method of claim 12, wherein: the first bonding pads are formed in regions in which the portions of silicon nitride material are not present after the step of locally irradiating the second subset of the portions of silicon nitride material with the laser beam; and at least one of the portions of silicon nitride material has a lateral dimension that is greater than a maximum lateral dimension of each of the first bonding pads, and has a depth that is greater than a vertical thickness of the first bonding pads.

15. The method of claim 12, further comprising: providing a second semiconductor die that includes a second substrate, a second semiconductor device on the second substrate, a second dielectric material layer on the second semiconductor device, and second bonding pads embedded in the second dielectric material layer; and bonding the second bonding pads to the first bonding pads.

16. The method of claim 15, further comprising: forming a pocket region in the first dielectric material layer by vertically recessing a portion of the first dielectric material layer; forming the mesa portion in the second dielectric material layer by recessing a peripheral portion of the second dielectric material layer around the mesa portion, wherein the second semiconductor die is bonded to a first semiconductor die, wherein the first semiconductor die includes the first substrate, the first semiconductor device on the first substrate, the first dielectric material layer on the first semiconductor device, and the first bonding pad embedded in the first dielectric material layer, wherein the mesa portion is within the recessed region; forming a buried bonding pad within the first dielectric material layer, wherein a top surface of the buried bonding pad is covered by an upper region of the first dielectric material layer; physically exposing a top surface of the buried bonding pad beneath the recessed region, wherein the buried bonding pad becomes a recessed bonding pad; forming a raised bonding pad in the mesa portion of the second dielectric material layer; and bonding the raised bonding pad to the recessed bonding pad.

17. The method of claim 16, wherein: the first silicon nitride material portion includes both a first silicon nitride strip and a first silicon nitride pillar; and the second silicon nitride material portion includes both a second silicon nitride strip and a second silicon nitride pillar.

18. The method of claim 15, wherein the second semiconductor die further includes: a third silicon nitride material portion embedded within an upper portion of the second dielectric material layer and imparting a tensile stress to a respective surrounding material portion; and a fourth silicon nitride material portion embedded within the upper portion of the second dielectric material layer and imparting a compressive stress to a respective surrounding material portion. ​ ​

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