Pixel sensor circuit and driving method thereof, detection panel and electronic device

Abstract

A pixel sensing circuit includes: a signal generating subcircuit, a reset subcircuit, an amplifying subcircuit and a reading subcircuit. The reset subcircuit is connected to a reset signal line, a first power line and a first node, and is configured to provide a signal of the first power line to the first node under the control of the reset signal line. The signal generating subcircuit is connected to a bias signal line and a first node, and is configured to detect a light signal and convert the detected light signal into an electrical signal. The amplifying subcircuit is connected to a second power line, a first node and a second node, and is configured to provide an amplified electrical signal to the second node according to a signal provided by the second power line under the control of the first node. The reading subcircuit is connected to a scanning signal line, a second node and a signal reading line, and is configured to output an amplified electrical signal to the signal reading line under the control of the scanning signal line.

Description

Technical Field

[0001] This article relates to but is not limited to the field of detection technology, and in particular to a pixel sensor circuit and a driving method thereof, a detection panel and an electronic device. Background Art

[0002] X-ray (X-Ray) imaging technology is widely used in industrial non-destructive testing, container scanning, circuit board inspection, medical, security, industry and other fields, and has broad application prospects. Traditional X-Ray imaging technology belongs to analog signal imaging, with low resolution and poor image quality. X-ray digital imaging technology (Digital Radiography, DR) appeared in the late 1990s. It uses X-ray flat-panel detectors to directly convert X-ray images into digital images. Because the converted digital images are clear, high in resolution, and easy to save and transmit, it has become a hot topic of current research. According to different structures, X-ray flat-panel detectors are divided into direct conversion type (Direct DR) and indirect conversion type (Indirect DR). Among them, the indirect conversion X-ray flat-panel detector technology is relatively mature, with relatively low cost, high detective quantum efficiency (Detective Quantum Efficiency, DQE), good reliability and other advantages, and has been widely developed and applied. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a pixel sensor circuit and a driving method thereof, a detection panel, and an electronic device.

[0005] On the one hand, the embodiment of the present disclosure provides a pixel sensor circuit, including: a signal generation subcircuit, a reset subcircuit, an amplification subcircuit and a reading subcircuit. The reset subcircuit is connected to a reset signal line, a first power line and a first node, and is configured to provide a signal of the first power line to the first node under the control of the reset signal line; the signal generation subcircuit is connected to a bias signal line and a first node, and is configured to detect an optical signal and convert the detected optical signal into an electrical signal; the amplification subcircuit is connected to a second power line, a first node and a second node, and is configured to provide an amplified electrical signal to the second node according to a signal provided by the second power line under the control of the first node; the reading subcircuit is connected to a scan signal line, a second node and a signal reading line, and is configured to output an amplified electrical signal to the signal reading line under the control of the scan signal line.

[0006] In some exemplary embodiments, the effective level signal provided by the first power line and the effective level signal provided by the second power line have the same polarity and different durations.

[0007] In some exemplary embodiments, a voltage value of the effective level signal provided by the second power line is greater than or equal to a voltage value of the effective level signal provided by the first power line.

[0008] In some exemplary embodiments, the scan signal line and the second power line provide the same pulse signal timing.

[0009] In some exemplary embodiments, the starting time of the valid level signal provided by the second power line is earlier than the starting time of the valid level signal provided by the scan signal line, and the ending time of the valid level signal provided by the second power line is not earlier than the ending time of the valid level signal provided by the scan signal line.

[0010] In some exemplary embodiments, the reset subcircuit includes: a reset transistor; the control electrode of the reset transistor is connected to the reset signal line, the first electrode of the reset transistor is connected to the first power line, and the second electrode of the reset transistor is connected to the first node. The signal generation subcircuit at least includes: a photoelectric converter; the first electrode of the photoelectric converter is connected to the first node, and the second electrode of the photoelectric converter is connected to the bias signal line. The amplification subcircuit includes: an amplification transistor, the control electrode of the amplification transistor is connected to the first node, the first electrode of the amplification transistor is connected to the second power line, and the second electrode of the amplification transistor is connected to the second node. The reading subcircuit includes: a reading transistor, the control electrode of the reading transistor is connected to the scanning signal line, the first electrode of the reading transistor is connected to the second node, and the second electrode of the reading transistor is connected to the signal reading line.

[0011] In some exemplary embodiments, the signal generating subcircuit further includes: a storage capacitor, a first electrode of the storage capacitor is connected to the first node, and a second electrode of the storage capacitor is connected to the bias signal line.

[0012] On the other hand, an embodiment of the present disclosure provides a driving method for a pixel sensor circuit, which is applied to the pixel sensor circuit as described above, and the driving method includes: the reset subcircuit provides a signal of a first power line to a first node under the control of a reset signal line; the signal generation subcircuit detects an optical signal and converts the detected optical signal into an electrical signal; the amplification subcircuit provides an amplified electrical signal to a second node according to a signal provided by a second power line under the control of an electrical signal generated by the signal generation subcircuit; and the reading subcircuit outputs the amplified electrical signal to a signal reading line under the control of a scanning signal line.

[0013] On the other hand, the embodiment of the present disclosure provides a detection panel, comprising: a detection area and a peripheral area located outside the detection area; the detection area comprises a plurality of pixel sensing circuits as described above arranged on the substrate; the peripheral area is at least provided with a power driver, and the power driver is configured to be connected to the pixel sensing circuit via a second power line.

[0014] In some exemplary embodiments, the power driver includes at least one of: an array substrate row driver (GOA) circuit disposed on the base substrate, a surface mount chip (COG) disposed on the base substrate, and an array off-line wiring (WOA) disposed on the base substrate.

[0015] In some exemplary embodiments, the peripheral area is provided with at least one Y-PCB, and the power driver is provided on the Y-PCB.

[0016] In some exemplary embodiments, the peripheral area is further provided with a gate driver configured to be connected to the pixel sensing circuit via a reset signal line and a scan signal line. The power driver and the gate driver are respectively provided on different Y-PCBs; or, the power driver and the gate driver are provided on the same Y-PCB.

[0017] In some exemplary embodiments, the peripheral area is further provided with an X-PCB, and the power driver is provided on the X-PCB.

[0018] On the other hand, an embodiment of the present disclosure provides an electronic device, comprising the detection panel as described above.

[0019] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shape and size of one or more components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0021] Figure 1 is a schematic diagram of a pixel sensor circuit according to at least one embodiment of the present disclosure;

[0022] Figure 2 is an equivalent circuit diagram of a pixel sensor circuit according to at least one embodiment of the present disclosure;

[0023] Figure 3 is another equivalent circuit diagram of a pixel sensor circuit according to at least one embodiment of the present disclosure;

[0024] Figure 4 for Figure 2 or Figure 3 An operation timing diagram of the pixel sensing circuit shown;

[0025] Figure 5 for Figure 2 or Figure 3 Another working timing diagram of the pixel sensing circuit shown;

[0026] Figure 6 A schematic diagram of a detection panel according to at least one embodiment of the present disclosure;

[0027] Figure 7 A working timing diagram of a detection panel of at least one embodiment of the present disclosure;

[0028] Figure 8 Another working timing diagram of the detection panel of at least one embodiment of the present disclosure;

[0029] Fig. 9 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure;

[0030] Fig.10 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure;

[0031] Fig.11 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure;

[0032] Fig.12 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure;

[0033] Fig.13 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure;

[0034] Fig.14 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0036] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0037] The ordinal numbers such as "first", "second", and "third" in the present disclosure are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present disclosure means a quantity of two or more.

[0038] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0039] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal connection of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transfer electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0040] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0041] In the present disclosure, in order to distinguish the two electrodes of the transistor other than the gate, one of the electrodes is called the first electrode and the other electrode is called the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate of the transistor is called a control electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0042] In the present disclosure, the effective level signal includes a level signal that turns on a transistor. For example, the effective level signal that turns on a P-type transistor is a low level signal, and the effective level signal that turns on an N-type transistor is a high level signal.

[0043] Generally speaking, the imaging principle of a simple indirect conversion flat panel detector (FPD) is as follows: X-rays irradiate the interior of the flat panel detector, first passing through a scintillator, which absorbs the X-rays and converts them into visible light. The visible light then enters the detection panel, and the pixel sensor circuit array on the detection panel converts the visible light generated by the scintillator into an electrical signal, which is amplified and converted into a digital signal through an analog-to-digital converter to obtain a displayed image.

[0044] The embodiments of the present disclosure provide a pixel sensor circuit and a driving method thereof, a detection panel and an electronic device, which can reduce the shot noise of the pixel sensor circuit, improve the signal-to-noise ratio, and improve the image quality of the detection panel.

[0045] Figure 1 FIG. 1 is a schematic diagram of a pixel sensor circuit according to at least one embodiment of the present disclosure. Figure 1 As shown, the pixel sensing circuit of this exemplary embodiment includes: a signal generating subcircuit, a reset subcircuit, an amplifying subcircuit and a reading subcircuit. The reset subcircuit is connected to the reset signal line RST, the first power line VDD1 and the first node N1, and is configured to provide the signal of the first power line VDD1 to the first node N1 under the control of the reset signal line RST. The signal generating subcircuit is connected to the bias signal line BIAS and the first node N1, and is configured to detect the optical signal and convert the detected optical signal into an electrical signal. The amplifying subcircuit is connected to the second power line VDD2, the first node N1 and the second node N2, and is configured to provide the amplified electrical signal to the second node N2 according to the signal provided by the second power line VDD2 under the control of the first node N1. The reading subcircuit is connected to the scanning signal line GL, the second node N2 and the signal reading line RL, and is configured to output the amplified electrical signal to the signal reading line RL under the control of the scanning signal line GL.

[0046] The pixel sensing circuit provided in this exemplary embodiment supports providing different power supply signals to the reset sub-circuit and the amplifying sub-circuit by separately connecting the reset sub-circuit and the amplifying sub-circuit to different power supply lines, thereby reducing the shot noise of the pixel sensing circuit and improving the signal-to-noise ratio.

[0047] In some exemplary embodiments, the polarity of the effective level signal provided by the first power line and the effective level signal provided by the second power line are the same, and the duration is different. For example, the effective level signals provided by the first power line and the second power line are both high-level signals, the first power line can continuously provide a high-level signal, and the second power line periodically provides a high-level signal, that is, the second power line provides a pulse signal with an effective voltage of a high level. However, this embodiment is not limited to this. In this exemplary embodiment, by providing different power signals to the reset subcircuit and the amplification subcircuit, the shot noise of the pixel sensor circuit can be reduced and the signal-to-noise ratio can be improved.

[0048] In some exemplary embodiments, the voltage value of the effective level signal provided by the second power line is greater than or equal to the voltage value of the effective level signal provided by the first power line. However, this embodiment is not limited to this. In this exemplary embodiment, by increasing the voltage value of the effective level signal of the second power line, the amplification gain of the amplification sub-circuit can be enhanced, and a better noise suppression effect can be achieved on the wiring and the readout processing circuit, thereby improving the signal-to-noise ratio.

[0049] In some exemplary embodiments, the scanning signal line and the second power line provide the same pulse signal timing. In this exemplary embodiment, by setting the pulse signal timing provided by the second power line to be the same as the pulse signal timing provided by the scanning signal line, the second power line can be used to provide an effective level signal to the amplifying subcircuit only when the reading subcircuit outputs the amplified electrical signal to the signal reading line, thereby avoiding the generation of shot noise due to the continuous provision of an effective level signal to the amplifying subcircuit through the second power line, and improving the signal-to-noise ratio of the pixel transfer circuit.

[0050] In some exemplary embodiments, the start time of the effective level signal provided by the second power line is earlier than the start time of the effective level signal provided by the scan signal line, and the end time of the effective level signal provided by the second power line is not earlier than the end time of the effective level signal provided by the scan signal line. In this exemplary embodiment, by setting the start time of the effective level signal provided by the second power line to be earlier than the start time of the effective level signal provided by the scan signal line, it is avoided that the start time of the effective level signal provided by the second power line and the scan signal line is the same to generate transient current, thereby further reducing noise and improving the signal-to-noise ratio.

[0051] Figure 2FIG. 1 is an equivalent circuit diagram of a pixel sensor circuit according to at least one embodiment of the present disclosure. Figure 2 As shown, the pixel sensing circuit of this exemplary embodiment includes: a signal generating subcircuit, a reset subcircuit, an amplifying subcircuit and a reading subcircuit. The signal generating subcircuit includes: a photoelectric converter PD. The first electrode of the photoelectric converter PD is connected to the first node N1, and the second electrode of the photoelectric converter PD is connected to the bias signal line BIAS. The reset subcircuit includes: a reset transistor Trst. The control electrode of the reset transistor Trst is connected to the reset signal line RST, the first electrode of the reset transistor Trst is connected to the first power line VDD1, and the second electrode of the reset transistor Trst is connected to the first node N1. The amplifying subcircuit includes: an amplifying transistor Tsf. The control electrode of the amplifying transistor Tsf is connected to the first node N1, the first electrode of the amplifying transistor Tsf is connected to the second power line VDD2, and the second electrode of the amplifying transistor Tsf is connected to the second node N2. The reading subcircuit includes: a reading transistor Tsel. The control electrode of the reading transistor Tsel is connected to the scanning signal line GL, the first electrode of the reading transistor Tsel is connected to the second node N2, and the second electrode of the reading transistor Tsel is connected to the signal reading line RL.

[0052] Figure 3 FIG. 1 is another equivalent circuit diagram of a pixel sensor circuit according to at least one embodiment of the present disclosure. Figure 3 As shown, the pixel sensing circuit of this exemplary embodiment includes: a signal generation subcircuit, a reset subcircuit, an amplification subcircuit and a reading subcircuit. The signal generation subcircuit includes: a storage capacitor Cst and a photoelectric converter PD. The first electrode of the storage capacitor Cst is connected to the first node N1, and the second electrode of the storage capacitor Cst is connected to the bias signal line BIAS. The first electrode of the photoelectric converter PD is connected to the first node N1, and the second electrode of the photoelectric converter PD is connected to the bias signal line BIAS. The reset subcircuit includes: a reset transistor Trst. The control electrode of the reset transistor Trst is connected to the reset signal line RST, the first electrode of the reset transistor Trst is connected to the first power line VDD1, and the second electrode of the reset transistor Trst is connected to the first node N1. The amplification subcircuit includes: an amplification transistor Tsf. The control electrode of the amplification transistor Tsf is connected to the first node N1, the first electrode of the amplification transistor Tsf is connected to the second power line VDD2, and the second electrode of the amplification transistor Tsf is connected to the second node N2. The reading subcircuit includes: a reading transistor Tsel. A control electrode of the read transistor Tsel is connected to the scanning signal line GL, a first electrode of the read transistor Tsel is connected to the second node N2, and a second electrode of the read transistor Tsel is connected to the signal read line RL.

[0053] In some exemplary embodiments, the photoelectric converter may be a PIN junction photodiode. However, this embodiment is not limited thereto. In some examples, the photoelectric converter may use other devices that implement photoelectric conversion, such as a pinned diode.

[0054] In this exemplary embodiment, Figure 2 and Figure 3 Some exemplary structures of the reset subcircuit, the amplification subcircuit, the reading subcircuit and the signal generation subcircuit are shown in FIG. It is easy for those skilled in the art to understand that the implementation of the reset subcircuit, the amplification subcircuit, the reading subcircuit and the signal generation subcircuit is not limited to this, as long as its functions can be achieved.

[0055] Below Figure 3 As an example, the reset transistor Trst, the amplifying transistor Tsf and the reading transistor Tsel shown in the figure are all N-type transistors. Figure 3 The working process of the pixel sensing circuit shown further illustrates the technical solution of the embodiment of the present disclosure. Figure 4 for Figure 2 or Figure 3 The working timing diagram of the pixel sensing circuit is shown in FIG. Figure 3 and Figure 4 As shown, the pixel sensing circuit of this exemplary embodiment includes 3 transistor units (i.e., reset transistor Trst, amplifying transistor Tsf, and reading transistor Tsel), 1 photodiode PD, 1 capacitor unit (i.e., storage capacitor Cst), 3 input terminals (i.e., reset signal line RST, scanning signal line GL, bias signal line BIAS), 1 output terminal (i.e., signal reading line RL), and 2 power supply terminals (i.e., first power supply line VDD1, second power supply line VDD2). Among them, the first power supply line VDD1 continuously provides a high-level signal, and the second power supply line VDD2 periodically provides a high-level signal. The polarity of the effective level signal provided by the first power supply line VDD1 and the second power supply line VDD2 can be set according to the type of transistor and the gate potential of the transistor. This embodiment is not limited to this.

[0056] The operation process of the pixel sensor circuit of this exemplary embodiment includes the following stages.

[0057] In the first stage S1, ie, the reset stage, the reset signal line RST provides a high level signal, the scanning signal line GL provides a low level signal, the reset transistor Trst is turned on, the level signal of the first node N1 is reset, and the reading transistor Tsel is turned off. The photoelectric converter PD is in a no-light state.

[0058] In the second stage S2, i.e. the integration stage, the reset signal line RST provides a low level signal, the scan signal line GL provides a low level signal, the reset transistor Trst is turned off, and the read transistor Tsel is turned off. The photoelectric converter PD generates an electrical signal in response to the received optical signal to change the level signal of the first node N1.

[0059] In the third stage S3, i.e., the readout stage, the reset signal line RST provides a low level signal, the scanning signal line GL provides a high level signal, the reset transistor Trst is turned off, and the read transistor Tsel is turned on. Under the control of the first node N1, the amplifier transistor Tsf provides an amplified electrical signal to the second node N2 according to the signal provided by the second power line VDD2. The read transistor Tsel is turned on and provides the electrical signal amplified by the amplifier transistor Tsf to the signal read line RL.

[0060] In this exemplary embodiment, in different stages, the first power line VDD1 continuously provides a high-level signal, while the second power line VDD2 provides a valid level signal only in the readout stage (i.e., the third stage S3), thereby avoiding the weak leakage current generated by the amplifying transistor in the non-readout stage from being read as shot noise, thereby reducing noise and improving the signal-to-noise ratio.

[0061] Figure 5 for Figure 2 or Figure 3 Another working timing diagram of the pixel sensing circuit shown in FIG. Figure 5 As shown, in this exemplary embodiment, the start time of the effective level signal of the second power line VDD2 is earlier than the start time of the effective level signal provided by the scan signal line GL, and the end time of the effective level signal provided by the second power line VDD2 is the same as the end time of the effective level signal provided by the scan signal line GL. However, this embodiment is not limited to this. For example, the end time of the effective level signal of the second power line may be later than the end time of the effective level signal provided by the scan signal line.

[0062] Compared to Figure 4 As shown in the working timing diagram, in this exemplary embodiment, the starting time of the effective level signal of the second power line is advanced to avoid the effective level signal of the second power line and the effective level signal of the scanning signal line being turned on at the same time to generate transient current, further reduce noise, and thus improve the signal-to-noise ratio.

[0063] For the remaining working stages of this exemplary embodiment, please refer to Figure 4 The description of the embodiment shown is therefore not repeated here.

[0064] At least one embodiment of the present disclosure also provides a driving method for a pixel sensor circuit, which is applied to the pixel sensor circuit as described above, and the driving method includes: a reset subcircuit provides a signal of a first power line to a first node under the control of a reset signal line; a signal generation subcircuit detects an optical signal and converts the detected optical signal into an electrical signal; an amplification subcircuit provides an amplified electrical signal to a second node according to a signal provided by a second power line under the control of an electrical signal generated by the signal generation subcircuit; and a reading subcircuit outputs the amplified electrical signal to a signal reading line under the control of a scanning signal line.

[0065] The description of the driving method of this embodiment can refer to the description of the above embodiment, so it will not be repeated here.

[0066] At least one embodiment of the present disclosure further provides a detection panel, comprising: a detection area and a peripheral area located outside the detection area. The detection area includes a plurality of pixel sensor circuits arranged on a substrate. The peripheral area is at least provided with a power driver, and the power driver is configured to be connected to the pixel sensor circuit through a second power line. The description of the pixel sensor circuit can refer to the description of the above embodiment, so it is not repeated here.

[0067] In some exemplary embodiments, a controller, a gate driver, and a data processor are also provided in the peripheral area. The gate driver is configured to provide a reset signal to the pixel sensing circuit through a reset signal line, and to provide a scan signal to the pixel sensing circuit through a scan signal line. The data controller is configured to read a signal from the pixel sensing circuit through a signal read line. The controller can provide a drive signal to the data processor and the gate driver. Among them, the actions of the gate driver and the data processor can be controlled by the controller, and the controller can provide a drive signal to the data processor so that the data processor processes the electrical signal read from the pixel sensing circuit of the specified row. The gate driver can select the pixel sensing circuit of the specified row to output an electrical signal under the control of the controller.

[0068] The detection panel of this embodiment is described below by means of multiple examples. The pixel sensing circuits in the following examples are the same as those described in the above embodiments, so they will not be described again.

[0069] Figure 6 FIG. 1 is a schematic diagram of a detection panel according to at least one embodiment of the present disclosure. Figure 6 As shown, the detection panel of this exemplary embodiment includes: a detection area and a peripheral area located outside the detection area. A plurality of regularly arranged pixel sensor circuits PL are arranged in the detection area. For example, the plurality of pixel sensor circuits PL can be arranged in an array. For example, the detection area is provided with n*m pixel sensor circuits, where n and m are both positive integers.

[0070] In some exemplary embodiments, Figure 6 As shown, the peripheral area is at least provided with a power driver, a gate driver and a data processor. The data processor is arranged on an X-PCB on one side of the substrate. The data processor can be connected to the pixel sensing circuit of the detection area through a signal reading line to read a signal from the pixel sensing circuit. The gate driver may include: a control circuit and an array substrate row drive (GOA) circuit 11 arranged on the substrate. The control circuit may be arranged on the X-PCB and configured to provide a reset signal to the pixel sensing circuit of the detection area through a reset signal line RST. The X-PCB may be configured to provide an initial signal and a clock signal to the GOA circuit 11. In some examples, the GOA circuit 11 may include a plurality of cascaded first shift register units. Among them, the input end of the first-stage first shift register unit is connected to the initial signal line to receive the initial signal, and the output end of the n-stage first shift register unit is connected to the input end of the n+1-stage first shift register unit. The GOA circuit 11 provides a scan signal to the pixel sensing circuit of the detection area through a scan signal line. For example, the output end of the nth level first shift register unit of the GOA circuit 11 provides a scan signal to the nth row pixel sensor circuit through the scan signal line GL(n). In some examples, the power driver may include: a GOA circuit 12 arranged on a substrate substrate. The X-PCB may be configured to provide an initial signal and a clock signal to the GOA circuit 12. In some examples, the GOA circuit 12 may include a plurality of cascaded second shift register units. Among them, the input end of the first-level second shift register unit is connected to the initial signal line to receive the initial signal, and the output end of the nth-level second shift register unit is connected to the input end of the n+1th-level second shift register unit. The GOA circuit 12 may provide a power signal to the pixel sensor circuit of the detection area through the second power line. For example, the output end of the nth-level second shift register unit of the GOA circuit 12 provides a power signal to the nth row pixel sensor circuit through the second power line VDD2(n). However, this embodiment is not limited to this.

[0071] In some exemplary embodiments, the GOA circuit 12 of the power driver and the GOA circuit 11 of the gate driver may be the same, so that the second power signal generated by the power driver and the scanning signal generated by the gate driver have the same pulse signal timing. The working timing of the detection panel of this exemplary embodiment may be as follows: Figure 7 As shown. Figure 7As shown, in the first stage S1, i.e. the reset stage, the reset transistors of all pixel sensing circuits in the detection area are synchronously turned on to initialize the signal generation subcircuit. In the second stage S2, i.e. the integration stage, the reset transistors and read transistors of all pixel sensing circuits in the detection area are turned off. In the third stage S3, i.e. the readout stage, the readout transistors of the pixel sensing circuits are turned on row by row so that the signals are read out row by row. Among them, the second power line and the scan signal line connected to the pixel sensing circuit of the current readout row provide a valid level signal, while the second power line and the scan signal line connected to the pixel sensing circuits of the remaining unread rows do not provide a valid level signal. By turning off the valid level signal of the second power line of the unread row when reading the signal row by row, the leakage current of the unread row can be reduced, thereby reducing the shot noise generated when the signal is read, and improving the signal-to-noise ratio.

[0072] In some exemplary embodiments, the timing of the pulse signals generated by the GOA circuit 12 of the power driver and the GOA circuit 11 of the gate driver may be different. The working timing of the detection panel of this exemplary embodiment may be as follows: Figure 8 As shown. The starting time of the effective level signal provided by the GOA circuit 12 through the second power line is earlier than the starting time of the effective level signal provided by the GOA circuit 11 through the scanning signal line, and the ending time of the effective level signal provided by the GOA circuit 12 through the second power line is the same as the ending time of the effective level signal provided by the GOA circuit 11 through the scanning signal line. In this exemplary embodiment, by advancing the starting time of the effective level signal of the second power line, transient current can be avoided, thereby further reducing noise and improving the signal-to-noise ratio.

[0073] In some exemplary embodiments, Figure 6 As shown, the GOA circuit 12 of the power driver and the GOA circuit 11 of the gate driver are arranged on opposite sides of the detection area of ​​the substrate, such as the left and right sides. The X-PCB is located on one side of the substrate, such as the upper side or the lower side. However, this embodiment is not limited to this.

[0074] The power driver of this exemplary embodiment is integrated on the substrate using the GOA method, which can reduce the use of external circuits of the detection panel and reduce costs, while saving the area occupied by external circuits, effectively reducing the frame area, and improving the integration of the detection panel.

[0075] Fig. 9 FIG. 2 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure. Fig. 9As shown, the detection panel of this exemplary embodiment includes: a detection area and a peripheral area located outside the detection area. The peripheral area is at least provided with a power driver, a gate driver and a data processor. The data processor can be arranged on an X-PCB on one side of the substrate. The gate driver can include: a surface mounted chip (COG, Chip On Glass) 21 arranged on the substrate. The power driver can include: a COG 22 arranged on the substrate. The X-PCB can provide control signals to the COG 21 and the OCG 22. However, this embodiment is not limited to this.

[0076] The remaining structures and working processes of this exemplary embodiment can be described with reference to Figure 6 The description of the corresponding embodiment has been completed, so it will not be repeated here.

[0077] The power driver of this exemplary embodiment is integrated on the substrate using the COG method, which can reduce the use of external circuits of the detection panel, reduce costs, reduce the size of the detection panel, facilitate miniaturization design, and further reduce noise and improve the signal-to-noise ratio.

[0078] Fig.10 FIG. 2 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure. Fig.10 As shown, the detection panel of this exemplary embodiment includes: a detection area and a peripheral area located outside the detection area. The peripheral area is at least provided with a power driver, a gate driver and a data processor. The data processor can be arranged on an X-PCB on one side of the substrate. The gate driver can include: a control circuit arranged on the X-PCB, an array outer wiring (WOA, Wire On Array) 31 arranged on the substrate substrate, and a gate drive circuit arranged outside the substrate substrate. The gate drive circuit is connected to the pixel sensing circuit through the WOA31, and is configured to provide a scan signal to the pixel sensing circuit of the detection area through the scan signal line GL. The control circuit can be arranged on the X-PCB, and is configured to provide a reset signal to the pixel sensing circuit through the reset signal line RST. The power driver can include: a power drive circuit and a WOA 32 arranged on the substrate substrate. The power drive circuit can be connected to the pixel sensing circuit through the WOA 32, and is configured to provide a power signal to the pixel sensing circuit of the detection area through the second power line VDD2. The X-PCB can provide control signals to the gate drive circuit and the power drive circuit.

[0079] The remaining structures and working processes of this exemplary embodiment can be described with reference to Figure 6 The description of the corresponding embodiment has been completed, so it will not be repeated here.

[0080] Fig.11 FIG. 2 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure. Fig.11 As shown, the detection panel of this exemplary embodiment includes: a detection area and a peripheral area located outside the detection area. The peripheral area is at least provided with a power driver, a gate driver and a data processor. The data processor can be arranged on an X-PCB on one side of the substrate. The gate driver is arranged on a Y-PCB 41, and the power driver is arranged on a Y-PCB 42. Y-PCB 41 and Y-PCB 42 can be located on opposite sides of the substrate, for example, on the left and right sides; the X-PCB is located on one side of the substrate, for example, on the upper side or the lower side. However, this embodiment is not limited to this.

[0081] The remaining structures and working processes of this exemplary embodiment can be described with reference to Figure 6 The description of the corresponding embodiment has been completed, so it will not be repeated here.

[0082] Fig.12 FIG. 2 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure. Fig.12 As shown, the detection panel of this exemplary embodiment includes: a detection area and a peripheral area located outside the detection area. The peripheral area is at least provided with a power driver, a gate driver and a data processor. The data processor can be arranged on an X-PCB on one side of the substrate. The gate driver and the power driver are both arranged on the Y-PCB 51. In some examples, the gate driver and the power driver can be separately arranged at different positions of the Y-PCB 51; or, the gate driver and the power driver can be integrated on the Y-PCB 51. The Y-PCB 51 can be located on one side of the substrate, for example, the left side or the right side; the X-PCB is located on one side of the substrate, for example, the upper side or the lower side. However, this embodiment is not limited to this.

[0083] The remaining structures and working processes of this exemplary embodiment can be described with reference to Figure 6 The description of the corresponding embodiment has been completed, so it will not be repeated here.

[0084] Fig.13 FIG. 2 is another schematic diagram of a detection panel according to at least one embodiment of the present disclosure. Fig.13 As shown, the detection panel of this exemplary embodiment includes: a detection area and a peripheral area located outside the detection area. The peripheral area is at least provided with a power driver, a gate driver and a data processor. The data processor and the power driver are arranged on an X-PCB on one side of the substrate. The gate driver is arranged on a Y-PCB. The Y-PCB can be located on one side of the substrate, for example, the left side or the right side; the X-PCB is located on one side of the substrate, for example, the upper side or the lower side. However, this embodiment is not limited to this.

[0085] The remaining structures and working processes of this exemplary embodiment can be described with reference to Figure 6 The description of the corresponding embodiment has been completed, so it will not be repeated here.

[0086] The above structures provided in the embodiments of the present disclosure are only some exemplary structures. In some examples, the above structures can be combined in the same manner. For example, the scan drive circuit can be provided on the substrate substrate in a COG manner, and the power drive circuit can be provided on the substrate substrate in a GOA manner. However, this embodiment is not limited to this.

[0087] The detection panel provided in this embodiment controls the effective level signal of the second power line of the pixel sensor circuit and the effective level signal of the first power line separately, and turns off the effective level signal of the second power line of the unread line in the line-by-line reading, so as to reduce the leakage current of the unread line to reduce the shot noise generated when the signal is read, thereby reducing the noise, improving the signal-to-noise ratio, and improving the display quality. Moreover, by controlling the effective level signal of the second power line separately, the effective level signal of the second power line can be improved, thereby increasing the amplification gain of the amplifying transistor, improving the signal-to-noise ratio, and improving the display quality.

[0088] Fig.14 FIG. 1 is a schematic diagram of an electronic device according to at least one embodiment of the present disclosure. Fig.14 As shown, at least one embodiment of the present disclosure further provides an electronic device 91, including: a detection panel 910. The detection panel 910 can be as described in the above embodiment, so it is not repeated here. The electronic device 91 can be a flat panel detector, a medical diagnostic device, an industrial detection device, a geological exploration device, etc. However, this embodiment is not limited to this.

[0089] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0090] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A pixel sensor circuit, characterized in that: include: A signal generating subcircuit, a resetting subcircuit, an amplifying subcircuit, and a reading subcircuit; The reset subcircuit is connected to the reset signal line, the first power line and the first node, and is configured to provide a signal of the first power line to the first node under the control of the reset signal line; The signal generating subcircuit is connected to the bias signal line and the first node, and is configured to detect the optical signal and convert the detected optical signal into an electrical signal; The amplifying subcircuit is connected to the second power line, the first node and the second node, and is configured to provide an amplified electrical signal to the second node according to a signal provided by the second power line under the control of the first node; The reading subcircuit is connected to the scanning signal line, the second node and the signal reading line, and is configured to output the amplified electrical signal to the signal reading line under the control of the scanning signal line; The effective level signal provided by the first power line and the effective level signal provided by the second power line have the same polarity and different durations; or, the scanning signal line and the second power line provide the same pulse signal timing; or, the starting time of the effective level signal provided by the second power line is earlier than the starting time of the effective level signal provided by the scanning signal line, and the ending time of the effective level signal provided by the second power line is not earlier than the ending time of the effective level signal provided by the scanning signal line.

2. The pixel sensor circuit according to claim 1, characterized in that: The voltage value of the effective level signal provided by the second power line is greater than or equal to the voltage value of the effective level signal provided by the first power line.

3. The pixel sensor circuit according to any one of claims 1 to 2, characterized in that: The reset subcircuit comprises: a reset transistor; a control electrode of the reset transistor is connected to a reset signal line, a first electrode of the reset transistor is connected to a first power line, and a second electrode of the reset transistor is connected to a first node; The signal generating subcircuit at least comprises: a photoelectric converter; a first electrode of the photoelectric converter is connected to a first node, and a second electrode of the photoelectric converter is connected to a bias signal line; The amplifying subcircuit comprises: an amplifying transistor, a control electrode of the amplifying transistor is connected to a first node, a first electrode of the amplifying transistor is connected to a second power line, and a second electrode of the amplifying transistor is connected to a second node; The reading subcircuit includes: a reading transistor, a control electrode of the reading transistor is connected to a scanning signal line, a first electrode of the reading transistor is connected to a second node, and a second electrode of the reading transistor is connected to a signal reading line.

4. The pixel sensor circuit according to claim 3, characterized in that: The signal generation subcircuit further includes: a storage capacitor, a first electrode of the storage capacitor is connected to the first node, and a second electrode of the storage capacitor is connected to the bias signal line.

5. A method for driving a pixel sensor circuit, characterized in that: Applied to the pixel sensor circuit according to any one of claims 1 to 4, the driving method comprises: The reset subcircuit provides a signal of the first power line to the first node under the control of the reset signal line; The signal generating subcircuit detects the optical signal and converts the detected optical signal into an electrical signal; The amplifying subcircuit provides an amplified electrical signal to the second node according to the signal provided by the second power line under the control of the electrical signal generated by the signal generating subcircuit; The reading subcircuit outputs the amplified electrical signal to the signal reading line under the control of the scanning signal line.

6. A detection panel, characterized in that: include: A detection area and a peripheral area located outside the detection area; the detection area includes a plurality of pixel sensor circuits as described in any one of claims 1 to 4 arranged on a substrate; The peripheral area is at least provided with a power driver, and the power driver is configured to be connected to the pixel sensing circuit through a second power line.

7. The detection panel according to claim 6, characterized in that: The power driver includes at least one of the following: an array substrate row driving GOA circuit arranged on the base substrate, a surface mount chip COG arranged on the base substrate, and an array external wiring WOA arranged on the base substrate.

8. The detection panel according to claim 6, wherein: At least one Y-PCB is arranged in the peripheral area, and the power driver is arranged on the Y-PCB.

9. The detection panel according to claim 8, wherein: The peripheral area is also provided with a gate driver configured to be connected to the pixel sensing circuit via a reset signal line and a scan signal line; The power driver and the gate driver are respectively arranged on different Y-PCBs; Alternatively, the power driver and the gate driver are arranged on the same Y-PCB.

10. The detection panel according to claim 6, wherein: The peripheral area is further provided with an X-PCB, and the power driver is provided on the X-PCB.

11. An electronic device, characterized in that: Comprising a detection panel as claimed in any one of claims 6 to 10.

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