Memory device and operating method thereof, memory system

Abstract

Embodiments of the present application provide a memory device and an operating method thereof, and a memory system. The memory device includes a plurality of finger memory regions, each of which includes a plurality of memory cell rows, each of which includes a plurality of memory cells arranged side by side in a direction parallel to a direction in which a gate isolation structure extends. The method includes performing a first programming operation on a first memory cell row and a second memory cell row of the plurality of memory cell rows; while performing the first programming operation, applying a first bit line voltage to a bit line coupled to the first memory cell row and applying a second bit line voltage to a bit line coupled to the second memory cell row, the first memory cell row and the second memory cell row belonging to different groups having different programming speeds, and the first bit line voltage and the second bit line voltage being different.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] Memory is a storage device used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed, and retention characteristics.

[0003] With the increasing demands on memory, reducing programming time and improving programming efficiency has become one of the most pressing technical problems to be solved in this field. Summary of the Invention

[0004] This invention provides a memory device, its operation method, and a memory system.

[0005] This invention provides an operation method for a memory device.

[0006] The memory device includes a plurality of pointer memory regions, each pointer memory region including a plurality of memory cell rows, and each memory cell row including a plurality of memory cells arranged side by side along a direction parallel to the extension direction of the gate isolation structure; the method includes:

[0007] A first programming operation is performed on the first and second memory cell rows of the plurality of memory cell rows. During the first programming operation, a first bit line voltage is applied to the bit line coupled to the first memory cell row, and a second bit line voltage is applied to the bit line coupled to the second memory cell row. The programming speeds of the groups to which the first and second memory cell rows belong are different, and the first bit line voltage and the second bit line voltage are different.

[0008] The method in the above scheme further includes:

[0009] Retrieve the value of the group to which each storage cell row belongs in multiple storage cell rows;

[0010] Applying a first bit line voltage to the bit line coupled to the first memory cell array and applying a second bit line voltage to the bit line coupled to the second memory cell array includes:

[0011] The value of the group to which the first memory cell row belongs is obtained as a first value, and a first bit line voltage is applied to the bit line coupled to the first memory cell row based on the first value; the value of the group to which the second memory cell row belongs is obtained as a second value, and a second bit line voltage is applied to the bit line coupled to the second memory cell row based on the second value.

[0012] In the above scheme, the programming speed of the group to which the first storage cell row belongs is the first speed, and the programming speed of the group to which the second storage cell row belongs is the second speed;

[0013] When the first speed is greater than the second speed, the first bit line voltage is greater than the second bit line voltage;

[0014] When the first speed is less than the second speed, the first bit line voltage is less than the second bit line voltage.

[0015] The method in the above scheme further includes:

[0016] The plurality of storage cell rows are grouped according to the programming speed of each storage cell row; wherein the number of the groups is less than or equal to the number of storage cell rows in a storage area.

[0017] The method in the above scheme further includes:

[0018] A second programming operation is performed on each of the multiple memory cell rows to obtain the programming speed of each memory cell row; wherein, during the second programming operation, the same bit line voltage is applied to the bit lines coupled to each memory cell row.

[0019] In the above scheme, the method further includes: applying a ground voltage to the bit lines coupled to each of the memory cell rows during the second programming operation.

[0020] The method in the above scheme further includes:

[0021] The programming speed of the memory cell row is determined based on the minimum distance between the memory cell row and any gate isolation structure.

[0022] In the above scheme, the smaller the minimum distance between the memory cell row and any gate isolation structure, the greater the programming speed of the memory cell row.

[0023] In the above scheme, grouping the multiple storage cell rows according to the programming speed of each storage cell row includes:

[0024] The memory cells with the lowest programming speed in a pointer memory area are divided into the first group, and the remaining memory cells in the pointer memory area other than the memory cells with the lowest programming speed are divided into the second group.

[0025] The first and second memory cell rows belong to groups with different programming speeds, including:

[0026] The first storage cell row belongs to the first group, and the second storage cell row belongs to the second group;

[0027] or,

[0028] The first storage cell row belongs to the second group, and the second storage cell row belongs to the first group.

[0029] In the above scheme, when the first storage cell row belongs to the first group and the second storage cell row belongs to the second group, the first bit line voltage is 0V, and the range of the second bit line voltage is 0.3V-0.5V;

[0030] When the first storage cell row belongs to the second group and the second storage cell row belongs to the first group, the range of the first bit line voltage is 0.3V-0.5V, and the second bit line voltage is 0V.

[0031] In the above scheme, a storage area includes M rows of storage units; M is a positive integer greater than two.

[0032] The step of grouping the multiple storage cell rows according to the programming speed of each storage cell row includes:

[0033] Divide the M storage units into M groups;

[0034] The first and second memory cell rows belong to groups with different programming speeds, and the first bit line voltage differs from the second bit line voltage, including:

[0035] The first storage cell row belongs to the i-th group, and the second storage cell row belongs to the j-th group. When the first bit line voltage is different from the bit line voltage applied to the bit line coupled to the first storage cell row when the first storage cell row belongs to any group other than the i-th group in the M-group, the second bit line voltage is different from the bit line voltage applied to the bit line coupled to the second storage cell row when the second bit line voltage is different from the bit line voltage applied to the bit line coupled to the second storage cell row when the second storage cell row belongs to any group other than the j-th group in the M-group, and i and j are positive integers less than or equal to M.

[0036] This invention also provides a memory device, the memory device comprising: a plurality of finger memory regions and peripheral circuitry coupled to the finger memory regions; wherein each finger memory region comprises a plurality of memory cell rows, and each memory cell row comprises a plurality of memory cells arranged in parallel along a direction parallel to the extension direction of the gate isolation structure;

[0037] The peripheral circuit is configured as follows:

[0038] A first programming operation is performed on the first and second memory cell rows of the plurality of memory cell rows. During the first programming operation, a first bit line voltage is applied to the bit line coupled to the first memory cell row, and a second bit line voltage is applied to the bit line coupled to the second memory cell row. The programming speeds of the groups to which the first and second memory cell rows belong are different, and the first bit line voltage and the second bit line voltage are different.

[0039] In the above scheme, the peripheral circuit is configured as follows:

[0040] The value of the group to which the first memory cell row belongs is obtained as a first value, and a first bit line voltage is applied to the bit line coupled to the first memory cell row based on the first value; the value of the group to which the second memory cell row belongs is obtained as a second value, and a second bit line voltage is applied to the bit line coupled to the second memory cell row based on the second value.

[0041] In the above scheme, the peripheral circuit is configured as follows:

[0042] The programming speed of the group to which the first storage cell row belongs is the first speed, and the programming speed of the group to which the second storage cell row belongs is the second speed;

[0043] When the first speed is greater than the second speed, the first bit line voltage is greater than the second bit line voltage;

[0044] When the first speed is less than the second speed, the first bit line voltage is less than the second bit line voltage.

[0045] In the above scheme, the peripheral circuit is configured to group the plurality of memory cell rows according to the programming speed of each memory cell row; wherein the number of the groups is less than or equal to the number of memory cell rows in a memory area.

[0046] In the above scheme, the peripheral circuit includes: a control logic unit, a voltage generator, and a column driver; the voltage generator and the column driver are coupled to the first memory cell row and the second memory cell row, and are controlled by the control logic unit;

[0047] The control logic unit is configured to: obtain a first value for the group to which the first storage unit row belongs in a plurality of storage unit rows, and a second value for the group to which the second storage unit row belongs, and perform a first programming operation on the first storage unit row and the second storage unit row;

[0048] The control logic unit is configured to: determine the first bit line voltage and the second bit line voltage to be generated based on the first value and the second value;

[0049] The voltage generator is configured to generate a first line voltage and a second line voltage to be generated.

[0050] The column driver is configured to apply a generated first bit line voltage to a bit line coupled to the first memory cell array and to apply a generated second bit line voltage to a bit line coupled to the second memory cell array.

[0051] In the above scheme, the memory device includes a three-dimensional NAND type memory.

[0052] This invention also provides a memory system, comprising:

[0053] One or more memory devices as described in any of the above embodiments; and

[0054] A memory controller, which is coupled to and controls the memory device.

[0055] In the above scheme, the memory system includes a memory card or a solid-state drive. Attached Figure Description

[0056] Figure 1a This is a schematic diagram of the word line voltage applied to the memory cell during programming operations using a step-pulse programming method according to an embodiment of the present invention;

[0057] Figure 1b This is a schematic diagram of the threshold voltage distribution under one pulse during programming operations using a step-pulse programming method according to an embodiment of the present invention;

[0058] Figure 2a This is a schematic diagram of the distribution of storage cell rows in a three-dimensional NAND type memory according to an embodiment of the present invention;

[0059] Figure 2b This is a schematic diagram of the distribution of storage cell rows in a three-dimensional NAND type memory according to an embodiment of the present invention;

[0060] Figure 3a This is a schematic diagram showing the relationship between programming voltage and threshold voltage for different rows of memory cells in a memory device according to an embodiment of the present invention.

[0061] Figure 3b This is a schematic diagram showing the threshold voltage distribution of different memory cells after a single programming operation and the overall threshold voltage distribution of a memory device according to an embodiment of the present invention.

[0062] Figure 3c This is a schematic diagram of the standard deviation of threshold voltage distribution for different rows of memory cells and the overall standard deviation of threshold voltage distribution in a memory device according to an embodiment of the present invention.

[0063] Figure 4 This is a schematic diagram illustrating the implementation flow of an operation method for a memory device according to another embodiment of the present invention;

[0064] Figure 5a This is a timing diagram illustrating the programming operation of a memory device according to an embodiment of the present invention;

[0065] Figure 5b This is a timing diagram illustrating the programming operation of a memory device according to another embodiment of the present invention;

[0066] Figure 6a This is a schematic diagram showing the relationship between programming voltage and threshold voltage for different rows of memory cells in a memory device according to another embodiment of the present invention.

[0067] Figure 6b This is a schematic diagram of the threshold voltage distribution of different memory cells after a single programming operation and the overall threshold voltage distribution of a memory device according to another embodiment of the present invention.

[0068] Figure 6c This is a schematic diagram of the standard deviation of threshold voltage distribution for different rows of memory cells and the overall standard deviation of threshold voltage distribution in a memory device according to another embodiment of the present invention.

[0069] Figure 7 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present invention;

[0070] Figure 8a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present invention;

[0071] Figure 8b This is a schematic diagram of an exemplary solid-state driver with a memory system according to an embodiment of the present invention;

[0072] Figure 9 This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present invention;

[0073] Figure 10 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present invention. Detailed Implementation

[0074] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0075] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, to avoid obscuring the invention, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0076] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0077] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention.

[0078] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0079] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0080] To gain a more detailed understanding of the features and technical content of the embodiments of the present invention, the implementation of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of the present invention.

[0081] The memory devices in the embodiments of the present invention include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0082] The programming of three-dimensional NAND flash memory mostly adopts the incremental step pulse program (ISPP) method. Figure 1aThis diagram illustrates the word line voltage applied to the memory cell during programming operations using the ISPP method according to an embodiment of the present invention. For NAND flash memory, when performing write operations using step-pulse programming, the write operation is performed on a page-by-page basis. Taking a memory cell within a page as an example, after programming begins, an initial programming voltage is applied to the memory cell, followed by a programming verification voltage to verify whether the target threshold voltage has been reached. If the target threshold voltage has not been reached, a voltage higher than the initial programming voltage is applied again, and the programming verification voltage is applied again to verify whether the target threshold voltage has been reached. This process is repeated until the threshold voltage of the memory cell is found to have been reached during the verification step. At this point, the programming of the memory cell is complete. Subsequently, a programming suppression voltage is applied to the memory cell to prevent it from being programmed again. When the threshold voltages of all memory cells in the page have been reached, the entire page programming process ends. Programming using the above-described step-pulse programming method can achieve a narrower final threshold voltage distribution. When using the above step-by-step programming method, the wider the threshold voltage distribution width after a single programming operation, the more programming and programming verification operations are required, and the longer the final programming time. Figure 1b This is a schematic diagram of the threshold voltage distribution under one pulse during programming operations using a step-pulse programming method according to an embodiment of the present invention.

[0083] like Figure 2a As shown, the storage array structure of the three-dimensional NAND memory consists of several rows of parallel and staggered storage cell rows parallel to the gate isolation structure. Every four rows of storage cell rows are separated by the gate isolation structure and the upper selected gate isolation structure. In order of decreasing distance from the nearest gate isolation structure, the four rows of storage cell rows are the first row, the second row, the third row, and the fourth row. Each of the four storage cell rows includes multiple storage cells.

[0084] Figure 2b A schematic diagram of the cell row distribution of another three-dimensional NAND flash memory is given, from... Figure 2b As can be seen, the gate isolation structure can include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory into multiple memory blocks, and multiple second gate isolation structures can divide the memory blocks into multiple finger memory areas.

[0085] It should be noted that, Figure 2a as well as Figure 2bThe number of memory cell rows between the gate isolation structure and the upper-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of memory cell rows in this invention. The following explanation uses four rows of memory cell rows between the gate isolation structure and the upper-select gate isolation structure as an example. Research has found that the programming characteristics (relationship between programming voltage and threshold voltage) of the four rows of memory cell rows separated by the gate isolation structure and the upper-select gate isolation structure differ, and the programming speed varies for different memory cell rows. Figure 3a The diagram illustrates the relationship between programming voltage and threshold voltage for different memory cell rows according to an embodiment of the present invention. It can be seen from the diagram that the programming speed of the four memory cell rows is different. The programming speed of the memory cell row closer to the gate isolation structure is faster. That is to say, the programming speed of the fourth row is the fastest and the programming speed of the first row is the slowest. Figure 3b The figure shows the threshold voltage distribution after a single programming operation of different memory cell rows according to an embodiment of the present invention, as well as the overall threshold voltage distribution. As can be seen from the figure, after a single programming operation, the threshold voltage distribution width of each memory cell row is similar. However, due to the difference in programming speed, the overall threshold voltage distribution width of the four memory cell rows is wider, which increases the number of programming verifications required and the overall programming time. Figure 3c The figure shows the standard deviation of threshold voltage distribution for different rows of memory cells and the overall standard deviation of threshold voltage distribution in an embodiment of the present invention. It can be seen from the figure that the standard deviation of threshold voltage distribution for the four rows of memory cells is not much different, but the overall standard deviation of threshold voltage distribution is larger than that of each row of memory cells.

[0086] To address the above-mentioned problems, another embodiment of the present invention employs the following technical solution.

[0087] Another embodiment of the present invention provides an operation method for a memory device, the memory device including a plurality of pointer storage regions, each pointer storage region including a plurality of memory cell rows, each memory cell row including a plurality of memory cells arranged side by side along a direction parallel to the extension direction of the gate isolation structure; such as Figure 4 As shown, the method includes:

[0088] Step 401: Perform a first programming operation on the first and second memory cell rows among the plurality of memory cell rows; during the first programming operation, apply a first bit line voltage to the bit line coupled to the first memory cell row and apply a second bit line voltage to the bit line coupled to the second memory cell row. The programming speeds of the groups to which the first and second memory cell rows belong are different, and the first bit line voltage and the second bit line voltage are different.

[0089] Here, the first storage cell row and the second storage cell row can be any of the multiple storage cell rows.

[0090] Here, when there is only one storage cell row in a group, the programming speed of the group is the programming speed of that single storage cell row; when there are multiple storage cell rows in a group, the programming speed of the group is the row programming speed that can reflect the programming speed of the multiple storage cell rows, for example, the average programming speed of the multiple storage cell rows.

[0091] In this embodiment of the invention, based on the different programming speeds of different memory cell rows, different bit line voltages are applied to the bit lines coupled to the memory cell rows during the first programming operation. This results in a narrower overall threshold voltage distribution of the memory cell rows after the first programming operation. Consequently, the number of programming operations and programming verification operations can be reduced during the programming operation of the memory cell rows, shortening the overall programming time and thus improving programming efficiency.

[0092] In this embodiment of the invention, when performing a first programming operation on the first and second memory cell rows, different bit line voltages are applied to the bit lines according to the programming speed of the group to which the first and second memory cell rows belong, thereby adjusting the programming speed of the memory cell rows. This improves the problem that the threshold voltage distribution of the entire memory cell row in a single memory area is wide due to the large difference in programming speed among multiple memory cell rows after a single programming operation. As a result, the threshold voltage distribution of the entire memory cell row becomes narrower after a single programming operation, thereby reducing the number of programming operations for the entire memory cell row, and thus shortening the programming time of the entire memory cell row and improving programming efficiency.

[0093] In some embodiments, the method further includes:

[0094] Retrieve the value of the group to which each storage cell row belongs in multiple storage cell rows;

[0095] Applying a first bit line voltage to the bit line coupled to the first memory cell array and applying a second bit line voltage to the bit line coupled to the second memory cell array includes:

[0096] The value of the group to which the first memory cell row belongs is obtained as a first value, and a first bit line voltage is applied to the bit line coupled to the first memory cell row based on the first value; the value of the group to which the second memory cell row belongs is obtained as a second value, and a second bit line voltage is applied to the bit line coupled to the second memory cell row based on the second value.

[0097] In some embodiments, the programming speed of the group to which the first storage cell row belongs is a first speed, and the programming speed of the group to which the second storage cell row belongs is a second speed;

[0098] When the first speed is greater than the second speed, the first bit line voltage is greater than the second bit line voltage;

[0099] When the first speed is less than the second speed, the first bit line voltage is less than the second bit line voltage.

[0100] It is understandable that the higher the programming speed of the group to which the storage cell row belongs, the higher the programming speed of the storage cell row itself. Since the programming speeds of multiple storage cell rows in a single storage area differ, the overall threshold voltage distribution after a single programming operation is relatively wide. In this embodiment of the invention, the programming speed of the storage cell row is adjusted by applying different bit line voltages to it. Specifically, the higher the programming speed of the group to which the storage cell row belongs, the higher the bit line voltage applied when programming the storage cell row. This reduces the difference in programming speed between multiple storage cell rows during programming operations, thereby narrowing the overall threshold voltage distribution of the storage cell row. As a result, when using step-pulse programming, the number of programming operations for the entire storage cell row is reduced, thus shortening the overall programming time and improving programming efficiency.

[0101] In some embodiments, the method further includes:

[0102] The plurality of storage cell rows are grouped according to the programming speed of each storage cell row; wherein the number of the groups is less than or equal to the number of storage cell rows in a storage area.

[0103] Here, the number of groups is less than or equal to the number of rows of storage cells in a storage area. It can be understood that each row of storage cells can be divided into a group, or multiple rows of storage cells can be divided into a group.

[0104] In practical applications, the number of groups can be selected based on specific circumstances. For example, after determining the programming speed of each memory cell row, if the difference in programming speed between two memory cell rows is greater than a first threshold, these two rows can be divided into two groups; if the difference is less than or equal to the first threshold, they are grouped into one group. In other words, the difference in programming speed among the memory cell rows in a group is less than or equal to the first threshold. This first threshold can be set according to the specific circumstances of the application. The smaller the first threshold, the more groups are formed for the same memory cell row, resulting in more effective control over the programming speed and making the programming speeds of multiple memory cell rows closer, thus narrowing the overall threshold voltage distribution after a single programming operation. Conversely, the larger the first threshold, the fewer groups are formed for the same memory cell row, achieving the goal of making the programming speeds of multiple memory cell rows closer, but the final overall threshold voltage distribution will be relatively wider. This is mainly due to the challenge of applying multiple bit line voltages during programming. In practical applications, the choice can be made by comprehensively considering both the implementation difficulty and the final effect.

[0105] The present invention does not limit how to determine the programming speed of each storage cell row. The following are only two exemplary schemes for determining the programming speed of each storage cell row.

[0106] Option 1:

[0107] In some embodiments, the method further includes:

[0108] A second programming operation is performed on each of the multiple memory cell rows to obtain the programming speed of each memory cell row; wherein, during the second programming operation, the same bit line voltage is applied to the bit lines coupled to each memory cell row.

[0109] In some embodiments, the method further includes applying a ground voltage to each bit line coupled to each of the memory cell rows during the second programming operation.

[0110] It is understood that, before performing the first programming operation on each of the multiple memory cell rows, when performing the second programming operation on each of the multiple memory cell rows, the same bit line voltage is applied to the bit lines coupled to each memory cell row. The applied bit line voltage can be a bit line voltage greater than zero or a bit line voltage equal to zero (i.e., ground voltage), thereby obtaining the programming speed of each memory cell row.

[0111] Option 2:

[0112] In some embodiments, the method further includes:

[0113] The programming speed of the memory cell row is determined based on the minimum distance between the memory cell row and any gate isolation structure.

[0114] In some embodiments, the smaller the minimum distance between the memory cell row and any gate isolation structure, the greater the programming speed of the memory cell row.

[0115] Understandably, in practical applications, during the formation of the channel vias that form the memory cell array, the size of the channel vias closer to the gate isolation structure is smaller due to process limitations. The smaller the size of the channel vias, the faster the programming speed of the memory cell array. Therefore, the speed of the memory cell array can be determined based on the distance between the memory cell array and the gate isolation structure, with the programming speed of the memory cell array being greater the closer it is to the gate isolation structure.

[0116] Here, the minimum distance between a row of memory cells and any gate isolation structure can be understood as follows: a memory region includes multiple rows of memory cells, which are separated by multiple gate isolation structures and multiple up-select gate isolation structures. The minimum distance between a row of memory cells and any gate isolation structure is also the distance between the row of memory cells and the nearest gate isolation structure.

[0117] In practical applications, the choice between the two schemes can be made based on the specific circumstances. Scheme 1, which directly measures the speed of the memory cell array by applying voltage, has a wider range of applications. Scheme 2, which determines the speed of the memory cell array based on the relationship between the minimum distance between the memory cell array and any gate isolation structure and the programming speed of the memory cell array, is suitable for certain process conditions and has a shorter judgment time.

[0118] The following examples illustrate two scenarios for grouping storage cell rows. It should be noted that in practical applications, the grouping is not limited to these two scenarios.

[0119] In some embodiments,

[0120] The step of grouping the multiple storage cell rows according to the programming speed of each storage cell row includes:

[0121] The memory cells with the lowest programming speed in a pointer memory area are divided into the first group, and the remaining memory cells in the pointer memory area other than the memory cells with the lowest programming speed are divided into the second group.

[0122] The first and second memory cell rows belong to groups with different programming speeds, including:

[0123] The first storage cell row belongs to the first group, and the second storage cell row belongs to the second group;

[0124] or,

[0125] The first storage cell row belongs to the second group, and the second storage cell row belongs to the first group.

[0126] In some embodiments, when the first storage cell row belongs to the first group and the second storage cell row belongs to the second group, the first bit line voltage is 0V, and the range of the second bit line voltage is 0.3V-0.5V.

[0127] When the first storage cell row belongs to the second group and the second storage cell row belongs to the first group, the range of the first bit line voltage is 0.3V-0.5V, and the second bit line voltage is 0V.

[0128] Figure 5a A timing diagram illustrating the programming operation according to an embodiment of the present invention is shown. Figure 5a As shown, during programming, a programming voltage is applied to the selected word line, a pass voltage is applied to the unselected word line, the selected bit line and the unselected upper select gate are grounded, an inhibit voltage is applied to the unselected bit line, and an enable voltage is applied to the selected upper select gate.

[0129] Figure 5b A timing diagram of the first programming operation during another embodiment of the present invention is shown. Figure 5b As shown, during the first programming operation, a programming voltage is applied to the selected word line, a pass voltage is applied to the unselected word line, the unselected upper selection gate is grounded (ground voltage is 0V), an inhibit voltage is applied to the unselected bit line, and an on voltage is applied to the selected upper selection gate. For the selected bit line, when the memory cell row coupled to the selected bit line belongs to the first group, a first bit line voltage is applied to the bit line coupled to the memory cell row during the first programming operation. When the memory cell row coupled to the selected bit line belongs to the second group, a second bit line voltage is applied to the bit line coupled to the memory cell row during the first programming operation. The second bit line voltage is greater than the first bit line voltage.

[0130] In practical applications, the voltage range can be 6V-9V; the programming voltage range can be 16V-20V; the first line voltage can be a low voltage, such as 0V; the second line voltage range can be 0.3V-0.5V; the disable voltage range can be 2V-3V; and the turn-on voltage can be 2.5V. It should be noted that the above voltage ranges are merely exemplary and do not limit the scope of the invention.

[0131] Figure 6a It shows in Figure 2aIn the case of the distribution of memory cell rows, the first row of memory cells is divided into a first group, and the second, third, and fourth rows of memory cells are divided into a second group. A first bit line voltage (0V) is applied to the first row of memory cells, and a second bit line voltage is applied to the second, third, and fourth rows of memory cells. This yields the average threshold voltage-programming voltage relationship diagram of the present invention, which is then compared with average threshold voltage-programming voltage relationship diagrams in related technologies. Figure 6a It can be seen that after applying the first bit line voltage (0V) to the first row of memory cells and the second bit line voltage to the second, third, and fourth rows of memory cells, the programming speed of the second, third, and fourth rows of memory cells slows down, and the programming speed of the four rows of memory cells becomes more convergent.

[0132] It should be noted that, Figure 2a The number of rows is used only as an example and is not intended to limit the number of rows of memory cells contained in a single memory area of ​​the three-dimensional NAND memory in this application. In practical applications, the number of rows of memory cells contained in a single memory area can be adjusted according to the actual situation, such as 2, 4, 8, 16, etc.

[0133] Figure 6b The graph showing the relationship between the number of bits and the threshold voltage for the first, second, third, and fourth rows of memory cells, and the overall memory cell rows, obtained by applying a first bit line voltage (0V) to the first row of memory cells and a second bit line voltage to the second, third, and fourth rows of memory cells, is derived from the present invention. Figure 6b As can be seen from this, the overall threshold voltage distribution after the first programming operation is similar to... Figure 3b The overall threshold voltage distribution shown in the image is narrower. Figure 6c For another embodiment of the present invention and one embodiment of the present invention, the relationship between the threshold voltage standard deviation and the sorting is as follows: Figure 6c It can be seen that the standard deviation of the overall threshold voltage distribution obtained by another embodiment of the present invention is significantly reduced, that is, the threshold voltage distribution of the other embodiment of the present invention is narrower. This results in fewer programming and verification operations during step-by-step programming, thus shortening the total programming time and increasing programming efficiency.

[0134] This invention, in a three-dimensional NAND flash memory, differentiates the programming speed of different rows of memory cells. For memory cell rows with faster programming speeds, a second bit line voltage is applied to their coupled bit lines, while for memory cell rows with slower programming speeds, a first bit line voltage of 0V is applied. It can be understood that for memory cells in a faster programming cell row, the effective programming voltage is optimized to the programming voltage minus the second bit line voltage. This suppresses the programming speed, making it similar to that of slower programming cell rows. Consequently, the width of the overall threshold voltage distribution after a single programming operation is narrowed, effectively reducing the number of programming and verification operations, ultimately reducing the total programming time.

[0135] In this embodiment of the invention, during the first programming operation, different bit line voltages are applied to the bit lines coupled to different rows of memory cells based on their different programming speeds. Without increasing programming operation time, by optimizing the voltage applied to the bit lines coupled to different rows of memory cells, the programming Vt distribution width is effectively reduced. The standard deviation of the Vt distribution is reduced from approximately 330mV to 270mV. Calculations show that this reduces the number of programming iterations by approximately 0.8 and the number of programming verification iterations by 1.8, saving approximately 5% of programming time.

[0136] In practical applications, the grouping of the storage cell row is not limited to two groups; there can be multiple groups. The following section provides a detailed explanation of the case where the storage cell row is divided into more than two groups.

[0137] In some embodiments, a storage area includes M rows of storage cells; M is a positive integer greater than two.

[0138] The step of grouping the multiple storage cell rows according to the programming speed of each storage cell row includes:

[0139] Divide the M storage units into M groups;

[0140] The first and second memory cell rows belong to groups with different programming speeds, and the first bit line voltage differs from the second bit line voltage, including:

[0141] The first storage cell row belongs to the i-th group, and the second storage cell row belongs to the j-th group. When the first bit line voltage is different from the bit line voltage applied to the bit line coupled to the first storage cell row when the first storage cell row belongs to any group other than the i-th group in the M-group, the second bit line voltage is different from the bit line voltage applied to the bit line coupled to the second storage cell row when the second bit line voltage is different from the bit line voltage applied to the bit line coupled to the second storage cell row when the second storage cell row belongs to any group other than the j-th group in the M-group, and i and j are positive integers less than or equal to M.

[0142] Here, the M rows of memory cells are divided into M groups, meaning each row of memory cells is grouped into a single group. Different bit line voltages are applied to the bit lines coupled to the memory cell rows in each group. The higher the programming speed of a memory cell row, the higher the bit line voltage applied to the bit lines coupled to that row. By applying a certain bit line voltage to the bit lines coupled to memory cell rows with faster programming speeds, the programming speed of these rows is reduced, making the programming speeds of multiple memory cell rows more similar, thus narrowing the overall programming threshold voltage width.

[0143] It is understandable that dividing each row of memory cells into a group and applying different bit line voltages to each row of memory cells according to their programming speed can achieve better control over the programming speed of the rows of memory cells. This makes the programming speed of each row of memory cells more similar during the first programming operation, thereby making the overall programming threshold voltage distribution narrower.

[0144] This invention provides an operation method for a memory device, the memory device including a plurality of pointer memory regions, each pointer memory region including a plurality of memory cell rows, each memory cell row including a plurality of memory cells arranged in parallel along a direction parallel to the extension direction of the gate isolation structure; the method includes: performing a first programming operation on a first memory cell row and a second memory cell row among the plurality of memory cell rows; during the first programming operation, applying a first bit line voltage to a bit line coupled to the first memory cell row, applying a second bit line voltage to a bit line coupled to the second memory cell row, wherein the programming speeds of the groups to which the first memory cell row and the second memory cell row belong are different, and the first bit line voltage and the second bit line voltage are different. In this embodiment of the invention, when the programming speeds of the first and second memory cell rows in multiple memory cell rows are different, different bit line voltages are applied to the bit lines coupled to the first and second memory cell rows respectively, thereby adjusting the programming speed of the memory cell rows. This improves the problem that the threshold voltage distribution of the entire memory cell row in a single memory area is wide due to the large difference in programming speed among multiple memory cell rows after a single programming operation. As a result, the threshold voltage distribution of the entire memory cell row becomes narrower after a single programming operation, thereby reducing the number of programming operations for the entire memory cell row, and thus shortening the programming time of the entire memory cell row and improving programming efficiency.

[0145] Based on the above-described operation method of the memory device, this embodiment of the invention also provides a memory device, the memory device including a plurality of finger storage regions and peripheral circuits coupled to the finger storage regions; wherein, each finger storage region includes a plurality of memory cell rows, and each memory cell row includes a plurality of memory cells arranged in parallel along a direction parallel to the extension direction of the gate isolation structure.

[0146] The peripheral circuit is configured as follows:

[0147] A first programming operation is performed on the first and second memory cell rows of the plurality of memory cell rows. During the first programming operation, a first bit line voltage is applied to the bit line coupled to the first memory cell row, and a second bit line voltage is applied to the bit line coupled to the second memory cell row. The programming speeds of the groups to which the first and second memory cell rows belong are different, and the first bit line voltage and the second bit line voltage are different.

[0148] In some embodiments, the peripheral circuit is configured as follows:

[0149] The value of the group to which the first memory cell row belongs is obtained as a first value, and a first bit line voltage is applied to the bit line coupled to the first memory cell row based on the first value; the value of the group to which the second memory cell row belongs is obtained as a second value, and a second bit line voltage is applied to the bit line coupled to the second memory cell row based on the second value.

[0150] In some embodiments, the peripheral circuit is configured as follows:

[0151] The programming speed of the group to which the first storage cell row belongs is the first speed, and the programming speed of the group to which the second storage cell row belongs is the second speed;

[0152] When the first speed is greater than the second speed, the first bit line voltage is greater than the second bit line voltage;

[0153] When the first speed is less than the second speed, the first bit line voltage is less than the second bit line voltage.

[0154] In some embodiments, the peripheral circuitry is configured to group the plurality of memory cell rows according to the programming speed of each memory cell row; wherein the number of groups is less than or equal to the number of memory cell rows in a memory area.

[0155] In some embodiments, the peripheral circuitry includes: a control logic unit, a voltage generator, and a column driver; the voltage generator and the column driver are coupled to the first memory cell row and the second memory cell row, and are controlled by the control logic unit.

[0156] The control logic unit is configured to: obtain a first value for the group to which the first storage unit row belongs in a plurality of storage unit rows, and a second value for the group to which the second storage unit row belongs, and perform a first programming operation on the first storage unit row and the second storage unit row;

[0157] The control logic unit is configured to: determine the first bit line voltage and the second bit line voltage to be generated based on the first value and the second value;

[0158] The voltage generator is configured to generate a first line voltage and a second line voltage to be generated.

[0159] The column driver is configured to apply a generated first bit line voltage to a bit line coupled to the first memory cell array and to apply a generated second bit line voltage to a bit line coupled to the second memory cell array.

[0160] It is understood that both the voltage generator and the column driver are controlled by the control logic unit. The control logic unit determines the grouping of the first and second memory cell rows, as well as the magnitude of the bit line voltages to be applied to the first and second memory cell rows. The voltage generator produces the bit line voltages, and the column driver applies the bit line voltages generated by the voltage generator to the bit lines coupled to the first and second memory cell rows. The execution entities that determine the grouping of the first and second memory cell rows and the magnitude of the bit line voltages to be applied to the first and second memory cell rows, the execution entities that generate the bit line voltages, and the execution entities that apply the bit line voltages to the bit lines coupled to the first and second memory cell rows, as described in the following embodiments, can all refer to the above description.

[0161] In some embodiments, the peripheral circuit is configured as follows:

[0162] A second programming operation is performed on each of the multiple memory cell rows to obtain the programming speed of each memory cell row; wherein, during the second programming operation, the same bit line voltage is applied to the bit lines coupled to each memory cell row.

[0163] In some embodiments, the peripheral circuit is configured as follows:

[0164] During the second programming operation, a ground voltage is applied to the bit lines coupled to each of the memory cell rows.

[0165] In some embodiments, the peripheral circuit is configured as follows:

[0166] The programming speed of the memory cell row is determined based on the minimum distance between the memory cell row and any gate isolation structure.

[0167] In some embodiments, the peripheral circuit is configured as follows:

[0168] The smaller the minimum distance between the memory cell row and any gate isolation structure, the greater the programming speed of the memory cell row.

[0169] In some embodiments, the peripheral circuit is configured as follows:

[0170] The memory cells with the lowest programming speed in a pointer memory area are divided into the first group, and the remaining memory cells in the pointer memory area other than the memory cells with the lowest programming speed are divided into the second group.

[0171] The first storage cell row belongs to the first group, and the second storage cell row belongs to the second group; it is determined that the first storage cell row belongs to the first group, and a first programming operation is performed on the first storage cell row. When performing the first programming operation, a first bit line voltage is applied to the bit line coupled to the first storage cell row.

[0172] or,

[0173] The first storage cell row belongs to the second group, and the second storage cell row belongs to the first group. It is determined that the first storage cell row belongs to the second group. A first programming operation is performed on the first storage cell row. During the first programming operation, a second bit line voltage is applied to the bit lines coupled to the first storage cell row; the second bit line voltage is greater than the first bit line voltage.

[0174] In some embodiments, when the first storage cell row belongs to the first group and the second storage cell row belongs to the second group, the first bit line voltage is 0V, and the range of the second bit line voltage is 0.3V-0.5V.

[0175] When the first storage cell row belongs to the second group and the second storage cell row belongs to the first group, the range of the first bit line voltage is 0.3V-0.5V, and the second bit line voltage is 0V.

[0176] In some embodiments, a storage area includes M rows of storage cells; M is a positive integer greater than two.

[0177] The peripheral circuit is configured as follows:

[0178] Divide the M storage units into M groups;

[0179] The first and second memory cell rows belong to groups with different programming speeds. The difference between the first and second bit line voltages determines the group to which the first memory cell row belongs among multiple memory cell rows. A first programming operation is performed on the first memory cell row, including:

[0180] The first storage cell row belongs to group i, and the second storage cell row belongs to group j. When the first bit line voltage is different from the bit line voltage applied to the bit lines coupled to the first storage cell row when the first storage cell row belongs to any group other than group i in group M; when the second bit line voltage is different from the bit line voltage applied to the bit lines coupled to the second storage cell row when the second storage cell row belongs to any group other than group j in group M; i and j are positive integers less than or equal to M, determining that the first storage cell row belongs to group i. A first programming operation is performed on the first storage cell row. During the first programming operation, a third bit line voltage is applied to the bit lines coupled to the first storage cell row; the third bit line voltage is different from the bit line voltage applied to the bit lines coupled to the first storage cell row when the first storage cell row belongs to any group other than group i in group M; i is a positive integer less than or equal to M.

[0181] In some embodiments, the memory device includes a three-dimensional NAND type memory.

[0182] This invention also provides a memory system, the memory system comprising:

[0183] One or more memory devices as described in any of the above embodiments; and a memory controller coupled to and controlling the memory devices.

[0184] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0185] In practical applications, the memory systems described in the embodiments of the present invention include, but are not limited to, solid-state drives (SSDs).

[0186] The memory device and memory system are further described below with reference to the accompanying drawings.

[0187] like Figure 7As shown, system 700 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. System 700 can include a host 704 and a memory system 701, the memory system 701 having one or more memory devices 702 and a memory controller 703. Host 704 can be a processor (e.g., central processing unit (CPU)) or system-on-a-chip (SoC) (e.g., application processor (AP)) of the electronic device. Host 704 can be configured to send data to or receive data from memory device 702.

[0188] The memory controller 703 and one or more memory devices 702 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 701 can be implemented and packaged into different types of end electronic products. Figure 8a In one example shown, the memory controller 703 and a single memory device 702 can be integrated into a memory card 801. The memory card 801 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 801 may also include a memory card connector 802 that couples the memory card 801 to a host computer. Figure 8b In another example shown, the memory controller 703 and multiple memory devices 702 may be integrated into the SSD 803. The SSD 803 may also include an SSD connector 804 that couples the SSD 803 to the host.

[0189] Figure 9 A schematic circuit diagram of an exemplary memory device 900 including peripheral circuitry according to some aspects of the present invention is shown. The memory device 900 may be... Figure 7An example of memory device 702 is shown. Memory device 900 may include a memory cell array 901 and peripheral circuitry 902 coupled to the memory cell array 901. The memory cell array 901 may be a NAND flash memory cell array, wherein memory cells 906 are provided in the form of an array of NAND memory strings 908, each NAND memory string 908 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 908 includes a plurality of memory cells 906 coupled in series and stacked vertically. Each memory cell 906 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 906. Each memory cell 906 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0190] In some implementations, each memory cell 906 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 906 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0191] like Figure 9As shown, each NAND memory string 908 may include a source select gate (SSG) 910 at its source end and a drain select gate (DSG) 912 at its drain end. The SSG 910 and DSG 912 can be configured to activate a selected NAND memory string 908 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 908 in the same block 904 are coupled via the same source line (SL) 914 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 908 in the same block 904 have an array common source (ACS). According to some embodiments, the DSG 912 of each NAND memory string 908 is coupled to a corresponding bit line 916, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 908 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 912) or a deselection voltage (e.g., 0V) to the corresponding DSG 912 via one or more DSG lines 913 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 910) or a deselection voltage (e.g., 0V) to the corresponding SSG 910 via one or more SSG lines 915.

[0192] like Figure 9 As shown, NAND memory strings 908 can be organized into multiple blocks 904, each of which can have a common source line 914 (e.g., coupled to ground). In some embodiments, each block 904 is the basic data unit for erase operations, i.e., all memory cells 906 on the same block 904 are erased simultaneously. Memory cells 906 of adjacent NAND memory strings 908 can be coupled via word lines 918, which select which row of memory cells 906 is affected by read and program operations. In some embodiments, each word line 918 is coupled to a memory page 920 of memory cell 906, which is the basic data unit for programming operations. A memory page can be programmed together, and a programming disable voltage can be applied once the programming state is reached. The size of a memory page 920, in bits, can be related to the number of NAND memory strings 908 coupled by word lines 918 in a block 904. Each word line 918 may include multiple control gates (gate electrodes) at each memory cell 906 in the corresponding memory page 920, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 2bA memory page 920 contains multiple memory cells 906, which are isolated from each other by an upselect gate isolation structure and a gate isolation structure. The memory cells between the upselect gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each row being parallel to both the gate isolation structure and the upselect gate isolation structure. Memory cells in memory chips sharing the same word line (an upselect gate isolation structure located in the middle of each pointer memory area can divide the pointer memory area into two parts, thus dividing the pointer memory area into two memory chips) form a programmable (read / write) memory page. During programming, different bit line voltages are applied to the bit lines coupled to different memory cell rows within the same memory page according to the programming speed of the group to which the memory cell row belongs.

[0193] In practical applications, memory device 702 may include memory cell array 901 and peripheral circuitry coupled to memory cell array 901. The peripheral circuitry may include any suitable analog, digital, and mixed-signal circuitry. Figure 10 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 1001, a column driver / bit line driver 1002, a row driver / word line driver 1003, a voltage generator 1004, a control logic unit 1005, a register 1006, an interface 1007, and a data bus 1008. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 10 Additional peripheral circuitry not shown.

[0194] Control logic unit 1005 is configured to control the operation of peripheral circuitry. Register 1006 may be coupled to control logic unit 1005 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of peripheral circuitry. Interface 1007 may be coupled to control logic unit 1005 and acts as a control buffer to buffer control commands received from the host and relay them to control logic unit 1005, and to buffer status information received from control logic unit 1005 and relay it to the host. Interface 1007 may also be coupled to column driver / bit line driver 1002 via data bus 1008 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 901.

[0195] The column driver / bit line driver 1002 can be configured to be controlled by the control logic unit 1005 and to select one or more NAND memory strings 908 by applying a bit line voltage generated from the voltage generator 1004.

[0196] The voltage generator 1004 can be configured to be controlled by the control logic unit 1005 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 901.

[0197] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of the invention, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the invention. The sequence numbers of the above-described embodiments of the invention are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0198] The methods disclosed in the several method embodiments provided by this invention can be arbitrarily combined without conflict to obtain new method embodiments.

[0199] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method of operating a memory device, comprising: The memory device includes a plurality of finger storage areas, each of the finger storage areas including a plurality of storage cell rows, each of the storage cell rows including a plurality of storage cells arranged side by side in a direction parallel to a direction in which the gate isolation structures extend; and the method includes: performing a first programming operation on a first storage cell row and a second storage cell row of the plurality of storage cell rows; and while performing the first programming operation, applying a first bit line voltage to selected bit lines of bit lines coupled to the first storage cell row and applying a second bit line voltage to selected bit lines of bit lines coupled to the second storage cell row, the first storage cell row and the second storage cell row belonging to different groups having different programming speeds, the first bit line voltage being different from the second bit line voltage.

2. The method of claim 1, wherein, The method further includes: obtaining a value of a group to which each of the plurality of storage cell rows belongs; the applying the first bit line voltage to the selected bit lines of the bit lines coupled to the first storage cell row and the applying the second bit line voltage to the selected bit lines of the bit lines coupled to the second storage cell row includes: obtaining a value of a group to which the first storage cell row belongs as a first value, and applying a first bit line voltage to the selected bit lines of the bit lines coupled to the first storage cell row according to the first value; and obtaining a value of a group to which the second storage cell row belongs as a second value, and applying a second bit line voltage to the selected bit lines of the bit lines coupled to the second storage cell row according to the second value.

3. The method of claim 1, wherein, the group to which the first storage cell row belongs has a first programming speed, and the group to which the second storage cell row belongs has a second programming speed; when the first speed is greater than the second speed, the first bit line voltage is greater than the second bit line voltage; when the first speed is less than the second speed, the first bit line voltage is less than the second bit line voltage.

4. The method of claim 1, wherein, The method further includes: grouping the plurality of storage cell rows according to the programming speed of each of the storage cell rows; wherein the number of the groups is less than or equal to the number of the storage cell rows in one finger storage area.

5. The method of claim 4, wherein, The method further includes: performing a second programming operation on each of the plurality of storage cell rows to obtain the programming speed of each of the storage cell rows; wherein the same bit line voltage is applied to the bit lines coupled to each of the storage cell rows while performing the second programming operation.

6. The method of claim 5, wherein, The method further includes: applying a ground voltage to the bit lines coupled to each of the storage cell rows while performing the second programming operation.

7. The method of claim 4, wherein, The method further includes: determining the programming speed of the storage cell row according to a minimum distance of the storage cell row to any gate isolation structure.

8. The method of claim 7, wherein, The smaller the minimum distance of the storage cell row to any gate isolation structure, the greater the programming speed of the storage cell row.

9. The method of claim 4, wherein: the grouping the plurality of storage cell rows according to the programming speed of each of the storage cell rows includes: dividing a storage cell row having a minimum programming speed in one finger storage area into a first group, and dividing the remaining storage cell rows in the finger storage area except for the storage cell row having the minimum programming speed into a second group; The first memory cell row and the second memory cell row belong to different groups in terms of programming speed, including: The first memory cell row belongs to a first group, and the second memory cell row belongs to a second group. Or, The first memory cell row belongs to a second group, and the second memory cell row belongs to a first group.

10. The method of claim 9, wherein, when the first memory cell row belongs to a first group and the second memory cell row belongs to a second group, the first bit line voltage is 0V, and the second bit line voltage ranges from 0.3V to 0.5V; when the first memory cell row belongs to a second group and the second memory cell row belongs to a first group, the first bit line voltage ranges from 0.3V to 0.5V, and the second bit line voltage is 0V.

11. The method of claim 4, wherein, One finger memory region includes M memory cell rows; M is a positive integer greater than two; The grouping of the plurality of memory cell rows according to the programming speed of each memory cell row includes: dividing the M memory cell rows into M groups; The first memory cell row and the second memory cell row belong to different groups in terms of programming speed, and the first bit line voltage is different from the second bit line voltage, including: The first memory cell row belongs to an i-th group, and the second memory cell row belongs to a j-th group, the first bit line voltage is different from the bit line voltage applied to the bit line coupled to the first memory cell row when the first memory cell row belongs to a group other than the i-th group among the M groups, and the second bit line voltage is different from the bit line voltage applied to the bit line coupled to the second memory cell row when the second memory cell row belongs to a group other than the j-th group among the M groups; i and j are positive integers less than or equal to M.

12. A memory device, comprising: The memory device includes a plurality of finger memory regions and a peripheral circuit coupled to the finger memory regions; wherein, Each finger memory region includes a plurality of memory cell rows, and each memory cell row includes a plurality of memory cells arranged side by side in a direction parallel to the extension direction of the gate isolation structure; The peripheral circuit is configured to: perform a first programming operation on a first memory cell row and a second memory cell row in the plurality of memory cell rows; when performing the first programming operation, apply a first bit line voltage to a selected bit line in the bit line coupled to the first memory cell row, and apply a second bit line voltage to a selected bit line in the bit line coupled to the second memory cell row, the first memory cell row and the second memory cell row belong to different groups in terms of programming speed, and the first bit line voltage is different from the second bit line voltage.

13. The memory device of claim 12, wherein, The peripheral circuit is configured to: obtain a value of a group to which the first memory cell row belongs as a first value, and apply a first bit line voltage to the bit line coupled to the first memory cell row according to the first value; obtain a value of a group to which the second memory cell row belongs as a second value, and apply a second bit line voltage to the bit line coupled to the second memory cell row according to the second value.

14. The memory device of claim 12, wherein, The peripheral circuit is configured to: The first storage cell row belongs to a group with a first programming speed, and the second storage cell row belongs to a group with a second programming speed; When the first speed is greater than the second speed, the first bit line voltage is greater than the second bit line voltage; When the first speed is less than the second speed, the first bit line voltage is less than the second bit line voltage.

15. The memory device of claim 12, wherein: The peripheral circuit is configured to group the plurality of storage cell rows according to the programming speed of each storage cell row, and the number of groups is less than or equal to the number of storage cell rows in a pointer memory area.

16. The memory device of claim 13, wherein, The peripheral circuit includes a control logic unit, a voltage generator, and a column driver; the voltage generator and the column driver are coupled to the first storage cell row and the second storage cell row, and are controlled by the control logic unit; The control logic unit is configured to obtain a value of a group to which the first storage cell row belongs in the plurality of storage cell rows as a first value, and a value of a group to which the second storage cell row belongs as a second value, and perform a first programming operation on the first storage cell row and the second storage cell row; The control logic unit is configured to determine a first bit line voltage to be generated and a second bit line voltage to be generated according to the first value and the second value; The voltage generator is configured to generate the first bit line voltage to be generated and the second bit line voltage to be generated; The column driver is configured to apply the generated first bit line voltage to a bit line coupled to the first storage cell row, and apply the generated second bit line voltage to a bit line coupled to the second storage cell row.

17. The memory device of claim 12, wherein, The memory device includes a three-dimensional NAND type memory.

18. A memory system, comprising: one or more memory devices as claimed in any one of claims 12 to 17; and a memory controller coupled to the memory device and controlling the memory device.

19. The memory system of claim 18, wherein, The memory system includes a memory card or a solid state disk.

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