Impedance configuration device for a memory interface

Abstract

An impedance configuration apparatus for a memory interface includes a processing unit coupled to a memory interface, a non-volatile memory, and a calibration interface. The processing unit sets a first resistance value associated with an on-chip termination resistance of a first receiver to a first default resistance value, sets a second resistance value associated with a drive variable resistance of a second transmitter to a second default resistance value, performs tests for a plurality of test combinations, wherein each combination includes a third resistance value associated with the drive variable resistance of the first transmitter and a fourth resistance value associated with the on-chip termination resistance of the second receiver, and stores test results for each test combination to a specific location of the non-volatile memory such that a calibration host can retrieve the test results for each test combination from the non-volatile memory.

Description

[0001] This application is a divisional application of the original application with the filing date of March 20, 2019, the application number of 201910211851.3, and the title of Impedance configuration method of memory interface and computer readable storage medium. TECHNICAL FIELD

[0002] The present application relates to a communication interface, in particular to an impedance configuration device of a memory interface. BACKGROUND

[0003] After the speed of the bus of a dynamic random access memory (DRAM) reaches a high transmission rate, such as 500Mb / s or higher, signal transmission problems at the system level can occur, such as reflections from the pin lines of connected peer devices (such as controllers, DRAM modules, etc.). The above-mentioned signal transmission problems can be solved by calibrating the driver and the on-die termination (ODT). Therefore, the present application proposes an impedance configuration device of a memory interface for calibrating the driver and the on-die termination in the memory interface. SUMMARY

[0004] Therefore, how to reduce or eliminate the above-mentioned deficiencies in the related art is a problem to be solved.

[0005] The present application proposes an impedance configuration device of a memory interface, which includes a processing unit coupled to a memory interface, a non-volatile memory and a calibration interface. The processing unit sets a first resistance value of an on-die termination associated with a first receiver to a first default resistance value, sets a second resistance value of a drive variable resistance associated with a second transmitter to a second default resistance value, performs tests for a plurality of test combinations, wherein each combination includes a third resistance value of a drive variable resistance associated with a first transmitter and a fourth resistance value of an on-die termination associated with a second receiver, and stores the test results of each test combination to a specific location of the non-volatile memory, so that a calibration host can obtain the test results of each test combination from the non-volatile memory.

[0006] One of the advantages of the above-mentioned embodiments is that by providing the test results of each test combination to the calibration host, the calibration host can determine the impedance setting of the memory interface accordingly.

[0007] Other advantages of the present application will be described in more detail in conjunction with the following description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0009] Figure 1 A diagram of a calibration system according to an embodiment of the application.

[0010] Figure 2 A block diagram of a calibration system according to an embodiment of the application.

[0011] Figure 3 A graphical user interface for impedance configuration of a memory interface according to an embodiment of the application.

[0012] Figure 4 A flowchart of a training method for a transmitter and a receiver in a memory interface according to an embodiment of the application.

[0013] Figure 5 An initial data representation intent for write training of a DDR4 DRAM according to an embodiment of the application.

[0014] Figure 6 An initial data representation intent for read training of a DDR4 DRAM according to an embodiment of the application.

[0015] Figure 7 A flowchart of a method for write and read training according to an embodiment of the application.

[0016] Figure 8 An example result of write training of a DDR4 DRAM according to an embodiment of the application is shown.

[0017] Figure 9 A flowchart of a method for write training according to an embodiment of the application.

[0018] Legend:

[0019] 130 substrate

[0020] 110 calibration host

[0021] 115 processing unit

[0022] 150 controller

[0023] 170 memory device

[0024] 190 display

[0025] 210 processing unit

[0026] 230 static random access memory

[0027] 250 calibration interface

[0028] 270 memory interface

[0029] 271 physical layer

[0030] 273 ODT gear register

[0031] 275 drive gear register

[0032] 277 MAC layer

[0033] 290 direct memory access controller

[0034] 300 memory calibration graphical user interface

[0035] 310 display block

[0036] 330 selection button

[0037] 335 selection menu

[0038] 350 test progress block

[0039] 370 start button

[0040] 390 test information block

[0041] S410-S470 method steps

[0042] S711-S790 method steps

[0043] 800 block defining a resistance setting at which the device can operate normally

[0044] 800a associated intermediate resistance

[0045] S910-S970 method steps DETAILED DESCRIPTION

[0046] Embodiments of the present application will be described below with reference to the accompanying drawings. In these drawings, like reference numerals indicate like or similar components or method flows.

[0047] It must be appreciated that the terms "comprising", "including", and the like used in the present specification are used to denote the presence of a stated technical feature, numerical value, method step, operation process, component, and / or elements but do not preclude the addition of further technical features, numerical values, method steps, operation processes, components, elements, or any combination thereof.

[0048] The use of words like "first", "second", "third" and the like in this disclosure is used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are not to be construed as limiting.

[0049] It must be noted that, as the term is used herein, the "connection" or "coupling" between components can be direct or through intervening components. Conversely, the term "directly connected" or "directly coupled" between components implies that no intervening components are present. Other words used to describe the relationship between components, such as "between" versus "directly between", or "adjacent" versus "directly adjacent", can be interpreted in a similar manner.

[0050] Referring to Figure 1 The controller 150 and the memory device 170 can be mounted on the substrate 130, and the controller 150 can be coupled or connected to the memory device 170 through the substrate 130. The memory device 370 can be a Dynamic Random Access Memory (DRAM) or the like. The calibration host 110 is coupled to the controller 150 to issue a command requesting the controller 150 to perform the impedance test method, then read the test results from the controller 150, and display the test results on the display 190, so that an engineer can decide impedance configurations in the interface of the controller 150 and the memory device 170 according to the test results. Alternatively, in other embodiments, the calibration host 110 can execute an application program for interpreting the test results and automatically deciding impedance settings in the interface of the controller 150 and the memory device 170 according to an algorithm. Then, the calibration host 110 can issue a command and the decided impedance settings to request the controller 150 to perform the impedance setting method of the memory interface. When the processing unit 210 in the controller 150 loads and executes the relevant firmware or software program code of the impedance setting method of the memory interface, the decided impedance settings are written into the non-volatile storage space in the controller 150 and the memory device 170 as the factory default values.

[0051] Referring to Figure 2The controller 150 includes a processing unit 210, which can be implemented in a variety of ways, such as using a general-purpose hardware (e.g., a single processor, a multi-processor with parallel processing capability, a graphics processor, or other processor with computing capability), and provides the functions described later when executing software and / or firmware instructions of a Mass Production Integrated System Program (MPISP). The controller 150 can include a calibration interface 250, such as an I2C interface, for the calibration host 110 to send commands to the processing unit 210 through the calibration interface 250 to initiate and execute the impedance test and setting method of the memory interface. After calibration is completed, the calibration host 110 can request the Direct Memory Access (DMA) controller to read the test results from the default local of the Static Random Access Memory (SRAM) 230 through the calibration interface 250. The MPISP can be stored in a Read Only Memory (ROM) (not shown) of the controller 150 at the time of factory shipment, or transferred to the controller 150 by the calibration host 110 through the calibration interface 250 or other interfaces before starting calibration. Figure 2

[0052] In some embodiments, the controller 170 can also be referred to as an Application-Specific Integrated Circuit (ASIC)-side, and the memory device 170 can be a DRAM, referred to as a DRAM-side, for buffering data required in the process of executing software and firmware instructions, such as variables, data tables, and various user data. The memory interface 270 can use a Double Data Rate (DDR) communication protocol to communicate with the DRAM, such as a third generation Double Data Rate (DDR3), a Low Power DDR3 (LPDDR3), a fourth generation Double Data Rate (DDR4), or other interfaces. The input and output signals between the memory interface 270 and the DRAM can include reset, CK, CK_N, CKE, ODT, CS_N, ACT_N, BG, BA, A, DM, DQS, DQS_N, DQ_lower, DQ_upper, and the like.

[0053] ​The memory interface 470 can include a physical layer (PHY) 471 having circuitry connected to the memory device 370. The DDR communication protocol and the associated physical layer 471 can provide the capability of communication for transmitting commands, addresses, and data, etc. to and receiving data, addresses, and information, etc. from the memory device 370. The physical layer 471 includes a transmitter and a receiver to transmit signals to the receiver of the memory device 370 and to receive signals from the transmitter of the memory device 370, respectively. The output of the transmitter (which can also be referred to as a driver) can be connected to a variable resistance (which can be referred to as a driving variable resistance) such that the processing unit 210 can adjust the resistance value of the driving variable resistance by changing the setting of the driving-stage register 275, thereby changing the driving strength of the output. On the other hand, the input of the receiver can be connected to a variable resistance (which can be referred to as an ODT variable resistance) such that the processing unit 210 can adjust the impedance of the ODT variable resistance by changing the setting of the on-die termination (ODT)-stage register 275.

[0054] The driving-stage register 275 can store a value of 4 bits, as shown in Table 1:

[0055] Table 1

[0056] Value (decimal) Ztarget (ohms) 0 480 1 240 2 160 3 120 4 96 5 80 6 68.6 7 60 8 53.3 9 48 10 43.6 11 40 12 36.9 13 34.3 14 32 15 30

[0057] For example, when the value stored by the driving-stage register 275 is set to 0, the resistance value of the driving variable resistance is adjusted to 480 ohm. When the value stored by the driving-stage register 275 is set to 1, the resistance value of the driving variable resistance is adjusted to 240 ohm. The rest of the settings change the resistance value of the driving variable resistance in a similar manner, which will not be described in detail for the sake of brevity.

[0058] The ODT-stage register 273 can store a value of 4 bits, as shown in Table 2:

[0059] Table 2

[0060] Value (decimal) Ztarget (ohms) 2 120 5 60 8 40

[0061] For example, when the value stored by the ODT-stage register 273 is set to 2, the resistance value of the driving variable resistance is adjusted to 120 ohm. The rest of the settings change the resistance value of the ODT variable resistance in a similar manner, which will not be described in detail for the sake of brevity.

[0062] In contrast, the memory device 170 can also include variable resistance settings similar to those used to change the output drive strength and ODT impedance. The processing unit 210 can instruct the MAC layer 277 to send a command to the memory device 170 through the physical layer 271 for changing the output drive strength of the transmitter and the ODT impedance of the receiver in the memory device 170.

[0063] When the memory interface 470 communicates with the memory device 170 using the DDR3 communication protocol, the processing unit 210 can instruct the MAC layer 277 to send an output input configuration command (I / O Configuration Command) and a setting value to the memory device 170 through the physical layer 271. The memory interface 470 can instruct the memory device 170 to adjust the resistance of the drive variable resistance therein to a particular level through the A5 and Al signals, as shown in Table 3:

[0064] Table 3

[0065]

[0066]

[0067] Those skilled in the art understand that RZQ is 240 ohm. For example, when the A5 and Al signals are both 0, the memory device 170 adjusts the resistance of the drive variable resistance to 40 ohm (i.e., RZQ / 6). When the A5 and Al signals are 1 and 0, respectively (reserved setting), the memory device 170 can not change the resistance of the drive variable resistance. The rest of the settings for changing the resistance of the drive variable resistance in the memory device 170 can be similarly applied and will not be described in detail for the sake of brevity. In addition, the memory interface 470 can instruct the memory device 170 to adjust the resistance of the ODT variable resistance therein to a particular level through the A9, A6 and A2 signals, as shown in Table 4:

[0068] Table 4

[0069] A9 A6 A2 Rtt_Nom 0 0 0 Not enabled 0 0 1 RZQ / 4 0 1 0 RZQ / 2 0 1 1 RZQ / 6 1 0 0 RZQ / 12 1 0 1 RZQ / 8 1 1 0 Reserved 1 1 1 Reserved

[0070] For example, when the A9, A6 and A2 signals are all 0, the memory device 170 can not enable the ODT. When the A9, A6 and A2 signals are 0, 0 and 1, respectively, the memory device 170 adjusts the resistance of the ODT variable resistance to 60 ohm (i.e., RZQ / 4). When the A9, A6 and A2 signals are 1, 1 and 0, respectively (reserved setting), the memory device 170 can not change the resistance of the drive variable resistance. The rest of the settings for changing the resistance of the ODT variable resistance in the memory device 170 can be similarly applied and will not be described in detail for the sake of brevity.

[0071] When the memory interface 470 communicates with the memory device 170 using the DDR4 communication protocol, the processing unit 210 can instruct the MAC layer 277 to send an I / O configuration command and a set value to the memory device 170 through the physical layer 271. The memory interface 470 can instruct the memory device 170 to adjust the resistance value of the drive variable resistor therein to a specific level through the A5 and A1 signals, as shown in Table 5:

[0072] Table 5

[0073] A5 A1 Output driver resistance 0 0 RZQ / 7 0 1 RZQ / 5 1 0 Reserved (or RZQ / 6) 1 1 Reserved

[0074] The resistance value change details of the drive variable resistor described in Table 5 can refer to the description of Table 3, and will not be described again in order to be brief. In addition, the memory interface 470 can instruct the memory device 170 to adjust the resistance value of the ODT variable resistor therein to a specific level through the A9, A6, and A2 signals, as shown in Table 6:

[0075] Table 6

[0076]

[0077]

[0078] The resistance value change details of the ODT variable resistor described in Table 6 can refer to the description of Table 4, and will not be described again in order to be brief.

[0079] When the memory interface 470 communicates with the memory device 170 using the LPDDR3 communication protocol, the processing unit 210 can instruct the MAC layer 277 to send a mode register write command and a set value to the memory device 170 through the physical layer 271. The memory interface 470 can instruct the memory device 170 to perform an I / O configuration (I / O Configuration) by writing "03H" to MA[7:0] in the mode register, and write a specific value to OP<3:0> in the mode register to instruct the memory device 170 to adjust the resistance value of the drive variable resistor therein to a specific level, as shown in Table 7:

[0080] Table 7

[0081]

[0082]

[0083] For example, when Op<3:0> in the mode register is written as "0010" (default value), the memory device 170 will drive the resistance of the variable resistor to 34.3 ohm (i.e., RZQ / 6). When Op<3:0> in the mode register is written as "1001", the memory device 170 will drive the pull-down resistance of the variable resistor to 34.3 ohm, the pull-up resistance to 40 ohm, and the termination resistance to 240 ohm. When Op<3:0> in the mode register is written as "0000" (reserved value) or other values not listed in Table 7, the memory device 170 can not change the resistance of the drive variable resistor. The rest of the settings for the resistance change of the drive variable resistor in the memory device 170 can be similarly applied and will not be repeated here for brevity.

[0084] In addition, the memory interface 470 can indicate the memory device 170 to perform ODT control by writing "0BH" to MA[7:0] in the mode register, and to adjust the resistance of the ODT variable resistor therein to a specific level by writing a specific value to OP<1:0> in the mode register, as shown in Table 8:

[0085] Table 8

[0086]

[0087]

[0088] For example, when Op<1:0> in the mode register is written as "00" (default value), the memory device 170 can not enable ODT. When Op<1:0> in the mode register is written as "01" (reserved value), the memory device 170 can not change the resistance of the ODT variable resistor. When Op<1:0> in the mode register is written as "10", the memory device 170 will adjust the resistance of the ODT variable resistor to 120 ohm (i.e., RZQ / 2). The rest of the settings for the resistance change of the ODT variable resistor in the memory device 170 can be similarly applied and will not be repeated here for brevity.

[0089] The processing unit 115 in the calibration host 110 can execute a calibration tool, which can provide a human-machine interface to facilitate engineers to configure the impedance of the memory interface. The display 190 displays the configuration of the impedance of the memory interface as shown in Figure 3A graphical user interface (hereinafter calibration GUI) 300 for memory calibration is shown. The calibration GUI 300 can provide a select button 330. When a user clicks the select button 330, the processing unit 115 can execute the On_click() Event Handler of the select button 330 to display a selection menu 335 on the display 190, which contains a plurality of items, each of which is associated with a MPISP, such as a DRAM MPISP, stored in the read-only memory of the controller 150. The display box 310 can display the MPISP decided by the user through the operation of the selection menu 335. The calibration GUI 300 can also provide a start button 370. When a user clicks the start button 370, the processing unit 115 of the calibration host 110 can execute the On_click() Event Handler of the start button 330 to instruct the processing unit 210 of the controller 150 to load and execute the MPISP decided by the user through the calibration interface 250. The calibration host 110 can continuously obtain the test results of the transceivers in the memory interface 270 and the memory device 170 through the calibration interface 250 and the direct memory access controller 290, and can update the contents of the test progress box 350 and the calibration information box 390 accordingly.

[0090] When the processing unit 210 loads and executes the specified MPISP, the calibration host 110 can implement the calibration process as shown in FIG. 4. The calibration host 110 can continuously obtain the test results of the transceivers in the memory interface 270 and the memory device 170 through the calibration interface 250 and the direct memory access controller 290, and can update the contents of the test progress box 350 and the calibration information box 390 accordingly. Figure 4The processing flow is shown. After initializing the memory device 170, the processing unit 210 can execute the instructions of the function vInitDramZQRemapIdx() to initialize the data tables for storing the test results. (Step S410) Next, the processing unit 210 can execute the instructions of the function vScanDramWindow(WrTraining) to perform the memory write training (step S430), and the instructions of the function vScanDramWindow(RdTraining) to perform the memory read training (step S450). Note that although the memory write and read training are implemented in a single function with different input parameters "WrTraining" and "RdTraining" in the embodiments, one skilled in the art can implement the memory write and read training in different functions. In other embodiments, the processing unit 210 can perform the memory read training first, and then perform the memory write training. In other embodiments, the processing unit 210 can not perform the memory read training, and directly set the impedances in the ODT of the receiver of the controller 150 and the driveable resistors of the transmitter of the memory device 170 for memory read to the default values (e.g. the middle range). Finally, the test results are provided to the static random access memory (SRAM) 230 (step S470).

[0091] In step S410, the processing unit 210 can initialize different data tables for the write and read training, respectively, for recording the subsequent test results. Taking the DRAM as an example: the write training data table includes two axes: one axis is associated with the signal strength of the ODT at the DRAM end, arranged from weak to strong or from strong to weak; the other axis is associated with the signal strength of the drive signal at the ASIC end, arranged from weak to strong or from strong to weak. The read training data table includes two axes: one axis is associated with the signal strength of the drive signal at the DRAM end, arranged from weak to strong or from strong to weak; the other axis is associated with the signal strength of the ODT at the ASIC end, arranged from weak to strong or from strong to weak. The purpose of the write training is to optimize the resistance value matching between the driveable resistors at the ASIC end and the ODT at the DRAM end, and the purpose of the read training is to optimize the resistance value matching between the driveable resistors at the DRAM end and the ODT at the ASIC end. Such remapping can help engineers or application algorithms to interpret and more efficiently find the appropriate resistance value range. The initialized data tables can be stored in the SRAM 230.

[0092] Taking the DDR4 DRAM as an example: refer to Figure 5For the convenience of engineers or applications, the size of the write training data table is 16x16 bytes, each byte records the test result when the driving variable resistance of the ASIC side is set to a first resistance value and the ODT of the DRAM side is set to a second resistance value. The cells of the data table can be conceptually divided into a group of 16 bytes. For example, when the driving variable resistance of the ASIC side is set to a specific resistance value (such as 480 ohm), the test result of changing the ODT resistance value of the DRAM side from high to low (such as from not enabling ODT to setting the ODT resistance value to RZQ / 7). Alternatively, when the ODT resistance value of the DRAM side is set to a specific resistance value (RZQ / 1), the test result of changing the resistance value of the driving variable resistance of the ASIC side from high to low (such as from 480 ohm to 30 ohm). Since the ODT gear of the DDR4 DRAM has only 8 gears, the values of the 0h to 7h cells associated with each specific resistance value of the driving variable resistance of the ASIC side (that is, each horizontal row) are initially "0x00", and the values of the 8h to Fh cells are initially "0x05" (which can be called an ignore value) to tell engineers or applications that this test result can be ignored.

[0093] For example, the DDR4 DRAM is taken as an example: reference Figure 6 For the convenience of engineers or applications, the size of the read training data table is 16x16 bytes, each byte records the test result when the driving variable resistance of the DRAM side is set to a first resistance value and the ODT of the ASIC side is set to a second resistance value. The cells of the data table can be conceptually divided into a group of 16 bytes. For example, when the driving variable resistance of the DRAM side is set to a specific resistance value (such as RZQ / 5), the test result of changing the ODT resistance value of the ASIC side from high to low (such as from 120 ohm to 40 ohm). Alternatively, when the ODT resistance value of the ASIC side is set to a specific resistance value (120 ohm), the test result of changing the resistance value of the driving variable resistance of the DRAM side from high to low (such as from RZQ / 5 to RZQ / 7). Since the driving gear of the DDR4 DRAM has only 2 files, the values of the 0h to 1h cells associated with each specific resistance value of the ODT of the ASIC side (that is, each horizontal row) are initially "0x00", and the values of the 2h to Fh cells are initially "0x05". The person skilled in the art can change the ignore value to any value between "0x05" and "0xFF", and the present application is not limited in this regard.

[0094] In some embodiments, the write training details described in step S430 can refer to, for example, Figure 9The method flowchart is shown. This method is implemented by the processing unit 210 when loading and executing the program code of the software or firmware module, including the following steps: setting the resistance value of the ODT associated with the receiver at the ASIC end to the default resistance value (step S910), setting the resistance value of the drive variable resistance associated with the transmitter at the device end to the default resistance value (step S930), performing tests for multiple groups of different test combinations according to a scan sequence, wherein each test combination includes the resistance value of the drive variable resistance associated with the transmitter at the ASIC end and the resistance value of the ODT associated with the receiver at the device end (step S950); and storing the test results of each test combination to a specific location of the SRAM 230, so that the calibration host 110 can obtain the test results of each test combination from the SRAM 230 through the calibration interface 250 (step S970). The details of the scan sequence, test combination, test procedure and test results can be referred to the description in the following paragraphs.

[0095] In other embodiments, the details of the training described in steps S430 and S450 can be referred to as Figure 7 The method flowchart is shown. Whether it is memory write training or read training, the entire process is repeatedly executed in a loop (steps S711 to S790) until all relevant resistance values of the ASIC end and the device end are tested (that is, scanned) (the "yes" path in step S790). The details of the execution of the write training and the read training are described respectively as follows:

[0096] When it is determined to be write training (the "yes" path in step S711), the processing unit 210 can determine the resistance values of the ODT at the ASIC end and the drive variable resistance at the device end to be the default resistance values, and determine the resistance value of the ODT at the device end and the resistance value of the drive variable resistance at the ASIC end according to the scan sequence (step S713). Taking the DDR4 DRAM as an example, the default resistance value of the ODT at the ASIC end can be 60 ohms in Table 2, and the default resistance value of the drive variable resistance at the device end can be RZQ / 5 in Table 5. As for the scan sequence, for example, refer to Figure 5, the processing unit 210 can first fix the ODT resistance of the device end at a certain gear, and then sequentially change the resistance of the driving variable resistance of the ASIC end from 480 ohm to 30 ohm. After all the resistances of the driving variable resistance of the ASIC end are tested, the ODT resistance of the device end is fixed at the next gear and the test is continued. Next, the memory device is initialized (step S730). For example, in the case of DDR4 DRAM, in step S730, the processing unit 410 can change the value of the ODT gear register 273 to the default resistance determined in step S713, and change the driving gear register 275 to the gear determined in step S713 according to the scan order. In addition, the processing unit 410 can instruct the MAC layer 277 to send the output input configuration command and the setting value to the memory device 170 through the physical layer 271, so as to set the resistance of the driving variable resistance of the memory device 170 to the default resistance determined in step S713, and set the ODT resistance of the memory device 170 to the gear determined in step S713 according to the scan order. The storage space of the memory device 170 includes a small piece of test local, in step S730, the memory device 170 can test-write-then-read in the test local, which is also called device end self-training. The memory device 170 can send the information of whether the device end self-training is passed to the processing unit 210 through the memory interface 270. When the device end self-training is not passed (the path of "No" in step S751), the processing unit 210 can store "0x01" to the corresponding storage cell in the write training data table as the test result (step S773).

[0097] To improve the reliability of the test, when the device-side self-training passes (the "Yes" path in step S751), the processing unit 210 can further perform a random read-write test (step S753). In the random read-write test, the processing unit 210 can instruct the MAC layer 277 to write 8 MB of random data pattern data to the memory device 170, and then instruct the MAC layer 277 to read back the data from the memory device 170 and check whether the read-back data is consistent with the previously written data. The processing unit 210 stores the test result to the corresponding storage cell in the write-training data table according to the execution of the random read-write test (step S773). In detail, when a read timeout occurs, the processing unit 210 can store "0x02" to the corresponding storage cell in the write-training data table. When the read-back data is inconsistent with the previously written data, the processing unit 210 can store "0x03" to the corresponding storage cell in the write-training data table. When a write timeout occurs, the processing unit 210 can store "0x04" to the corresponding storage cell in the write-training data table. When the read-back data is consistent with the previously written data, the processing unit 210 can store "0x00" to the corresponding storage cell in the write-training data table, or in other embodiments, can not store any data to the write-training data table because the corresponding storage cell has been initially "0x00".

[0098] When it is determined that the read training (the "No" path in step S711), the processing unit 210 can determine that the resistance values of the drive variable resistors on the ASIC side and the ODT on the device side are the default resistance values, and determine the resistance value levels of the drive variable resistors on the device side and the ODT on the ASIC side according to the scan sequence (step S715). For example, for DDR4 DRAM, the default resistance value of the drive variable resistors on the ASIC side can be 60 ohms in Table 1, and the default resistance value of the ODT on the device side can be RZQ / 4 in Table 6. Regarding the scan sequence, for example, refer to Figure 6, the processing unit 210 can first fix the resistance value of the device-end driving variable resistor to a certain gear, and then sequentially change the ODT resistance value of the ASIC-end from 120 ohm to 40 ohm. After all the ODT resistance values of the ASIC-end are tested, the resistance value of the device-end driving variable resistor is fixed to the next gear and the testing is continued. Then, the memory device is initialized (step S730). The details of the execution of step S730 can refer to the description of the above paragraph, and will not be described herein for the sake of brevity. When the device-end self-training passes (the "Yes" path in step S751), the processing unit 210 can further perform a random read-write test (step S753). The details of the execution of step S753 can refer to the description of the above paragraph, and will not be described herein for the sake of brevity. Then, the processing unit 210 stores the test results to the corresponding storage cells in the read training data table according to the execution of the random read-write test (step S775). In detail, when a read timeout occurs, the processing unit 210 can store "0x02" to the corresponding storage cell in the read training data table. When the read-back data is inconsistent with the previously written data, the processing unit 210 can store "0x03" to the corresponding storage cell in the read training data table. When a write timeout occurs, the processing unit 210 can store "0x04" to the corresponding storage cell in the read training data table. When the read-back data is consistent with the previously written data, the processing unit 210 can store "0x00" to the corresponding storage cell in the read training data table, or in other embodiments, can not store any data to the read training data table because the corresponding storage cell has been initialized to "0x00".

[0099] It can be understood herein that the more error types recorded in the storage cells, the more helpful for the engineers or the program executed by the processing unit 115 to diagnose the impedance matching problem caused by a certain setting.

[0100] In step S470, the processing unit 115 of the calibration host 110 can drive the direct memory access controller 290 to read the content of a certain local part in the SRAM 230 through the calibration interface 250 as the basis for configuring the transceiver of the memory interface. The read content can be displayed on the display 190 for the engineers to refer to when configuring. Referring to Figure 8 According to the example results shown, the engineers or the processing unit 115 can find that when the resistance value of the ASIC-end driving variable resistor is between 60 ohm and 36.9 ohm and the ODT resistance value of the device-end is between RZQ / 1 and RZQ / 5 (as shown in the dashed box 800), the memory interface 270 can operate normally. The engineers or the processing unit 115 can write the gear of the ASIC-end driving variable resistor and ODT resistance value and the gear of the device-end driving variable resistor and ODT resistance value associated with the middle value 800a in the normal local part 800 to the non-volatile storage space in the controller 150 as the factory setting when executing the application program.

[0101] All or part of the steps in the method of the present application can be implemented by a computer program, such as an operating system of a computer, a driver of a specific hardware in the computer, or a software program. In addition, it can also be implemented in other types of programs as shown above. A person skilled in the art can write the method of the embodiments of the present application into a computer program for the sake of simplicity and will not be described herein. The computer program implemented according to the method of the embodiments of the present application can be stored in a suitable computer-readable data carrier, such as a DVD, a CD-ROM, a USB disk, a hard disk, or can be placed in a network server accessible through a network (for example, the Internet, or other suitable carriers).

[0102] Although Figure 2 the above-described components are included in the present application, it is not excluded that more other additional components can be used to achieve better technical effects without violating the spirit of the present application. In addition, although Figure 4 , Figure 7 and Figure 9 the flowcharts are executed in a specified order, a person skilled in the art can modify the order of the steps to achieve the same effects without violating the spirit of the present application, so the present application is not limited to only using the order as described above. In addition, a person skilled in the art can also integrate several steps into one step, or perform more steps in sequence or in parallel in addition to the steps, and the present application is not limited thereto.

[0103] Although the present application is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present application. On the contrary, the present application covers the modifications and similar arrangements obvious to a person skilled in the art. Therefore, the scope of protection of the present application is defined by the scope of the claims.

Claims

1. An impedance configuration device for a memory interface, characterized in that, Include: A memory interface coupled to a memory device and including a first transmitter and a first receiver, wherein the memory device includes a second transmitter and a second receiver; Non-volatile memory; Calibration interface; and A processing unit, coupled to the memory interface, the non-volatile memory, and the calibration interface, is configured to: for a first training program, set a first resistance value associated with an on-chip termination resistor of the first receiver to a first default resistance value, wherein the first receiver is configured to receive signals from a second transmitter in the memory device; for the first training program, set a second resistance value associated with a drive variable resistor of the second transmitter to a second default resistance value, wherein the first transmitter is configured to transmit signals to the second receiver in the memory device; perform tests for a plurality of first test combinations, wherein each first test combination includes a third resistance value and a fourth resistance value, the third resistance value being associated with a drive variable resistor of the first transmitter, and the fourth resistance value being associated with an on-chip termination resistor of the second receiver; and store the test results of each first test combination in a specific location in the non-volatile memory, such that a calibration host can obtain the test results of each first test combination from the non-volatile memory via the calibration interface. The first training procedure comprises multiple loops, each loop corresponding to one of the multiple first test combinations, and includes the following steps: The driving variable resistor of the first transmitter is changed according to the corresponding third resistance value; Based on the corresponding fourth resistance value, the internal termination resistor of the second receiver is changed; and The test is performed when the internal termination resistor of the first receiver is fixed at the first default resistance value and the driving variable resistor of the second transmitter is fixed at the second default resistance value.

2. The impedance configuration device for a memory interface as described in claim 1, characterized in that, The processing unit is configured to receive commands and impedance settings from the calibration host, wherein the impedance settings are determined by the calibration host based on the test results of the first test combination; and to write the impedance settings into the impedance configuration device of the memory interface and the non-volatile storage space of the non-volatile memory as factory default values.

3. The impedance configuration device for a memory interface as described in any one of claims 1 to 2, characterized in that, The test results of the first test combination are stored in a data table, which includes a first axis and a second axis. The first axis is associated with the signal strength of the in-chip termination resistor of the memory device, arranged from weak to strong or from strong to weak. The second axis is associated with the drive signal strength of the memory interface, arranged from weak to strong or from strong to weak.

4. The impedance configuration device for a memory interface as described in claim 3, characterized in that, The data table contains multiple bytes, each byte recording the test results when the drive variable resistor of the memory interface is set to the fifth resistance value and the chip termination resistor of the memory device is set to the sixth resistance value.

5. The impedance configuration device for a memory interface as described in claim 4, characterized in that, When the byte is the first value, it means that the memory device failed to perform a test read / write operation in the test area of ​​the storage space.

6. The impedance configuration device for a memory interface as described in claim 4, characterized in that, When the byte is a second value, it indicates that a read timeout occurred when the processing unit instructed the memory interface to perform a random read / write test; when the byte is a third value, it indicates that a write timeout occurred when the processing unit instructed the memory interface to perform a random read / write test. And when the byte is the fourth value, it means that the data read back during the random read / write test performed by the processing unit on the memory interface is inconsistent with the data previously written.

7. The impedance configuration device for a memory interface as described in claim 1, characterized in that, The processing unit is configured to, for the second training procedure, set a fifth resistance value of the on-chip termination resistor associated with the second receiver to a third default resistance value, wherein the second receiver is configured to receive signals from the first transmitter in the memory interface; set a sixth resistance value of the drive variable resistor associated with the first transmitter to a fourth default resistance value; in the second training procedure, perform tests for a plurality of second test combinations, wherein each second test combination includes a seventh resistance value and an eighth resistance value, the seventh resistance value being associated with the drive variable resistor of the second transmitter, and the eighth resistance value being associated with the on-chip termination resistor of the first receiver, wherein the second transmitter is configured to send signals to the first receiver in the memory interface; and store the test results of each second test combination to a specific location in the non-volatile memory, such that the calibration host can obtain the test results of each second test combination from the non-volatile memory through the calibration interface.

8. The impedance configuration device for a memory interface as described in claim 7, characterized in that, The processing unit is configured to receive commands and impedance settings from the calibration host, wherein the impedance settings are determined by the calibration host based on the test results of the first test combination and the second test combination; and to write the impedance settings into the impedance configuration device of the memory interface and the non-volatile memory as factory default values.

9. The impedance configuration device for a memory interface as described in any one of claims 7 to 8, characterized in that, The test results of the first test combination are stored in a first data table. The first data table includes a first axis and a second axis. The first axis is associated with the signal strength of the on-chip termination resistor of the memory device, arranged from weak to strong or from strong to weak. The second axis is associated with the drive signal strength of the memory interface, arranged from weak to strong or from strong to weak. The test results of the second test combination are stored in a second data table. The second data table includes a third axis and a fourth axis. The third axis is associated with the drive signal strength of the memory device, arranged from weak to strong or from strong to weak. The fourth axis is associated with the signal strength of the on-chip termination resistor of the memory interface, arranged from weak to strong or from strong to weak.

10. The impedance configuration device for a memory interface as described in any one of claims 1, 2, 7 to 8, characterized in that, The memory device is a dynamic random access memory.

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