Semiconductor structure and method of manufacturing the same, memory

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, and a memory. The manufacturing method comprises the following steps: providing a substrate, wherein the substrate has a plurality of parallel gate structures extending along a first direction; the first direction is parallel to the surface of the substrate; forming a plurality of parallel first grooves extending along the first direction between adjacent gate structures; forming a sacrificial layer with a preset depth in the first grooves; the preset depth is less than or equal to the depth of the first grooves; forming a barrier layer covering the sacrificial layer; removing the sacrificial layer from at least one opening position of the first grooves in the first direction to form an air gap.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure and its manufacturing method, and a memory. Background Technology

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and products. Among them, the increasing integration of semiconductor devices has led to a continuous reduction in critical dimension (CD), which has placed higher demands on the related manufacturing processes.

[0003] Random Access Memory (RAM), a type of volatile memory, is a commonly used semiconductor memory device in computers. RAM contains densely packed conductive structures. As the distance between adjacent conductive structures decreases, the parasitic capacitance between these structures increases, leading to increased capacitive coupling. This, in turn, causes delays in electrical signals within the semiconductor device, such as capacitive-resistive delays, ultimately affecting the device's performance. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor structure, a method for manufacturing the same, and a memory.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor structure, the method comprising:

[0006] A substrate is provided having a plurality of mutually parallel gate structures extending along a first direction; the first direction is parallel to the surface of the substrate;

[0007] A plurality of parallel first grooves extending in a first direction are formed between adjacent gate structures;

[0008] A sacrificial layer of a predetermined depth is formed in the first trench; the predetermined depth is less than or equal to the depth of the first trench.

[0009] A barrier layer is formed covering the sacrificial layer;

[0010] The sacrificial layer is removed from at least one opening location of the first trench in the first direction to form an air gap.

[0011] In some embodiments, removing the sacrificial layer from at least one opening location of the first trench in the first direction to form an air gap includes:

[0012] At least one opening communicating with the sacrificial layer is formed from the surface or back side of the substrate;

[0013] The sacrificial layer is removed from the at least one opening to form an air gap.

[0014] In some embodiments, forming at least one opening from the surface or back side of the substrate communicating with the sacrificial layer includes:

[0015] The first trench is etched from the surface or back of the substrate at at least one end in the first direction to expose at least a portion of the sacrificial layer to form at least one opening.

[0016] In some embodiments, forming at least one opening from the surface or back side of the substrate communicating with the sacrificial layer includes:

[0017] The first trench is etched at multiple locations in the first direction from the surface or back of the substrate to expose at least a portion of the sacrificial layer, thereby forming a plurality of spaced openings.

[0018] In some embodiments, the method further includes:

[0019] A protective layer is formed covering the inner wall of the first trench;

[0020] The formation of a sacrificial layer of a predetermined depth in the first trench includes:

[0021] The sacrificial layer is formed in the first trench, whose inner wall is covered by the protective layer.

[0022] In some embodiments, forming a sacrificial layer of a predetermined depth in the first trench includes:

[0023] Fill the first trench with sacrificial material until the sacrificial material covers the surface of the substrate;

[0024] A portion of the sacrificial material is removed from the surface of the substrate, while sacrificial material at a predetermined depth is retained within the first trench to form the sacrificial layer.

[0025] In some embodiments, the barrier layer forming the sacrificial layer includes:

[0026] Fill the first trench in which the sacrificial layer is formed with a barrier material until the barrier material covers the surface of the substrate;

[0027] The barrier material on the surface of the substrate is planarized, and the remaining barrier material is the barrier layer.

[0028] In some embodiments, the method further includes:

[0029] A plurality of mutually parallel second trenches extending along the first direction are formed in the substrate;

[0030] A dielectric layer is formed at the bottom of the second trench;

[0031] A letter line structure is formed that covers the sidewall of the second trench and extends along the first direction;

[0032] A filling material is filled into the second trench where the dielectric layer and the word line structure are formed, to form a filling layer;

[0033] The dielectric layer, the word line structure, and the fill layer constitute the gate structure.

[0034] In some embodiments, the word line structure forming the sidewalls of the second trench and extending along the first direction includes:

[0035] A gate oxide layer is formed covering the two opposite sidewalls of the second trench;

[0036] A gate electrode is formed covering the gate oxide layer.

[0037] On the other hand, embodiments of this application also provide a semiconductor structure, the semiconductor structure comprising:

[0038] Substrate;

[0039] A plurality of mutually parallel gate structures located in the substrate and extending along a first direction; the first direction is parallel to the surface of the substrate;

[0040] A plurality of parallel isolation structures are located between adjacent gate structures and extend along a first direction; each isolation structure has an air gap extending along the first direction and a barrier layer covering the air gap.

[0041] In some embodiments, the isolation structure further includes:

[0042] A protective layer is located on the inner wall of the isolation structure; the space formed by the protective layer and the barrier layer is the air gap.

[0043] In some embodiments, the gate structure includes:

[0044] The dielectric layer is located at the bottom of the gate structure;

[0045] The character line structure covers the sidewall of the gate structure and extends along the first direction;

[0046] A fill layer is located within the gate structure; the fill layer separates the word line structures located on two opposite sidewalls of the gate structure.

[0047] In some embodiments, the word line structure includes:

[0048] A gate oxide layer covering the two opposite sidewalls of the gate structure;

[0049] Gate electrode covering the gate oxide layer.

[0050] In some embodiments, in a direction perpendicular to the surface of the substrate, the depth of the isolation structure is less than or equal to the depth of the gate structure, and the bottom of the isolation structure is lower than the lower end of the gate electrode.

[0051] In some embodiments, in a direction perpendicular to the surface of the substrate, the top of the air gap is higher than or flush with the upper end of the gate electrode, and the bottom of the air gap is lower than or flush with the lower end of the gate electrode.

[0052] This application also provides a memory, including:

[0053] Any of the above semiconductor structures; wherein the portion of the substrate between the gate structure and the isolation structure constitutes the channel pillar of the transistor;

[0054] A storage capacitor is located on the surface of the substrate;

[0055] The bit line structure is located on the back side of the substrate; the storage capacitor is connected to the bit line structure through the channel post.

[0056] The semiconductor structure manufacturing method provided in this application involves forming a sacrificial layer of a predetermined depth in a first trench between adjacent gate structures, and then removing the sacrificial layer through at least one opening in the first trench in a first direction to form an air gap. In this way, on the one hand, by forming a sacrificial layer of a predetermined depth, the position and size of the air gap are controllable and have good uniformity; on the other hand, it reduces the difficulty of sealing the air gap and solves the problem of large parasitic capacitance in highly integrated semiconductor devices. Attached Figure Description

[0057] Figure 1 A flowchart illustrating the steps of a method for manufacturing a semiconductor structure, as provided in this application embodiment;

[0058] Figures 2A to 2I A schematic diagram of the manufacturing process of a semiconductor structure provided in an embodiment of this application;

[0059] Figures 3A to 3E A schematic diagram of the manufacturing process of a gate structure provided in an embodiment of this application;

[0060] Figure 4A and Figure 4B A schematic diagram of the manufacturing process of a word line structure provided in an embodiment of this application;

[0061] Figure 5 This application provides a schematic diagram of a process for forming a protective layer according to an embodiment of the present application.

[0062] Figure 6A and Figure 6B This is a schematic diagram of a process for forming a sacrificial layer, provided in an embodiment of this application.

[0063] Figure 7A and Figure 7B This is a schematic diagram of a process for forming a barrier layer, provided in an embodiment of this application.

[0064] Figures 8A to 8C A schematic diagram of a process for forming an air gap is provided for an embodiment of this application;

[0065] Figure 9 A schematic diagram of a process for forming an opening is provided for an embodiment of this application;

[0066] Figure 10 A schematic diagram of another process for forming an opening, provided for an embodiment of this application;

[0067] Figure 11A and Figure 11B A schematic diagram of a semiconductor structure provided in an embodiment of this application;

[0068] Figure 12 This is a schematic diagram of a protective layer in a semiconductor structure provided in an embodiment of this application;

[0069] Figure 13 A schematic diagram of another semiconductor structure provided in the embodiments of this application;

[0070] Figure 14 This is a partial structural diagram of a memory provided in an embodiment of this application. Detailed Implementation

[0071] To facilitate understanding of this application, exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of the disclosure of this application to those skilled in the art.

[0072] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In some embodiments, to avoid confusion with this application, some technical features well-known in the art are not described; that is, not all features of the actual embodiments may be described herein, nor well-known functions and structures may be described in detail.

[0073] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0074] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0075] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0076] like Figure 1 As shown in the figure, this application provides a method for manufacturing a semiconductor structure, the corresponding structure of which is as follows. Figures 2A to 2I As shown, the manufacturing method includes the following steps:

[0077] Step S10: Provide a substrate 100 having a plurality of mutually parallel gate structures 110 extending along a first direction; the first direction is parallel to the surface of the substrate 100.

[0078] Step S20: Form a plurality of parallel first grooves 120 extending along a first direction between adjacent gate structures 110;

[0079] Step S30: A sacrificial layer 130 of a preset depth is formed in the first trench 120; the preset depth is less than or equal to the depth of the first trench 120.

[0080] Step S40: Form a barrier layer 140 covering the sacrificial layer 130;

[0081] Step S50: Remove the sacrificial layer 130 from at least one opening position of the first trench 120 in the first direction to form an air gap 150.

[0082] In this embodiment, the substrate 100 may be a single-element semiconductor material such as silicon (Si) or germanium (Ge), or a compound semiconductor material such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP). The substrate 100 may also be doped, or may include doped and undoped regions. In some embodiments, the dynamic random access memory (DRAM) is composed of an array of memory cells, and each memory cell includes one transistor and one capacitor, wherein the substrate 100 is used to form multiple transistors arranged in an array in the dynamic random access memory.

[0083] In the embodiments of this application, such as Figure 2A As shown, the substrate 100 has a plurality of parallel gate structures 110 extending along a first direction. The side of the substrate 100 with the gate structures 110 can be used as the surface of the substrate 100, and the side opposite to the surface of the substrate 100 can be used as the back surface of the substrate 100. The first direction is parallel to the surface of the substrate 100 and is consistent with the X-direction. It should be understood that, in order to clearly show all structures, the dimensional proportions of the structures in the figure may not conform to the actual structures.

[0084] In some embodiments, such as Figure 2BAs shown, the depth of the gate structure 110 in the Z direction is less than or equal to the thickness of the substrate 100. The gate electrode 111 in the gate structure 110 can be perpendicular to the surface of the substrate 100, i.e., a vertical gate structure. The portion of the substrate 100 adjacent to the gate structure 110 serves as a vertical channel pillar 101. The channel pillar 101 corresponds to the two ends of the surface and back side of the substrate 100, respectively, for forming the drain (D) and source (S) of the transistor. Thus, the vertical gate electrode 111 results in a smaller transistor area, thereby increasing the density of memory cells per unit area of ​​the substrate 100. In some embodiments, due to the close proximity of adjacent gate structures 110, the parasitic capacitance between the gate structures 110 increases, leading to increased capacitive coupling and problems such as capacitance-resistance delay, ultimately affecting the performance of the semiconductor device.

[0085] In the embodiments of this application, such as Figure 2C and Figure 2D As shown, a plurality of parallel first trenches 120 extending along the X direction are formed between adjacent gate structures 110. The first trenches 120 are used to form air gaps between adjacent gate structures 110 in subsequent processes. These air gaps provide good physical isolation and reduce parasitic capacitance between multiple gate structures 110. Exemplarily, a mask corresponding to the first trenches 120 is formed on the surface of the substrate 100 using photolithography, and then the substrate 100 is etched through the mask using etching to form the first trenches 120 between adjacent gate structures 110. Generally, etching processes can be divided into dry etching and wet etching. Dry etching can include ion milling etching, plasma etching, reactive ion etching, or laser ablation; wet etching uses solvents or solutions, such as acid or alkali solutions, for etching.

[0086] In the embodiments of this application, such as Figure 2D As shown, the depth of the first trench 120 formed by the above process in the Z direction is less than or equal to the depth of the gate structure 110. Therefore, during the subsequent thinning of the back side of the substrate 100, the bottom of the air gap in the first trench 120 is not easily penetrated, thereby reducing defects and failures caused by the air gap being exposed to the external environment.

[0087] In some embodiments, such as Figure 2EAs shown, an air gap 150 is formed in the first trench 120 using a direct sealing method. Direct sealing involves depositing dielectric material directly after the first trench 120 is formed, thus sealing the trench opening. When the depth-to-width ratio of the trench is large, the filling capacity is insufficient to completely fill the trench, easily leading to voids. The air gap 150 can be formed by adjusting the dimensions of the trench and the parameters of the filling process. However, the direct sealing method has many limitations; the size and position of the formed air gap 150 are essentially uncontrollable. Furthermore, due to the large trench opening, the sealing time varies between trenches, resulting in different amounts of material being filled into the trench, leading to poor uniformity of the air gaps 150.

[0088] In the embodiments of this application, such as Figure 2F As shown, a sacrificial layer 130 of a predetermined depth is formed in the first trench 120, and the predetermined depth of the sacrificial layer 130 in the Z direction is less than or equal to the depth of the first trench 120. The sacrificial layer 130 will be removed in a subsequent process to form air gaps. Exemplarily, a sacrificial material is filled into the first trench 120 using a deposition process, and then a portion of the sacrificial material near the surface of the substrate 100 is removed using etching and / or chemical mechanical polishing (CMP) processes to form a sacrificial layer 130 with a predetermined depth. The sacrificial material here is carbon, but it can also be other materials such as silicon nitride. Therefore, by adjusting the parameters of the deposition, etching, and other processes for the sacrificial material, a sacrificial layer 130 of the target size and position can be obtained, making the size and position of the corresponding air gaps formed in the first trench 120 controllable, and ensuring good uniformity among the air gaps. The deposition processes include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0089] In the embodiments of this application, such as Figure 2GAs shown, after a sacrificial layer 130 of a predetermined depth is formed in the first trench 120, a barrier layer 140 is formed to cover the sacrificial layer 130. The barrier layer 140 is used to seal the first trench 120. After the sacrificial layer 130 is removed, the space formed by the barrier layer 140 and the inner wall of the first trench 120 is the air gap. Exemplarily, using a deposition process, a barrier material is filled into the first trench 120 above the sacrificial layer 130 to form the barrier layer 140. Here, the barrier material is silicon oxide, but it can also be other materials. Thus, by forming a barrier layer 140 covering the sacrificial layer 130 for sealing, the time difference in sealing multiple first trenches 120 can be reduced, resulting in good uniformity of the formed air gap. In addition, the embodiments of this application can further reduce the size of the trench opening of the first trench 120, reducing the process difficulty of manufacturing the air gap.

[0090] In the embodiments of this application, such as Figure 2H As shown, the sacrificial layer 130 is removed from at least one opening in the first trench 120 in the X direction to form an air gap 150. Exemplarily, to remove the sacrificial layer 130 within the first trench 120 after forming the barrier layer 140, the first trench 120 can be etched at a corresponding position on the surface or back side of the substrate 100 to form at least one opening 102 exposing a portion of the sacrificial layer 130 from the surface or back side of the substrate 100. The sacrificial layer 130 is then removed through the opening 102 to form the air gap 150. If the sacrificial layer 130 is carbon, an ashing process is used to remove the sacrificial layer 130 from the at least one opening 102. Alternatively, etching or other processes can be used to remove the sacrificial layer 130. The final structure of the air gap 150 in the YZ section is as follows. Figure 2I As shown. Thus, by forming openings of controllable number, size, and position on the surface or back of the substrate 100, the sacrificial layer 130 can be effectively removed, reducing sacrificial material residue and simplifying the fabrication process of the air gap 150.

[0091] In some embodiments, such as Figures 3A to 3E As shown, the method further includes:

[0092] A plurality of mutually parallel second trenches 160 extending along the first direction are formed in the substrate 100;

[0093] A dielectric layer 161 is formed at the bottom of the second trench 160;

[0094] A letter line structure 162 is formed that covers the sidewall of the second groove 160 and extends along the first direction;

[0095] An insulating material is filled into the second trench 160, in which the dielectric layer 161 and the word line structure 162 are formed, to form a filling layer 163;

[0096] The dielectric layer 161, the word line structure 162, and the fill layer 163 constitute the gate structure 110.

[0097] In the embodiments of this application, such as Figure 3A As shown, a plurality of mutually parallel second trenches 160 extending along the X direction are formed on the surface of the substrate 100. The second trenches 160 are used to form the gate structure 110. Figure 3B As shown, the depth of the second trench 160 in the Z direction is less than the thickness of the substrate 100. Exemplarily, a mask corresponding to the second trench 160 is formed on the surface of the substrate 100 using a photolithography process, and then the substrate 100 is etched through the mask using an etching process to form the second trench 160. It is worth noting that after forming the second trench 160, an oxide layer can also be formed on the inner wall of the second trench 160 to serve as the gate oxide layer in the word line structure 162.

[0098] In the embodiments of this application, such as Figure 3C As shown, a dielectric layer 161 is formed at the bottom of a second trench 160 on which a gate oxide layer is formed on the inner wall. Exemplarily, the dielectric layer 161 is formed at the bottom of the second trench 160 by a process such as deposition. The dielectric layer 161 is used to prevent leakage current from the bottom of the gate structure 110. Furthermore, during subsequent thinning of the substrate 100 from the back side of the substrate 100, the dielectric layer 161 can also serve as a stop layer to prevent damage to the gate structure 110 and the air gap during thinning. The material of the dielectric layer 161 can be silicon nitride (Si3N4), or other dielectric materials such as silicon oxide (SiO2), spin-on dielectrics (SOD), silicon oxynitride (SiON), etc.

[0099] In the embodiments of this application, such as Figure 3D As shown, a word line structure 162 is formed covering the sidewalls of the second trench 160 and extending along the X direction. Exemplarily, the word line structure 162 is formed on the sidewalls of the second trench 160 by a process such as deposition. The word line structure 162 may include a gate electrode and the aforementioned gate oxide layer. The gate oxide layer may be a material such as silicon oxide; the gate electrode may be a conductive material, including but not limited to one or more of tungsten (W), titanium nitride (TiN), copper (Cu), and silver (Ag). Thus, the vertical gate electrode results in a smaller transistor footprint, thereby increasing the density of memory cells per unit area of ​​the substrate 100.

[0100] In the embodiments of this application, such as Figure 3EAs shown, a filling layer 163 is formed by filling an insulating material into a second trench 160, where a dielectric layer 161 and word line structures 162 are formed; wherein the dielectric layer 161, word line structures 162, and filling layer 163 constitute a gate structure 110. Exemplarily, the filling layer 163 is formed by filling the second trench 160 with an insulating material through a process such as deposition. The filling layer 163 serves to separate the word line structures 162 located on two opposite sidewalls of the second trench 160, thereby preventing short circuits between two word line structures 162 located in the same gate structure 110. The insulating material here includes, but is not limited to, silicon oxide, spin-coated insulating dielectric, silicon nitride, silicon oxynitride, etc.

[0101] In some embodiments, such as Figure 4A and Figure 4B As shown, the letter line structure 162, which forms a line covering the sidewall of the second groove 160 and extends along the first direction, includes:

[0102] A gate oxide layer 112 is formed covering the two opposite sidewalls of the second trench 160;

[0103] A gate electrode 111 is formed covering the gate oxide layer 112.

[0104] In the embodiments of this application, such as Figure 4A As shown, a gate oxide layer 112 is formed on two opposing sidewalls of the second trench 160. Exemplarily, a gate oxide layer 112 of the target thickness is formed on the sidewalls of the second trench 160 by a thermal oxidation process, such as in-situ steam generation (ISSG) or rapid thermal oxidation (RTO). It is understood that, to simplify the process, the gate oxide layer 112 can also be formed on the inner wall of the second trench 160, where the inner wall includes the sidewalls and bottom surface of the second trench 160.

[0105] In the embodiments of this application, such as Figure 4B As shown, a gate electrode 111 is formed covering the gate oxide layer 112. It is worth noting that the gate electrode 111 can be formed after the dielectric layer 161. Exemplarily, the gate electrode 111 is formed on the gate oxide layer 112 by a process such as deposition; the gate electrode 111 can be a conductive material, including but not limited to one or more of tungsten, titanium nitride, copper, and silver. In the Z-direction, the top of the gate electrode 111 can be lower than the surface of the substrate 100, and the bottom of the gate electrode 111 can be higher than the bottom surface of the second trench 160, thereby reducing the occurrence of problems such as leakage current and short circuits.

[0106] In some embodiments, such as Figure 5 As shown, the method further includes:

[0107] A protective layer 170 is formed covering the inner wall of the first trench 120;

[0108] The formation of a sacrificial layer 130 of a predetermined depth in the first trench 120 includes:

[0109] The sacrificial layer 130 is formed in the first trench 120, whose inner wall is covered by the protective layer 170.

[0110] In the embodiments of this application, such as Figure 5 As shown, before forming the sacrificial layer 130 of a predetermined depth in the first trench 120, a protective layer 170 can be formed on the inner wall of the first trench 120 using processes such as deposition. The protective layer 170 is a thin, dense oxide layer to protect the substrate 100 from oxidation during subsequent processing. Exemplarily, the protective layer 170 is formed on the inner wall of the first trench 120 using an atomic layer deposition process. Here, the protective layer 170 can be silicon oxide or other materials.

[0111] The sacrificial layer 130 can be formed in the first groove 120, whose inner wall is covered by the protective layer 170. Thus, after the sacrificial layer 130 is removed, the protective layer 170 serves as the inner wall of the cavity for the air gap, resulting in a more uniform shape for the air gap, i.e., the width of the air gap is basically the same at all positions in the Z direction.

[0112] In some embodiments, such as Figure 6A and Figure 6B As shown, forming a sacrificial layer 130 of a predetermined depth in the first trench 120 includes:

[0113] The first trench 120 is filled with sacrificial material until the sacrificial material covers the surface of the substrate 100;

[0114] A portion of the sacrificial material is removed from the surface of the substrate 100, while sacrificial material at a predetermined depth is retained within the first trench 120 to form the sacrificial layer 130.

[0115] In the embodiments of this application, such as Figure 6A As shown, a sacrificial material can be filled into the first trench 120 using processes such as deposition until the sacrificial material covers the surface of the substrate 100. For the sacrificial material to completely fill the first trench 120, the deposition thickness of the sacrificial material needs to be greater than or equal to the depth of the first trench 120. The sacrificial material here is carbon, but it can also be other materials such as silicon nitride. Exemplarily, carbon is deposited in the first trench 120 until the carbon covers the surface of the substrate 100. The deposition process here includes, but is not limited to, one or more of chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

[0116] In the embodiments of this application, such as Figure 6B As shown, a portion of the sacrificial material is removed from the surface of the substrate 100, leaving a sacrificial material at a predetermined depth within the first trench 120 to form a sacrificial layer 130. Exemplarily, a process such as etching is used to remove a portion of the sacrificial material, leaving a sacrificial material at a predetermined depth within the first trench 120, thereby forming the sacrificial layer 130, wherein the predetermined depth is less than or equal to the depth of the first trench 120. This process allows for the adjustment of the sacrificial material removal rate and time to obtain a sacrificial layer 130 with a controllable predetermined depth, thereby adjusting the final position of the air gap and making the position of the air gap controllable.

[0117] In some embodiments, such as Figure 7A and Figure 7B As shown, the barrier layer 140 forming the barrier layer 140 covering the sacrificial layer 130 includes:

[0118] The first trench 120, in which the sacrificial layer 130 is formed, is filled with a barrier material until the barrier material covers the surface of the substrate 100;

[0119] The barrier material on the surface of the substrate 100 is planarized, and the remaining barrier material is the barrier layer 140.

[0120] In the embodiments of this application, such as Figure 7A As shown, a barrier material can be filled into the first trench 120, where a sacrificial layer 130 of a predetermined depth is formed, using processes such as deposition, until the barrier material covers the surface of the substrate 100. To ensure that the barrier material completely seals the trench opening of the first trench 120, the deposition height of the barrier material needs to be higher than the surface of the substrate 100. The barrier material here is silicon oxide, but other materials may also be used. Exemplarily, silicon oxide is deposited above the sacrificial layer 130 in the first trench 120 until the silicon oxide covers the surface of the substrate 100. The deposition process here includes, but is not limited to, one or more of chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

[0121] In the embodiments of this application, such as Figure 7B As shown, the surface of substrate 100 can be planarized using processes such as chemical mechanical polishing to remove excess barrier material. Specifically, firstly, a portion of the barrier material on the surface of substrate 100 undergoes a chemical reaction with oxidants, catalysts, etc., in the polishing slurry to generate a relatively easy-to-remove soft layer. Then, the soft layer is removed by the mechanical action of abrasives and a polishing pad in the polishing slurry. Repeating these steps, the surface of substrate 100 is planarized through the combined action of chemical reaction and mechanical polishing, and the remaining barrier material is the barrier layer 140.

[0122] It is understood that, compared with the direct sealing method of the trench in the above embodiments, the present application embodiment seals the trench by forming a barrier layer 140 covering the sacrificial layer 130, which can reduce the time difference in sealing multiple first trenches 120 and make the formed air gap have good uniformity. In addition, the present application embodiment can further reduce the size of the trench opening of the first trench 120, reducing the process difficulty of making the air gap.

[0123] In some embodiments, such as Figures 8A to 8C As shown, removing the sacrificial layer 130 from at least one opening location of the first trench 120 in the first direction to form an air gap 150 includes:

[0124] At least one opening 102 communicating with the sacrificial layer 130 is formed from the surface or back of the substrate 100;

[0125] The sacrificial layer 130 is removed from the at least one opening 102 to form an air gap 150.

[0126] In the embodiments of this application, such as Figure 8A As shown, in order to remove the sacrificial layer 130 within the first trench 120 after the formation of the barrier layer 140, the first trench 120 can be etched at a corresponding position on the surface or back side of the substrate 100 to form at least one opening 102 exposing a portion of the sacrificial layer 130 from the surface or back side of the substrate 100. Taking the formation of the opening 102 from the surface of the substrate 100 as an example, firstly, a photolithography process is used to form a mask corresponding to the opening 102 on the surfaces of the substrate 100 and the barrier layer 140. Then, an etching process is used to etch through the mask, removing a portion of the substrate 100 and the barrier layer 140, forming the opening 102 communicating with the sacrificial layer 130. It can be understood that through the above patterning and etching processes, openings 102 of controllable shape and size can be formed at multiple locations to facilitate the removal of the sacrificial layer 130.

[0127] In the embodiments of this application, such as Figure 8B As shown, the sacrificial layer 130 is removed through at least one opening 102 to form an air gap 150. Exemplarily, if the sacrificial layer 130 is carbon, an ashing process is used to remove the sacrificial layer 130 from the at least one opening 102. Alternatively, other processes such as etching can also be used to remove the sacrificial layer 130. The final structure of the air gap 150 in the YZ section is as follows. Figure 8C As shown, by forming openings 102 of controllable number, size and position on the surface or back of the substrate 100, the sacrificial layer 130 can be effectively removed, reducing sacrificial material residue and simplifying the fabrication process of the air gap 150.

[0128] In some embodiments, such as Figure 9 As shown, forming at least one opening 102 from the surface or back side of the substrate 100 communicating with the sacrificial layer 130 includes:

[0129] The first trench 120 is etched from the surface or back of the substrate 100 at at least one end in the first direction to expose at least a portion of the sacrificial layer 130 to form at least one opening 102.

[0130] In the embodiments of this application, such as Figure 9 As shown, at least one end of the first trench 120 in the X direction is etched from the surface or back side of the substrate 100 to form at least one opening 102, through which at least a portion of the sacrificial layer 130 is exposed. When the length of the first trench 120 in the X direction is small, it is only necessary to form the opening 102 at one or both ends of the first trench 120 in the X direction to completely remove the sacrificial layer 130 within the first trench 120.

[0131] Taking the formation of an opening 102 from the surface of substrate 100 as an example, firstly, a photolithography process is used to form a mask corresponding to the opening 102 on the surfaces of substrate 100 and barrier layer 140. The position of the opening 102 in the mask is set at one or both ends of barrier layer 140 in the X direction. Then, an etching process is used to etch through the mask to remove part of substrate 100 and barrier layer 140, forming an opening 102 that connects to sacrificial layer 130. It can be understood that through the above patterning and etching process, an opening 102 of controllable shape and size can be formed at one or both ends of the first trench 120 to facilitate the removal of sacrificial layer 130.

[0132] In some embodiments, such as Figure 10 As shown, forming at least one opening 102 from the surface or back side of the substrate 100 communicating with the sacrificial layer 130 includes:

[0133] The first trench 120 is etched at multiple locations in the first direction from the surface or back side of the substrate 100 to expose at least a portion of the sacrificial layer 130, thereby forming a plurality of spaced openings 102.

[0134] In the embodiments of this application, such as Figure 10 As shown, the first trench 120 is etched at multiple locations in the X direction from the surface or back side of the substrate 100 to form multiple spaced openings 102, through which at least a portion of the sacrificial layer 130 is exposed. When the length of the first trench 120 in the X direction is large, it is necessary to form openings 102 at multiple locations in the first trench 120 along the X direction in order to completely remove the sacrificial layer 130 within the first trench 120.

[0135] Taking the formation of openings 102 from the surface of substrate 100 as an example, firstly, a photolithography process is used to form multiple masks corresponding to the openings 102 on the surfaces of substrate 100 and barrier layer 140. The positions corresponding to the multiple openings 102 in the mask are spaced apart along the X direction on barrier layer 140. Then, an etching process is used to etch through the mask to remove parts of substrate 100 and barrier layer 140, forming openings 102 that connect to sacrificial layer 130. It can be understood that through the above patterning and etching process, openings 102 of controllable shape and size can be formed at multiple locations in the first trench 120 to facilitate the removal of sacrificial layer 130.

[0136] like Figure 11A and Figure 11B As shown in the embodiments of this application, a semiconductor structure is also provided, the semiconductor structure comprising:

[0137] Substrate 200;

[0138] A plurality of mutually parallel gate structures 210 are located in the substrate 200 and extend along a first direction; the first direction is parallel to the surface of the substrate 200.

[0139] A plurality of parallel isolation structures 220 are located between adjacent gate structures 210 and extend along a first direction; each isolation structure 220 has an air gap 250 extending along the first direction and a barrier layer 240 covering the air gap.

[0140] In the embodiments of this application, the substrate 200 may be a single semiconductor material such as silicon or germanium, or a compound semiconductor material such as gallium nitride, gallium arsenide, or indium phosphide; the substrate 200 may also be doped, or may include doped regions and undoped regions in the substrate.

[0141] In the embodiments of this application, such as Figure 11A As shown, the substrate 200 has a plurality of parallel gate structures 210 extending along a first direction. The side of the substrate 200 with the gate structures 210 can be used as the surface of the substrate 200, and the side opposite to the surface of the substrate 200 can be used as the back surface of the substrate 200. The first direction is parallel to the surface of the substrate 200 and is consistent with the X direction.

[0142] In the embodiments of this application, such as Figure 11BAs shown, the depth of the gate structure 210 in the Z direction is less than or equal to the thickness of the substrate 200. The gate electrode in the gate structure 210 can be perpendicular to the surface of the substrate 200, i.e., a vertical gate structure. The portion of the substrate 200 adjacent to the gate structure 210 serves as a vertical channel pillar 201. The channel pillar 201 corresponds to the two ends of the surface and back side of the substrate 200, respectively, for forming the drain D and source S of the transistor. Thus, the vertical gate structure allows the transistor to occupy a smaller area, resulting in a higher density of memory cells per unit area of ​​the substrate 200.

[0143] In the embodiments of this application, such as Figure 11B As shown, the substrate 200 also includes several parallel isolation structures 220 located between adjacent gate structures 210 and extending along the X direction. The isolation structures 220 separate two channel pillars 201 located between adjacent gate structures 210. Each isolation structure 220 includes a barrier layer 240 on top of the isolation structure 220. The barrier layer 240 is made of silicon oxide, but other materials may also be used. The space formed by the barrier layer 240 and the inner walls of the isolation structures 220 is an air gap 250. The air gap 250 extends along the X direction and provides good physical isolation, reducing parasitic capacitance between multiple gate structures 210. Each air gap 250 exhibits good uniformity, and the width of each air gap 250 is substantially the same at all positions in the Z direction. Furthermore, the position, size, and shape of the air gap 250 within the isolation structure 220 can be adjusted according to the manufacturing method in other embodiments.

[0144] In some embodiments, such as Figure 12 As shown, the isolation structure 220 further includes:

[0145] The protective layer 270 is located on the inner wall of the isolation structure 220; the space formed by the protective layer 270 and the barrier layer 240 is the air gap 250.

[0146] In the embodiments of this application, such as Figure 12 As shown, the inner wall of the isolation structure 220 has a protective layer 270. The protective layer 270 is a thin, dense oxide layer to protect the substrate 200 from oxidation during the formation of the air gap 250. The protective layer 270 can be silicon oxide or other materials. It is understood that the space formed by the protective layer 270 and the barrier layer 240 is the air gap 250.

[0147] In some embodiments, such as Figure 13 As shown, the gate structure 210 includes:

[0148] Dielectric layer 261 is located at the bottom of the gate structure 210;

[0149] The character line structure 262 covers the sidewall of the gate structure 210 and extends along the first direction;

[0150] A filler layer 263 is located within the gate structure 210; the filler layer 263 separates the word line structures 262 located on two opposite sidewalls of the gate structure 210.

[0151] In the embodiments of this application, such as Figure 13 As shown, dielectric layer 261 is located at the bottom of gate structure 210. Dielectric layer 261 is used to prevent leakage current from occurring at the bottom of gate structure 210. The material of dielectric layer 261 can be silicon nitride or other dielectric materials, such as silicon oxide, spin-coated insulating dielectric, silicon oxynitride, etc. In some embodiments, since the back side of substrate 200 needs to be thinned when forming structures such as capacitors and bit lines, dielectric layer 261 can also serve as a thinning stop layer to prevent damage to gate structure 210 during thinning.

[0152] In the embodiments of this application, such as Figure 13 As shown, the word line structure 262 covers the sidewall of the gate structure 210 and extends along the X direction. Since the word line structure 262 is located on the sidewall of the gate structure 210, i.e., a vertical gate structure, the direction of the transistor is consistent with the Z direction, the transistor occupies a smaller area, and therefore the density of memory cells in the substrate 200 per unit area is greater.

[0153] In the embodiments of this application, such as Figure 13 As shown, the fill layer 263 is located within the gate structure 210 and separates the word line structures 262 located on two opposite sidewalls of the gate structure 210. The fill layer 263 is used to prevent short circuits between two word line structures 262 located in the same gate structure 210. The material of the fill layer 263 includes, but is not limited to, silicon oxide, spin-coated insulating dielectric, silicon nitride, silicon oxynitride, etc.

[0154] In some embodiments, such as Figure 13 As shown, the word line structure 262 includes:

[0155] Gate oxide layer 212 covering the two opposite sidewalls of the gate structure 210;

[0156] Gate electrode 211 covering the gate oxide layer 212.

[0157] In the embodiments of this application, such as Figure 13 As shown, the word line structure 262 also includes a gate oxide layer 212 covering the two opposite sidewalls of the gate structure 210. The gate oxide layer 212 can be formed by a thermal oxidation process.

[0158] In the embodiments of this application, such as Figure 13As shown, the gate electrode 211 covers the gate oxide layer 212. The gate electrode 211 can be a conductive material, including but not limited to one or more of tungsten, titanium nitride, copper, and silver. In the Z direction, the top of the gate electrode 211 can be lower than the surface of the substrate 200, thereby reducing the occurrence of problems such as leakage current and short circuits.

[0159] In some embodiments, such as Figure 13 As shown, in a direction perpendicular to the surface of the substrate 200, the depth of the isolation structure 220 is less than or equal to the depth of the gate structure 210, and the bottom of the isolation structure 220 is lower than the lower end of the gate electrode 211.

[0160] In the embodiments of this application, such as Figure 13 As shown, in the Z direction, the depth of the isolation structure 220 is less than or equal to the depth of the gate structure 210. Since the back side of the substrate 200 will form structures such as capacitors and bit lines in subsequent processes, it needs to be thinned. When the depth of the isolation structure 220 is greater than the depth of the gate structure 210, excessive thinning can damage the isolation structure 220 and even expose the air gap 250 to the external environment, leading to defects and failures. Therefore, the depth of the isolation structure 220 in the Z direction is less than or equal to the depth of the gate structure 210. On the other hand, to ensure the isolation effect of the isolation structure 220 between adjacent gate electrodes 211, the bottom of the isolation structure 220 needs to be lower than the bottom of the gate electrode 211; that is, in the Z direction, the length of the isolation structure 220 is greater than the length of the gate electrode 211.

[0161] In some embodiments, such as Figure 13 As shown, in a direction perpendicular to the surface of the substrate 200, the top of the air gap 250 is higher than or flush with the upper end of the gate electrode 211, and the bottom of the air gap 250 is lower than or flush with the lower end of the gate electrode 211.

[0162] In the embodiments of this application, such as Figure 13 As shown, in the Z direction, the top of the air gap 250 is higher than or flush with the upper end of the gate electrode 211, and the bottom of the air gap 250 is lower than or flush with the lower end of the gate electrode 211. To ensure the isolation effect of the air gap 250 and effectively reduce the parasitic capacitance between adjacent gate electrodes 211, the projection of the gate electrode 211 in the Y direction needs to fall completely within the air gap 250, that is, the top of the air gap 250 is not lower than the upper end of the gate electrode 211, and the bottom of the air gap 250 is not higher than the lower end of the gate electrode 211.

[0163] like Figure 14 As shown in the embodiments of this application, a memory is also provided, the memory comprising:

[0164] Substrate 300;

[0165] A plurality of mutually parallel gate structures 310 are located in the substrate 300 and extend along a first direction; the first direction is parallel to the surface of the substrate 300.

[0166] A plurality of parallel isolation structures 320 are located between adjacent gate structures 310 and extend along a first direction; each isolation structure 320 has an air gap 350 extending along the first direction and a barrier layer 340 covering the air gap.

[0167] The portion of the substrate 300 between the gate structure 310 and the isolation structure 320 constitutes the channel pillar 301 of the transistor.

[0168] Storage capacitor 380 is located on the surface of substrate 300;

[0169] Bit line structure 390 is located on the back side of the substrate 300; the storage capacitor 380 is connected to the bit line structure 390 through the channel post 301.

[0170] In the embodiments of this application, such as Figure 14 As shown, the portion of substrate 300 located between gate structure 310 and isolation structure 320 serves as the channel pillar 301 of the transistor. The channel pillar 301 has a drain (D) and a source (S) at its two ends corresponding to the surface and back side of the substrate 300, respectively. Therefore, the vertical channel pillar 301 results in a smaller transistor area, thus allowing for a higher density of memory cells per unit area of ​​substrate 300.

[0171] In this embodiment, at least one storage capacitor 380 is located on the surface of the substrate 300, while the bit line structure 390 is located on the back side of the substrate 300. It is understood that the storage capacitor 380 can be located on either the surface or the back side of the substrate 300, while the bit line structure 390 only needs to be located on the opposite side of the storage capacitor 380. When the gate electrode in the gate structure 310 controls the conduction between the source S and the drain D, the bit line structure 390 performs data reading and writing operations on the storage capacitor 380.

[0172] In this embodiment, the air gap 350 extends along the X direction and provides good physical isolation. While isolating adjacent channel posts 301, the air gap 350 also reduces parasitic capacitance between multiple gate structures 310. Each air gap 350 exhibits good uniformity, and the width of the air gap 350 is substantially the same at all positions along the Z direction. Furthermore, the position, size, and shape of the air gap 350 within the isolation structure 320 can be adjusted according to the manufacturing method in other embodiments.

[0173] In some embodiments, such as Figure 14 As shown, the gate structure 310 further includes: a dielectric layer 361 located at the bottom of the gate structure 310; a word line structure 362 covering the sidewalls of the gate structure 310 and extending along the first direction; and a fill layer 363 located within the gate structure 310. The fill layer 363 separates the word line structures 362 located on two opposite sidewalls of the gate structure 310. The word line structure 362 includes: a gate oxide layer 312 covering the two opposite sidewalls of the gate structure 310; and a gate electrode 311 covering the gate oxide layer 312.

[0174] In some embodiments, such as Figure 14 As shown, the isolation structure 320 also includes a protective layer 370 located on the inner wall of the isolation structure 320; the space formed by the protective layer 370 and the barrier layer 340 is an air gap 350.

[0175] It should be noted that the embodiments provided in this application can be applied to random access memory (RAM), such as dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change random access memory (PCRAM), magnetic random access memory (MRAM), etc.; and can also be applied to other semiconductor devices.

[0176] It should be noted that the features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0177] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, The method includes: A substrate is provided having a plurality of mutually parallel gate structures extending along a first direction; the first direction is parallel to the surface of the substrate; A plurality of parallel first grooves extending in a first direction are formed between adjacent gate structures; A sacrificial layer of a predetermined depth is formed in the first trench; the predetermined depth is less than or equal to the depth of the first trench. A barrier layer is formed covering the sacrificial layer; The sacrificial layer is removed from at least one opening location of the first trench in the first direction to form an air gap.

2. The method according to claim 1, characterized in that, Removing the sacrificial layer from at least one opening location of the first trench in the first direction to form an air gap includes: At least one opening communicating with the sacrificial layer is formed from the surface or back side of the substrate; The sacrificial layer is removed from the at least one opening to form an air gap.

3. The method according to claim 2, characterized in that, The formation of at least one opening from the surface or back of the substrate communicating with the sacrificial layer includes: The first trench is etched from the surface or back of the substrate at at least one end in the first direction to expose at least a portion of the sacrificial layer to form at least one opening.

4. The method according to claim 2, characterized in that, The formation of at least one opening from the surface or back of the substrate communicating with the sacrificial layer includes: The first trench is etched at multiple locations in the first direction from the surface or back of the substrate to expose at least a portion of the sacrificial layer, thereby forming a plurality of spaced openings.

5. The method according to claim 1, characterized in that, The method further includes: A protective layer is formed covering the inner wall of the first trench; The formation of a sacrificial layer of a predetermined depth in the first trench includes: The sacrificial layer is formed in the first trench, whose inner wall is covered by the protective layer.

6. The method according to claim 1, characterized in that, The step of forming a sacrificial layer of a predetermined depth in the first trench includes: Fill the first trench with sacrificial material until the sacrificial material covers the surface of the substrate; A portion of the sacrificial material is removed from the surface of the substrate, while sacrificial material at a predetermined depth is retained within the first trench to form the sacrificial layer.

7. The method according to claim 1, characterized in that, The barrier layer forming the sacrificial layer includes: Fill the first trench in which the sacrificial layer is formed with a barrier material until the barrier material covers the surface of the substrate; The barrier material on the surface of the substrate is planarized, and the remaining barrier material is the barrier layer.

8. The method according to claim 1, characterized in that, The method further includes: A plurality of mutually parallel second trenches extending along the first direction are formed in the substrate; A dielectric layer is formed at the bottom of the second trench; A letter line structure is formed that covers the sidewall of the second trench and extends along the first direction; A filling material is filled into the second trench where the dielectric layer and the word line structure are formed, to form a filling layer; The dielectric layer, the word line structure, and the fill layer constitute the gate structure.

9. The method according to claim 8, characterized in that, The word line structure forming the sidewalls of the second trench and extending along the first direction includes: A gate oxide layer is formed covering the two opposite sidewalls of the second trench; A gate electrode is formed covering the gate oxide layer.

10. A semiconductor structure, characterized in that, include: Substrate; A plurality of mutually parallel gate structures located in the substrate and extending along a first direction; The first direction is parallel to the surface of the substrate; wherein the gate structure includes: a dielectric layer located at the bottom of the gate structure; a word line structure covering the sidewalls of the gate structure and extending along the first direction; and a fill layer located within the gate structure; the fill layer separates the word line structures located on two opposite sidewalls of the gate structure; A plurality of parallel isolation structures are located between adjacent gate structures and extend along a first direction; each isolation structure has an air gap extending along the first direction and a barrier layer covering the air gap.

11. The semiconductor structure according to claim 10, characterized in that, The isolation structure also includes: A protective layer is located on the inner wall of the isolation structure; the space formed by the protective layer and the barrier layer is the air gap.

12. The semiconductor structure according to claim 11, characterized in that, The word line structure includes: A gate oxide layer covering the two opposite sidewalls of the gate structure; Gate electrode covering the gate oxide layer.

13. The semiconductor structure according to claim 12, characterized in that, In a direction perpendicular to the surface of the substrate, the depth of the isolation structure is less than or equal to the depth of the gate structure, and the bottom of the isolation structure is lower than the lower end of the gate electrode.

14. The semiconductor structure according to claim 12, characterized in that, In a direction perpendicular to the surface of the substrate, the top of the air gap is higher than or flush with the upper end of the gate electrode, and the bottom of the air gap is lower than or flush with the lower end of the gate electrode.

15. A memory, characterized in that, include: The semiconductor structure according to any one of claims 10 to 14; wherein the portion of the substrate between the gate structure and the isolation structure constitutes a channel pillar of a transistor; A storage capacitor is located on the surface of the substrate; The bit line structure is located on the back side of the substrate; the storage capacitor is connected to the bit line structure through the channel post.

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