Phase change memory and preparation method thereof

Abstract

An embodiment of the present disclosure provides a phase change memory and a preparation method thereof, wherein the phase change memory includes a first conductive line, a first memory cell, a second conductive line, a second memory cell, and a third conductive line stacked in sequence along a first direction; wherein the first conductive line and the third conductive line extend along a second direction, and the second conductive line extends along a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other; the first memory cell includes a first bottom electrode, a first gating layer, a first intermediate electrode, a first phase change memory layer, and a first top electrode stacked in sequence along the first direction; the second memory cell includes a second bottom electrode, a second gating layer, a second intermediate electrode, a second phase change memory layer, and a second top electrode stacked in sequence along the first direction; wherein the second phase change memory layer and the first phase change memory layer have different materials and / or thicknesses, and the threshold voltages of the second memory cell and the first memory cell are substantially the same.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a phase change memory and a preparation method thereof. Background Art

[0002] As electronic devices continue to increase their demands for integration and data storage density, two-dimensional phase change memory with single-layer memory cells is unable to meet the requirements. In this situation, three-dimensional phase change memory (3D Phase Change Random Access Memory, 3D PCRAM) came into being.

[0003] The architecture of a 3D phase-change memory can include a single layer of memory cells, two layers of stacked memory cells, four layers of stacked memory cells, or more layers of stacked memory cells. Each layer of memory cells is typically self-aligned at the intersection of mutually perpendicular word lines (WL) and bit lines (BL), with two adjacent memory cells in the plumb direction sharing a common bit line or word line.

[0004] However, while the three-dimensional phase change memory improves the storage density, there are also some issues that affect the reliability of the three-dimensional phase change memory that need to be solved urgently. Summary of the Invention

[0005] According to a first aspect of the present disclosure, a phase change memory is provided, comprising:

[0006] A first conductive line, a first memory unit, a second conductive line, a second memory unit, and a third conductive line are sequentially stacked along a first direction; wherein the first conductive line and the third conductive line extend along a second direction, the second conductive line extends along a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other;

[0007] The first memory cell includes a first bottom electrode, a first gating layer, a first intermediate electrode, a first phase-change memory layer, and a first top electrode stacked in sequence along the first direction;

[0008] The second memory cell includes a second bottom electrode, a second gating layer, a second intermediate electrode, a second phase-change memory layer, and a second top electrode stacked in sequence along the first direction;

[0009] The second phase-change memory layer and the first phase-change memory layer are made of different materials and / or have different thicknesses, and the threshold voltages of the second memory cell and the first memory cell are substantially the same.

[0010] According to a second aspect of the present disclosure, a method for preparing a phase change memory is provided, comprising:

[0011] A first conductive line layer and a first memory unit material layer are stacked along a first direction; wherein the first memory unit material layer includes a first phase change memory material layer; and the first direction is perpendicular to the plane where the first conductive line layer is located;

[0012] forming a plurality of first isolation structures penetrating the first conductive line layer and the first memory cell material layer; wherein each of the first isolation structures extends along a second direction, and the plurality of first isolation structures divide the first conductive line layer into a plurality of first conductive lines; and the second direction is perpendicular to the first direction;

[0013] forming a second conductive line layer covering the first memory cell material layer and the plurality of first isolation structures;

[0014] forming a plurality of second isolation structures penetrating the second conductive line layer and the first memory cell material layer; wherein each second isolation structure extends along a third direction, and the plurality of second isolation structures divide the second conductive line layer into a plurality of second conductive lines; the plurality of first isolation structures and the plurality of second isolation structures divide the first memory cell material layer into a plurality of mutually independent first memory cells; and the third direction is perpendicular to the second direction and the first direction;

[0015] forming a second memory cell material layer covering the second conductive line layer and the plurality of second isolation structures; wherein the second memory cell material layer comprises a second phase-change memory material layer;

[0016] forming a plurality of third isolation structures penetrating the second memory cell material layer; wherein each of the third isolation structures extends along the third direction;

[0017] forming a third conductive line layer covering the second memory cell material layer and the plurality of third isolation structures;

[0018] A plurality of fourth isolation structures are formed that penetrate the third conductive line layer and the second memory cell; wherein each of the fourth isolation structures extends along the second direction, and the plurality of fourth isolation structures divide the third conductive line layer into a plurality of third conductive lines; the plurality of third isolation structures and the plurality of fourth isolation structures divide the second memory cell material into a plurality of mutually independent second memory cells; the second phase-change memory material layer and the first phase-change memory material layer have different materials and / or thicknesses, and the threshold voltages of the second memory cell and the first memory cell are substantially the same.

[0019] The phase-change memory provided by the embodiments of the present disclosure can improve the reliability of the phase-change memory and ensure that the phase-change memory has good storage performance by adjusting the material of the first phase-change memory layer in the first memory cell and / or the second phase-change memory layer in the second memory cell, or adjusting the thickness of the first phase-change memory layer and / or the second phase-change memory layer. Therefore, the threshold voltage of the memory cell is relatively sensitive to the elemental composition of the material of the phase-change memory layer, the content of each element, and the thickness of the phase-change memory layer. Therefore, it is easy to fine-tune the threshold voltage by appropriately adjusting the material and / or thickness of the phase-change memory layer, which has high control efficiency, has little impact on the structure and process of the phase-change memory, and has low improvement costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic structural diagram of a phase change memory provided by an embodiment of the present disclosure;

[0021] Figure 2 for Figure 1 A cross-sectional view of a phase change memory is shown;

[0022] Figure 3 A schematic diagram showing how the heat of the phase-change memory layer in the upper memory unit and the lower memory unit changes over time according to an embodiment of the present disclosure;

[0023] Figure 4 A schematic structural diagram of another phase change memory provided by an embodiment of the present disclosure;

[0024] Figure 5 A schematic structural diagram of another phase change memory provided by an embodiment of the present disclosure;

[0025] Figure 6 A schematic structural diagram of another phase change memory provided by an embodiment of the present disclosure;

[0026] Figure 7 A schematic structural diagram of another phase change memory provided by an embodiment of the present disclosure;

[0027] Figure 8 A schematic structural diagram of another phase change memory provided by an embodiment of the present disclosure;

[0028] Figure 9 A schematic flow chart of a method for preparing a phase change memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The technical solution of the present disclosure is further elaborated in detail below with reference to the accompanying drawings and specific embodiments.

[0030] In the description of the present disclosure, it should be understood that the terms "length", "width", "depth", "up", "down", "outside", etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0031] A major advantage of phase change memory is that it can be three-dimensionally stacked in the vertical direction to increase the storage density of phase change memory. Figure 1 A schematic diagram of the structure of a phase change memory provided by an embodiment of the present disclosure is shown in FIG. Figure 2 for Figure 1 The cross-sectional view of the phase change memory is shown in FIG. Figure 1 and Figure 2 As shown, the phase change memory includes two layers of stacked memory cells in the vertical direction. The phase change memory includes a bit line 10 extending along the X direction and a word line 70 extending along the Y direction. In the vertical direction, the bit line 10 and the word line 70 are alternately stacked. The memory cell is located at the intersection of the bit line 10 and the word line 70, and each memory cell includes the same structure. Specifically, each memory cell includes a bottom electrode 20, a selection layer 30, an intermediate electrode 40, a phase change memory layer 50 and a top electrode 60 stacked in sequence along the vertical direction. Here, the vertical direction refers to the direction perpendicular to the extension direction of the bit line 10 and the extension direction of the word line 70, that is, the Z direction.

[0032] The basic principle of phase change memory is to apply an electric pulse with a large signal value and a short duration (i.e., high and narrow) to the memory cell. Under the action of Joule heat, a portion of the initially crystalline phase change memory layer 50 melts due to the temperature being higher than the melting temperature. After the electric pulse is interrupted, the melted portion cools rapidly and remains in the amorphous state with low atomic order, thus completing the transition from low resistance to high resistance. This is the erase (Reset) process. The melted portion in this process is called the programming volume. If an electric pulse with a small signal value and a long duration (i.e., low and wide) is applied, so that the temperature in the programming volume reaches above the crystallization temperature and below the melting temperature, and lasts long enough for the amorphous structure in the programming volume to crystallize, a low resistance state is obtained. This is the write (Set) process.

[0033] Theoretically, the two layers of memory cells of the phase change memory include the same structure. When the same electric pulse is applied to the two layers of memory cells respectively, the heating efficiency of the phase change memory layer should be the same, the temperature distribution should be the same, and then the electrical parameters should also be the same.

[0034] However, tests on the electrical parameters of the two layers of memory cells under the same electrical pulse signal show that the electrical parameters of the two layers of memory cells are different when the same electrical pulse is applied to the two layers of memory cells.

[0035] For example, the threshold voltage of the upper memory cell 400' is greater than the threshold voltage of the lower memory cell 200'. Here, the threshold voltage includes a first threshold voltage at which the memory cell transitions from a low resistance state to a high resistance state, and a second threshold voltage at which the memory cell transitions from a high resistance state to a low resistance state.

[0036] From another perspective, it can also be understood that the erase pulse of the upper memory cell 400 ′ reaching the same threshold voltage is greater than the erase pulse of the lower memory cell 200 ′.

[0037] For example, the read voltage of the upper memory cell 400' is greater than the read voltage of the lower memory cell 200'. It can be understood that the read voltage is between the first threshold voltage and the second threshold voltage. Therefore, when the threshold voltage of the upper memory cell 400' is greater than the threshold voltage of the lower memory cell 200', the read voltage of the upper memory cell 400' is also greater than the read voltage of the lower memory cell 200'.

[0038] It should be noted that, in the two memory cells stacked in parallel along the vertical direction, the memory cell relatively far from the horizontal plane is the upper memory cell, and the memory cell relatively close to the horizontal plane is the lower memory cell. Figure 1 In the specific illustration, the upper memory cell 400 ′ refers to a memory cell located above the word line 70 in the Z direction, and the lower memory cell 200 ′ refers to a memory cell located below the word line 70 in the Z direction.

[0039] When the first threshold voltage of the upper memory cell 400' is greater than the first threshold voltage of the lower memory cell 200', the electrical pulse that causes the lower memory cell 200' to reach a high impedance state may fail to cause the upper memory cell 400' to reach a high impedance state, resulting in erase failure of the upper memory cell 400'.

[0040] When the second threshold voltage of the upper memory cell 400' is greater than that of the lower memory cell 200', the electrical pulse that causes the lower memory cell 200' to reach a low resistance state may fail to cause the upper memory cell 400' to reach a low resistance state, resulting in write failure of the upper memory cell 400'.

[0041] When the read voltage of the upper memory cell 400' is greater than the read voltage of the lower memory cell 200', the voltage that can be read to show that the lower memory cell 200' is in a low resistance state cannot determine the state of the upper memory cell 400', thereby reducing the reliability of the phase change memory.

[0042] Furthermore, if Figure 2 As shown, the present disclosure also discovered that, under the same electric pulse, the programming volume of the phase-change memory layer 50 in the upper memory cell 400 ′ is larger than the programming volume of the phase-change memory layer 50 in the lower memory cell 200 ′.

[0043] Under an electric pulse, the test of the temperature distribution within the phase-change memory layer 50 in the upper memory unit 400' and the lower memory unit 200' also found that the temperature peak of the phase-change memory layer 50 in the upper memory unit 400' is higher than the temperature peak of the phase-change memory layer 50 in the lower memory unit 200', and the temperature gradient of the phase-change memory layer 50 in the upper memory unit 400' is also smaller than the temperature gradient of the phase-change memory layer 50 in the lower memory unit 200'.

[0044] Since the temperature distribution of the phase change memory layer 50 is affected by the heat of the phase change memory layer 50, the heat distribution of the two-layer memory cells can be obtained from the above test on the programming volume and temperature distribution of the two-layer memory cells as follows: Figure 3 As shown, under one electric pulse, the total heat of the phase-change memory layer 50 of the upper memory cell 400' is greater than the total heat of the phase-change memory layer 50 in the lower memory cell 200', and the peak heat of the phase-change memory layer 50 in the upper memory cell 400' is greater than the peak heat of the phase-change memory layer 50 in the lower memory cell 200'.

[0045] This study found that in the vertical direction, combined with Figure 2 As shown, taking two adjacent memory cells sharing the same word line 70 and being controlled by different bit lines 10 as an example, when performing a write operation or an erase operation, the voltage applied to the word line 70 is greater than the voltage of the bit line 10. For the lower memory cell 200', the current direction is along the top electrode 60 toward the bottom electrode 20, while for the upper memory cell 400', the current direction is along the bottom electrode 20 toward the top electrode 60.

[0046] It can be understood that, in some embodiments, two adjacent memory cells stacked in the vertical direction may share the same bit line 10 and use different word lines 70 .

[0047] For phase-change memory, the phase change process of the phase-change memory layer 50 mainly includes the generation of Joule heat. At the same time, when current flows through the interface of different conductors and / or semiconductors, a voltage drop is formed at the interface, and a thermoelectric effect occurs. The thermoelectric effect and Joule heat generate a feedback loop, which ultimately causes the heating efficiency of the phase-change memory layer 50 in the lower memory cell 200' to be lower than the heating efficiency of the phase-change memory layer 50 in the upper memory cell 400', thereby causing the temperature peak of the phase-change memory layer 50 in the lower memory cell 200' to be lower than the temperature peak of the phase-change memory layer 50 in the upper memory cell 400', and the threshold voltage of the lower memory cell 200' to be lower than the threshold voltage of the upper memory cell 400'.

[0048] The present disclosure provides a phase change memory, such as Figure 4 and Figure 5 As shown, the phase change memory includes:

[0049] A first conductive line 100, a first memory cell 200, a second conductive line 300, a second memory cell 400, and a third conductive line 500 are sequentially stacked along a first direction; wherein the first conductive line 100 and the third conductive line 500 extend along a second direction, and the second conductive line 300 extends along a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other;

[0050] The first memory cell 200 includes a first bottom electrode 201, a first gating layer 202, a first intermediate electrode 203, a first phase-change memory layer 204, and a first top electrode 205 stacked in sequence along a first direction;

[0051] The second memory cell 400 includes a second bottom electrode 401, a second gating layer 402, a second intermediate electrode 403, a second phase-change memory layer 404, and a second top electrode 405 stacked in sequence along the first direction;

[0052] The second phase-change memory layer 404 is made of a different material and / or thickness than the first phase-change memory layer 204 , and the threshold voltages of the second memory cell 400 and the first memory cell 200 are substantially the same.

[0053] Here, the threshold voltage includes a first threshold voltage at which the memory cell transitions from a low resistance state to a high resistance state, and / or a second threshold voltage at which the memory cell transitions from a high resistance state to a low resistance state. It is understood that the threshold voltages of the second phase-change memory layer 404 and the first phase-change memory layer 204 are substantially the same, which also means that the read voltages of the second phase-change memory layer 404 and the first phase-change memory layer are substantially the same.

[0054] Here, the first direction refers to the Z direction, the second direction refers to the X direction, and the third direction refers to the Y direction.

[0055] For example, the first conductive line 100 comprises a bit line, the second conductive line 300 comprises a word line, and the third conductive line 500 comprises a bit line. During a write operation, generally, the voltage applied to the second conductive line 300 is greater than the voltage applied to the first conductive line 100 and the third conductive line 500. In other words, the voltage applied to the word line is greater than the voltage applied to the bit line.

[0056] For example, the material of the first top electrode 205, the first intermediate electrode 203, and the first bottom electrode 201 includes at least one of carbon, amorphous carbon, titanium nitride, tantalum nitride, tantalum carbide, or a metal, and the metal may include copper, tungsten, aluminum, gold, cobalt, titanium, tantalum, etc. The materials of the first top electrode 205, the first intermediate electrode 203, and the first bottom electrode 201 may be the same or different. The material of the first gating layer 202 may include an Ovonic Threshold Switch (OTS) material.

[0057] For example, the material of the second top electrode 405, the second intermediate electrode 403, and the second bottom electrode 401 includes at least one of carbon, amorphous carbon, titanium nitride, tantalum nitride, tantalum carbide, or a metal. The metal may include copper, tungsten, aluminum, gold, cobalt, titanium, tantalum, or the like. The materials of the second top electrode 405, the second intermediate electrode 403, and the second bottom electrode 401 may be the same or different. The material of the second gating layer 402 may include an Ovonic Threshold Switch (OTS) material.

[0058] For example, the materials of the first phase-change memory layer 204 and the second phase-change memory layer 404 include at least one of the following: germanium telluride (Ge-Te) compound, antimony telluride (Sb-Te) compound, germanium antimony telluride (Ge-Sb-Te) compound, silicon antimony telluride (Si-Sb-Te) compound, titanium antimony telluride (Ti-Sb-Te) compound, aluminum antimony telluride (Al-Sb-Te) compound, and these compounds may also be doped with at least one of light elements such as carbon (C), nitrogen (N), and oxygen (O).

[0059] Since the threshold voltage of the memory cell is relatively sensitive to the elemental composition of the material of the phase change memory layer, the content of each element, and the thickness of the phase change memory layer, it is easy to fine-tune the threshold voltage by appropriately adjusting the material and / or thickness of the phase change memory layer, thereby reducing the difference in threshold voltage between the first memory cell 200 and the second memory cell 400, ensuring that the first memory cell 200 and the second memory cell 400 have substantially the same threshold voltage, and improving the reliability of the phase change memory.

[0060] Here, the appropriate adjustment of the materials and / or thicknesses of the first phase-change memory layer 204 and the second phase-change memory layer 404 can be achieved by making the first phase-change memory layer 204 and the second phase-change memory layer 404 the same thickness but adjusting the elemental composition to be different; or making the first phase-change memory layer 204 and the second phase-change memory layer 404 the same thickness but adjusting the elemental composition type and elemental content to be different; or making the first phase-change memory layer 204 and the second phase-change memory layer 404 the same elemental composition type and elemental content but adjusting the first phase-change memory layer 204 and the second phase-change memory layer 404 to be different thicknesses. In other words, the threshold voltages of the first memory cell 200 and the second memory cell 400 can be made substantially the same by adjusting only one of the elemental composition, the content of some elements, or the thickness of the first phase-change memory layer 204 and the second phase-change memory layer 404. In this way, the impact on the structure and process of the phase change memory is small and the improvement cost is low.

[0061] Figure 4 This is a schematic diagram of the structure of a phase change memory provided by an embodiment of the present disclosure. Figure 4 As shown, the thicknesses of the first phase-change memory layer 204 and the second phase-change memory layer 404 are substantially the same, and the materials of the first phase-change memory layer 204 and the second phase-change memory layer 404 are different.

[0062] In this embodiment, by adjusting the elemental composition and the content of each element of the phase change memory layer (referring to the first phase change memory layer 204 and / or the second phase change memory layer 404), the crystallization temperature, resistivity, thermal conductivity and Seebeck coefficient of the phase change memory layer can be changed, thereby changing the heating efficiency of the phase change memory layer and the temperature distribution of the phase change memory layer, and ultimately achieving the adjustment of the threshold voltage of the memory cell.

[0063] The present disclosure does not limit the manner of adjusting the materials of the first phase-change memory layer 204 and the second phase-change memory layer 404 .

[0064] This embodiment ensures that the threshold voltages of the first memory cell 200 and the second memory cell 400 are substantially the same by simply adjusting the material of the phase-change memory layer, resulting in high adjustment efficiency. Furthermore, this embodiment does not modify the thickness of the phase-change memory layer, the electrodes, or the gate layer, resulting in minimal impact on the structure and process of the phase-change memory and low cost improvements.

[0065] In some embodiments, the first phase change memory layer 204 and the second phase change memory layer 404 have the same type of constituent elements, including at least two constituent elements; wherein the first phase change memory layer 204 and the second phase change memory layer 404 have different contents of at least some of the constituent elements.

[0066] The first phase-change memory layer 204 and the second phase-change memory layer 404 are composed of the same element type, which means that the element type of the matrix material of the first phase-change memory layer 204 and the second phase-change memory layer 404 is the same. Furthermore, if the first phase-change memory layer 204 and the second phase-change memory layer 404 include doping elements, then the doping elements they include are also the same.

[0067] The first phase-change memory layer 204 and the second phase-change memory layer 404 may have different contents of at least some of the elements in their matrix materials. Furthermore, if the first phase-change memory layer 204 and the second phase-change memory layer 404 include doping elements, the doping elements may have different contents. Alternatively, the matrix materials may have different contents of at least some of the elements, and the doping elements may also have different contents.

[0068] In this embodiment, the types of constituent elements of the first phase change memory layer 204 and the second phase change memory layer 404 are not changed, and only the contents of at least some of the elements are changed, which has little impact on the preparation process of the phase change memory and reduces the cost of improvement.

[0069] The following describes, in conjunction with specific embodiments provided herein, methods for adjusting the content of at least some of the constituent elements in the first phase-change memory layer 204 and / or the second phase-change memory layer 404. It will be appreciated that the effect of changing the material of the phase-change memory layer on the threshold voltage of the memory cell is not determined by a single parameter of the phase-change memory layer, but rather is the result of the combined effects of various parameters (e.g., resistivity, thermal conductivity, or Seebeck coefficient).

[0070] In one embodiment, the first phase-change memory layer 204 includes a first germanium-antimony-tellurium compound, and the second phase-change memory layer 404 includes a second germanium-antimony-tellurium compound; wherein the first germanium-antimony-tellurium compound and the second germanium-antimony-tellurium compound have different germanium contents and / or antimony contents.

[0071] For example, the germanium content of the first germanium antimony tellurium compound is 5wt% to 20wt%, the germanium content of the second germanium antimony tellurium compound is 5wt% to 20wt%, and the difference between the germanium content of the first germanium antimony tellurium compound and the germanium content of the second germanium antimony tellurium compound is D1, 0wt%≤D1≤15wt%.

[0072] For example, the antimony content of the first germanium antimony tellurium compound is 20 wt% to 35 wt%, the germanium content of the second germanium antimony tellurium compound is 20 wt% to 35 wt%, and the difference between the antimony content of the first germanium antimony tellurium compound and the antimony content of the second germanium antimony tellurium compound is D2, 0 wt% ≤ D2 ≤ 15 wt%.

[0073] It is understood that when the germanium content of the first germanium-antimony-tellurium compound is different from that of the second germanium-antimony-tellurium compound, the antimony content of the first germanium-antimony-tellurium compound and the second germanium-antimony-tellurium compound may be the same; alternatively, when the antimony content of the first germanium-antimony-tellurium compound and the second germanium-antimony-tellurium compound is different, the germanium content of the first germanium-antimony-tellurium compound and the second germanium-antimony-tellurium compound may be the same. In some embodiments, the first germanium-antimony-tellurium compound and the second germanium-antimony-tellurium compound may have different germanium contents and antimony contents.

[0074] In germanium antimony telluride compounds (such as Ge x -Sb2Te3), as the germanium content increases, the crystallization temperature of the phase change memory layer increases, and a larger current is required to reach the same threshold voltage.

[0075] like Figure 4 As shown, when the current direction of the first memory cell 200 is along the direction of the first top electrode 205 toward the first bottom electrode 201, and the current direction of the second memory cell 400 is along the direction of the second bottom electrode 401 toward the second top electrode 405, the threshold voltage of the second memory cell 400 is greater than the threshold voltage of the first memory cell 200.

[0076] In this embodiment, the germanium content of the second phase-change memory layer 404 can be increased to increase the crystallization temperature of the second phase-change memory layer 404. When the electric pulse remains unchanged, a smaller threshold voltage is obtained, and the threshold voltages of the first memory cell 200 and the second memory cell 400 are substantially the same. In another embodiment, the germanium content of the first phase-change memory layer 204 can be reduced to lower the crystallization temperature of the first phase-change memory layer 204. When the electric pulse remains unchanged, a larger threshold voltage is obtained, and the threshold voltages of the first memory cell 200 and the second memory cell 400 are substantially the same.

[0077] In germanium antimony telluride compounds (such as Ge1Sb x In Te1), as the antimony content increases, the crystallization temperature of the phase change memory layer decreases, and a smaller current is required to reach the same threshold voltage.

[0078] When the threshold voltage of the second memory cell 400 is greater than that of the first memory cell 200, the antimony content of the second phase-change memory layer 404 can be reduced to increase the crystallization temperature of the second phase-change memory layer 404 and obtain a lower threshold voltage. Alternatively, the antimony content of the first phase-change memory layer 204 can be increased to lower the crystallization temperature of the first phase-change memory layer 204 and obtain a higher threshold voltage when the electric pulse remains unchanged. In this way, the threshold voltages of the first memory cell 200 and the second memory cell 400 are substantially the same.

[0079] In summary, in this embodiment, the types of constituent elements of the matrix materials of the first phase-change memory layer 204 and the second phase-change memory layer 404 remain unchanged; only the content of at least some of the elements in the matrix materials is changed, resulting in minimal impact on the phase-change memory manufacturing process. For example, when using magnetron co-sputtering to prepare the phase-change memory layers, the element content in the first phase-change memory layer 204 and the second phase-change memory layer 404 can be fine-tuned by simply adjusting the sputtering power and sputtering interval of different target materials. This results in minimal process adjustments and low cost improvements.

[0080] In some embodiments, the first phase-change memory layer 204 and the second phase-change memory layer 404 include the same base material;

[0081] The first phase-change memory layer further includes a doping element with a first content, and the second phase-change memory layer further includes a doping element with a second content different from the first content, wherein the doping element includes nitrogen and / or carbon.

[0082] Doping germanium antimony telluride compounds with light elements such as carbon and nitrogen can refine the grains, increase the resistivity of the phase-change memory layer, and require less current to achieve the same threshold voltage.

[0083] For example, the first phase-change memory layer 204 and the second phase-change memory layer 404 include the same germanium-rich germanium-antimony-tellurium compound (referring to a germanium-antimony-tellurium compound with a higher germanium content than Ge2Sb2Te5, such as Ge-Ge2Sb2Te5, GGST). When the threshold voltage of the second memory cell 400 is greater than the threshold voltage of the first memory cell 200, the first phase-change memory layer 204 can be doped with a first content of carbon, and the second phase-change memory layer 404 can be doped with a second content of carbon lower than the first content to appropriately reduce the resistivity of the second phase-change memory layer 404. When the electric pulse remains unchanged, a smaller threshold voltage is obtained, so that the threshold voltages of the first memory cell 200 and the second memory cell 400 are basically the same.

[0084] In this embodiment, the base materials of the first phase change memory layer 204 and the second phase change memory layer 404 are not changed, and only the doping content is adjusted, which has little impact on the preparation process of the phase change memory and has low improvement cost.

[0085] Furthermore, in some embodiments, the first phase-change memory layer 204 and the second phase-change memory layer 404 are composed of different types of constituent elements, and the threshold voltages of the first memory cell and the second memory cell are substantially the same.

[0086] For example, the first phase-change memory layer 204 and the second phase-change memory layer 404 include the same base material;

[0087] The first phase-change memory layer 204 further includes a doping element with a first content; or,

[0088] The second phase-change memory layer 404 further includes a doping element with a second content, wherein the doping element includes carbon and / or nitrogen.

[0089] The following describes the doping method of the first phase change memory layer 204 or the second phase change memory layer 404 by taking the case where the matrix materials of the first phase change memory layer 204 and the second phase change memory layer 404 include the same germanium-rich germanium antimony telluride compound as an example.

[0090] As mentioned above, doping light elements such as carbon and nitrogen into germanium antimony telluride compounds can refine the grains, increase the resistivity of the phase change memory layer, and require a smaller current to achieve the same threshold voltage.

[0091] When the threshold voltage of the second memory cell 400 is greater than the threshold voltage of the first memory cell 200, nitrogen can be doped into the first phase-change memory layer 204 to increase the resistivity of the first phase-change memory layer 204. When the electric pulse remains unchanged, a larger threshold voltage is obtained, so that the threshold voltages of the first memory cell 200 and the second memory cell 400 are substantially the same.

[0092] In this embodiment, the base materials of the first phase change memory layer 204 and the second phase change memory layer 404 are not changed. Only the doping step is added to add new elements to the phase change memory layer to change the threshold voltage of the memory cell. This has little impact on the preparation process of the phase change memory and the improvement cost is low.

[0093] Figure 5 This is a structural diagram of another phase change memory provided by the embodiment of the present disclosure. Figure 5 As shown, the first phase-change memory layer 204 and the second phase-change memory layer 404 have different thicknesses.

[0094] Since the resistivity of the phase change memory layer is related to its thickness, the resistance of the phase change memory layer (referring to the first phase change memory layer 204 and / or the second phase change memory layer 404) can be adjusted by adjusting its thickness, thereby changing the voltage division of the phase change memory layer, thereby changing the heating efficiency of the phase change memory layer, changing the temperature distribution of the phase change memory layer, and ultimately adjusting the threshold voltage of the phase change memory layer.

[0095] In some embodiments, the first phase change memory layer 204 and the second phase change memory layer 404 are made of different materials; along the first direction, the first phase change memory layer 204 has a first thickness, and the second phase change memory layer 404 has a second thickness, and the ratio of the first thickness to the second thickness is R, 0.5≤R≤2.

[0096] For example, a ratio of 0.5 between the first thickness and the second thickness indicates that the first thickness is half of the second thickness, and a ratio of 2 between the first thickness and the second thickness indicates that the first thickness is twice the second thickness. Here, the first thickness may also be equal to the second thickness, that is, R is equal to 1.

[0097] In some embodiments, the first phase change memory layer 204 and the second phase change memory layer 404 are made of the same material; along the first direction, the first phase change memory layer 204 has a first thickness, and the second phase change memory layer 404 has a second thickness, and the ratio of the first thickness to the second thickness is R, 0.5≤R≤2, and R is not equal to 1.

[0098] Here, it is understood that the materials and thicknesses of the first phase change memory layer 204 and the second phase change memory layer 404 cannot be the same at the same time. Therefore, when the materials of the first phase change memory layer 204 and the second phase change memory layer 404 are the same, R is not equal to 1.

[0099] For example, when the first phase-change memory layer 204 and the second phase-change memory layer 404 include the same germanium antimony telluride compound and the thickness of the first phase-change memory layer 204 and the second phase-change memory layer 404 are both greater than 100 nm, the resistance of the phase-change memory layer increases with increasing thickness. Furthermore, as the resistivity of the phase-change memory layer increases, the current required to reach the same threshold voltage decreases.

[0100] like Figure 5 As shown, when the current direction of the first memory cell 200 is along the direction of the first top electrode 205 toward the first bottom electrode 201, and the current direction of the second memory cell 400 is along the direction of the second bottom electrode 401 toward the second top electrode 405, the threshold voltage of the second memory cell 400 is greater than the threshold voltage of the first memory cell 200.

[0101] In this embodiment, while keeping the constituent material of the first phase change memory layer 204 unchanged, the thickness of the first phase change memory layer 204 can be increased to increase the resistivity of the first phase change memory layer 204, so as to obtain a larger threshold voltage when the electric pulse remains unchanged, thereby achieving that the threshold voltages of the first memory unit 200 and the second memory unit 400 are substantially the same.

[0102] In another embodiment, while keeping the constituent material of the second phase-change memory layer 404 unchanged, the thickness of the second phase-change memory layer 404 can also be reduced to reduce the resistivity of the second phase-change memory layer 404, so as to obtain a smaller threshold voltage without changing the electric pulse, thereby achieving that the threshold voltages of the first memory cell 200 and the second memory cell 400 are substantially the same.

[0103] It should be noted that the resistance and thickness of some phase-change memory materials may not change monotonically, for example, they may first increase and then decrease, or first decrease and then increase. Therefore, in some embodiments, the thickness of the first phase-change memory layer 204 and the second phase-change memory layer 404 may be appropriately selected based on the corresponding relationship between the thickness and resistivity of the phase-change memory material.

[0104] In this embodiment, only the thickness of the first phase change memory layer 204 and / or the second phase change memory layer 404 can be adjusted to achieve substantially the same threshold voltage of the first memory cell 200 and the second memory cell 400 without changing the material, electrode, and selection layer of the phase change memory layer. This has little impact on the structure and process of the phase change memory and reduces the cost of improvement.

[0105] Figure 6 This is a structural diagram of another phase change memory provided by the embodiment of the present disclosure. Figure 6 As shown, the first memory cell 200 further includes a heating layer 600 located between the first intermediate electrode 203 and the first phase-change memory layer 204; or,

[0106] The second memory cell 400 further includes a heating layer 600 located between the second intermediate electrode 403 and the second phase-change memory layer 404 .

[0107] In this embodiment, whether the heating layer 600 is disposed between the first intermediate electrode 203 and the first phase-change memory layer 204 or between the second intermediate electrode 403 and the second phase-change memory layer 404 depends on the threshold voltages of the first memory cell 200 and the second memory cell 400. Typically, the heating layer 600 is added between the intermediate electrode and the phase-change memory layer of the memory cell having the lower threshold voltage.

[0108] For example, Figure 6 As shown, when the current direction of the first memory cell 200 is along the direction from the first top electrode 205 to the first bottom electrode 201, and the current direction of the second memory cell 400 is along the direction from the second bottom electrode 401 to the second top electrode 405, the threshold voltage of the second memory cell 400 is greater than the threshold voltage of the first memory cell 200. Therefore, the heating layer 600 is provided between the first intermediate electrode 203 and the first phase-change memory layer 204 of the first memory cell 200.

[0109] The heating layer 600 includes a conductive material with high resistivity. The heating layer 600 can improve the interface thermal resistance and the heating efficiency of the first phase-change memory layer 204 , and can also change the voltage division of the first memory unit 200 .

[0110] Specifically, after adding the heating layer 600, the resistance of the first memory cell 200 increases, the current flowing through the first memory cell 200 decreases, the partial voltage of the first selection layer 202 decreases, and the total partial voltage of the heating layer 600 and the first phase-change memory layer 204 increases, which increases Joule heat and improves the heating efficiency of the first phase-change memory layer 204. The increased heating efficiency of the first phase-change memory layer 204 can increase the temperature of the first phase-change memory layer 204, and under the same electrical pulse, the first phase-change memory layer 204 obtains a higher threshold voltage, thereby achieving substantially the same threshold voltage for the first memory cell 200 and the second memory cell 400.

[0111] Illustratively, the material of the heating layer 600 includes transition metal nitride and / or transition metal silicon nitride, such as titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), etc.

[0112] Figure 7 This is a structural diagram of another phase change memory provided by an embodiment of the present disclosure. Figure 7 As shown, the first memory unit 200 further includes: a first adhesion layer 206, the first adhesion layer 206 is located between the first intermediate electrode 203 and the first phase change memory layer 204; the second memory unit 400 further includes: a second adhesion layer 406, the second adhesion layer 406 is located between the second intermediate electrode 403 and the second phase change memory layer 404; wherein the materials and / or thicknesses of the first adhesion layer 206 and the second adhesion layer 406 are different.

[0113] By way of example, the material of the first adhesion layer 206 and the second adhesion layer 406 includes tungsten silicon nitride (WSiN) and / or titanium silicon nitride (TiSiN).

[0114] Generally, the adhesion layer (referring to the first adhesion layer 206 and the second adhesion layer 406) is used to strengthen the adhesion between the intermediate electrode and the phase-change memory layer, reducing the probability of separation between the intermediate electrode and the phase-change memory layer during subsequent processing. In some embodiments, the adhesion layer can also be used to reduce the mutual diffusion of materials between the phase-change memory layer and the intermediate electrode. In the disclosed embodiment, the adhesion layer material also has the characteristic of high resistivity, and the adhesion layer is used as the heating layer 600.

[0115] In this embodiment, according to the different threshold voltages of the first memory unit 200 and the second memory unit 400, the material and / or thickness of the first adhesion layer 206 and the second adhesion layer 406 are adaptively adjusted to make the resistivity of the two different, thereby making the thermal contributions of the two to the first phase change memory layer 204 and the second phase change memory layer 404 different, thereby compensating for the difference in heating efficiency of the first phase change memory layer 204 and the second phase change memory layer 404, thereby achieving that the first phase change memory layer 204 and the second phase change memory layer 404 have substantially the same heating efficiency, thereby achieving that the first memory unit 200 and the second memory unit 400 have substantially the same threshold voltage.

[0116] In some embodiments, first adhesion layer 206 and second adhesion layer 406 have the same thickness and are composed of the same type of elements, including at least two elements. The first adhesion layer 206 and second adhesion layer 406 have different contents of at least some of these elements. Thus, by fine-tuning the element contents of first adhesion layer 206 and / or second adhesion layer 406, first memory cell 200 and second memory cell 400 can achieve substantially the same threshold voltage, minimizing the impact on the structure and process of the phase-change memory and reducing the cost of improvement.

[0117] For example, the material of the first adhesion layer 206 includes a first tungsten silicon nitride, and the material of the second adhesion layer 406 includes a second tungsten silicon nitride; wherein the nitrogen content of the first tungsten silicon nitride is different from that of the second tungsten silicon nitride.

[0118] In tungsten silicon nitride, as the nitrogen content increases, the resistivity of the adhesion layer increases, and a smaller current is required to reach the same threshold voltage.

[0119] like Figure 7 As shown, when the current direction of the first memory cell 200 is along the direction from the first top electrode 205 to the first bottom electrode 201, and the current direction of the second memory cell 400 is along the direction from the second bottom electrode 401 to the second top electrode 405, the threshold voltage of the second memory cell 400 is greater than the threshold voltage of the first memory cell 200. The nitrogen content of the first adhesion layer 206 can be increased to improve the resistivity of the first adhesion layer 206, thereby obtaining a larger threshold voltage when the electric pulse remains unchanged, so that the threshold voltages of the first memory cell 200 and the second memory cell 400 are substantially the same.

[0120] In another embodiment, the nitrogen content of the second adhesion layer 406 may be reduced to lower the resistivity of the second adhesion layer 406 , thereby obtaining a smaller threshold voltage while keeping the electric pulse constant, and achieving substantially the same threshold voltages for the first memory cell 200 and the second memory cell 400 .

[0121] In addition, if Figure 7 As shown, the first memory cell 200 further includes a plurality of third adhesion layers 207 located between the first conductive line 100 and the first bottom electrode 201 , between the first phase change memory layer 204 and the first top electrode 205 , and between the first top electrode 205 and the second conductive line 300 .

[0122] The second memory cell 400 further includes a plurality of fourth adhesion layers 407 located between the second conductive line 300 and the second bottom electrode 401 , between the second phase-change memory layer 404 and the second top electrode 405 , and between the second top electrode 405 and the third conductive line 500 .

[0123] For example, the material of the third adhesion layer 207 and the fourth adhesion layer 407 includes at least one of tungsten silicon nitride (WSiN), titanium silicon nitride (TiSiN), titanium nitride (TiN), or tungsten nitride (WN). The materials of the first adhesion layer 206 and the third adhesion layer 207 can be the same or different. The materials of the second adhesion layer 406 and the fourth adhesion layer 407 can be the same or different.

[0124] like Figure 7 As shown, the first intermediate electrode 203 may further include a first sub-intermediate electrode and a second sub-intermediate electrode, wherein the second sub-intermediate electrode is disposed between the first sub-intermediate electrode and the first phase-change memory layer 204. The second intermediate electrode 403 may further include a third sub-intermediate electrode and a fourth sub-intermediate electrode, wherein the fourth sub-intermediate electrode is disposed between the third sub-intermediate electrode and the second phase-change memory layer 404.

[0125] For example, the first and third sub-intermediate electrodes are made of carbon and / or amorphous carbon, and the second and fourth sub-intermediate electrodes are made of metal, such as tungsten, copper, gold, cobalt, aluminum, etc. The second sub-intermediate electrode can block elements of the first sub-intermediate electrode from diffusing into the first phase-change memory layer 204, and the fourth sub-intermediate electrode can block elements of the third sub-intermediate electrode from diffusing into the second phase-change memory layer 404, thereby reducing the probability of device performance degradation.

[0126] like Figure 7 As shown, the first top electrode 205 may further include a first sub-top electrode and a second sub-top electrode, with the first sub-top electrode being disposed between the first phase-change memory layer 204 and the second sub-top electrode. The second top electrode 405 may further include a third sub-top electrode and a fourth sub-top electrode, with the third sub-top electrode being located between the second phase-change memory layer 404 and the fourth sub-top electrode.

[0127] For example, the second and fourth sub-top electrodes are made of carbon and / or amorphous carbon, and the first and third sub-top electrodes are made of metal, such as tungsten, copper, gold, cobalt, aluminum, etc. The first sub-top electrode can block elements of the second sub-top electrode from diffusing into the first phase-change memory layer 204, and the third sub-top electrode can block elements of the fourth sub-top electrode from diffusing into the second phase-change memory layer 404, thereby reducing the probability of device performance degradation.

[0128] like Figure 7 As shown, the first memory cell 200 further includes a first isolation layer 208, which covers the side surfaces of the first bottom electrode 201, the first gating layer 202, the first intermediate electrode 203, the first phase-change memory layer 204, and the first top electrode 205. The second memory cell 400 further includes a second isolation layer 408, which covers the side surfaces of the second bottom electrode 401, the second gating layer 402, the second intermediate electrode 403, the second phase-change memory layer 404, and the second top electrode 405. The first isolation layer 208 and the second isolation layer 408 are used to reduce heat dissipation in the phase-change memory layer and to minimize thermal interference between adjacent memory cells in the same layer.

[0129] Figure 8 A schematic diagram of the structure of another phase change memory provided by an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, the first conductive line, the first memory unit, the second conductive line, the second memory unit and the third conductive line form a sub-stack structure, and at least two sub-stack structures are stacked in the vertical direction.

[0130] Figure 8 The phase-change memory shown includes two sub-stack structures, forming four layers of stacked memory cells. Vertically adjacent memory cells share a common bit line or word line. During write or erase operations, the current in the odd-numbered memory cells (such as the first memory cell 200 and the third memory cell 700) flows from the top electrode toward the bottom electrode, while the current in the even-numbered memory cells (such as the second memory cell 400 and the fourth memory cell 800) flows from the bottom electrode toward the top electrode.

[0131] In view of the current direction of the multi-layer stacked memory cells as described above, in some embodiments, when the phase change memory includes multi-layer stacked memory cells in a vertical direction, the material and thickness of the phase change memory layer in the memory cells of the odd layers can be set to be the same, and the material and thickness of the phase change memory layer in the memory cells of the even layers can be set to be the same; however, the material and / or thickness of the phase change memory layer of the memory cells of the odd layers are different from those of the phase change memory layers of the memory cells of the even layers, and the threshold voltages of the memory cells in different layers are basically the same.

[0132] For example, Figure 8As shown, the first phase-change memory layer 204 of the first memory unit 200 and the third phase-change memory layer 704 of the third memory unit 700 have the same material and thickness, and the second phase-change memory layer 404 of the second memory unit 400 and the fourth phase-change memory layer 804 of the fourth memory unit 800 have the same material and thickness; however, the first phase-change memory layer 204 and the second phase-change memory layer 404 are made of different materials.

[0133] For example, the first phase change memory layer 204 and the third phase change memory layer 704 have the same material and thickness, and the second phase change memory layer 404 and the fourth phase change memory layer 804 have the same material and thickness; however, the first phase change memory layer 204 and the second phase change memory layer 404 have different thicknesses.

[0134] In another embodiment, when the phase change memory includes multiple layers of memory cells stacked in a vertical direction, a heating layer 600 may be set in the memory cells of odd layers (such as the first memory cell 200 and the third memory cell 700), and the heating layer 600 is located on a side of the phase change memory layer relatively close to the selection layer.

[0135] In addition, in some embodiments, when the phase change memory includes multiple memory cells stacked in a vertical direction, the materials and / or thicknesses of the phase change memory layers in the memory cells in different layers may be different, and the threshold voltages of the memory cells in different layers may be substantially the same.

[0136] In some phase change memories, as the number of stacked layers increases, the structure of the memory cells may have slight differences in the vertical direction. For example, the memory cells at the top layer ( Figure 8 The horizontal cross-sectional dimension (XY cross-sectional dimension) of the fourth memory cell 800 in FIG. 8 may be smaller than that of the memory cell located at the bottom ( Figure 8 The horizontal cross-sectional dimensions of the first memory cell 200 in FIG. This is because the bottom of the trench is generally smaller than the top during deep trench etching. Vertical structural differences in the memory cells can lead to differences in the threshold voltages of the memory cells. The present disclosure allows for substantially uniform threshold voltages of the memory cells in different vertical layers by varying the materials and / or thicknesses of the phase change storage layers in the memory cells.

[0137] According to another aspect of the present disclosure, a method for preparing a phase change memory is also provided. Figure 9 As shown, the preparation method of the phase change memory includes:

[0138] S100: forming a stacked first conductive line layer and a first memory cell material layer along a first direction; wherein the first memory cell material layer includes a first phase change memory material layer; and the first direction is perpendicular to the plane where the first conductive line layer is located;

[0139] S200: forming a plurality of first isolation structures penetrating the first conductive line layer and the first memory cell material layer; wherein each first isolation structure extends along a second direction, and the plurality of first isolation structures divide the first conductive line layer into a plurality of first conductive lines; and the second direction is perpendicular to the first direction;

[0140] S300: forming a second conductive line layer covering the first memory cell material layer and the plurality of first isolation structures;

[0141] S400: forming a plurality of second isolation structures penetrating the second conductive line layer and the first memory cell material layer; wherein each second isolation structure extends along a third direction, and the plurality of second isolation structures divide the second conductive line layer into a plurality of second conductive lines; the plurality of first isolation structures and the plurality of second isolation structures divide the first memory cell material layer into a plurality of mutually independent first memory cells; and the third direction is perpendicular to the second direction and the first direction.

[0142] S500: forming a second memory cell material layer covering the second conductive line layer and the plurality of second isolation structures; wherein the second memory cell material layer includes a second phase-change memory material layer;

[0143] S600: forming a plurality of third isolation structures penetrating the second memory cell material layer; wherein each third isolation structure extends along a third direction;

[0144] S700: forming a third conductive line layer covering the second memory cell material layer and a plurality of third isolation structures;

[0145] S800: forming a plurality of fourth isolation structures penetrating the third conductive line layer and the second memory cell; wherein each fourth isolation structure extends along the second direction, and the plurality of fourth isolation structures divide the third conductive line layer into a plurality of third conductive lines; the plurality of third isolation structures and the plurality of fourth isolation structures divide the second memory cell material into a plurality of second memory cells independent of each other; the second phase-change memory material layer and the first phase-change memory material layer have different materials and / or thicknesses, and the threshold voltages of the second memory cell and the first memory cell are substantially the same.

[0146] Here, the first direction refers to the Z direction, the second direction refers to the X direction, and the third direction refers to the Y direction.

[0147] For example, the materials of the first, second, third, and fourth isolation structures may include silicon nitride, silicon oxide, or other low-k dielectric layers. The first and second isolation structures are used to electrically isolate independent first memory cells and reduce heat transfer between adjacent first memory cells. The third and fourth isolation structures are used to electrically isolate independent second memory cells and reduce heat transfer between adjacent second memory cells.

[0148] In step S200, each first isolation structure extends along the second direction, and multiple first isolation structures are arranged in parallel along the third direction. The multiple first isolation structures divide the first conductive line layer to form multiple first conductive lines. Each first conductive line extends along the second direction, and multiple first conductive lines are arranged in parallel along the third direction.

[0149] In step S400, each second isolation structure extends along the third direction, and multiple second isolation structures are arranged in parallel along the second direction. The multiple second isolation structures divide the second conductive line layer to form multiple second conductive lines. Each second conductive line extends along the third direction, and multiple second conductive lines are arranged in parallel along the second direction.

[0150] It should be noted that the second isolation structure only penetrates the second conductive line layer and the first memory cell material layer along the first direction, but does not penetrate the first conductive line layer.

[0151] In step S600, each third isolation structure extends along the third direction, and multiple third isolation structures are arranged in parallel along the second direction. The second memory cell material layer between adjacent third isolation structures contacts the second conductive line, so that the second memory cell and the first memory cell share the second conductive line.

[0152] In step S800, each fourth isolation structure extends along the second direction, and multiple fourth isolation structures are arranged in parallel along the third direction. The multiple fourth isolation structures divide the third conductive line layer to form multiple third conductive lines. Each third conductive line extends along the second direction, and the multiple third conductive lines are arranged in parallel along the third direction.

[0153] For example, the phase change memory material layer may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) processes, wherein physical vapor deposition includes but is not limited to magnetron co-sputtering and electron beam evaporation.

[0154] In this embodiment, magnetron co-sputtering can be used to form the phase change memory material layer, and the constituent elements, element content and thickness of the phase change memory material layer can be adjusted by adjusting parameters such as the target material, the sputtering power of the target material, and the sputtering interval time.

[0155] In some embodiments, the first phase change memory layer and the second phase change memory layer have the same constituent elements, which include at least two constituent elements; wherein the first phase change memory layer and the second phase change memory layer have different contents of at least some constituent elements.

[0156] In some embodiments, the first phase-change memory layer includes a first germanium-antimony-tellurium compound, and the second phase-change memory layer includes a second germanium-antimony-tellurium compound; wherein the first germanium-antimony-tellurium compound and the second germanium-antimony-tellurium compound have different germanium contents and / or antimony contents.

[0157] In some embodiments, the first phase change memory layer and the second phase change memory layer include the same base material; the first phase change memory layer also includes a first content of a doping element, and the second phase change memory layer also includes a second content of a doping element different from the first content, wherein the doping element includes nitrogen and / or carbon.

[0158] According to the research disclosed in the present invention, the threshold voltage of the phase change memory is relatively sensitive to the elemental composition of the phase change memory layer material, the content of each element, and the thickness of the phase change memory layer. Therefore, in the present invention, the threshold voltage of the phase change memory can be fine-tuned by appropriately adjusting the material and / or thickness of the phase change memory layer, thereby reducing the difference in threshold voltage between the first memory cell and the second memory cell, ensuring that the first memory cell and the second memory cell have substantially the same threshold voltage, and improving the reliability of the phase change memory.

[0159] Here, it can be understood that in the present disclosure, by adjusting the material and / or thickness of the phase change storage layer, other electrical parameters of the first memory cell and the second memory cell can be kept consistent while achieving substantially the same threshold voltage of the first memory cell and the second memory cell. For example, parameters such as crystalline resistance and amorphous resistance can also be synchronously adjusted to keep consistent.

[0160] In some embodiments, the first memory cell material layer also includes a first bottom electrode material layer, a first selection material layer, a first intermediate electrode material layer and a first top electrode material layer stacked in sequence along a first direction, and the first phase change memory material layer is located between the first intermediate electrode material layer and the first top electrode material layer.

[0161] In step S200 and step S400, after the multiple first isolation structures and the multiple second isolation structures divide the first memory cell material layer into multiple independent first memory cells, each first memory cell includes a first bottom electrode, a first selection layer, a first intermediate electrode, a first phase change storage layer and a first top electrode stacked in sequence along a first direction.

[0162] In some embodiments, the first memory cell material layer further includes a heating material layer; and the step S100 of forming the first memory cell material layer further includes:

[0163] Before forming the first phase-change memory material layer, a heating material layer is formed on the first intermediate electrode material layer.

[0164] The heating material layer is located between the first intermediate electrode material layer and the first phase-change memory material layer. It will be appreciated that when the plurality of first isolation structures and the plurality of second isolation structures divide the first memory cell material layer into a plurality of mutually independent first memory cells, the heating material layer is simultaneously divided into a plurality of heating layers. Each heating layer is located between the first intermediate electrode and the first phase-change memory layer of a first memory cell.

[0165] For example, the material of the heating material layer includes transition metal nitride and / or transition metal silicon nitride, such as titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), etc.

[0166] In this embodiment, when the threshold voltage of the first memory cell is lower than the threshold voltage of the second memory cell, a heating layer is added to the first memory cell, thereby increasing the resistance of the first memory cell, reducing the current flowing through the first memory cell, and lowering the partial voltage of the first selection layer. While the total partial voltage of the heating layer and the first phase-change memory layer increases, Joule heating is increased, thereby improving the heating efficiency of the first phase-change memory layer. This increased heating efficiency of the first phase-change memory layer can increase the temperature of the first phase-change memory layer, allowing the first phase-change memory layer to achieve a higher threshold voltage under the same electrical pulse, thereby achieving substantially the same threshold voltage for the first and second memory cells.

[0167] In some embodiments, the first memory cell material layer also includes a second bottom electrode material layer, a second selection material layer, a second intermediate electrode material layer, and a second top electrode material layer stacked in sequence along the first direction, and the second phase change memory material layer is located between the second intermediate electrode material layer and the second top electrode material layer.

[0168] In step S600 and step S800, after the plurality of third isolation structures and the plurality of fourth isolation structures divide the second memory cell material layer into a plurality of independent second memory cells, each second memory cell includes a second bottom electrode, a second selection layer, a second intermediate electrode, a second phase change storage layer and a second top electrode stacked in sequence along the first direction.

[0169] In some embodiments, the first memory cell material layer further includes a first adhesion material layer, and the second memory cell material layer further includes a second adhesion material layer;

[0170] The step S100 forms a first memory cell material layer, further comprising:

[0171] Before forming the first phase-change memory material layer, forming a first adhesion material layer on the first intermediate electrode material layer;

[0172] In step S500, a second memory cell material layer is formed, further comprising:

[0173] Before forming the second phase-change memory material layer, a second adhesion material layer is formed on the first intermediate electrode material layer; wherein the second adhesion material layer and the first adhesion material layer have the same type of constituent elements, including at least two constituent elements, and the second adhesion material layer and the first adhesion material layer have different contents of at least some of the constituent elements.

[0174] The first adhesion material layer is located between the first intermediate electrode material layer and the first phase-change memory material layer. It will be appreciated that when the multiple first isolation structures and the multiple second isolation structures divide the first memory cell material layer into multiple independent first memory cells, the first adhesion material layer is simultaneously divided into multiple first adhesion layers. Each first adhesion layer is located between the first intermediate electrode and the first phase-change memory layer of a first memory cell.

[0175] The second adhesion material layer is located between the second intermediate electrode material layer and the second phase-change memory material layer. It will be understood that when the plurality of third isolation structures and the plurality of fourth isolation structures divide the second memory cell material layer into a plurality of independent second memory cells, the second adhesion material layer is simultaneously divided into a plurality of second adhesion layers. Each second adhesion layer is located between the second intermediate electrode and the second phase-change memory layer of a second memory cell. The second adhesion layer and the first adhesion layer have the same component elements, including at least two components, and the content of at least some of the components in the second adhesion layer and the first adhesion layer differs.

[0176] For example, the material of the first adhesion layer includes a first tungsten silicon nitride, and the material of the second adhesion layer includes a second tungsten silicon nitride; wherein the nitrogen content of the first tungsten silicon nitride is different from that of the second tungsten silicon nitride.

[0177] In this embodiment, the adhesion layer's material has a high resistivity and serves as a heating layer. Based on the different threshold voltages of the first and second memory cells, the materials and / or thicknesses of the first and second adhesion layers are adaptively adjusted to achieve different resistivities, thereby varying their contributions to the heat of the first and second phase-change memory layers. This compensates for the difference in heating efficiency between the first and second phase-change memory layers, ensuring that the first and second phase-change memory layers have substantially the same heating efficiency, and thus ensuring that the first and second memory cells have substantially the same threshold voltages.

[0178] It should be noted that when the threshold voltage of a memory cell is controlled by adding a heating layer to the memory cell, the material and / or thickness of the phase-change memory layer may be adjusted simultaneously, or the material and thickness of the phase-change memory layer may not be adjusted. For example, a heating layer may be added to the first memory cell only, without adjusting the materials and thicknesses of the first and second phase-change memory layers, to achieve the same threshold voltage for the first and second memory cells.

[0179] Similarly, when adjusting the material and / or thickness of the adhesion layer to control the threshold voltage of the memory cell, the material and / or thickness of the phase-change memory layer may be adjusted simultaneously, or the material and thickness of the phase-change memory layer may not be adjusted. For example, by adjusting only the content of the constituent elements of the first adhesion layer in the first memory cell, without adjusting the materials and thicknesses of the first and second phase-change memory layers, the threshold voltages of the first and second memory cells may be the same.

[0180] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A phase change memory, characterized in that: include: A first conductive line, a first memory unit, a second conductive line, a second memory unit, and a third conductive line are sequentially stacked along a first direction; wherein the first conductive line and the third conductive line extend along a second direction, the second conductive line extends along a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other; The first memory cell includes a first bottom electrode, a first gating layer, a first intermediate electrode, a first adhesion layer, a first phase-change memory layer, and a first top electrode stacked in sequence along the first direction; The second memory cell includes a second bottom electrode, a second gating layer, a second intermediate electrode, a second adhesion layer, a second phase-change memory layer, and a second top electrode sequentially stacked along the first direction; Wherein, the second phase-change memory layer and the first phase-change memory layer have different materials and / or thicknesses, and the first adhesion layer and the second adhesion layer have different materials and / or thicknesses; In a case where a direction of current in the first memory cell is opposite to a direction of current in the second memory cell, threshold voltages of the second memory cell and the first memory cell are substantially the same.

2. The phase change memory according to claim 1, wherein: The first phase change memory layer and the second phase change memory layer have the same constituent elements, which include at least two elements; wherein the first phase change memory layer and the second phase change memory layer have different contents of at least some of the constituent elements.

3. The phase change memory according to claim 2, wherein: The first phase-change memory layer includes a first germanium-antimony-tellurium compound, and the second phase-change memory layer includes a second germanium-antimony-tellurium compound; The first germanium-antimony-tellurium compound and the second germanium-antimony-tellurium compound have different germanium content and / or antimony content.

4. The phase change memory according to claim 1, wherein: The first phase-change memory layer and the second phase-change memory layer include the same base material; The first phase-change memory layer further includes a doping element with a first concentration, and the second phase-change memory layer further includes the doping element with a second concentration different from the first concentration, wherein the doping element includes nitrogen and / or carbon.

5. The phase change memory according to claim 1, wherein: The first phase-change memory layer and the second phase-change memory layer are made of the same material; Along the first direction, the first phase-change memory layer has a first thickness, the second phase-change memory layer has a second thickness, a ratio of the first thickness to the second thickness is R, 0.5≤R≤2, and R is not equal to 1.

6. The phase change memory according to claim 1, wherein: The first phase-change memory layer and the second phase-change memory layer are made of different materials; Along the first direction, the first phase-change memory layer has a first thickness, the second phase-change memory layer has a second thickness, and the first thickness and the second thickness are substantially the same.

7. The phase change memory according to claim 1, wherein: The first adhesion layer and the second adhesion layer have the same type of constituent elements, which include at least two types; wherein the first adhesion layer and the second adhesion layer have different contents of at least some of the constituent elements.

8. The phase change memory according to claim 7, wherein: The material of the first adhesion layer includes a first tungsten silicon nitride, and the material of the second adhesion layer includes a second tungsten silicon nitride; The nitrogen content of the first tungsten silicon nitride is different from that of the second tungsten silicon nitride.

9. A phase change memory, characterized in that: include: A first conductive line, a first memory unit, a second conductive line, a second memory unit, and a third conductive line are sequentially stacked along a first direction; wherein the first conductive line and the third conductive line extend along a second direction, the second conductive line extends along a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other; The first memory cell includes a first bottom electrode, a first gating layer, a first intermediate electrode, a first phase-change memory layer, and a first top electrode stacked in sequence along the first direction; The second memory cell includes a second bottom electrode, a second gating layer, a second intermediate electrode, a second phase-change memory layer, and a second top electrode stacked in sequence along the first direction; The second phase-change memory layer and the first phase-change memory layer have different materials and / or thicknesses, and a heating layer is provided between the first intermediate electrode and the first phase-change memory layer or between the second intermediate electrode and the second phase-change memory layer; In a case where a direction of current in the first memory cell is opposite to a direction of current in the second memory cell, threshold voltages of the second memory cell and the first memory cell are substantially the same.

10. The phase change memory according to claim 9, wherein: The material of the heating layer includes transition metal nitride and / or transition metal silicon nitride.

11. A method for preparing a phase change memory, characterized in that: include: A first conductive line layer and a first memory cell material layer are stacked along a first direction; wherein the first memory cell material layer includes a first phase-change memory material layer and a first adhesion material layer; and the first direction is perpendicular to the plane where the first conductive line layer is located; forming a plurality of first isolation structures penetrating the first conductive line layer and the first memory cell material layer; wherein each of the first isolation structures extends along a second direction, and the plurality of first isolation structures divide the first conductive line layer into a plurality of first conductive lines; and the second direction is perpendicular to the first direction; forming a second conductive line layer covering the first memory cell material layer and the plurality of first isolation structures; forming a plurality of second isolation structures penetrating the second conductive line layer and the first memory cell material layer; wherein each second isolation structure extends along a third direction, and the plurality of second isolation structures divide the second conductive line layer into a plurality of second conductive lines; the plurality of first isolation structures and the plurality of second isolation structures divide the first memory cell material layer into a plurality of mutually independent first memory cells; and the third direction is perpendicular to the second direction and the first direction; forming a second memory cell material layer covering the second conductive line layer and the plurality of second isolation structures; wherein the second memory cell material layer comprises a second phase-change memory material layer and a second adhesion material layer; forming a plurality of third isolation structures penetrating the second memory cell material layer; wherein each of the third isolation structures extends along the third direction; forming a third conductive line layer covering the second memory cell material layer and the plurality of third isolation structures; A plurality of fourth isolation structures are formed that penetrate the third conductive line layer and the second memory cell; wherein each of the fourth isolation structures extends along the second direction, and the plurality of fourth isolation structures divide the third conductive line layer into a plurality of third conductive lines; the plurality of third isolation structures and the plurality of fourth isolation structures divide the second memory cell material layer into a plurality of mutually independent second memory cells; the second phase-change memory material layer and the first phase-change memory material layer have different materials and / or thicknesses, and the second adhesion material layer and the first adhesion material layer have different materials and / or thicknesses; when the direction of the current in the first memory cell is opposite to the direction of the current in the second memory cell, the threshold voltages of the second memory cell and the first memory cell are substantially the same.

12. The method for preparing a phase change memory according to claim 11, wherein: The first memory cell material layer further includes a first bottom electrode material layer, a first gating material layer, a first intermediate electrode material layer, and a first top electrode material layer sequentially stacked along a first direction, the first phase-change memory material layer is located between the first intermediate electrode material layer and the first top electrode material layer, and the first adhesion material layer is located between the first intermediate electrode material layer and the first phase-change memory material layer; The second memory cell material layer further includes a second bottom electrode material layer, a second gating material layer, a second intermediate electrode material layer, and a second top electrode material layer sequentially stacked along a first direction, the second phase-change memory material layer is located between the second intermediate electrode material layer and the second top electrode material layer, and the second adhesion material layer is located between the second intermediate electrode material layer and the second phase-change memory material layer; The second adhesive material layer and the first adhesive material layer have the same type of constituent elements, which include at least two types. The second adhesive material layer and the first adhesive material layer have different contents of at least some of the constituent elements.

13. A method for preparing a phase change memory, characterized in that: include: A first conductive line layer and a first memory unit material layer are stacked along a first direction; wherein the first memory unit material layer includes a first phase change memory material layer; and the first direction is perpendicular to the plane where the first conductive line layer is located; forming a plurality of first isolation structures penetrating the first conductive line layer and the first memory cell material layer; wherein each of the first isolation structures extends along a second direction, and the plurality of first isolation structures divide the first conductive line layer into a plurality of first conductive lines; and the second direction is perpendicular to the first direction; forming a second conductive line layer covering the first memory cell material layer and the plurality of first isolation structures; forming a plurality of second isolation structures penetrating the second conductive line layer and the first memory cell material layer; wherein each second isolation structure extends along a third direction, and the plurality of second isolation structures divide the second conductive line layer into a plurality of second conductive lines; the plurality of first isolation structures and the plurality of second isolation structures divide the first memory cell material layer into a plurality of mutually independent first memory cells; and the third direction is perpendicular to the second direction and the first direction; forming a second memory cell material layer covering the second conductive line layer and the plurality of second isolation structures; wherein the second memory cell material layer comprises a second phase-change memory material layer; forming a plurality of third isolation structures penetrating the second memory cell material layer; wherein each of the third isolation structures extends along the third direction; forming a third conductive line layer covering the second memory cell material layer and the plurality of third isolation structures; A plurality of fourth isolation structures are formed that penetrate the third conductive line layer and the second memory cell; wherein each of the fourth isolation structures extends along the second direction, and the plurality of fourth isolation structures divide the third conductive line layer into a plurality of third conductive lines; the plurality of third isolation structures and the plurality of fourth isolation structures divide the second memory cell material layer into a plurality of second memory cells that are independent of each other; the second phase-change memory material layer and the first phase-change memory material layer have different materials and / or thicknesses, and the first memory cell material layer or the second memory cell material layer further includes a heating material layer; when the direction of the current in the first memory cell is opposite to the direction of the current in the second memory cell, the threshold voltages of the second memory cell and the first memory cell are substantially the same.

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