A method for improving the voltage resistance of an SGT MOSFET, an SGT MOSFET device and a manufacturing method

Abstract

The application discloses a method for improving the voltage resistance of an SGT MOSFET, an SGT MOSFET device and a manufacturing method, wherein the method introduces a third electric field peak between a first electric field peak formed at the bottom of a P-well region of the SGT MOSFET and a second electric field peak formed at the bottom of source polysilicon. The technical scheme introduces the third electric field peak, the peak improves the recessed electric field between the first electric field peak and the second electric field peak, increases the area of the distance integral of the electric field strength, and realizes the improvement of the voltage resistance of the device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor, in particular relates to a method for improving the voltage resistance of SGT MOSFET, and also relates to a SGT MOSFET device, a method for manufacturing P-junction region and a SGT MOSFET device manufacturing method. BACKGROUND

[0002] SGT (Shielded Gate Transistor) MOSFET is a new type of power semiconductor device. SGT process is simpler than ordinary trench, and has smaller switching loss. In addition, SGT is 3-5 times deeper than ordinary trench process, and more epitaxial volume can be used to block voltage, which also makes the internal resistance of SGT more than 2 times lower than that of ordinary MOSFET.

[0003] The conventional SGT (Split-Gate-Trench) MOSFET structure and electric field distribution are shown in Figure 1 The N+ semiconductor substrate is arranged on the back metal layer 1 of the conventional SGT structure, the N- epitaxial layer 3 is formed on the surface of the N+ semiconductor substrate such as silicon substrate 2, the trench is formed in the N- epitaxial layer 3, the gate structure is formed in the trench, including the oxide layer 4, the source polysilicon 5, the IPO oxide layer 6, the gate polysilicon 7, the dielectric layer 8 and the gate oxide 13; the P-well region 11 is formed in the surface region of the N- epitaxial layer 3, the N- epitaxial layer 3 at the bottom of the P-well region 11 is used as the drift region; the N+ source region 10 is formed on the surface of the P-well region 11.

[0004] The SGT (Split-Gate-Trench) MOSFET structure has a charge coupling effect, which introduces horizontal depletion on the basis of vertical depletion of the traditional trench MOSFET, thereby obtaining higher device breakdown voltage (BV). In this way, a more concentrated N- epitaxial layer 3 can be used under the same breakdown voltage (BV), thereby reducing the on-resistance (Rdson). However, the conventional SGT MOSFET structure has a first electric field peak at the bottom of the P-well region 11, a second electric field peak at the bottom of the source polysilicon 5, and a concave distribution of electric field between the two peaks, which limits the voltage resistance of the device. SUMMARY

[0005] In order to solve the technical problems existing in the prior art, the present application provides a method for improving the voltage resistance of SGT MOSFET, which optimizes and improves the electric field distribution in the concave region between the first electric field peak and the second electric field peak, thereby improving the voltage resistance of the device.

[0006] The method for improving the voltage resistance of SGT MOSFET provided by the application introduces a third electric field peak between a first electric field peak formed at the bottom of the P-well region of the SGT MOSFET and a second electric field peak formed at the bottom of the source polysilicon, and the third electric field peak is used to pull up the electric field between the first electric field peak and the second electric field peak.

[0007] In some embodiments, the third electric field peak is introduced to the position with the lowest electric field intensity between the first electric field peak and the second electric field peak. The introduction of the third electric field peak to the position with the lowest electric field intensity further improves the voltage resistance effect.

[0008] Another aspect of the application provides an SGT MOSFET device including a P-junction region for forming a third electric field peak, which is formed between a first electric field peak formed at the bottom of the P-well region of the SGT MOSFET and a second electric field peak formed at the bottom of the source polysilicon.

[0009] In some embodiments, the P-junction region is located at the top region of the source polysilicon.

[0010] A third aspect of the application provides a method for manufacturing a P-junction region, which includes the following steps:

[0011] Step 1: boron-doped substance deposition;

[0012] Step 2: boron-doped substance etching to a specified position;

[0013] Step 3: high-temperature rapid annealing, so that the boron in the boron-doped substance diffuses into the Si material at the periphery of the trench to form a P-junction region.

[0014] In some embodiments, the boron-doped substance is etched to the top of the source polysilicon by 1500Ǻ~3000Ǻ.

[0015] In some embodiments, when the boron in the boron-doped substance diffuses into the Si material at the periphery of the trench, the concentration of the diffused boron is greater than the concentration of phosphorus in the substrate at the position, so as to ensure the formation of a stable and effective P-junction region.

[0016] In some embodiments, the annealing temperature in step 3 is between 800℃ and 1000℃.

[0017] The present application provides a SGT MOSFET device manufacturing method in this last aspect, the manufacturing method of the resulting SGT MOSFET device includes a P-junction region for forming a third electric field peak between a first electric field peak formed at the bottom of the P-well region of the SGT MOSFET and a second electric field peak formed at the bottom of the source polysilicon; the manufacturing method is manufactured according to the SGT process until the IPO oxide layer is deposited, and the following steps are performed during the oxide layer etching back:

[0018] Step one: etching back the oxide layer to below the source polysilicon;

[0019] Step two: boron-doped material deposition;

[0020] Step three: etching back the boron-doped material to a specified position;

[0021] Step four: high-temperature rapid annealing, diffusing boron in the boron-doped material into Si material outside the trench periphery to form a P-junction region;

[0022] Step five: boron-doped material removal;

[0023] After the boron-doped material is removed, the gate polysilicon, dielectric layer, front metal layer, N+ source region, P-well region, and gate oxide are manufactured according to the SGT process to obtain a SGT MOSFET device.

[0024] In some embodiments, the oxide layer is etched back to 1500Ǻ~2000Ǻ below the source polysilicon.

[0025] In some embodiments, the boron-doped material is etched back to 1500Ǻ~3000Ǻ above the source polysilicon top region.

[0026] In some embodiments, the annealing temperature is between 800℃~1000℃.

[0027] The technical scheme of the present application can achieve the following beneficial effects:

[0028] 1) The technical scheme introduces a third electric field peak, which improves the recessed electric field between the first and second electric field peaks, increases the area of the distance integral of the electric field strength, and realizes the improvement of the device voltage withstanding capability.

[0029] 2) The boron-doped material is etched back to 1500Ǻ~3000Ǻ above the source polysilicon top region, because the electric field strength near the P-well region is the lowest, the third electric field peak of the P-junction region is introduced to pull up, but it cannot be connected (connection may cause the threshold of the device to be too large, even unable to open), to more optimally improve the recessed region electric field distribution between the first and second electric field peaks, and the voltage withstanding improvement effect is better.

[0030] 3) The annealing temperature is controlled between 800-1000℃, which effectively prevents under-diffusion (P-junction region 12 is too shallow and low in concentration, affecting the improvement of voltage resistance) or over-diffusion (P-junction region is too deep, and in severe cases, the trenches are connected, and the device cannot be normally turned on). BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application. It is to be understood that the drawings are only schematic and that they do not necessarily represent a limiting case of the application. The embodiments described in the following description are only exemplary embodiments of the application. For a person skilled in the art, other embodiments can be derived from these drawings without inventive skill. In the drawings:

[0032] Figure 1 is a conventional SGT MOSFET structure and electric field distribution diagram;

[0033] Figure 2 is an SGT MOSFET structure and electric field distribution diagram provided by the application;

[0034] Figures 3-8 is a step-by-step schematic diagram of the SGT MOSFET device manufacturing method provided by the application;

[0035] In the drawings: In the drawings: 1-back metal layer, 2-N+ substrate, 3-N- epitaxial, 4-oxide layer, 5-source polysilicon, 6-IPO oxide layer, 7-gate polysilicon, 8-dielectric layer, 9-front metal layer, 10-N+ source region, 11-P-well region, 12-P-junction region, 13-gate oxide, 14-boron-doped substance. DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0037] The conventional SGT (Split-Gate-Trench) MOSFET structure and electric field distribution are shown in Figure 1 There is an electric field intensity peak 1 at the bottom of the P-well region 11, and an electric field intensity peak 2 at the bottom of the source polysilicon 5, and the electric field between the two peaks is concave, which limits the voltage resistance capability of the device.

[0038] The present application improves the electric field distribution in the recessed area by optimization, thereby improving the withstand voltage capability of the device. The present application introduces a third electric field peak between the first electric field peak formed at the bottom of the P-well region of the SGT MOSFET and the second electric field peak formed at the bottom of the source polysilicon, as shown in Figure 2 The withstand voltage of the SGT device is the integral of the electric field intensity with respect to distance. The introduction of the third electric field peak improves the recessed electric field between the first electric field peak and the second electric field peak, increases the area of the integral of the electric field intensity with respect to distance, and thereby improves the withstand voltage capability of the device.

[0039] In the present disclosure, the third electric field peak is used to optimize the recessed electric field between the first electric field peak and the second electric field peak, and its position can be set arbitrarily based on the characteristics of the SGT device. In the present disclosure, the third electric field peak is set at the position where the electric field intensity is the lowest near the P-well region 11. The third electric field peak is used to raise the electric field intensity at the position where the electric field intensity is the lowest, and the improvement of the withstand voltage is good.

[0040] The SGT MOSFET structure provided by the present application is Figure 2 An exemplary configuration includes a back metal layer 1, an N+ substrate 2, an N- epitaxial layer 3, an oxide layer 4, a source polysilicon 5, an IPO oxide layer 6, a gate polysilicon 7, a dielectric layer 8, a front metal layer 9, an N+ source region 10, a P-well region 11, a P-junction region 12, and a gate oxide 13. The N+ substrate 2 is arranged on the back metal layer 1. The N- epitaxial layer 3 is formed on the surface of the N+ substrate 2, such as a silicon substrate. A trench is formed in the N- epitaxial layer 3. A gate structure is formed in the trench, including the oxide layer 4, the source polysilicon 5, the IPO oxide layer 6, the gate polysilicon 7, the dielectric layer 8, and the gate oxide 13. The P-well region 11 is formed in the surface region of the N- epitaxial layer 3. The N- epitaxial layer 3 at the bottom of the P-well region 11 serves as a drift region. The N+ source region 10 is formed on the surface of the P-well region 11.

[0041] In the SGT MOSFET structure, the P-junction region 12 is used to form a third electric field peak, which is used to optimize the recessed electric field between the first electric field peak and the second electric field peak. The position of the P-junction region 12 can be set arbitrarily. Based on the characteristics of the SGT device, the P-junction region 12 is set at the top region of the source polysilicon 5, so that the third electric field peak formed by the P-junction region 12 raises the electric field intensity at the position where the electric field intensity is the lowest, and the improvement of the withstand voltage is good.

[0042] The P-junction region 12 in the present disclosure is prepared by depositing a boron-doped substance -> etching back the boron-doped substance -> high-temperature rapid annealing, and the specific steps are as follows:

[0043] Step one: depositing a boron-doped substance 14. The boron-doped substance 14 is deposited in the trench in a stacking manner, and the deposition thickness is sufficient to fill the trench, so as to ensure sufficient consumption for subsequent etching back.Figure 4 as shown.

[0044] Step two: boron-doped substance 14 is etched back, and the boron-doped substance 14 is etched back to a specified position, as shown in Figure 5 In this step, the boron-doped substance 14 is etched back to a specified position by dry etching, wet etching, CMP, or other etching methods.

[0045] Step three: high-temperature rapid annealing, so that the boron in the boron-doped substance 14 diffuses into the Si material outside the trench to form a P-junction region 12, as shown in Figure 6 After the boron in the boron-doped substance 14 diffuses, its concentration is greater than that of phosphorus in the N-epitaxial layer 3 at this position, so as to ensure the formation of an effective P-junction region 12.

[0046] In order to prevent the boron from being under-diffused and causing the P-junction region 12 to be very shallow and have a very low concentration, affecting the voltage endurance improvement effect, or over-diffused and causing the P-junction region 12 to be too deep, and in severe cases causing the trenches to be connected, the device cannot be normally turned on, the annealing temperature is controlled to be between 800°C and 1000°C during the high-temperature rapid annealing process.

[0047] When the boron-doped substance 14 is etched back, the specified position is any position in the region corresponding to the recessed electric field between the first electric field peak and the second electric field peak, as shown in Figure 1 any position in the region between the upper dashed line and the lower dashed line in the electric field distribution, but cannot be connected to the P-well region 11; in this case, the boron-doped substance 14 is etched back to the top of the source polysilicon 5 by 1500Ǻ-3000Ǻ, and this position is close to the P-well region 11 with the lowest electric field intensity, and the introduction of the P-junction region 12 peak 3 can improve the voltage endurance, but cannot be connected to the P-well region 11 (connection may cause the threshold of the device to be too large, or even unable to be turned on), so that the voltage endurance improvement effect is better, of course, it can be understood that the boron-doped substance 14 can also be etched back to other positions to improve the recessed electric field, so as to optimize the recessed electric field effect and improve the voltage endurance of the device.

[0048] In combination with Figures 3-8 , the SGT MOSFET device provided in the present application is manufactured according to the conventional SGT MOSFET process until the IPO oxide layer 6 is deposited, and the following steps are performed when the oxide layer 4 is etched back:

[0049] Step one: etch back the oxide layer 4 to 1500Ǻ-2000Ǻ below the source polysilicon 5 or other positions, as shown in Figure 3 .

[0050] Step two: deposit the boron-doped substance 14, and the boron-doped substance 14 is deposited in the trench by stacking, and the deposition thickness fills the trench, as shown in Figure 4 .

[0051] Step three: Boron-doped substance 14 is etched back, and the Boron-doped substance 14 is etched back to a specified position, as shown in FIG. 4; here, the specified position is any position in the region corresponding to the recessed electric field between the first electric field peak and the second electric field peak, as shown in the area between the upper dashed line and the lower dashed line in the electric field distribution, but cannot be connected with the P-well region 11, that is, the P-junction region 12 cannot be connected with the P-well region 11, otherwise the device cannot be turned on; in this embodiment, the Boron-doped substance 14 is etched back to the top of the source polysilicon 5 by 1500-3000 angstroms, and this position is close to the position where the electric field intensity of the P-well region 11 is the lowest, and the peak 3 of the P-junction region 12 is introduced to increase the voltage resistance, but cannot be connected with the P-well region 11 (after being connected, the threshold value of the device can be too large, and the device can even not be turned on), so that the voltage resistance improvement effect is better; in this step, the etching back of the Boron-doped substance 14 can be performed in a dry etching mode, a wet etching mode, CMP, or other etching modes capable of etching back the Boron-doped substance 14 to the specified position. Figure 5 Figure 1

[0052] Step four: high-temperature rapid annealing, so that the Boron in the Boron-doped substance 14 diffuses into the Si material outside the trench to form the P-junction region 12, as shown in FIG. 5; the annealing temperature is controlled to be between 800-1000 degrees Celsius. Figure 6

[0053] Step five: the Boron-doped substance 14 is removed, and the silicon is as shown in FIG. 6; the Boron-doped substance 14 contains a certain amount of Boron, and if it is not removed, it will continue to diffuse in the subsequent process, which is not conducive to the control of the device structure; after the Boron-doped substance 14 is removed, the gate polysilicon, the dielectric layer, the front metal layer, the N+ source region, the P-well region, and the gate oxide are manufactured according to the SGT process to obtain an SGT MOSFET device, as shown in FIG. 7. Figure 7 Figure 8

[0054] When the Boron-doped substance 14 is removed, wet removal is adopted, which can effectively avoid the loss of the trench sidewall and thus affect the performance of the device.

[0055] In this disclosure, the Boron-doped substance 14 is the source of Boron, and the P-junction region 12 is formed by Boron diffusion; here, the Boron-doped substance 14 is configured as borosilicate glass BSG, and the P-junction region 12 is formed on the top of the source polysilicon 5 by the borosilicate glass BSG, or is configured as polysilicon to replace the borosilicate glass BSG to obtain the P-junction region 12; or other Boron-doped substances.

[0056] ​​​​​The SGT MOSFET device in the present disclosure can be manufactured according to the manufacturing method disclosed in the prior art SGT device and the manufacturing method thereof (publication number: CN109935517A, publication date: June 25, 2019) until the IPO oxide layer 6 is deposited, the oxide layer 4 is etched back, and the boron-doped substance is removed. Of course, it can be understood that it can also be manufactured according to other conventional SGT MOSFET processes.

[0057] The technical scheme of the present application introduces a third electric field peak to improve the recessed electric field between the first electric field peak and the second electric field peak, and compared with the conventional SGT MOSFET, the device withstand voltage capacity is obviously improved; the P-junction region 12 in the SGT MOSFET device cannot be connected with the P-well region 11, otherwise it will cause the device to be unable to turn on.

[0058] The present disclosure has been described by the above-mentioned related embodiments, however, the above-mentioned embodiments are only examples for implementing the present disclosure. It must be pointed out that the disclosed embodiments do not limit the scope of the present disclosure. On the contrary, variations and modifications made without departing from the spirit and scope of the present disclosure are within the scope of the patent protection of the present disclosure.

Claims

1. An SGT MOSFET device, characterized by, The device comprises a P-junction region for forming a third electric field peak, which is formed between a first electric field peak formed at the bottom of a P-well region of the SGT MOSFET and a second electric field peak formed at the bottom of a source polysilicon, for pulling up the electric field between the first electric field peak and the second electric field peak; The third electric field peak is introduced to the lowest electric field intensity between the first electric field peak and the second electric field peak; The P-junction region is not connected to the P-well region, and is prepared by the following steps: Step one: boron-doped substance deposition; Step two: boron-doped substance etching to a specified position; Step three: high-temperature rapid annealing at 800-1000°C, so that boron in the boron-doped substance diffuses into Si material outside the trench, and the boron concentration after diffusion is greater than the phosphorus concentration of the substrate at this position, forming a P-junction region.

2. The SGT MOSFET device of claim 1, wherein, The P-junction region is located at the top region of the source polysilicon.

3. A method of fabricating an SGT MOSFET device, characterized by, The manufacturing method produces an SGT MOSFET device comprising a P-junction region for forming a third electric field peak, which is formed between a first electric field peak formed at the bottom of a P-well region of the SGT MOSFET and a second electric field peak formed at the bottom of a source polysilicon, for pulling up the electric field between the first electric field peak and the second electric field peak, and the P-junction region is not connected to the P-well region; the manufacturing method performs the following steps during oxidation layer etching before IPO oxidation layer deposition according to the SGT process: Step one: etching the oxidation layer to below the source polysilicon; Step two: boron-doped substance deposition; Step three: boron-doped substance etching to a specified position; Step four: high-temperature rapid annealing at 800-1000°C, so that boron in the boron-doped substance diffuses into Si material outside the trench, and the boron concentration after diffusion is greater than the phosphorus concentration of the substrate at this position, forming a P-junction region; Step five: boron-doped substance removal; After the boron-doped substance is removed, gate polysilicon, dielectric layer, front metal layer, N+ source region, P-well region, and gate oxide are manufactured according to the SGT process to obtain an SGT MOSFET device.

4. The SGT MOSFET device fabrication method of claim 3, wherein: The oxidation layer is etched to below the source polysilicon by 1500-2000Å.

5. The method of claim 3, wherein: The boron-doped substance is etched to the top region of the source polysilicon by 1500-3000Å.

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