Semiconductor Structure, Method for Manufacturing the Same, and Memory

Abstract

An embodiment of the present application discloses a semiconductor structure, a manufacturing method thereof, and a memory. The method includes: providing a substrate structure on which at least a first dielectric layer is formed; forming a first portion of a second dielectric layer on the first dielectric layer, the first portion of the second dielectric layer having a first wet etching rate in an etching solution; forming a second portion of the second dielectric layer on the first portion of the second dielectric layer, the second portion of the second dielectric layer having a second wet etching rate in the etching solution; wherein the second rate is less than the first rate; after forming the second portion of the second dielectric layer, the mass percentage of a first element in the first dielectric layer is less than a first preset value.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure, a manufacturing method thereof, and a memory. Background Art

[0002] Three-dimensional cross-point memory, such as phase change memory (PCM), is a storage technology that uses chalcogenide as a storage medium and utilizes the resistance difference of materials in different states to store data. PCM has advantages such as bit-addressability, data non-loss after power-off, high storage density, and fast read / write speed, and is considered to be the most promising next-generation memory.

[0003] However, in related technologies, three-dimensional cross-point memory still faces various challenges. Summary of the Invention

[0004] To solve the problems in related technologies, embodiments of this application propose a semiconductor structure, a manufacturing method thereof, and a memory.

[0005] Embodiments of this application provide a manufacturing method of a semiconductor structure, the method including:

[0006] Providing a substrate structure, on which at least a first dielectric layer is formed;

[0007] Forming a first part of a second dielectric layer on the first dielectric layer, the first part of the second dielectric layer having a first wet etching rate in an etching solution;

[0008] Forming a second part of the second dielectric layer on the first part of the second dielectric layer, the second part of the second dielectric layer having a second wet etching rate in the etching solution;

[0009] Wherein, the second rate is less than the first rate; after forming the second part of the second dielectric layer, the mass percentage of a first element in the first dielectric layer is less than a first preset value.

[0010] In the above solution, the forming of the first part of the second dielectric layer on the first dielectric layer includes:

[0011] Forming the first part of the second dielectric layer on the first dielectric layer by applying a first power;

[0012] The forming of the second part of the second dielectric layer on the first part of the second dielectric layer includes:

[0013] Forming the second part of the second dielectric layer on the first part of the second dielectric layer by applying a second power;

[0014] Wherein, the first power is less than the second power.

[0015] In the above solution,

[0016] Forming the first part of the second dielectric layer on the first dielectric layer includes:

[0017] Introducing a first gas at a first gas flow rate to form the first part of the second dielectric layer on the first dielectric layer;

[0018] Forming the second part of the second dielectric layer on the first part of the second dielectric layer includes:

[0019] Introducing the first gas at a second gas flow rate to form the second part of the second dielectric layer on the first part of the second dielectric layer;

[0020] Wherein, the first gas flow rate is less than the second gas flow rate.

[0021] In the above solution,

[0022] The first gas includes oxygen.

[0023] In the above solution, the material of the first dielectric layer includes silicon nitride, the material of the second dielectric layer includes silicon oxide, and the first element includes oxygen element.

[0024] In the above solution,

[0025] Forming the first part of the second dielectric layer on the first dielectric layer includes:

[0026] Using plasma enhanced atomic layer deposition (PEALD, Plasma Enhanced Atomic Layer Deposition) process or plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition) process to form the first part of the second dielectric layer on the first dielectric layer;

[0027] Forming the second part of the second dielectric layer on the first part of the second dielectric layer includes:

[0028] Using plasma enhanced atomic layer deposition process or plasma enhanced chemical vapor deposition process to form the second part of the second dielectric layer on the first part of the second dielectric layer.

[0029] In the above solution,

[0030] A plurality of memory cells are further formed on the substrate structure, trenches are formed between the plurality of memory cells, and the first dielectric layer is formed in the trenches;

[0031] Forming the first portion of the second dielectric layer on the first dielectric layer includes: forming the first portion of the second dielectric layer in the trench formed with the first dielectric layer;

[0032] Forming the second portion of the second dielectric layer on the first portion of the second dielectric layer includes: forming the second portion of the second dielectric layer in the trench formed with the first dielectric layer and the first portion of the second dielectric layer.

[0033] An embodiment of the present application further provides a semiconductor structure, including: a substrate structure, on which at least a first dielectric layer is formed;

[0034] The first portion of the second dielectric layer covering the first dielectric layer; and

[0035] The second portion of the second dielectric layer covering the first portion of the second dielectric layer;

[0036] Wherein, the wet etching rate of the second portion of the second dielectric layer in the etching solution is less than the wet etching rate of the first portion of the second dielectric layer in the etching solution, and the mass percentage of the first element in the first dielectric layer is less than the first preset value.

[0037] In the above solution, the material of the first dielectric layer includes silicon nitride, the material of the second dielectric layer includes silicon oxide, and the first element includes oxygen element.

[0038] An embodiment of the present application further provides a memory, including:

[0039] A substrate structure, on which a first dielectric layer and a plurality of memory cells are formed. Among them, trenches are formed between the plurality of memory cells, and the first dielectric layer is formed in the trenches;

[0040] The first portion of the second dielectric layer formed in the trench and covering the first dielectric layer; and

[0041] The second portion of the second dielectric layer formed in the trench and covering the first portion of the second dielectric layer;

[0042] Wherein, the wet etching rate of the second portion of the second dielectric layer in the etching solution is less than the wet etching rate of the first portion of the second dielectric layer in the etching solution, and the mass percentage of the first element in the first dielectric layer is less than the first preset value.

[0043] In the above solution, the material of the first dielectric layer includes silicon nitride, the material of the second dielectric layer includes silicon oxide, and the first element includes oxygen element.

[0044] In the above solution, the memory includes a phase change memory, and the storage unit includes a phase change memory PCM element, a selection element, and a plurality of electrodes which are stacked.

[0045] An embodiment of the present application provides a semiconductor structure, a manufacturing method thereof, and a memory. The method includes: providing a substrate structure on which at least a first dielectric layer is formed; forming a first part of a second dielectric layer on the first dielectric layer, where the first part of the second dielectric layer has a first wet etching rate in an etching solution; forming a second part of the second dielectric layer on the first part of the second dielectric layer, where the second part of the second dielectric layer has a second wet etching rate in the etching solution; where the second rate is less than the first rate; after forming the second part of the second dielectric layer, the mass percentage of a first element in the first dielectric layer is less than a first preset value. In the embodiment of the present application, the first part of the second dielectric layer with a higher wet etching rate is formed first, and then the second part of the second dielectric layer with a lower wet etching rate is formed. Since the first part of the second dielectric layer formed first can protect the first dielectric layer, the problem that the first dielectric layer is denatured when forming the second part of the second dielectric layer is improved, and at the same time, it does not affect the formation of a high-quality second dielectric layer. Description of the Drawings

[0046] Figure 1 It is a schematic flow chart of the implementation of a manufacturing method of a semiconductor structure provided by an embodiment of the present application;

[0047] Figures 2a - 2c It is a schematic structural diagram in a manufacturing method of a semiconductor structure provided by an embodiment of the present application;

[0048] Figures 3a - 3c It is a schematic structural diagram in a manufacturing method of a semiconductor structure provided by another embodiment of the present application;

[0049] Figure 4 It is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application;

[0050] Figure 5 It is a schematic diagram of the contents of oxygen and nitrogen elements in the first dielectric layer of a semiconductor structure provided by an embodiment of the present application;

[0051] Figure 6 It is a schematic diagram of the contents of oxygen and nitrogen elements in the first dielectric layer of a semiconductor structure provided by another embodiment of the present application. Detailed Embodiments

[0052] Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0053] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, to avoid obscuring the present application, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0054] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals denote like elements throughout.

[0055] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, or portion discussed below can be denoted as the second element, component, region, layer, or portion. And when discussing the second element, component, region, layer, or portion, it does not imply that the present application necessarily has a first element, component, region, layer, or portion.

[0056] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0057] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0058] In order to be able to more fully understand the characteristics and technical content of the embodiments of the present application, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present application.

[0059] The semiconductor structure involved in the embodiments of the present application is to be used in subsequent processes to form at least a part of the final device structure. Here, the final device may include a memory, and the memory includes, but is not limited to, a phase change memory. Only the phase change memory will be taken as an example for illustration below.

[0060] In a phase change memory, it is necessary to seal and protect the memory cells of the phase change memory. In an embodiment of the present application, silicon nitride for encapsulation (PPSiN) is filled in the trenches between the memory cells, and then silicon oxide is filled in the trenches filled with silicon nitride. By filling silicon nitride and silicon oxide, it plays an important role in protecting the memory cells of the PCM. In an embodiment of the present application, the method of filling silicon oxide into the trenches between the memory cells is the plasma enhanced atomic layer deposition method. Since the plasma enhanced atomic layer deposition method can form a high-quality silicon oxide film with good densification and uniformity, it can protect the formed silicon nitride and avoid damage to the silicon nitride in subsequent processes, thereby playing a good sealing role for the memory cells of the PCM.

[0061] However, it is found in the research that when forming silicon oxide by using the plasma enhanced atomic layer deposition method, due to the use of a relatively high power, the formed silicon nitride combines with oxygen ions (O2 + ) under the condition of high power to undergo oxidation and form oxides. The oxidation of the formed silicon nitride deteriorates the quality of the silicon nitride, thereby deteriorating the encapsulation ability of the silicon nitride for the memory cells of the PCM.

[0062] Therefore, the following technical solutions of the embodiments of the present application are proposed.

[0063] An embodiment of the present application provides a manufacturing method of a semiconductor structure, Figure 1 which is a schematic implementation flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present application. As Figure 1 shown, the method includes the following steps:

[0064] Step 101: Provide a substrate structure, on which at least a first dielectric layer is formed;

[0065] Step 102: Form a first part of a second dielectric layer on the first dielectric layer, and the first part of the second dielectric layer has a first wet etching rate in an etching solution;

[0066] Step 103: Form a second part of the second dielectric layer on the first part of the second dielectric layer, and the second part of the second dielectric layer has a second wet etching rate in the etching solution;

[0067] Wherein, the second rate is less than the first rate; after forming the second part of the second dielectric layer, the mass percentage of the first element in the first dielectric layer is less than a first preset value.

[0068] In step 101, referring to Figure 2a , provide a substrate 201, and a first dielectric layer 202 is formed on the substrate 201.

[0069] The substrate 201 can be a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0070] The method for forming the first dielectric layer 202 includes but is not limited to chemical vapor deposition process, atomic layer deposition process, physical vapor deposition, etc.

[0071] In some embodiments, the material of the first dielectric layer 202 includes silicon nitride.

[0072] It should be noted that the materials of the first dielectric layer 202 shown above are only used as examples. In the present application, the materials of the first dielectric layer 202 include but are not limited to silicon nitride, and the materials of the first dielectric layer 202 can also include silicon and any other materials that are prone to denaturation under the condition of applying high power.

[0073] In step 102, refer to Figure 2b , a first part 203 of a second dielectric layer is formed on the first dielectric layer 202. The second dielectric layer can include a first part and a second part. Here, the first part 203 of the second dielectric layer is formed first.

[0074] In some embodiments, forming the first part of the second dielectric layer on the first dielectric layer includes:

[0075] By applying a first power, a first part 203 of a second dielectric layer is formed on the first dielectric layer.

[0076] Here, the power is applied to the machine during the deposition of the second dielectric layer. The applied power can be used to generate plasma to form the second dielectric layer. The first power is a relatively low power that can generate a small amount of plasma.

[0077] In some embodiments, the range of the first power is: 200w - 500w.

[0078] In some embodiments, forming the first part 203 of the second dielectric layer on the first dielectric layer 202 includes:

[0079] A first gas is introduced at a first gas flow rate to form a first part 203 of a second dielectric layer on the first dielectric layer 202.

[0080] Here, the first gas is a precursor for forming the second dielectric layer. The flow rate of the first gas refers to the volume of the first gas introduced per unit time. By controlling the flow rate of the first gas, the content of the first gas per unit time can be controlled. The flow rate of the first gas is a relatively low flow rate of the first gas, and under the condition of the flow rate of the first gas, the content of the first gas per unit time is relatively small.

[0081] Here, the range of the flow rate of the first gas is: 200 sccm - 500 sccm.

[0082] In step 103, referring to Figure 2c , the second part 204 of the second dielectric layer is formed on the first part 203 of the second dielectric layer.

[0083] In some embodiments, forming the second part of the second dielectric layer on the first part of the second dielectric layer includes:

[0084] Forming the second part of the second dielectric layer on the first part of the second dielectric layer by applying a second power;

[0085] Wherein, the first power is less than the second power.

[0086] The second power is a relatively high power capable of generating a large amount of plasma.

[0087] In some embodiments, the range of the second power is: greater than 1000 w.

[0088] Here, the wet etching rate is an important index characterizing the properties of the dielectric thin film. It can be understood that the wet etching rate is closely related to the denseness of the thin film. The lower the wet etching rate, the better the denseness of the thin film, and the higher the wet etching rate, the worse the denseness of the thin film. That the second rate is less than the first rate can be understood as that the denseness of the second part of the second dielectric layer is better than that of the first part of the second dielectric layer.

[0089] In some specific examples, the etching solution may be hydrofluoric acid diluted according to a volume ratio of water to hydrofluoric acid of 1000:1. In practical applications, the etching solution is not limited thereto.

[0090] In some specific examples, the range of the first rate is: greater than / Min; the range of the second rate is: less than / Min. It should be noted that the first rate and the second rate given here are only exemplary demonstrations and are not used to limit the ranges of the first rate and the second rate in the present application.

[0091] Exemplarily, the first rate may be / Min, and the second rate may be / Min.

[0092] In some embodiments, the material of the second dielectric layer includes silicon oxide, and the first element includes oxygen.

[0093] It should be noted that the material of the second dielectric layer shown above is only used as an example, and the material of the second dielectric layer is not limited to silicon oxide. The material of the second dielectric layer can be any material generated by applying a higher power and introducing a gas that is likely to denature the first dielectric layer 202.

[0094] Here, the first power being less than the second power can be understood as follows: when forming silicon oxide, first apply a lower first power to form a thinner layer of silicon oxide, which improves the problem of oxidation of the already formed silicon nitride and denaturation of the silicon nitride when forming silicon oxide at a high power; then apply a higher second power to form a thicker silicon oxide. Since the thinner layer of silicon oxide formed by applying the first power first protects the silicon nitride, when applying the higher second power subsequently, a high-quality silicon oxide thin film can be formed without damaging the already formed silicon nitride.

[0095] In some specific examples, the range of the first part of the second dielectric layer in the total thickness of the second dielectric layer is: 20% - 25%.

[0096] Here, after forming the second part 204 of the second dielectric layer, the mass percentage of the first element in the first dielectric layer 202 is less than a first preset value, which can be understood as follows: since silicon nitride is prone to denaturation, such as oxidation, under the condition of applying the second power, in the embodiments of the present application, by first applying the first power to form a low-quality ultra-thin silicon oxide thin film to protect the already formed silicon nitride, and then applying the second power to form the second part of high-quality silicon oxide, the oxidation problem of the already formed silicon nitride is improved, so that the mass percentage of oxygen element in the silicon nitride is less than the first preset value after forming the second part of the silicon oxide.

[0097] It can be understood that the wet etching rate of the first part of the second dielectric layer formed at a lower power is greater than the wet etching rate of the second part of the second dielectric layer formed at a higher power, indicating that the performance (such as compactness) of the second part is much better than that of the first part, and it can play a protective role required by the device. Here, high quality can be understood as better compactness of the thin film, and low quality can be understood as poorer compactness of the thin film.

[0098] Here, the first preset value can be set according to specific circumstances. The smaller the first preset value, the higher the quality requirement for the silicon nitride. In practical applications, the finally formed silicon nitride can meet the process requirements. An exemplary value of the first preset value is given in the application scenario of the memory introduced below.

[0099] In some embodiments, forming the second part 204 of the second dielectric layer on the first part 203 of the second dielectric layer includes:

[0100] Introducing a first gas at a second gas flow rate to form the second part 204 of the second dielectric layer on the first part 203 of the second dielectric layer;

[0101] Wherein, the first gas flow rate is less than the second gas flow rate.

[0102] Here, the second gas flow rate is the flow rate of the first gas at a higher level, and the content of the first gas per unit time is higher under the condition of the second gas flow rate.

[0103] In some embodiments, the second gas flow rate is greater than 1000 sccm.

[0104] It should be noted that the ranges of the above first power, second power, first gas flow rate, and second gas flow rate are only used as examples and are not used to limit the magnitudes of the first power, second power, first gas flow rate, and second gas flow rate in the present application.

[0105] In some embodiments, the first gas includes oxygen.

[0106] It should be noted that the material of the first gas shown above is only used as an example, and the first gas is not limited to oxygen. The first gas can be any gas that is likely to cause the first dielectric layer 202 to denature under high-power conditions.

[0107] It can be understood that since silicon nitride is more likely to undergo oxidation denaturation at higher power and higher oxygen flow rates, in the embodiments of the present application, by first forming the first part of silicon oxide at a lower oxygen flow rate and then forming the second part of silicon oxide at a higher oxygen flow rate, the oxidation of the already formed silicon nitride can be further reduced due to the lower oxygen flow rate when forming the first part of silicon oxide. After forming the first part of silicon oxide, the second part of silicon oxide is formed at a higher oxygen flow rate. In this way, both the oxidation effect on silicon oxide is reduced and the formation of high-quality silicon nitride is not affected.

[0108] In some embodiments, forming the first part 203 of the second dielectric layer on the first dielectric layer 202 includes:

[0109] Using plasma-enhanced atomic layer deposition process or plasma-enhanced chemical vapor deposition process to form the first part 203 of the second dielectric layer on the first dielectric layer 202;

[0110] Forming the second part 204 of the second dielectric layer on the first part 203 of the second dielectric layer includes:

[0111] The second part 204 of the second dielectric layer is formed on the first part 203 of the second dielectric layer by using a plasma-enhanced atomic layer deposition process or a plasma-enhanced chemical vapor deposition process.

[0112] It should be noted that the method for forming the second dielectric layer in the embodiments of the present application includes, but is not limited to, the above-mentioned plasma-enhanced atomic layer deposition process or plasma-enhanced chemical vapor deposition process, and may also include any other deposition process using plasma.

[0113] Taking the process of plasma-enhanced atomic layer deposition as an example, a brief introduction to the plasma-enhanced atomic layer deposition process is as follows. Atomic layer deposition is to alternately introduce gas-phase precursors in a heated reactor, and grow ultra-thin films with self-limiting growth through alternating surface saturation reactions. Atomic layer deposition has inherent advantages compared with traditional deposition processes such as metal-organic chemical vapor deposition, molecular beam epitaxy, and physical vapor deposition: it precisely controls the thickness of the thin film by controlling the number of reaction cycles; the growth rate is not affected by the size of the substrate area, the temperature distribution in the substrate, and the shape of the gas flow, etc., and a uniform film thickness can be obtained. Plasma-enhanced atomic layer deposition is an extension of atomic layer deposition. By introducing plasma, a large number of active radicals are generated, enhancing the reaction activity of precursor substances, thereby expanding the selection range and application requirements of precursors for atomic layer deposition, shortening the time of the reaction cycle, and at the same time reducing the requirement for the deposition temperature of the sample, enabling low-temperature or even room-temperature deposition. In addition, the introduction of plasma can further remove impurities in the thin film, and lower resistivity and higher film density can be obtained. Plasma can also clean the reaction chamber and perform surface activation treatment on the substrate, etc.

[0114] In some embodiments, referring to Figure 3a , a plurality of memory cells 305 are further formed on the substrate 301 structure, trenches 306 are formed between the plurality of memory cells 305, and the first dielectric layer 302 is formed in the trenches 306;

[0115] Referring to Figure 3b , forming the first part 303 of the second dielectric layer on the first dielectric layer 302 includes: forming the first part 303 of the second dielectric layer in the trench 306 where the first dielectric layer 302 is formed;

[0116] Referring to Figure 3c , forming the second part 304 of the second dielectric layer on the first part 303 of the second dielectric layer includes: forming the second part 304 of the second dielectric layer in the trench 306 where the first dielectric layer 302 and the first part 303 of the second dielectric layer are formed.

[0117] Here, each of the multiple memory cells 305 is located on the same plane and is columnar, and grooves 306 are formed between the multiple memory cells 305. In practical applications, after the memory cells 305 are formed, some dielectric materials need to be filled into the grooves 306 to protect the memory cells 305 and isolate each memory cell 305 at the same time. In practical applications, the method of forming the columnar memory cells 305 may include an etching process, including but not limited to dry etching.

[0118] In some embodiments, as Figure 4 shown, the memory includes a phase change memory, and the memory cell 305 includes a phase change memory PCM element 405, a select element 404, and multiple electrodes 403 stacked. The memory further includes a substrate 301, a peripheral circuit 401 located on the substrate 301, and an interconnect layer 402 located on the peripheral circuit 401.

[0119] In practical applications, the heating or quenching of the PCM element 405 by the electrode 403 is achieved by the conduction of the select element 404 to achieve the switching between the crystalline state and the amorphous state of the PCM element 405; the storage of data is achieved by the switching between the crystalline state and the amorphous state of the PCM element 405. In practical applications, the material of the PCM element 405 includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or includes any other suitable phase change material; the material of the select element 404 may include any suitable OTS material, such as Zn x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te z etc.; the material of the electrode 403 may include a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicide, or any combination thereof. In some specific embodiments, the material of the electrode 403 includes carbon, such as amorphous carbon.

[0120] Silicon nitride can be used to prevent water vapor, oxygen, etc. from entering the PCM element 405 and the select element 404 in the memory cell 305 to avoid affecting the performance of the phase change memory. The silicon oxide formed by plasma-enhanced atomic layer deposition can protect the formed silicon nitride from being damaged in subsequent processes, that is, under the combined action of silicon oxide and silicon nitride, the PCM element 405 and the select element 404 in the memory cell 305 can be better protected.

[0121] Figure 5 It shows a schematic diagram of the contents of oxygen and nitrogen elements in silicon nitride formed by the method of one-step plasma-enhanced atomic layer deposition in the embodiments of the present application; Figure 6 It shows a schematic diagram of the contents of oxygen and nitrogen elements in silicon nitride formed by the method of two-step plasma-enhanced atomic layer deposition in the embodiments of the present application. It is found that the mass percentage of oxygen element in silicon nitride formed by the method of one-step plasma-enhanced atomic layer deposition is about 42.2%, and the mass percentage of nitrogen element is about 21.4%; while the mass percentage of oxygen element in silicon nitride formed by the method of two-step plasma-enhanced atomic layer deposition is about 14.7%, and the mass percentage of nitrogen element is about 46%. It can be seen that after the silicon oxide is formed by the two-step method in the present application, the content of oxygen element in the silicon nitride is significantly reduced. Therefore, the first preset value here can be 30%.

[0122] It can be understood that in some embodiments when forming silicon oxide, although the method of one-step plasma-enhanced atomic layer deposition can form silicon oxide with good compactness and uniformity at a relatively fast speed, due to the too high plasma energy and too large oxygen flow rate, it will cause a certain damage to the already formed silicon nitride, and an oxide layer will be formed on the surface of the silicon nitride, reducing the protection performance of the silicon nitride for the storage unit. The embodiments of the present application adopt a multi-step scheme for forming silicon oxide in the process of plasma-enhanced atomic layer deposition, so as to not only maintain the high quality of the silicon oxide, but also improve the damage to the already formed silicon nitride.

[0123] In the embodiments of the present application, the silicon oxide formed by the method of plasma-enhanced atomic layer deposition has good uniformity and compactness, can shorten the reaction cycle, save reaction time, reduce production costs, and in addition, because the reaction can be carried out at low temperature or even room temperature, damage to the storage unit caused by high temperature when forming silicon oxide can be avoided.

[0124] In the embodiments of the present application, during the deposition process of plasma-enhanced atomic layer deposition and plasma-enhanced chemical vapor deposition, the main deposition step is divided into two steps, different powers are applied in different steps, a relatively low power and a relatively low oxygen flow rate are applied in the starting step, and a relatively high power and a relatively high oxygen flow rate are applied in the subsequent step. On the one hand, it improves the problem of damage to the surface of the silicon nitride; on the other hand, because a relatively low power is used in the starting step, the stress of the first part of the formed silicon oxide is small, so that the adhesion between the silicon nitride and the second part of the silicon oxide can be increased; on the third hand, applying a relatively high power and a relatively high oxygen flow rate in the subsequent step enables the quality of the second part of the silicon oxide to be guaranteed. Thus, the protection effect of the silicon nitride on the storage unit of the PCM can be improved.

[0125] An embodiment of the present application provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate structure, on which at least a first dielectric layer is formed; forming a first portion of a second dielectric layer on the first dielectric layer, the first portion of the second dielectric layer having a first wet etching rate in an etching solution; forming a second portion of the second dielectric layer on the first portion of the second dielectric layer, the second portion of the second dielectric layer having a second wet etching rate in the etching solution; wherein the second rate is less than the first rate; after forming the second portion of the second dielectric layer, the mass percentage of a first element in the first dielectric layer is less than a first preset value. In the embodiment of the present application, the first portion of the second dielectric layer with a higher wet etching rate is formed first, and then the second portion of the second dielectric layer with a lower wet etching rate is formed. Since the first portion of the second dielectric layer formed first can protect the first dielectric layer, the problem of denaturation of the first dielectric layer during the formation of the second portion of the second dielectric layer is improved, and at the same time, the formation of a high-quality second dielectric layer is not affected.

[0126] Based on the above method for manufacturing a semiconductor structure, an embodiment of the present application further provides a semiconductor structure, comprising: a substrate structure, on which at least a first dielectric layer is formed;

[0127] a first portion of a second dielectric layer covering the first dielectric layer; and

[0128] a second portion of the second dielectric layer covering the first portion of the second dielectric layer;

[0129] wherein the second portion of the second dielectric layer has a wet etching rate in the etching solution less than that of the first portion of the second dielectric layer in the etching solution, and the mass percentage of the first element in the first dielectric layer is less than a first preset value.

[0130] In some embodiments, the material of the first dielectric layer includes silicon nitride, the material of the second dielectric layer includes silicon oxide, and the first element includes oxygen.

[0131] Based on the above method for manufacturing a semiconductor structure, an embodiment of the present application further provides a memory, comprising:

[0132] a substrate structure, on which a first dielectric layer and a plurality of memory cells are formed, trenches are formed between the plurality of memory cells, and the first dielectric layer is formed in the trenches;

[0133] a first portion of a second dielectric layer formed in the trenches and covering the first dielectric layer; and

[0134] A second portion of the second dielectric layer that is formed in the trench and covers the first portion of the second dielectric layer;

[0135] Wherein, the wet etching rate of the second portion of the second dielectric layer in the etching solution is less than the wet etching rate of the first portion of the second dielectric layer in the etching solution, and the mass percentage of the first element in the first dielectric layer is less than a first preset value.

[0136] In some embodiments, the material of the first dielectric layer includes silicon nitride, the material of the second dielectric layer includes silicon oxide, and the first element includes oxygen.

[0137] In some embodiments, the memory includes a phase change memory, and the storage unit includes a phase change memory PCM element, a select gate element, and a plurality of electrodes that are stacked.

[0138] The memory related to the embodiments of the present application may include a three-dimensional memory composed of vertically and horizontally interleaved bit lines, word lines, and storage units, including but not limited to PCM, ferroelectric memory (FeRAM, Ferroelectric, Random Access Memory), magnetic memory (MRAM, Magnetoresistive Random Access Memory), resistive random access memory (RRAM, Resistive Random Access Memory), etc.

[0139] It should be noted that the solution provided by the embodiments of the present application is not only applicable to the above-mentioned memories, but also applicable to any semiconductor structure that needs to form a first dielectric layer and a second dielectric layer, and the first dielectric layer is prone to denaturation when forming the second dielectric layer.

[0140] The relevant details of the semiconductor structure and the memory introduced above have been described in detail in the corresponding manufacturing method, and will not be repeated here.

[0141] It should be understood that "an embodiment" or "one embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in an embodiment" or "in one embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the magnitudes of the sequence numbers of the above processes do not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The sequence numbers of the embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0142] In the method disclosed in several method embodiments provided by this application, they can be arbitrarily combined without conflict to obtain new method embodiments.

[0143] As described above, it is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claimed rights.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, The method includes: Providing a substrate structure, on which at least a first dielectric layer is formed; By applying a first power, using a plasma-enhanced atomic layer deposition process or a plasma-enhanced chemical vapor deposition process, forming a first portion of a second dielectric layer on the first dielectric layer, the first portion of the second dielectric layer having a first wet etching rate in an etching solution; By applying a second power, using a plasma-enhanced atomic layer deposition process or a plasma-enhanced chemical vapor deposition process, forming a second portion of the second dielectric layer on the first portion of the second dielectric layer, the second portion of the second dielectric layer having a second wet etching rate in the etching solution; wherein, the first power is less than the second power; the applied first power and the second power are used to generate plasma; Wherein, the second rate is less than the first rate; after forming the second portion of the second dielectric layer, the mass percentage of the first element in the first dielectric layer is less than a first preset value.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that Forming the first portion of the second dielectric layer on the first dielectric layer includes: Introducing a first gas at a first gas flow rate to form the first portion of the second dielectric layer on the first dielectric layer; Forming the second portion of the second dielectric layer on the first portion of the second dielectric layer includes: Introducing the first gas at a second gas flow rate to form the second portion of the second dielectric layer on the first portion of the second dielectric layer; Wherein, the first gas flow rate is less than the second gas flow rate.

3. The manufacturing method of the semiconductor structure according to claim 2, characterized in that The first gas includes oxygen.

4. The manufacturing method of the semiconductor structure according to claim 1, wherein The material of the first dielectric layer includes silicon nitride, the material of the second dielectric layer includes silicon oxide, and the first element includes oxygen element.

5. The manufacturing method of the semiconductor structure according to claim 1, characterized in that A plurality of memory cells are further formed on the substrate structure, trenches are formed between the plurality of memory cells, and the first dielectric layer is formed in the trenches; Forming the first portion of the second dielectric layer on the first dielectric layer includes: forming the first portion of the second dielectric layer in the trench where the first dielectric layer is formed; Forming the second portion of the second dielectric layer on the first portion of the second dielectric layer includes: forming the second portion of the second dielectric layer in the trench where the first dielectric layer and the first portion of the second dielectric layer are formed.

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