A short-wavelength VCSEL with a tunnel junction oxide aperture hybrid structure grown by MOCVD and a preparation method thereof

Abstract

The application discloses a kind of MOCVD growth's tunnel junction oxide aperture hybrid short wavelength VCSEL and preparation method, it is related to semiconductor optoelectronic technical field, the VCSEL chip is with GaAs as substrate material system, lasing wavelength range is 750nm-1200nm;The VCSEL chip includes substrate, the surface of substrate is deposited with buffer layer, first N type doped DBR, active region, tunnel junction, N type doped oxide confinement layer, second N type doped DBR and ohmic contact layer from bottom to top in sequence using MOCVD process.The application is innovatively replaced P type doped oxide confinement layer with N type doped oxide confinement layer above active region, and N type doped oxide confinement layer is set to above tunnel junction, such design can greatly improve the yield and uniformity of VCSEL mass production, reduce manufacturing difficulty;It can also effectively prevent the migration of crystal defects near oxide aperture to active region, to effectively overcome the defects of prior art, improve the reliability of VCSEL chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronics technology, and in particular to a short-wavelength VCSEL with mixed-aperture tunnel junction oxide aperture grown by MOCVD and its preparation method. Background Technology

[0002] Traditional VCSEL chips typically employ an "NDBR-active region-P-type doped oxide confinement layer-PDBR" structure. However, in actual production environments, the P-DBR in this VCSEL chip exhibits high optical absorption loss and series resistance, leading to significant heat loss and consequently reducing the device's output power and conversion efficiency. US Patent Application No. US2001050934A1 describes a long-wavelength (1340nm) VCSEL chip with a GaAs-based InGaAsN quantum well and a dual oxide confinement layer. The proposed solution involves placing a tunnel junction above the active region to reverse the polarity of the P-DBR, thereby replacing the top P-DBR with an N-DBR and avoiding the drawbacks of optical absorption loss and series resistance associated with the P-DBR.

[0003] However, both the traditional "NDBR-active region-P-type doped oxide confinement layer-PDBR" structure and the technical solution proposed in US Patent Application No. US2001050934A1 employ a P-type doped oxide confinement layer, which is located between the active region layer and the tunnel junction. During the wet oxidation process to form oxide apertures, the P-type doped oxide confinement layer introduces stress and lattice defects. The high-density current injected during VCSEL chip operation and the temperature rise in the active region cause lattice defects near the oxide apertures to migrate to the active region, ultimately leading to VCSEL failure. Furthermore, in US Patent Application No. US2001050934A1, due to the poor crystal quality of the InGaAsN quantum well resulting in insufficient gain (a generally accepted inherent defect), the chip suffers from excessively high threshold current. Therefore, this technical solution uses two oxide confinement layers (one on each side of the active region) to reduce the threshold current and also uses these two oxide confinement layers to reduce the junction capacitance of the VCSEL chip, thereby improving its modulation bandwidth. However, VCSEL chips with a double oxide confinement layer structure have problems such as high manufacturing difficulty, low thermal conductivity and high resistance, posing significant challenges and problems in terms of manufacturing process and performance.

[0004] In the semiconductor field, two types of epitaxial growth equipment are commonly used: molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD). MBE is used in laboratory settings, with a small chamber, typically using small-sized epitaxial wafers, and producing a small number of epitaxial wafers per batch. Furthermore, its operation and maintenance costs are extremely high, thus it is mostly used in laboratories and rarely for mass production. MOCVD, on the other hand, is a mature vapor-phase epitaxial growth technology with advantages such as wide applicability, easy growth control, and suitability for large-scale production. However, mass-production-ready MOCVD reactors have very large reaction chambers, capable of growing multiple large-sized epitaxial wafers simultaneously. Uniform distribution of the reactive gas is difficult to achieve, and temperature distribution is uneven between different epitaxial wafers and within different regions of the same epitaxial wafer.

[0005] In the aforementioned US patent's proposed long-wavelength VCSEL chip structure based on GaAs-based InGaAsN quantum wells, due to the unique characteristics of InGaAsN quantum wells, epitaxial growth can only be performed using MBE equipment, making large-scale industrial production impossible. Consequently, the issue and challenge of epitaxial material uniformity are not addressed. However, the traditional short-wavelength VCSEL structure grown using MOCVD, which can be mass-produced, suffers from poor oxide pore size uniformity. This is because the dopant source for the P-type doped oxide confinement layer grown by MOCVD is CBr4, and the Br4 generated during MOCVD growth... - It will selectively corrode Al x Ga 1-x The degree of corrosion of Ga atoms in As is determined by the growth temperature and different Br- concentrations. Therefore, in the mass production of short-wavelength VCSELs using MOCVD, the growth temperature and Br- concentration vary between different epitaxial wafers in the same furnace, and even between different regions of the same epitaxial wafer. - Even the slightest difference in concentration can cause a significant increase in Al levels. x Ga 1-x The difference in Al content in As, and the Al content in the oxide confinement layer x Ga 1-x Even slight differences in Al content can significantly affect the oxidation rate and the final pore size, ultimately leading to a loss in VCSEL yield and impacting performance uniformity.

[0006] Based on this, we provide a high-yield and high-reliability MOCVD-grown tunnel junction oxide aperture hybrid short-wavelength VCSEL and its fabrication method. Summary of the Invention

[0007] This invention provides a short-wavelength VCSEL with mixed-aperture tunnel junction oxide pore size grown by MOCVD and its preparation method, the main purpose of which is to solve the problems existing in the prior art.

[0008] The present invention adopts the following technical solution:

[0009] A short-wavelength VCSEL with mixed tunnel junction and oxide aperture grown by MOCVD, wherein the VCSEL chip is based on GaAs as a substrate and the lasing wavelength range is 750nm-1200nm; the VCSEL chip includes a substrate, and the surface of the substrate is deposited sequentially from bottom to top by MOCVD process with a buffer layer, a first N-type doped DBR, an active region, a tunnel junction, an N-type doped oxide confinement layer, a second N-type doped DBR and an ohmic contact layer.

[0010] Furthermore, the N-type doped oxide confinement layer includes a central unoxidized region and an outer ring oxide region, wherein the central unoxidized region is Al. x Ga 1-x As material (x is Al) x Ga 1-x As material (Al content), the outer circumferential oxide region is Al2O3 material, and the pore size range of the unoxidized central region is 2-100μm.

[0011] Furthermore, the thickness of the N-type doped oxide confinement layer ranges from 5 to 50 nm.

[0012] Furthermore, the unoxidized region in the middle of the N-type doped oxide confinement layer is Al doped with Si or Te. x Ga 1-x As material, and the doping concentration is above 10 16 -10 18 cm -3 Order of magnitude.

[0013] Furthermore, the tunneling junction comprises, from bottom to top, a P-type heavily doped layer and an N-type heavily doped layer.

[0014] Furthermore, the P-type heavily doped layer is GaAs, AlGaAs, or InGaP, and the N-type heavily doped layer is AlGaAs, GaAs, or InGaP.

[0015] Furthermore, the p-type heavily doped layer contains C, Mg, Zn, or Be as dopants, and the n-type heavily doped layer contains Se or Te as dopants, and both the p-type and n-type heavily doped layers have a doping concentration of 10. 19 -10 20 cm -3 Order of magnitude.

[0016] Furthermore, the thickness of the P-type heavily doped layer ranges from 8 to 50 nm, and the thickness of the N-type heavily doped layer ranges from 10 to 50 nm.

[0017] Furthermore, the active region employs quantum well materials such as InGaAs / GaAs, InGaAs / AlGaAs, InGaAs / GaAsP, GaAs / AlGaAs, AlInGaAs / AlGaAs, InGaAsP / AlGaAs, or AlGaInP / GaAs.

[0018] A method for fabricating a short-wavelength VCSEL chip with mixed oxide aperture in a tunnel junction based on MOCVD, characterized by the following steps:

[0019] (1) The reaction chamber pressure is controlled at 45-55 mbar. H2 is used as the carrier gas, and trimethylgallium, trimethylaluminum, trimethylindium, silane, carbon tetrabromide, arsine and phosphine are used as the reaction source gases. The buffer layer, the first N-type doped DBR, the active region, the tunnel junction, the N-type doped oxide confinement layer prefabricated layer, the second N-type doped DBR and the ohmic contact layer are deposited sequentially on the surface of the substrate using MOCVD process. The growth of the entire epitaxial structure is completed at the same high temperature, which is 600-750℃.

[0020] (2) The N-type doped oxide confinement layer prefabricated layer is oxidized by wet oxidation process to form an N-type doped oxide confinement layer. The oxidation temperature is 300-500℃ and the oxidation time is 10-60min.

[0021] (3) N-type metal electrodes are fabricated at the bottom of the substrate and the top of the ohmic contact layer, respectively.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0023] 1. This invention overcomes the limitation of existing technologies where the oxide confinement layer above the active region of a VCSEL chip can only be a P-type doped oxide confinement layer. It innovatively relies on the reversal of the polarity of the tunnel junction and replaces the P-type doped oxide confinement layer with an N-type doped oxide confinement layer, placing the N-type doped oxide confinement layer above the tunnel junction. On the one hand, this increases the distance between the N-type doped oxide confinement layer and the active region, preventing crystal defects generated near the oxide aperture from rapidly migrating to the active region. More importantly, the built-in electric field of the P+N+ tunnel junction between the N-type doped oxide confinement layer and the active region can effectively act as a barrier, further preventing crystal defects near the oxide aperture from migrating to the active region. This effectively overcomes the shortcomings of existing technologies and improves the reliability of VCSEL chips.

[0024] 2. The VCSEL provided by this invention adopts a single oxide confinement layer and is a short-wavelength material system that can be produced by MOCVD with GaAs as the substrate. The lasing wavelength range is 750nm-1200nm. It does not have the many problems of high manufacturing difficulty, low epitaxial yield and high resistance caused by the need to set a double oxide confinement layer due to the large threshold current of the long-wavelength 1300nm VCSEL using InGaAsN quantum well in the prior art.

[0025] 3. This invention uses an N-type doped oxide confinement layer instead of a P-type doped oxide confinement layer. On the one hand, the N-type doped oxide confinement layer uses Si (Si₂H₆) or Te as the N-type dopant, and the doping concentration is not sensitive to temperature, has good repeatability, and will not affect the Al₂O₃ content of the N-type doped oxide confinement layer prefabrication layer. x Ga 1-x The uniformity of the Al composition of As and the repeatability between furnaces have an impact, which improves the yield and uniformity of VCSEL mass production. On the other hand, the oxidation rate of the N-type doped oxide confinement layer preform is slower than that of the P-type doped oxide confinement layer preform, so the controllability of the oxidation pore size process is better and the manufacturing difficulty is reduced.

[0026] 4. Since the epitaxial growth temperature of the N-type doped oxide confinement layer prefabricated layer is relatively higher than that of the P-type doped oxide confinement layer prefabricated layer, for aluminum-containing materials, high-temperature growth is beneficial for better crystal quality, while low-temperature growth is prone to crystal defects and higher background doping. In the "tunneling junction + N-type oxide confinement layer + N-type doped DBR" structure, the higher epitaxial growth temperature of the oxide confinement layer prefabricated layer improves the crystal quality of the oxide confinement layer and reduces epitaxial defects. In terms of epitaxial process, this is reflected in the fact that the epitaxial growth temperature is maintained at a high temperature throughout, simplifying the epitaxial process steps.

[0027] 5. Unlike traditional oxide aperture VCSELs that use P-type and N-type metals as contact layers on the back and front sides of the chip respectively, the tunnel junction combined with oxide aperture short-wavelength VCSEL in this patent uses N-type contact metals on both the back and front sides of the chip, which helps to further reduce contact resistance and improve chip performance. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the epitaxial structure of the VCSEL chip in Embodiments 1 to 3 of the present invention.

[0029] Figure 2 This is a schematic diagram of the inversion confinement layer in Embodiments 1 to 3 of the present invention.

[0030] Figure 3 This is a schematic diagram of the epitaxial growth temperature of the VCSEL core in Embodiment 1 of the present invention.

[0031] In the figure: 1. Substrate; 2. Buffer layer; 3. First N-type doped DBR; 4. Active region; 5. Inversion confinement layer; 51. Tunnel junction; 52. N-type doped oxide confinement layer; 6. Second N-type doped DBR; 7. Ohmic contact layer. Detailed Implementation

[0032] Specific embodiments of the present invention will now be described with reference to the accompanying drawings. Many details are described below to provide a comprehensive understanding of the invention; however, those skilled in the art will be able to implement the invention without these details.

[0033] Example 1:

[0034] like Figure 1 and Figure 2 As shown, a short-wavelength VCSEL with a tunnel junction oxide aperture hybrid structure grown by MOCVD is disclosed. The VCSEL chip uses GaAs as the substrate 1 and has a lasing wavelength of 980 nm. The VCSEL chip includes a substrate 1, on which a buffer layer 2, a first N-type doped DBR 3, an active region 4, an inversion confinement layer 5, a second N-type doped DBR 6, and an ohmic contact layer 7 are deposited sequentially from bottom to top using MOCVD technology. The inversion confinement layer 5 includes a tunnel junction 51 and an N-type doped oxide confinement layer 52 from bottom to top.

[0035] like Figure 2 As shown, specifically, the tunnel junction 51 comprises a heavily doped P-type layer and a heavily doped N-type layer from bottom to top. Preferably, the heavily doped P-type layer is a heavily doped AlGaAs C layer with a thickness of 20 nm and a doping concentration of 10. 20 cm -3 Order of magnitude; the N-type heavily doped layer is an AlGaAs heavily doped Te layer with a thickness of 12.5 nm and a doping concentration of 10. 19 cm -3 Order of magnitude.

[0036] like Figure 2 As shown, specifically, the outer ring oxide region of the N-type doped oxide confinement layer 52 is made of Al2O3 material, while the central unoxidized region is made of Al. 0.98 Ga 0.02 The material is As, with a pore size of 2 μm in the unoxidized central region and a 5 nm thick N-type doped oxide confinement layer, whose doping atoms are Si and the doping concentration is 10. 18 cm -3 Order of magnitude

[0037] The doping source for p-type doped oxide confinement layers is typically CBr4, with Br4 generated during MOCVD growth. - It will selectively corrode Al x Ga 1-xThe degree of corrosion of Ga atoms in As is determined by the growth temperature and different Br- concentrations. Therefore, in the mass production of short-wavelength VCSELs using MOCVD, the growth temperature and Br- concentration vary between different epitaxial wafers in the same furnace, and even between different regions of the same epitaxial wafer. - Even minute differences in concentration can cause significant Al... x Ga 1-x Differences in the Al content of As ultimately lead to yield loss and performance uniformity issues in VCSELs. This embodiment uses Si as the doping atom; the doping concentration is temperature-insensitive, has good repeatability, and does not affect the Al content of the oxide confinement layer prefabricated layer. 0.98 Ga 0.02 The uniformity of the As composition and the repeatability between furnaces affect the yield and uniformity of VCSEL mass production.

[0038] like Figure 1 and Figure 2 As shown, specifically, active region 4 uses GaAsP / InGaAs MQW.

[0039] This invention also provides a method for preparing a short-wavelength VCSEL with mixed oxide aperture tunnel junction grown by MOCVD, which includes the following steps:

[0040] (1) The reaction chamber pressure was controlled at 45 mbar, with H2 as the carrier gas and trimethylgallium, trimethylaluminum, trimethylindium, dimethylsilane, carbon tetrabromide, arsine, and phosphine as the reaction source gases. A buffer layer 2, a first N-type doped DBR 3, an active region 4, a tunnel junction 51, an N-type doped oxide confinement layer prefabricated layer, a second N-type doped DBR 6, and an ohmic contact layer 7 were sequentially deposited on the surface of substrate 1 using MOCVD. The entire epitaxial structure was grown at the same high-temperature growth temperature of 750℃. Figure 3 As shown in (c);

[0041] (2) The N-type doped oxide confinement layer prefabricated layer is oxidized by wet oxidation process to form N-type doped oxide confinement layer 52. The oxidation temperature is 300℃ and the oxidation time is 11min.

[0042] (3) N-type metal electrodes are fabricated at the bottom of substrate 1 and the top of ohmic contact layer 7, respectively.

[0043] Unlike traditional oxide aperture VCSELs that use P-type and N-type metals as contact layers on the back and front sides of the chip respectively, the VCSEL in this invention uses N-type metal on both the back and front sides of the chip, thereby further reducing contact resistance and improving chip performance.

[0044] like Figure 3As shown, (a) is a schematic diagram of the growth temperature of the traditional “P-type doped oxide confinement layer + P-type doped DBR” epitaxial structure, (b) is a schematic diagram of the growth temperature of the “P-type doped oxide confinement layer + tunnel junction + second N-type doped DBR” epitaxial structure similar to that provided by the US Patent Application No. US2001050934A1, and (c) is a schematic diagram of the growth temperature of the “tunnel junction + N-type doped oxide confinement layer + second N-type doped DBR” epitaxial structure provided in this embodiment.

[0045] In terms of manufacturing process, the advantages of this embodiment compared to the prior art are as follows:

[0046] 1. Comparing Figures (b) and (c), it can be seen that the epitaxial growth temperature of the N-type doped oxide confinement layer prefabricated layer in this embodiment is higher than that of the P-type doped oxide confinement layer prefabricated layer. For aluminum-containing materials, high-temperature growth is beneficial to obtaining better crystal material quality, which improves the crystal quality of the oxide confinement layer and reduces epitaxial defects. Therefore, when the two epitaxial structures, "P-type doped oxide confinement layer + tunnel junction + second N-type doped DBR" and "tunnel junction + N-type doped oxide confinement layer + second N-type doped DBR", are oxidized in the same wet oxidation environment (high temperature, high humidity), the N-type oxide confinement layer prefabricated layer will have fewer crystal defects after oxidation.

[0047] 2. Comparing Figures (a), (b), and (c), it can be seen that the epitaxial growth temperature of this embodiment (Figure c) is maintained at a high temperature of T+ΔT, while the growth environment temperature of the other two structures (Figures a and b) fluctuates. Therefore, the epitaxial structure of this embodiment is conducive to further simplifying the process steps.

[0048] 3. Since the oxidation rate of N-type AlGaAs is slower than that of P-type AlGaAs, under the same wet oxidation conditions, the wet oxidation process of the P-type doped oxide confinement layer preform has a smaller time tolerance. Therefore, the controllability of using the N-type oxide confinement layer in the oxidation pore size process is better than that of using the P-type oxide confinement layer.

[0049] Example 2:

[0050] like Figure 1 and Figure 2 As shown, unlike Example 1, the lasing wavelength of the VCSEL in this example is 795 nm. The p-type heavily doped layer is an AlGaAs heavily doped C layer with a thickness of 50 nm and a doping concentration of 10. 19 cm -3 Order of magnitude; the N-type heavily doped layer is an AlGaAs heavily doped Te layer with a thickness of 50 nm and a doping concentration of 10. 19 cm -3Order of magnitude. The outer ring oxide region of the N-type doped oxide confinement layer 52 is Al2O3 material, while the central unoxidized region is Al. 0.98 Ga 0.02 The material is As, with a pore size of 55 μm in the unoxidized central region and a 40 nm thick N-type doped oxide confinement layer, whose doping atoms are Si and the doping concentration is 10. 17 cm -3 Order of magnitude. Furthermore, during the fabrication of the VCSEL chip, the reaction chamber pressure was 55 mbar, the epitaxial growth temperature was 600℃, the oxidation temperature was 500℃, and the oxidation time was 50 min.

[0051] Example 3:

[0052] like Figure 1 and Figure 2 As shown, unlike Example 1, the lasing wavelength range of the VCSEL chip in this example is 1064 nm. The p-type heavily doped layer is an AlGaAs heavily doped C layer with a thickness of 8 nm and a doping concentration of 10. 19 cm -3 Order of magnitude; the N-type heavily doped layer is an AlGaAs heavily doped Te layer with a thickness of 10 nm and a doping concentration of 10. 19 cm -3 Order of magnitude. The outer ring oxide region of the N-type doped oxide confinement layer 52 is Al2O3 material, while the central unoxidized region is Al. 0.98 Ga 0.02 The material is As, with a pore size of 100 μm in the unoxidized central region and a 50 nm thick N-type doped oxide confinement layer, whose doping atoms are Si and whose doping concentration is 10. 17 cm -3 Order of magnitude. Furthermore, during the fabrication of the VCSEL chip, the reaction chamber pressure was 50 mbar, the epitaxial growth temperature was 745℃, the oxidation temperature was 350℃, and the oxidation time was 18 min.

[0053] The above are merely specific embodiments of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept shall be considered as infringing upon the protection scope of the present invention.

Claims

1. A short-wavelength VCSEL with mixed-aperture tunnel junction oxide structure grown by MOCVD, characterized in that: The VCSEL chip uses GaAs as a substrate and has a lasing wavelength range of 750nm-1200nm. The VCSEL chip includes a substrate, on the surface of which a buffer layer, a first N-type doped DBR, an active region, an inversion confinement layer, a second N-type doped DBR, and an ohmic contact layer are deposited sequentially from bottom to top using an MOCVD process. The inversion confinement layer comprises, from bottom to top, a tunnel junction and an N-type doped oxide confinement layer, and the tunnel junction, the N-type doped oxide confinement layer, and the second N-type doped DBR enable the growth of the entire epitaxial structure to be completed at the same growth temperature. The method for fabricating the VCSEL chip includes the following steps: (1) The reaction chamber pressure is controlled at 45-55 mbar. H2 is used as the carrier gas, and trimethylgallium, trimethylaluminum, trimethylindium, silane, carbon tetrabromide, arsine and phosphine are used as the reaction source gases. The buffer layer, the first N-type doped DBR, the active region, the tunnel junction, the N-type doped oxide confinement layer prefabricated layer, the second N-type doped DBR and the ohmic contact layer are deposited sequentially on the surface of the substrate using MOCVD process. The growth of the entire epitaxial structure is completed at the same growth temperature, which is 600-750℃. (2) The N-type doped oxide confinement layer prefabricated layer is oxidized by wet oxidation process to form an N-type doped oxide confinement layer. The oxidation temperature is 300-500℃ and the oxidation time is 10-60min. (3) N-type metal electrodes are fabricated at the bottom of the substrate and the top of the ohmic contact layer, respectively.

2. The MOCVD-grown tunnel junction oxide aperture hybrid short-wavelength VCSEL as described in claim 1, characterized in that: The N-type doped oxide confinement layer includes a central unoxidized region and an outer ring oxide region. The central unoxidized region is Al. x Ga 1-x The outer oxidized region is made of Al2O3 material, and the pore size range of the unoxidized region in the middle is 2-100 μm.

3. The MOCVD-grown tunnel junction oxide aperture hybrid short-wavelength VCSEL as described in claim 1, characterized in that: The thickness of the N-type doped oxide confinement layer ranges from 5 to 50 nm.

4. The MOCVD-grown tunnel junction oxide aperture hybrid short-wavelength VCSEL as described in claim 2, characterized in that: The unoxidized region in the middle of the N-type doped oxide confinement layer is an Al doped with Si or Te. x Ga 1-x As material, and the doping concentration is above 10 16 -10 18 cm -3 Order of magnitude.

5. The MOCVD-grown tunnel junction oxide aperture hybrid short-wavelength VCSEL as described in claim 1, characterized in that: The tunneling junction comprises, from bottom to top, a P-type heavily doped layer and an N-type heavily doped layer.

6. The MOCVD-grown tunnel junction oxide aperture hybrid short-wavelength VCSEL as described in claim 5, characterized in that: The P-type heavily doped layer is GaAs, AlGaAs, or InGaP, and the N-type heavily doped layer is AlGaAs, GaAs, or InGaP.

7. A short-wavelength VCSEL with mixed oxide aperture and tunnel junction grown by MOCVD as described in claim 5, characterized in that: The p-type heavily doped layer contains C, Mg, Zn, or Be as dopants, and the n-type heavily doped layer contains Se or Te as dopants, with both the p-type and n-type heavily doped layers having a doping concentration of 10. 19 -10 20 cm -3 Order of magnitude.

8. A short-wavelength VCSEL with mixed oxide aperture and tunnel junction grown by MOCVD as described in claim 5, characterized in that: The thickness of the P-type heavily doped layer ranges from 8 to 50 nm, and the thickness of the N-type heavily doped layer ranges from 10 to 50 nm.

9. A short-wavelength VCSEL with mixed oxide aperture and tunnel junction grown by MOCVD as described in claim 1, characterized in that: The active region uses quantum well materials such as InGaAs / GaAs, InGaAs / AlGaAs, InGaAs / GaAsP, GaAs / AlGaAs, AlInGaAs / AlGaAs, InGaAsP / AlGaAs, or AlGaInP / GaAs.

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