Line-to-line DC power flow controller, control method and multi-terminal DC system

Abstract

The application discloses an interline direct current power flow controller, a control method and a multi-terminal direct current system. In a power flow control state, first bypass switches and second bypass switches are turned off, the duty cycles of power devices in first H-bridge circuits and second H-bridge circuits are controlled to adjust the output direct current voltage of the interline direct current power flow controller, and the adjustment of the direct current transmission line current and the direct current capacitor voltage is realized by time-sharing control, so that power flow redistribution is realized. In a short-circuit fault state, the power devices in the first H-bridge circuits and the second H-bridge circuits are controlled to be turned off, the direct current capacitors are charged through the anti-parallel diodes in the H-bridge circuits, part of the short-circuit fault current is absorbed, the current limiting function of the short-circuit fault is realized, when the voltage protection upper limit of the direct current capacitors is reached, the first bypass switches and the second bypass switches are turned on, the bypass of the first H-bridge circuits and the second H-bridge circuits is realized, and the self-protection function of the interline direct current power flow controller is realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of direct current transmission, and particularly relates to an interline direct current power flow controller with fault current limiting and self-protection functions, a control method and a multi-terminal direct current system. BACKGROUND

[0002] In recent years, based on the shortage of fossil fuels and the consideration of environmental protection, various countries are working to change the energy structure and effectively utilize renewable energy such as solar energy, water energy and wind energy. However, renewable energy has the disadvantages of low utilization efficiency, uneven distribution and volatility and intermittency. Multi-terminal high-voltage direct current transmission is an effective technical solution for long-distance and large-capacity power transmission. However, due to the weak power flow control ability and small degree of freedom of the direct current grid, the development of the direct current transmission system is limited. The introduction of a direct current power flow controller can not only increase the degree of freedom of system control, but also improve the power flow control ability of the multi-terminal direct current transmission system. At present, a large amount of research on direct current power flow controllers is carried out at home and abroad.

[0003] The existing direct current power flow controllers are divided into two types in principle: variable resistance type and variable voltage type. The variable resistance type direct current power flow controller has a simple and intuitive structure and control method, and a relatively low rated power. However, the power flow control range is limited by the resistance value, and the resistance is a dissipative device, so the economy is poor, and the power flow direction can only be adjusted, the degree of freedom of power flow control is insufficient, and the flexibility is not high.

[0004] The variable voltage type direct current power flow controller is divided into three types: DC / DC converter type, series voltage source type and interline direct current power flow controller. The DC / DC converter type is a direct current transformer connected in series in the line, which modulates the one-port voltage into a two-port voltage. The capacity is large, the cost and loss are large, the structure and control are complex, and the system complexity is high. The series voltage source type uses an adjustable direct current voltage source to adjust the current, which generally needs an additional power supply, has high cost, and has a complex structure and control. The interline direct current power flow controller controls the power flow by exchanging energy between two lines, can realize bidirectional regulation of power flow, and does not need external energy, has small cost and loss.

[0005] The existing interline direct current power flow controllers have the following structures:

[0006] Based on magnetic coupling: (1) Inductive coupling: two capacitors are connected in each of the two lines, and a bypass switch is connected in parallel with each capacitor. The capacitors are connected through the inductors and the switching devices. The power flow is controlled by the energy exchange between the inductors and the capacitors. (2) Transformer coupling: an additional voltage is added to the line to change the voltage drop of the line. The alternating current side balances its own power through the connection with the alternating current transformer, avoiding the connection with the external alternating current system to take energy. (3) Based on capacitive coupling: a capacitor is connected in two different lines at different times to adjust the power flow. The structure is simple, and the cost is low.

[0007] In summary, the interline DC power flow controller is one of the effective solutions to improve the power flow control capability of the DC power transmission system. When the DC power grid fails, due to its low resistance, the fault current can increase to tens of times of the rated current within 10 ms, endangering the safe operation of the converter station device and the entire DC system. At present, the current limiting function of the fault line is mostly realized by a special fault current limiter, which increases the design difficulty and cost. SUMMARY

[0008] The purpose of the present application is to provide an interline DC power flow controller, a control method and a multi-terminal DC system to solve the problems that the existing power flow control mostly does not have the fault current limiting capability, and the design difficulty is large and the cost is high due to the need for a special fault current limiter.

[0009] The present application solves the above technical problems by the following technical scheme: an interline DC power flow controller, comprising a first H-bridge circuit, a second H-bridge circuit, a DC capacitor, a first bypass switch and a second bypass switch; the first bypass switch is connected with the output end of the first H-bridge circuit, and the second bypass switch is connected with the output end of the second H-bridge circuit; the first H-bridge circuit is connected with the second H-bridge circuit through the DC capacitor;

[0010] In the power flow control state, the duty cycles of the power devices in the first H-bridge circuit and the second H-bridge circuit and the on-off of the first bypass switch and the second bypass switch are controlled to realize the redistribution of the DC line current; in the short-circuit fault state, the on-off of the power devices in the first H-bridge circuit and the second H-bridge circuit and the on-off of the first bypass switch and the second bypass switch are controlled to reduce the DC line fault current and realize current limiting and self-protection.

[0011] In the present application, in the power flow control state, the first bypass switch and the second bypass switch are turned off, the duty cycles of the power devices in the first H-bridge circuit and the second H-bridge circuit are controlled to realize the adjustment of the output DC voltage of the interline DC power flow controller, and thus the adjustment of the DC transmission line current is realized, thereby realizing the power flow redistribution; in the short-circuit fault state, the power devices in the first H-bridge circuit and the second H-bridge circuit are controlled to be in the off state, the anti-parallel diodes in the H-bridge circuit charge the DC capacitor to absorb part of the short-circuit fault current, thereby realizing the current limiting function of the short-circuit fault, when the voltage protection upper limit of the DC capacitor is reached, the first bypass switch and the second bypass switch are turned on to realize the bypass of the first H-bridge circuit and the second H-bridge circuit, thereby realizing the self-protection function of the interline DC power flow controller, which has strong reliability. The interline DC power flow controller has the power flow control function, the current limiting and self-protection functions, is easy to realize, has simple design and low cost.

[0012] Further, the first bypass switch and the second bypass switch are a group of anti-parallel thyristors.

[0013] The application also provides a control method of the line-to-line DC power flow controller, comprising the following steps:

[0014] Step 1: connecting the line-to-line DC power flow controller to a multi-terminal DC system, the multi-terminal DC system comprising at least one main converter station 1 and two slave converter stations 2 / 3, one end of the first bypass switch and the second bypass switch of the line-to-line DC power flow controller being connected in series and connected to the main converter station 1, and the other end of the first bypass switch and the second bypass switch being connected to the slave converter station 2 and the slave converter station 3, respectively;

[0015] Step 2: controlling the duty cycle of the power devices in the first H-bridge circuit and the second H-bridge circuit and the on-off of the first bypass switch and the second bypass switch in the power flow control state to realize the redistribution of the DC line current;

[0016] Step 2: controlling the duty cycle of the power devices in the first H-bridge circuit and the second H-bridge circuit and the on-off of the first bypass switch and the second bypass switch in the power flow control state to realize the redistribution of the DC line current;

[0017] Further, in the step 2, in the power flow control state, the first bypass switch and the second bypass switch are in the off state, and the specific control process in the power flow control state comprises a steady state process and a transient state process;

[0018] In the steady state, the output voltage of the first H-bridge circuit and the second H-bridge circuit is adjusted to increase or decrease the input line current of the slave converter station 2 and the input line current of the slave converter station 3, thereby realizing the redistribution of the DC line current;

[0019] In the transient state, the duty cycle of the power devices in the first H-bridge circuit and the second H-bridge circuit is controlled to realize the time-sharing control of the DC line current and the DC capacitor voltage.

[0020] Further, the time-sharing control process in the transient state process is as follows:

[0021] Step 2.11: dividing the control period into a first half period and a second half period; the first half period is used for adjusting the DC line current, and the second half period is used for adjusting the DC capacitor voltage;

[0022] Step 2.12: In the first half cycle, the duty cycle of the power device in the first H-bridge circuit or the second H-bridge circuit is controlled to make the first H-bridge circuit or the second H-bridge circuit in the PWM regulation state, while the second H-bridge circuit or the first H-bridge circuit is controlled to be in the bypass state; in the second half cycle, the first H-bridge circuit or the second H-bridge circuit is controlled to be in the bypass state, while the duty cycle of the power device in the second H-bridge circuit or the first H-bridge circuit is controlled to make the second H-bridge circuit or the first H-bridge circuit in the PWM regulation state.

[0023] Since the charging and discharging of the direct current capacitor cannot be performed simultaneously, the control cycle is divided into the first half cycle and the second half cycle, and the first H-bridge circuit and the second H-bridge circuit are controlled to enable the direct current line current and the direct current capacitor voltage to be controlled in time division, respectively, so as to realize the power flow control function and ensure the power balance of the line-to-line direct current power flow controller, and the control is more reliable.

[0024] Further, the specific implementation process of the step 2.12 is divided into two cases according to the regulation object of the PWM regulation state:

[0025] Case 1: In the first half cycle, the control target is the line current, the second H-bridge circuit is in the bypass state, when the line current modulation wave input from the converter station 2 is greater than the line current carrier wave input from the converter station 2, the line current input from the converter station 2 flows through the first H-bridge circuit, the first H-bridge circuit outputs ±U C or 0, the second H-bridge circuit is in the bypass state, so that the line current input from the converter station 2 increases and the line current input from the converter station 3 decreases; when the line current modulation wave input from the converter station 2 is less than the line current carrier wave input from the converter station 2, the line current input from the converter station 2 flows through the first H-bridge circuit, the first H-bridge circuit outputs 0 or ±U C , the second H-bridge circuit is in the bypass state, so that the line current input from the converter station 2 decreases and the line current input from the converter station 3 increases;

[0026] In the second half cycle, the control target is the capacitor voltage, the first H-bridge circuit is in the bypass state, when the direct current capacitor voltage modulation wave is less than the direct current capacitor voltage carrier wave, the line current input from the converter station 3 flows through the second H-bridge circuit to discharge the direct current capacitor, the second H-bridge circuit outputs ±U C , the first H-bridge circuit is in the bypass state, at this time, the current flowing through the capacitor and the direction of the capacitor voltage are opposite, so the direct current capacitor voltage decreases; when the direct current capacitor voltage modulation wave is greater than the direct current capacitor voltage carrier wave, the line current input from the converter station 3 flows through the second H-bridge circuit, the second H-bridge circuit outputs 0, the first H-bridge circuit is in the bypass state, at this time, the capacitor discharging phenomenon in the case that the direct current capacitor voltage modulation wave is less than the direct current capacitor voltage carrier wave disappears, so the direct current capacitor voltage increases;

[0027] Case 2: In the first half cycle, the control target is line current, the first H-bridge circuit is in bypass state, when the line current modulation wave from converter station 2 is greater than the line current carrier wave from converter station 2, the line current from converter station 3 flows through the second H-bridge circuit, the second H-bridge circuit outputs ±U C or 0, the first H-bridge circuit is in bypass state, so that the line current from converter station 2 increases, and the line current from converter station 3 decreases; when the line current modulation wave from converter station 2 is less than the line current carrier wave from converter station 2, the line current from converter station 3 flows through the second H-bridge circuit, the second H-bridge circuit outputs 0 or ±U C , the first H-bridge circuit is in bypass state, so that the line current from converter station 2 decreases, and the line current from converter station 3 increases;

[0028] In the second half cycle, the control target is capacitor voltage, the second H-bridge circuit is in bypass state, when the DC capacitor voltage modulation wave is less than the DC capacitor voltage carrier wave, the line current from converter station 2 flows through the first H-bridge circuit to discharge the DC capacitor, the first H-bridge circuit outputs ±U C , the second H-bridge circuit is in bypass state, at this time the current flowing through the capacitor and the direction of the capacitor voltage are opposite, so the DC capacitor voltage decreases; when the DC capacitor voltage modulation wave is greater than the DC capacitor voltage carrier wave, the line current from converter station 2 flows through the first H-bridge circuit, the first H-bridge circuit outputs 0, and the second H-bridge circuit is in bypass state, at this time the capacitor discharge phenomenon under the condition that the DC capacitor voltage modulation wave is less than the DC capacitor voltage carrier wave disappears, so the DC capacitor voltage increases.

[0029] Further, the calculation expression of the line current from converter station 2 is:

[0030]

[0031] The calculation expression of the line current from converter station 3 is:

[0032]

[0033] Wherein, U1, U2, U3 are the output DC voltage of the main converter station 1, the input DC voltage from the slave converter station 2, and the input DC voltage from the slave converter station 3, respectively; U a is the voltage after power flow control, the power flow controller is connected in series between the main converter station 1 and the slave converter station 2; U b is the voltage after power flow control, the power flow controller is connected in series between the main converter station 1 and the slave converter station 3; R L1 is the equivalent resistance of the line from the slave converter station 2; R L2 is the equivalent resistance of the line from the slave converter station 3; I L1is the average current flowing through the line from the slave converter station 2, i.e. the line current from the slave converter station 2. L2 is the average current flowing through the line from the slave converter station 3, i.e. the line current from the slave converter station 3.

[0034] Further, the specific control process in the step 2 when the short-circuit fault state includes:

[0035] acquiring a short-circuit fault signal, and making the power devices in the first H-bridge circuit and the second H-bridge circuit be in an off state according to the short-circuit fault signal, and making the first H-bridge circuit and the second H-bridge circuit be in a non-controllable rectification state;

[0036] the fault current charges the DC capacitor through the anti-parallel diodes in the first H-bridge circuit and the second H-bridge circuit, and fault current limiting is realized;

[0037] when the DC capacitor voltage is greater than or equal to the upper limit protection voltage of the DC capacitor, the first bypass switch and the second bypass switch are controlled to be turned on, the line-to-line DC power flow controller is bypassed, and self-protection is realized.

[0038] Further, the acquisition process of the short-circuit fault signal is that when any one of the line current from the slave converter station 2 or the DC capacitor voltage exceeds the respective short-circuit threshold value, a short-circuit fault signal is sent out.

[0039] The short-circuit threshold value I OC of the line current from the slave converter station 2 is 15A, and the short-circuit threshold value U OC of the DC capacitor voltage is 50V.

[0040] The application also provides a multi-terminal DC system, which at least includes a main converter station 1 and two slave converter stations 2 / 3, and further includes the line-to-line DC power flow controller as described above, one end of the first bypass switch and the second bypass switch in the line-to-line DC power flow controller is connected in series and connected with the main converter station 1, and the other end of the first bypass switch and the second bypass switch is connected with the slave converter station 2 and the slave converter station 3 respectively.

[0041] Beneficial effects

[0042] Compared with the prior art, the line-to-line DC power flow controller, the control method and the multi-terminal DC system provided by the application adopt the method of PI control and time-sharing control, control the output voltage of each branch by adjusting the duty cycle of the power device, and play the role of re-distributing the line current; in the fault current limiting mode, the peak value of the current can be limited, and the self-protection of the line-to-line DC power flow controller can be realized after the bypass switch is turned on. The application has both DC line power flow control and current limiting protection functions, and improves the flexibility and reliability of the DC power transmission system control. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the present application, the drawings required to be used in the following embodiment description will be briefly introduced. Obviously, the drawings in the following description are only one embodiment of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0044] Figure 1 is the topological structure of the interline DC power flow controller in the embodiment of the present application;

[0045] Figure 2 is the equivalent circuit diagram of the power transmission line on which the interline DC power flow controller is installed in the embodiment of the present application;

[0046] Figure 3 is the PWM control diagram of the power transmission line 2' current and DC capacitor voltage in the embodiment of the present application;

[0047] Figure 4 is the control block diagram of the fault current limiting in the embodiment of the present application;

[0048] Figure 5 is the test loop system built in the embodiment of the present application;

[0049] Fig. 6 is the current average distribution simulation waveform diagram in the power flow control stage in the embodiment of the present application, Figure 6a is the DC capacitor voltage simulation waveform diagram, Figure 6b is the bus current and the current flowing through each branch simulation waveform diagram;

[0050] Fig. 7 is the current uneven distribution simulation waveform diagram in the power flow control stage in the embodiment of the present application, Figure 7a is the DC capacitor voltage simulation waveform diagram, Figure 7b is the bus current and the current flowing through each branch simulation waveform diagram;

[0051] Fig. 8 is the simulation waveform diagram in the fault current limiting stage in the embodiment of the present application, Figure 8a is the DC capacitor voltage simulation waveform diagram, Figure 8b is the bus current and the current flowing through each branch simulation waveform diagram;

[0052] Figure 9 is the fault current limiting effect comparison diagram under the action of the current limiting in the embodiment of the present application;

[0053] Figure 10 is the prototype experiment waveform diagram under the action of the current limiting in the embodiment of the present application;

[0054] Figure 11 is the prototype experiment waveform diagram under the action of the current limiting in the embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] like Figure 1 As shown, the inter-line DC power flow controller provided in this embodiment includes a first H-bridge circuit FBS1, a second H-bridge circuit FBS2, a DC capacitor, a first bypass switch Q1, and a second bypass switch Q2; the first bypass switch Q1 is connected to the output terminal of the first H-bridge circuit FBS1, and the second bypass switch Q2 is connected to the output terminal of the second H-bridge circuit FBS2; the first H-bridge circuit FBS1 is connected to the second H-bridge circuit FBS2 through the DC capacitor.

[0057] Both the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 are composed of IGBTs with four sets of anti-parallel diodes; that is, the power devices in the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 are IGBTs. The first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 can output three levels: +U C -U C 0, where U C This is the DC capacitor voltage. The first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 are equivalent to an adjustable voltage source. By adjusting their output voltage, the desired voltage value U can be inserted into the DC line. a and U b This allows for the regulation of line current and the realization of power flow control. The topology of this inter-line DC power flow controller is easily expandable and modularly cascaded. The first bypass switch Q1 and the second bypass switch Q2 are both a set of anti-parallel thyristors. The first bypass switch Q1 and the second bypass switch Q2 are turned on under fault conditions to realize the self-protection of IDCPFC (Interline DC Power-Flow Controller).

[0058] like Figure 2As shown, the line-to-line DC power flow controller of the embodiment has four terminals, which are directly installed on the DC nodes to realize the installation of the line-to-line DC power flow controller in the multi-terminal DC system. The multi-terminal DC system includes at least one main converter station 1 and two slave converter stations 2 / 3. Correspondingly, the bus terminal transmission line is 1', i.e. the output line of the main converter station 1 is 1', the output terminal transmission lines are 2' and 3', i.e. the input line of the slave converter station 2 is 2' and the input line of the slave converter station 3 is 3'. The terminal 1 and the terminal 2 of the line-to-line DC power flow controller are connected in series and connected to the bus terminal transmission line 1', the terminal 3 is connected to the output terminal transmission line 2', and the terminal 4 is connected to the output terminal transmission line 3', i.e. the installation of the line-to-line DC power flow controller in the multi-terminal DC system is completed.

[0059] As shown in Figure 1 and 2 According to the Kirchhoff's voltage and current law, there are:

[0060]

[0061] Wherein, U1, U2, U3 are the DC voltages of the bus terminal and the two output terminals, i.e. U1, U2, U3 are the output terminal DC voltage of the main converter station 1, the input terminal DC voltage of the slave converter station 2, and the input terminal DC voltage of the slave converter station 3, respectively; U a is the voltage between the main converter station 1 and the slave converter station 2 after power flow control, and the line-to-line DC power flow controller is connected in series; U b is the voltage between the main converter station 1 and the slave converter station 3 after power flow control, and the line-to-line DC power flow controller is connected in series; R L1 is the equivalent resistance of the transmission line 2'; R L2 is the equivalent resistance of the transmission line 3'; L L1 is the equivalent inductance of the transmission line 2'; L L2 is the equivalent inductance of the transmission line 3'; I L1 is the average current flowing through the transmission line 2'; I L2 is the average current flowing through the transmission line 3'; i L1 and i L2 are instantaneous current values; I1 is the average current flowing through the transmission line 1'; since the inductance of the transmission line can be ignored in the steady state, there are:

[0062]

[0063] The embodiment also provides a control method of the line-to-line DC power flow controller as described above, including the following steps:

[0064] 1. The line-to-line DC power flow controller is connected to the multi-terminal DC system as shown in Figure 2 , and the multi-terminal DC system includes at least one main converter station 1 and two slave converter stations 2 / 3.

[0065] 2. The inter-line DC power flow controller has two operating conditions in a multi-terminal DC system: power flow control mode and short-circuit fault mode.

[0066] In power flow control mode, the duty cycle of the power devices in the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2, as well as the first bypass switch Q1 and the second bypass switch Q2, are controlled to be in the off state, thereby realizing the redistribution of DC line current, i.e., power flow control. In short-circuit fault mode, the power devices in the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 are controlled to be in the off state, and the first bypass switch Q1 and the second bypass switch Q2 are controlled to be on and off, thereby reducing the DC line fault current and realizing current limiting and self-protection.

[0067] 2.1 Power Flow Control under Normal Conditions

[0068] like Figure 3 As shown, the power flow control employs PI control and time-sharing control. A1 and A2 represent the current modulation wave of line 2' (i.e., the line current modulation wave input from converter station 2) and the DC capacitor voltage modulation wave, respectively. B1 and B2 represent the current carrier wave of line 2' and the DC capacitor voltage carrier wave, respectively. Since the charging and discharging of the DC capacitor cannot occur simultaneously, time-sharing control (i.e., independent control to make the control process more reliable) is required for the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 at both ends. This achieves the power flow control function while ensuring the power balance of the inter-line DC power flow controller itself.

[0069] Based on the different current flow direction and adjustment direction, there are 8 operating conditions, as shown in Table 1.

[0070] Table 1 IDCPFC Operating Conditions

[0071]

[0072] In Table 1, 0 indicates that the IGBT is in the off state, and 1 indicates that the IGBT is in the on state.

[0073] The specific control process of power flow control includes steady-state process and transient process;

[0074] In steady state, the output voltages of the first H-bridge circuit and the second H-bridge circuit are adjusted to increase or decrease the input line current from converter station 2 and the input line current from converter station 3, thereby realizing the redistribution of DC line current.

[0075] During transient states, the duty cycle of the power devices in the first H-bridge circuit and the second H-bridge circuit is controlled to achieve time-sharing control of the DC line current and the DC capacitor voltage.

[0076] The first operating condition: the current of the transmission line 2' and the current of the transmission line 3' are both positive, and the current of the line 2' decreases and the current of the line 3' increases, and the positive direction refers to the direction from the main converter station 1 to the slave converter station 2 / 3.

[0077] As shown in Table 1, the specific process of the power flow control is as follows:

[0078] The first H-bridge circuit FBS1 outputs a positive voltage U a , which is equivalent to connecting a positive resistance to the transmission line 2', so that the current of the transmission line 2' decreases; and the second H-bridge circuit FBS2 outputs a negative voltage U b , which is equivalent to connecting a negative resistance to the transmission line 3', so that the current of the transmission line 3' increases.

[0079] As shown in Table 1, the specific process of the power flow control is as follows: Figure 3

[0080] In the first half cycle T1, the control target is the line current, in the period t0-t1, the current I L1 modulation wave A1 is less than the current I L1 carrier B1, and the current I L1 flows through the anti-parallel diode pair of the power device S1 and the power device S4 in the first H-bridge circuit FBS1 to charge the DC capacitor, and the first H-bridge circuit FBS1 outputs +U C , which is equivalent to connecting a positive resistance, so that the current I L1 of the line 2' decreases, and at the same time, in order to prevent the current coupling phenomenon of the left and right bridge arms, the second H-bridge circuit FBS2 should be in a positive bypass state; in the period t1-t2, the current I L1 modulation wave A1 is greater than the current I L1 carrier B1, the first H-bridge circuit FBS1 outputs 0, and the second H-bridge circuit FBS2 is still in the bypass state, and since the positive resistance phenomenon in the period t0-t1 disappears, the output of the first H-bridge circuit FBS1 is 0, which is equivalent to the current I L1 of the line 2' increases; the process in the period t2-t3 is the same as that in the period t0-t1.

[0081] In the second half cycle T2, the control target is the DC capacitor voltage, in the period t3-t4, the DC capacitor voltage modulation wave A2 is less than the DC capacitor voltage carrier B2, and the line current I L2 from the slave converter station 3 flows through the IGBT pair of the power device S5 and the power device S8 in the second H-bridge circuit FBS2 to discharge the DC capacitor, and the second H-bridge circuit FBS2 outputs -U C ​As the DC capacitor voltage decreases, the first H-bridge circuit FBS1 is in a negative bypass state. During the time period t4-t5, the DC capacitor voltage modulation wave A2 is greater than the DC capacitor voltage carrier wave B2. The first H-bridge circuit FBS1 is still in a bypass state, and the output of the second H-bridge circuit FBS2 is 0. The capacitor discharge phenomenon during the time period t3-t4 disappears, and the capacitor voltage will increase. The process during the time period t5-t6 is the same as that during the time period t3-t4.

[0082] As shown in Table 1, the controlled devices are S2, S3, S5, and S8 within one control cycle of this operating condition.

[0083] The second operating condition: the current in both transmission line 2' and transmission line 3' is positive, and the current in line 2' increases while the current in line 3' decreases.

[0084] As shown in Table 1, the specific process of power flow control is as follows:

[0085] The first H-bridge circuit FBS1 outputs a negative voltage U. a This is equivalent to adding a negative resistor in series with transmission line 2', increasing the current in transmission line 2'; the second H-bridge circuit FBS2 outputs a positive voltage U. b This is equivalent to adding a positive resistor in series with the transmission line 3', which reduces the current in the transmission line 3'.

[0086] like Figure 3 As shown, the specific control process for the transient state is as follows:

[0087] During the first half of the cycle T1, the control target is the line current. During the time interval t1-t2, the current I... L1 The modulated wave A1 is greater than the current I L1 Carrier B1, current I L2 The DC capacitor is charged by the anti-parallel diodes of power devices S6 and S7 in the second H-bridge circuit FBS2, and the output of the second H-bridge circuit FBS2 is +U. C This is equivalent to inserting a positive resistor in series. The current in line 3' decreases, and the current in line 2' increases. Simultaneously, to prevent current coupling between the left and right bridge arms, the first H-bridge circuit FBS1 should be in a forward bypass state at this time. During the time interval t2-t3, the current I... L1 Modulation wave A1 is less than current I L1 With carrier B1, the output of the second H-bridge circuit FBS2 is 0, and the first H-bridge circuit FBS1 is still in bypass mode. Since the positive resistance phenomenon disappears during the t1-t2 time period, the output of the second H-bridge circuit FBS2 is 0, which is equivalent to the current of line 3' increasing and the current of line 2' decreasing. The process of the t0-t1 time period is the same as that of the t2-t3 time period.

[0088] In the latter half of the cycle T2, the control target is the DC capacitor voltage. During the time interval t3-t4, the DC capacitor voltage modulation wave A2 is less than the DC capacitor voltage carrier wave B2, and the current I... L1 The IGBTs of power devices S2 and S3 in the first H-bridge circuit FBS1 discharge the DC capacitor, and the output of the first H-bridge circuit FBS1 is -U. C As the DC capacitor voltage decreases, the second H-bridge circuit FBS2 is in a negative bypass state. During the time period t4-t5, the DC capacitor voltage modulation wave A2 is greater than the DC capacitor voltage carrier wave B2, and the second H-bridge circuit FBS2 is still in a bypass state. The output of the first H-bridge circuit FBS1 is 0, the capacitor discharge phenomenon during the time period t3-t4 disappears, and the capacitor voltage will increase. The process during the time period t5-t6 is the same as that during the time period t3-t4.

[0089] Within one control cycle of this operating condition, the controlled devices are S2, S3, S5, and S8.

[0090] The third operating condition: the current in both transmission line 2' and transmission line 3' is negative, and the current in line 2' decreases while the current in line 3' increases. Negative direction refers to the direction from converter station 2 / 3 into the main converter station 1.

[0091] As shown in Table 1, the specific control process of power flow control is as follows:

[0092] The first H-bridge circuit FBS1 outputs a negative voltage U. a Since all currents are negative, the current in line 2' decreases; the second H-bridge circuit FBS2 outputs a positive voltage U. b Since all currents are in the negative direction, the current in line 3' increases.

[0093] like Figure 3 As shown, the specific control process for the transient state is as follows:

[0094] During the first half of the cycle T1, the control target is the line current. During the time interval t1-t2, the current I... L1 The modulated wave A1 is greater than the current I L1 Carrier B1, current I L1 The anti-parallel diodes flowing through S2 and S3 charge the DC capacitor, and the first H-bridge circuit FBS1 outputs -U. C This is equivalent to having a negative resistor in series, and the current I in line 2' is... L1 To increase the current, and to prevent current coupling between the left and right bridge arms, the second H-bridge circuit FBS2 should be in a forward bypass state at this time; during the time period t2-t3, the current I... L1 Modulation wave A1 is less than current I L1With carrier B1, the first H-bridge circuit FBS1 outputs 0, and the second H-bridge circuit FBS2 remains in bypass mode. Since the negative resistance phenomenon disappears during the t1-t2 time period, the output of the first H-bridge circuit FBS1 is 0, which is equivalent to the current in line 2' decreasing. The process during the t0-t1 time period is the same as that during the t2-t3 time period.

[0095] During the second half of the cycle T2, the control target is the capacitor voltage. In the time interval t3-t4, the DC capacitor voltage modulation wave A2 is less than the DC capacitor voltage carrier wave B2, and the current I... L2 The IGBTs flowing through S6 and S7 discharge the DC capacitor, and the output of the second H-bridge circuit FBS2 is +U. C Furthermore, due to the direction of the capacitor voltage and I L2 The current flows through the capacitor in the opposite direction, so it is equivalent to discharging the capacitor, reducing the capacitor voltage, and FBS1 is in a negative bypass state; during the time period t4-t5, the DC capacitor voltage modulation wave A2 is greater than the DC capacitor voltage carrier wave B2, the first H-bridge circuit FBS1 is still in a bypass state, the output of the second H-bridge circuit FBS2 is 0, the capacitor discharge phenomenon during the time period t3-t4 disappears, so the capacitor voltage increases; the process during the time period t5-t6 is the same as that during the time period t3-t4.

[0096] Within one control cycle of this operating condition, the controlled devices are S1, S4, S6, and S7.

[0097] The fourth operating condition: the current in transmission line 2' is positive and the current in transmission line 3' is negative, and the current in line 2' decreases while the current in line 3' increases.

[0098] As shown in Table 1, the specific control process of power flow control is as follows:

[0099] The first H-bridge circuit FBS1 outputs a positive voltage U. a This is equivalent to adding a positive resistor in series with line 2', reducing the current in line 2'; the second H-bridge circuit FBS2 outputs a positive voltage U. b Since the current in line 3' is negative, the current in line 3' increases.

[0100] like Figure 3 As shown, the specific control process for the transient state is as follows:

[0101] During the first half of the cycle T1, the control target is the line current. During the time interval t0-t1, the current I... L1 Modulation wave A1 is less than current I L1 Carrier B1, current I L1 The anti-parallel diodes flowing through S1 and S4 charge the DC capacitor, and the output of the first H-bridge circuit FBS1 is +U. C, equivalent to a positive resistance in series, the line 2' current decreases, while to prevent the left and right bridge arm current coupling phenomenon, the second H-bridge circuit FBS2 at this time should be in the positive bypass state; t1-t2 time period, the current I L1 Modulation wave A1 greater than the current I L1 Carrier B1, the first H-bridge circuit FBS1 output 0, the second H-bridge circuit FBS2 is still in the bypass state, because the positive resistance phenomenon in the t0-t1 time period disappears, so the first H-bridge circuit FBS1 output is 0, which is equivalent to the current in line 2' is increasing; t2-t3 time period and the process of t0-t1 time period is the same.

[0102] In the second half of the cycle T2, the control target is the capacitor voltage, t3-t4 time period, the DC capacitor voltage modulation wave A2 is less than the DC capacitor voltage carrier B2, the current I L2 IGBT through S6 and S7 discharge DC capacitor, the second H-bridge circuit FBS2 output +U C , because the capacitor voltage direction and I L2 The direction of the current through the capacitor is opposite, so it is equivalent to discharge the capacitor, the capacitor voltage decreases, the first H-bridge circuit FBS1 is in the negative bypass state; t4-t5 time period, the DC capacitor voltage modulation wave A2 is greater than the DC capacitor voltage carrier B2, the first H-bridge circuit FBS1 is still in the bypass state, the second H-bridge circuit FBS2 output is 0, t3-t4 time period of the discharge phenomenon disappears, so the capacitor voltage increases; t5-t6 time period and the process of t3-t4 time period is the same.

[0103] The control cycle of this operating condition, the controlled device is S2, S3, S6, S7.

[0104] From the above analysis, for other operating conditions, due to the different direction of the current and the regulation direction, only need to replace the direction of the current reference value and the controlled device.

[0105] Figure 3 In this case, the given current I L1ref In the range of no overload can be set, the given voltage is determined according to the level of line voltage, the given voltage U Cref is 30V in the embodiment.

[0106] The duty cycle of the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 is not greater than 50%, which has:

[0107]

[0108] Wherein, D1, D2 represent the capacitor voltage input coefficient of the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 after the power flow control.

[0109] Based on the inter-line DC power flow controller in this embodiment, according to Kirchhoff's current law, we have: I1 = I L1 +I L2 Under ideal conditions, the net power of the inter-line DC power flow controller is zero, and thus:

[0110] U a I L1 +U b I L2 =0 (4)

[0111] 2.2 Current limiting and self-protection control under fault conditions

[0112] Current limiting and self-protection are divided into two control phases:

[0113] First control phase: In the event of a short-circuit fault at one end (i.e., when a short-circuit fault signal is detected), the current I of transmission line 2'... L1 The current rises sharply, and an overcurrent protection command block is issued based on the short-circuit fault signal. According to the overcurrent protection command block, the power devices in the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 are blocked, so that the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 are in an uncontrolled rectification state. The DC capacitor connected in series in the line is charged through the anti-parallel diodes in the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 to absorb part of the fault current in the charging mode, thereby achieving current limiting.

[0114] Second control stage: When the DC capacitor voltage is greater than or equal to the upper limit voltage of the DC capacitor protection, that is, when the DC capacitor is overcharged, the power flow controller protection command step_n is issued to control the first bypass switch Q1 and the second bypass switch Q2 to be turned on, so that the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2 are bypassed, thereby realizing the self-protection function.

[0115] like Figure 4 As shown, in the event of a short-circuit fault at one end, the line current and DC capacitor voltage of the inter-line DC power flow controller are sampled twice. When the current I of transmission line 2' is... L1 or DC capacitor voltage U c Any one exceeding its corresponding short-circuit threshold (I oc =15A, U oc When the voltage reaches 50V, a short circuit fault is identified. Upon detecting a short circuit fault, an overcurrent protection command (block) is issued, blocking the power devices in the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2. The fault current charges the DC capacitor through the anti-parallel diodes of the first H-bridge circuit FBS1 and the second H-bridge circuit FBS2, outputting +U. c, the line fault current is reduced. Once the DC capacitor voltage U c reaches its protection upper limit value (U Cmax = 160V), the instruction step_n is sent to turn on the first bypass switch Q1 and the second bypass switch Q2, achieving the purpose of self-protection. The first control stage outputs a negative voltage opposite to the system voltage, limiting the current peak value; the second control stage protects the IDCPFC, which has no effect on the fault current.

[0116] 3. Simulation verification

[0117] A test loop system as shown in Figure 5 is built to experimentally verify the power flow control and fault current limiting functions thereof. The DC power supply U1 is the output DC voltage of the main converter station 1, which is the system voltage source, and the resistor R1 simulates the system power source. By setting different series inductances and resistances, the line inductance and resistance are simulated. The switch SF functions to put in the small resistance R2 to simulate short-circuit overcurrent. The multi-terminal DC system simulation parameters are shown in Table 2:

[0118] Table 2 System simulation parameters

[0119] Parameter [CDATA[U1(V)]]> [R L1 (Ω)]]> [R L2 (Ω)]]> [R1(Ω)] [R 2( Ω)]]> L L1 (H)]]> L L2 (H)]]> Value 1000 3 5 100 20 0.05 0.05

[0120] 3.1 Power flow control

[0121] In a DC bus and two shunt branches, the interline DC power flow controller of the embodiment is inserted, the given value I L1ref = 5A, U Cref = 30V, and the simulation waveform diagram of the current average distribution in the power flow control mode is shown in Fig. 6. Without the interline DC power flow controller of the embodiment, the line current is naturally distributed, I1 = 9.80A, I L1 = 6.13A, and I L2 = 3.67A. After the interline DC power flow controller of the embodiment is put in, when the system is in a steady state, I1 = 9.80A, I L1 = 5.00A, and I L2 = 4.80A (as shown in Figure 6b ), the DC capacitor voltage appears a short-term sharp peak and becomes 30V (as shown in Figure 6a ) after stabilization, which is basically consistent with the given value. This simulation result corresponds to the first operating condition of 2.1.

[0122] The given value I L1ref = 8A, U Cref = 30V is set again. The simulation waveform diagram of the current uneven distribution in the power flow control mode is shown in Fig. 7. Without the interline DC power flow controller of the embodiment, the line current is naturally distributed, I1 = 9.80A, I L1= 6.13 A, I L2 = 3.67 A. After the line DC power flow controller is put into the system, when the system is in steady state, I1= 9.80 A, I L1 = 8.02 A, I L2 = 1.78 A (as shown in Figure 7b ), the DC capacitor voltage appears a short sharp peak and becomes 30 V (as shown in Figure 7a ) after stabilization, and basically keeps consistent with the given value. Such simulation results correspond to the second operating condition of 2.1.

[0123] It can be concluded that after the line DC power flow controller is put into the system, the line current and the capacitor voltage can closely follow the given value in both current average distribution and current uneven distribution.

[0124] 3.2 Fault current limiting

[0125] The protection upper limit of the DC capacitor voltage U Cmax = 160 V is set, the short-circuit time Tf= 1 s is set, and the fault clearing time Td= Tf+ 0.003 = 1.003 s, that is, at t = 1 s, the system has a short-circuit fault, and the fault is cleared after 3 ms. The simulation waveform diagram under the fault current limiting mode is shown in Fig. 8. It can be seen from Figure 8a and Figure 8b that the simulation waveform in the first 1 s, that is, before the short-circuit fault occurs, is the same as that under the power flow control mode, 4.26 ms after the fault occurs, the DC capacitor voltage U C is charged to the protection threshold value 160 V, then the first bypass switch Q1 and the second bypass switch Q2 are turned on, and the IDCPFC is bypassed and protected.

[0126] Figure 9 The waveform diagram showing the influence of the system with and without current limiting on the current limiting effect is given. Figure 9 It can be seen from the

[0127] From the above, the current limiting effect is related to the capacitance value and the capacitor voltage limit. The smaller the capacitance value, the faster the capacitor voltage rises in a limited short-circuit time (generally, the DC short-circuit fault can be cleared by the circuit breaker within a few milliseconds), the greater the counter-pressure in the line, and the stronger the short-circuit current suppression capability. However, if the capacitance value is too small, the capacitor will be charged to the upper limit of the voltage in a very short time, and the capacitor will be bypassed when the short-circuit fault is not cleared, and the current will continue to increase at a relatively high rate. At this time, due to the short current suppression time, the current limiting effect is almost negligible. The greater the upper limit of the capacitor voltage, the longer the short-circuit current suppression time. However, blindly pursuing the current limiting time will increase the requirement for the rated value of the capacitor, increase the size of the device, and increase the difficulty of device selection. Therefore, the capacitance value and the upper limit of the capacitor voltage need to be selected according to the specific working conditions. The most ideal case is to reach the upper limit of the capacitor voltage when the fault is cleared, which can fully exert the current limiting capability and provide current limiting effect during the entire short-circuit process.

[0128] 4. Prototype test

[0129] Figure 10 The prototype test waveform of the application under the current limiting effect. When a fault occurs, under the current limiting effect, I1 rises to a peak value of 27.93A at 5ms after the fault occurs.

[0130] Figure 11 The prototype test waveform of the application under the current limiting effect. The system parameters are set as follows: U1=250V, I L1ref =3A, U Cref =30V, and the DC capacitance value is 550uF. In the steady state, the given values of I L1 and U C are 3A and 30V respectively. It can be seen that when the system reaches a steady state, the line current and the capacitor voltage are substantially equal to their reference values. Under the current limiting effect, when the current I1 rises to 17.52A, IDCPFC detects the fault and starts current limiting. Due to the low system voltage level, as the capacitor voltage rises, the line current begins to decrease. At 4.4ms, U Cmax =155V, the capacitor is bypassed, and the line current decreases to 10.51A. Since there is no circuit breaker, the line current will continue to rise. The fault in the actual system will be cleared by the circuit breaker within 3-4ms.

[0131] The above disclosure is only a specific embodiment of the application, but the protection scope of the application is not limited thereto. Any person skilled in the art can easily think of changes or modifications within the technical scope disclosed by the application, which should be covered within the protection scope of the application.

Claims

1. A control method of a line DC power flow controller, characterized by, The line-to-line direct current flow controller comprises a first H-bridge circuit, a second H-bridge circuit, a direct current capacitor, a first bypass switch and a second bypass switch; the first bypass switch is connected with an output end of the first H-bridge circuit, and the second bypass switch is connected with an output end of the second H-bridge circuit; the first H-bridge circuit is connected with the second H-bridge circuit through the direct current capacitor; The control method comprises the following steps: Step 1: connecting the line-to-line direct current flow controller to a multi-terminal direct current system, wherein the multi-terminal direct current system comprises at least one main converter station 1 and two slave converter stations 2 / 3, one end of the first bypass switch and the second bypass switch of the line-to-line direct current flow controller is connected with the main converter station 1 in series, and the other end of the first bypass switch and the second bypass switch is connected with the slave converter station 2 and the slave converter station 3 respectively; Step 2: controlling the duty cycle of the power devices in the first H-bridge circuit and the second H-bridge circuit and the on-off of the first bypass switch and the second bypass switch in the flow control state to realize the redistribution of the direct current line current; In the flow control state, the first bypass switch and the second bypass switch are both in the off state, and the specific control process in the flow control state comprises a steady state process and a transient state process; in the transient state, the duty cycle of the power devices in the first H-bridge circuit and the second H-bridge circuit is controlled to realize the time-sharing control of the direct current line current and the direct current capacitor voltage; The time-sharing control process in the transient state process is that: the control period is divided into a first half period and a second half period; the direct current line current is adjusted in the first half period, and the direct current capacitor voltage is adjusted in the second half period; One specific implementation process of the time-sharing control is that: In the first half cycle, when the line current modulation wave input from converter station 2 is greater than the line current carrier wave input from converter station 2, the line current input from converter station 2 flows through the first H-bridge circuit, the first H-bridge circuit outputs ± U C or 0, the second H-bridge circuit is in bypass state, so that the line current input from converter station 2 increases, and the line current input from converter station 3 decreases; when the line current modulation wave input from converter station 2 is less than the line current carrier wave input from converter station 2, the line current input from converter station 2 flows through the first H-bridge circuit, the first H-bridge circuit outputs 0 or ± U C , the second H-bridge circuit is in bypass state, so that the line current input from converter station 2 decreases, and the line current input from converter station 3 increases; In the second half of the cycle, when the DC capacitor voltage modulation wave is less than the DC capacitor voltage carrier, the line current from the converter station 3 flows through the second H-bridge circuit to discharge the DC capacitor, the second H-bridge circuit outputs ± U C , the first H-bridge circuit is in a bypass state, and the DC capacitor voltage decreases; when the DC capacitor voltage modulation wave is greater than the DC capacitor voltage carrier, the line current from the converter station 3 flows through the second H-bridge circuit, the second H-bridge circuit outputs 0, the first H-bridge circuit is in a bypass state, and the DC capacitor voltage increases.

2. The control method according to claim 1, characterized by: Another specific implementation process of the time-sharing control is that: In the first half cycle, when the line current modulation wave input from converter station 2 is greater than the line current carrier wave input from converter station 2, the line current input from converter station 3 flows through the second H-bridge circuit, and the second H-bridge circuit outputs ± U C or 0, the first H-bridge circuit is in a bypass state, so that the line current input from converter station 2 increases and the line current input from converter station 3 decreases; when the line current modulation wave input from converter station 2 is less than the line current carrier wave input from converter station 2, the line current input from converter station 3 flows through the second H-bridge circuit, and the second H-bridge circuit outputs 0 or ± U C , the first H-bridge circuit is in a bypass state, so that the line current input from converter station 2 decreases and the line current input from converter station 3 increases; In the second half of the cycle, when the DC capacitor voltage modulation wave is less than the DC capacitor voltage carrier, the line current from the converter station 2 flows through the first H-bridge circuit to discharge the DC capacitor, the first H-bridge circuit outputs ± U C , the second H-bridge circuit is in a bypass state, and the DC capacitor voltage decreases; when the DC capacitor voltage modulation wave is greater than the DC capacitor voltage carrier, the line current from the converter station 2 flows through the first H-bridge circuit, the first H-bridge circuit outputs 0, the second H-bridge circuit is in a bypass state, and the DC capacitor voltage increases.

3. The control method according to claim 1, characterized by: The first bypass switch and the second bypass switch are both a group of anti-parallel thyristors.

4. The control method of claim 1, wherein: In the steady state, the output voltage of the first H-bridge circuit and the second H-bridge circuit is adjusted to increase or decrease the input line current of the slave converter station 2 and the input line current of the slave converter station 3, so as to realize the redistribution of the direct current line current.

5. The control method of claim 1, wherein: The calculation expression of the input line current of the slave converter station 2 is: The calculation expression of the input line current of the slave converter station 3 is: wherein U 1, U 2, U 3 are the output DC voltage of the master converter station 1, the input DC voltage of the slave converter station 2, the input DC voltage of the slave converter station 3, respectively; U a Vc is the voltage across the power flow controller after the power flow controller is connected in series between the master converter station 1 and the slave converter station 2; U b Vc is the voltage across the power flow controller after the power flow controller is connected in series between the master converter station 1 and the slave converter station 3; R L1 R2 is the equivalent resistance of the input line of the slave converter station 2; R L2 R3 is the equivalent resistance of the input line of the slave converter station 3; I L1 I2 is the average current flowing through the input line of the slave converter station 2, i.e. the input line current of the slave converter station 2; I L2 I3 is the average current flowing through the input line of the slave converter station 3, i.e. the input line current of the slave converter station 3.

6. The control method according to any one of claims 1 to 5, characterized by: Step 2 further comprises the following steps in the short-circuit fault state: controlling the on-off of the power devices in the first H-bridge circuit and the second H-bridge circuit and the on-off of the first bypass switch and the second bypass switch to reduce the direct current line fault current, so as to realize the current limiting and self-protection; The specific control process in the short-circuit fault state comprises the following steps: acquiring a short-circuit fault signal, and making the power devices in the first H-bridge circuit and the second H-bridge circuit be in the off state according to the short-circuit fault signal, so as to make the first H-bridge circuit and the second H-bridge circuit be in the uncontrolled rectification state; the fault current charges the direct current capacitor through the anti-parallel diodes in the first H-bridge circuit and the second H-bridge circuit; when the direct current capacitor voltage is greater than or equal to the upper limit protection voltage of the direct current capacitor, the first bypass switch and the second bypass switch are controlled to be turned on, so as to bypass the line-to-line direct current flow controller.

7. The control method according to claim 6, characterized by: The short-circuit fault signal is obtained when any one of the line current or the DC capacitor voltage input from the converter station 2 exceeds the respective short-circuit threshold value, and the short-circuit fault signal is sent out; The short-circuit threshold of the line current input from the converter station 2 I OC The short-circuit threshold of the DC capacitor voltage is 15 A U OC 50 V.

8. A multi-terminal DC system comprising at least a main converter station 1 and two slave converter stations 2 / 3, characterized in that: The line-to-line DC power flow controller is connected to the main converter station 1 after the first bypass switch and the second bypass switch are connected in series, and the other ends of the first bypass switch and the second bypass switch are connected to the slave converter station 2 and the slave converter station 3, respectively; the line-to-line DC power flow controller is controlled by the control method in any one of claims 1-7.

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