Video signal processing circuit and video signal processing method

Abstract

An embodiment of the present application discloses a video signal processing circuit and a video signal processing method. The video signal processing circuit is coupled to an external memory and generates a video signal stream. The external memory stores partial data of a first frame. The video signal processing circuit includes: a memory, a control circuit, an image processing circuit, and a video signal encoding circuit. The control circuit is configured to read a first image block from the external memory and store the first image block into the memory. The first image block is a part of the first frame. The image processing circuit is configured to read the first image block from the memory and process the first image block to generate a second image block, wherein the second image block is a part of a second frame, and the second frame is not equal to the first frame. The video signal encoding circuit is configured to read the first image block from the memory and encode the first image block to generate a part of the video signal stream.

Description

Technical Field

[0001] This application relates to image processing, and more particularly to the generation of video streaming. Background Art

[0002] Figure 1 FIG. 1 shows a functional block diagram of an embodiment of a well-known video signal processing circuit 100. The video signal processing circuit 100 includes an image processing circuit 110, memories 122, 124, 126, and a video signal encoding circuit 130. The video signal processing circuit 100 processes input data Din to generate video streams Dout_M, Dout_S1, Dout_S2,.... The image processing circuit 110 is used to process the input data Din to generate source data Din_M for the video stream Dout_M, source data Din_S1 for the video stream Dout_S1, and source data Din_S2 for the video stream Dout_S2. The source data Din_M (source data Din_S1 or source data Din_S2) includes a plurality of frames, which are sequentially stored in the memory 122 (memory 124 or memory 126) for the video signal encoding circuit 130 to access. The video signal encoding circuit 130 encodes the source data Din_M, source data Din_S1, and source data Din_S2 to generate the video streams Dout_M, Dout_S1, and Dout_S2, respectively.

[0003] As Figure 1 shown, the memory 122 includes two memory blocks: memory block 122a and memory block 122b, one of which is used to store the (N - 1)th frame of the source data Din_M, and the other is used to store the Nth frame of the source data Din_M. The same applies to the memories 124 and 126 and will not be elaborated further. In other words, for any video stream (Dout_M, Dout_S1, Dout_S2, or others), the video signal processing circuit 100 needs to store at least two complete frames of the source data of the video stream simultaneously, which undoubtedly consumes a lot of system resources and makes the product less competitive. This drawback becomes more significant when the number of video streams output by the video signal processing circuit 100 is larger.

[0004] Please refer to Figure 2 , Figure 2 is Figure 1Timing diagram of the data. The falling edge of the clock CLK (i.e., time points t2, t4, t6, …) indicates the start point of a frame, and the rising edge of the clock CLK (i.e., time points t1, t3, t5, …) indicates the end point of a frame. In this example, the image processing circuit 110 includes three sub - circuits (the three sub - circuits process the input data Din to generate source data Din_M, source data Din_S1, and source data Din_S2 respectively), so the image processing circuit 110 can simultaneously output the (N - 1)th frame M(N - 1) (gray background) of the source data Din_M, the (N - 1)th frame S1(N - 1) (gray background) of the source data Din_S1, and the (N - 1)th frame S2(N - 1) (gray background) of the source data Din_S2 between time points t2 and t3, and can simultaneously output the Nth frame M(N) (gray background) of the source data Din_M, the Nth frame S1(N) (gray background) of the source data Din_S1, and the Nth frame S1(N) (gray background) of the source data Din_S2 between time points t4 and t5. When the image processing circuit 110 generates the Nth frame (i.e., between time points t4 and t5, the Nth frame is stored in one of the two memory blocks), the video signal encoding circuit 130 encodes the (N - 1)th frame stored in the other memory block (i.e., the (N - 1)th frame M(N - 1) (gray background) of the source data Din_M, the (N - 1)th frame S1(N - 1) (gray background) of the source data Din_S1, and the (N - 1)th frame S2(N - 1) (gray background) of the source data Din_S2) to generate the (N - 1)th frame of the video signal stream (i.e., M(N - 1) (grid), S1(N - 1) (grid), and S2(N - 1) (grid)). In other words, there is a one - frame delay between the image processing circuit 110 and the video signal encoding circuit 130.

[0005] In summary, the well - known video signal processing circuit 100 not only consumes hardware resources (the memory requires a large amount of space and the image processing circuit 110 includes multiple sub - circuits), but also has poor efficiency (with a delay). Summary of the Invention

[0006] Embodiments of the present application provide a video signal processing circuit and a video signal processing method to improve the deficiencies of the prior art.

[0007] An embodiment of the present application provides a video signal processing circuit, which is coupled to an external memory that stores partial data of a first frame. The video signal processing circuit generates a video signal stream, and the video signal processing circuit includes: a memory, a control circuit, an image processing circuit, and a video signal encoding circuit. The control circuit is configured to read a first image block from the external memory and store the first image block into the memory, where the first image block is a part of the first frame. The image processing circuit is configured to read the first image block from the memory and process the first image block to generate a second image block, where the second image block is a part of a second frame, and the second frame is not equal to the first frame. The video signal encoding circuit is configured to read the first image block from the memory and encode the first image block to generate a part of the video signal stream.

[0008] An embodiment of the present application provides a video signal processing method for generating a video signal stream based on a first frame. The video signal processing method includes the following steps: reading a first image block from an external memory and storing the first image block into a memory, where the first image block is a part of the first frame; a scaling operation of reading the first image block from the memory and processing the first image block to generate a second image block, where the second image block is a part of a second frame, and the second frame is not equal to the first frame; and an encoding operation of reading the first image block from the memory and encoding the first image block to generate a part of the video signal stream.

[0009] An embodiment of the present application provides a video signal processing method for generating a first video signal stream and a second video signal stream. The video signal processing method includes the following steps: reading a first image block of a first frame from an external memory and storing the first image block into an internal memory; processing the first image block to generate a second image block, where the second image block is a part of a second frame, and the second frame is not equal to the first frame; storing the second image block into the external memory; encoding the first image block to generate a part of the first video signal stream; reading the second image block from the external memory and storing the second image block into the internal memory; and encoding the second image block to generate a part of the second video signal stream.

[0010] The technical means embodied in the embodiments of the present application can improve at least one of the disadvantages of the prior art. Therefore, compared with the prior art, the present application can save memory and / or reduce latency.

[0011] The features, implementation, and effects of the present application will be described in detail with reference to the accompanying drawings in the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 A functional block diagram showing an embodiment of a well-known video signal processing circuit;

[0014] Figure 2 Show Figure 1 A timing diagram of the data;

[0015] Figure 3 Is a functional block diagram of an embodiment of the image processing system of the present application;

[0016] Figure 4 Is a flowchart of an embodiment of the video signal processing method of the present application;

[0017] Figure 5 Show Figure 3 And Figure 4 An example of a timing diagram of the data;

[0018] Figure 6 Show Figure 4 A flowchart of an embodiment of step S320 or S360;

[0019] Figure 7A And 7B Respectively show frame 710 and frame 720;

[0020] Figure 8A Show Figure 4 Another implementation of step S320, step S360, and step S380;

[0021] Figure 8B Show Figure 4 Another implementation of step S320 and step S360;

[0022] Figure 9 A flowchart showing an embodiment of step S320A, S320B, S360A, or S360B;

[0023] Figure 10 Show Figure 3 The internal circuit of the memory 232;

[0024] Figure 11A Flowchart of the display control circuit reading data from the memory 210 and writing the data into the memory 232;

[0025] Figure 11B and Figure 11C Flowchart of the display image processing circuit and the video signal encoding circuit reading data from the memory 232.

[0026]

Symbol Explanation

[0027] 100, 230: Video signal processing circuit

[0028] 110, 234: Image processing circuit

[0029] 122, 124, 126, 210, 232: Memory

[0030] 130, 236: Video signal encoding circuit

[0031] Din: Input data

[0032] Dout_M, Dout_S1, Dout_S2: Video signal stream

[0033] Din_M, Din_S1, Din_S2: Source data

[0034] 122a, 122b, 212, 214, 232a, 232b: Memory block

[0035] CLK: Clock

[0036] t1~t10: Time point

[0037] 200: Image processing system

[0038] 220: Processor

[0039] 231: Control circuit

[0040] 710, 720: Frame

[0041] S310, S320, S330, S335, S340, S350, S360, S362, S364, S370, S380, S382, S384, S410, S412, S414, S416, S420, S430, S432, S434, S440, S320A, S320B, S360A, S360B, S380A, S910, S920, S1112, S1114, S1116, S1118, S1122, S1124, S1126, S1128, S1129, S1132, S1134, S1136, S1138: Step Detailed implementation manners

[0042] The technical terms in the following description refer to the customary terms in the technical field to which this application pertains. If this specification provides an explanation or definition for some terms, the explanations of such terms shall be subject to the explanations or definitions provided in this specification.

[0043] The disclosure of this application includes a video signal processing circuit and a video signal processing method. Since some of the components included in the video signal processing circuit of this application may be known components individually, the details of the known components will be omitted in the following description without affecting the full disclosure and practicability of the device invention. In addition, some or all of the processes of the video signal processing method of this application may be in the form of software and / or hardware, and can be executed by the video signal processing circuit of this application or its equivalent device. Without affecting the full disclosure and practicability of the method invention, the description of the method invention will focus on the step content rather than the hardware.

[0044] Figure 3 FIG. 11 is a functional block diagram of an embodiment of the image processing system 200 of this application. The image processing system 200 includes a memory 210, a processor 220, and a video signal processing circuit 230.

[0045] The memory 210 includes a memory block 212 and a memory block 214. The memory block 212 is used to store the source data Din_M, and the memory block 214 is used to store the source data Din_Sx (x = 1, 2, 3,...). More specifically, each of the source data Din_M and the source data Din_Sx includes a plurality of frames; the stored content of the memory block 212 includes all or part of the data of one frame of the source data Din_M, and the stored content of the memory block 214 includes all or part of the data of one frame of the source data Din_Sx. The source data Din_M may be unscaled data (for example, the output image of an image sensor), or scaled data (for example, the scaled-down output image).

[0046] The video signal processing circuit 230 includes a control circuit 231, a memory 232, an image processing circuit 234, and a video signal encoding circuit 236. In some embodiments, the memory 210 is a Dynamic Random Access Memory (DRAM), and the memory 232 is a Static Random Access Memory (SRAM).

[0047] For the video signal processing circuit 230, the memory 210 is an external memory, and the memory 232 is an internal memory.

[0048] Figure 4 It is a flowchart of an embodiment of the video signal processing method of the present application. Figure 4 Assume that the video signal processing circuit 230 generates k + 1 video signal streams (i.e., Dout_M, Dout_S1, Dout_S2, …, Dout_Sk, where k is an integer greater than 1). Figure 5 is Figure 3 and Figure 4 An example of a timing diagram of the data. In Figure 5 example, k = 2. Similarly, the falling edges of the clock CLK (i.e., time points t2, t4, t8, …) indicate the start of a frame, and the rising edges of the clock CLK (i.e., time points t1, t3, t6, …) indicate the end of a frame. The following will describe the operation details of the video signal processing circuit 230 in conjunction with Figure 4 and Figure 5 to illustrate the operation details of the video signal processing circuit 230.

[0049] S310: The control circuit 231 reads the target image block A1 of the Nth frame (i.e., frame M(N) (gray background)) of the source data Din_M from an external memory (more specifically, from the memory block 212), and stores the target image block A1 in the memory 232. The stored content of the memory block 212 includes partial data (e.g., at least one image block) or all data of the Nth frame of the source data Din_M, and when executing step S310, the control circuit 231 can copy or move the partial data (i.e., the target image block A1) of the Nth frame to the memory 232.

[0050] S320: The image processing circuit 234 and the video signal encoding circuit 236 respectively generate an output image block B1 (i.e., a part of the Nth frame S1(N) (gray background) of the source data Din_S1) and a part of the video signal stream Dout_M (i.e., a part of the Nth frame M(N) (mesh) of the video signal stream Dout_M) based on the target image block A1, and the image processing circuit 234 stores the output image block B1 in the external memory (more specifically, stores it in the memory block 214). For example, this step may correspond to Figure 5 between the time points t5 and t7. The video signal processing circuit 230 performs image processing based on the image block. After processing each target image block A1, it stores the output image block B1 in the memory block 214 and outputs the corresponding video signal stream. In some embodiments, the Nth frame M(N) (mesh) of the video signal stream Dout_M and the Nth frame S1(N) (gray background) of the source data Din_S1 start to be generated substantially simultaneously (time point t5) and are generated completely substantially simultaneously (time point t7).

[0051] Since the video signal processing circuit 230 performs image processing based on image blocks (instead of frames), the Nth frame S1(N) (gray background) of the source data Din_S1 and the Nth frame M(N) (grid) of the video signal stream Dout_M can start being generated at time point t5, without having to wait until the Nth frame M(N) (gray background) of the source data Din_M ends (i.e., time point t6) to start generating. In one embodiment, the video signal processing circuit 230 and the previous-stage circuit (e.g., an image signal processor or a scaling circuit, not shown in the figure) access the memory block 212 in a ring buffer manner to achieve this purpose. The principle and operation details of the ring buffer are well-known to those of ordinary skill in the art, so they will not be elaborated here. From the foregoing description, since the image processing circuit 234 and the video signal encoding circuit 236 share the target image block A1 in the memory 232, before the image processing circuit 234 and the video signal encoding circuit 236 respectively generate the output image block B1 and a part of the video signal stream Dout_M, the control circuit 231 only writes the target image block A1 from the external memory to the memory 232 once. Thus, the bandwidth requirement between the video signal processing circuit 230 and the external memory can be reduced.

[0052] S330: Determine whether the image processing circuit 234 and the video signal encoding circuit 236 have completed all the image blocks of a frame. If not, determine the next target image block A1 (step S335) and then return to step S310; if so, proceed to step S340.

[0053] S340: The control circuit 231 reads the target image block A2 of the Nth frame of the source data Din_Sx from the external memory (more specifically, from the memory block 214) and stores the target image block A2 in the memory 232. The stored content of the memory block 214 includes part of the data (e.g., at least one image block) or all of the data of the Nth frame of the source data Din_Sx, and when executing step S340, the control circuit 231 can copy or move part of the data (i.e., the target image block A2) of the Nth frame to the memory 232.

[0054] S350: If the video signal processing circuit 230 is processing the Nth frame of the last video signal stream (i.e., x = k, in other words, the Nth frames of the source data Din_M, source data Din_S1, source data Din_S2,..., source data Din_Sk-1 have all been processed and the corresponding video signal streams have been generated), then execute steps S380 - S384; otherwise, execute steps S360 - S364.

[0055] S360: The image processing circuit 234 and the video signal encoding circuit 236 respectively generate an output image block B2 (i.e., a part of the Nth frame of the source data Din_Sx+1) and a part of the video signal stream Dout_Sx based on the target image block A2. Moreover, the image processing circuit 234 stores the output image block B2 into an external memory (more specifically, stores it into the memory block 214).

[0056] S362: Determine whether the image processing circuit 234 and the video signal encoding circuit 236 have completed all the image blocks of a frame. If not, then determine the next target image block A2 of the Nth frame of the source data Din_Sx (step S370) and then return to step S340; if so, then proceed to step S364.

[0057] S364: Let x = x + 1, and then return to step S340 to continue processing the Nth frame of the next video signal stream.

[0058] Steps S360 to S364 can correspond to Figure 5 the time points between t7 and t9. More specifically, the target image block A2 is an image block of S1(N) (gray background), a part of the video signal stream Dout_Sx is a part of the Nth frame S1(N) (grid) of the video signal stream Dout_S1, and the output image block B2 is a part of the Nth frame S2(N) (gray background) of the source data Din_S2. Similarly, because the video signal processing circuit 230 performs image processing based on the image blocks (i.e., after processing each target image block A2, it stores the output image block B2 into the memory block 214 and outputs the corresponding video signal stream), so S1(N) (grid) and S2(N) (gray background) substantially start to be generated simultaneously (time point t7) and substantially complete generation simultaneously (time point t9).

[0059] S380: The video signal encoding circuit 236 generates a part of the video signal stream Dout_Sx based on the target image block A2. Step S380 can correspond to Figure 5 the time points between t9 and t10; more specifically, the target image block A2 is an image block of S2(N) (gray background), and a part of the video signal stream Dout_Sx is a part of the Nth frame S2(N) (grid) of the video signal stream Dout_S2.

[0060] S382: Determine whether the video signal encoding circuit 236 has completed all the image blocks of a frame. If not, then determine the next target image block A2 of the Nth frame of the source data Din_Sx (step S370) and then return to step S340; if so, then proceed to step S384.

[0061] S384: Let N = N + 1, reset x to 1, and then return to step S310 to continue processing the next frame (i.e., the (N + 1)-th frame).

[0062] From the above discussion, it can be seen that except for the initial source data Din_M (not generated by the video signal processing circuit 230), other source data generated by the video signal processing circuit 230 (source data Din_S1, source data Din_S2, …) are stored in the memory block 214; in other words, the source data generated by the video signal processing circuit 230 share the memory block 214 to save memory. In addition, the video signal processing circuit 230 can also reduce the latency (i.e., the N-th frame M(N) (grid) of the video signal stream Dout_M starts to be generated at time point t5, rather than after time point t6).

[0063] In some embodiments, steps S340 and S360 can be executed simultaneously or partially simultaneously. For example, the control circuit 231 and the image processing circuit 234 access the memory block 214 in a ring buffer manner.

[0064] Figure 6 Yes Figure 4 is a flowchart of an embodiment of step S320 or S360. Figure 6 Includes the following steps.

[0065] S410: Scaling operation, including sub-steps S412, S414, and S416, is performed by the image processing circuit 234.

[0066] S412: Read a part of the target image block (A1 or A2) from the memory 232. Please refer to Figure 7A and 7B , Figure 7A and 7B respectively display frame 710 and frame 720. Frame 710 is the N-th frame of the source data Din_M or the N-th frame of the source data Din_Sx, and frame 720 is the N-th frame of the source data Din_S1 or the N-th frame of the source data Din_Sx + 1. In Figure 7A and 7B 's example, frame 710 includes 6 image blocks (A(a, b), 1 ≤ a ≤ 3, 1 ≤ b ≤ 2, and each image block A(a, b) is sequentially selected as Figure 4 's target image block A1 or target image block A2), and frame 720 includes 2 image blocks (B(c, d), c = 1, 1 ≤ d ≤ 2, and each image block B(c, d) can be Figure 4The output image block B1 or output image block B2). The stored content of the memory 232 includes at least one image block. In this step, the image processing circuit 234 reads a column of data of the target image block each time for processing. For example, assuming the target image block is A(1,1), the image processing circuit 234 reads the pixel data P1~P5, P16~P20, P31~P35 or P46~P50 each time this step is executed.

[0067] S414: Process this part of the target image block (A1 or A2) to generate a part of the output image block (B1 or B2). The output image block is an image block of frame 720. Taking the scaling down operation as an example (assuming the scaling ratio is 1 / 3), the image processing circuit 234 executes Equation (1) to generate the output image block.

[0068]

[0069] It should be noted that when the image processing circuit 234 processes a column of pixels of the image block A(2,1) (for example, P6~P10), it will use (1) some pixels of the same column of pixels of the adjacent image block A(1,1) (for example, P1~P5), or (2) the calculation result obtained based on the same column of pixels of the adjacent image block A(1,1). Continuing with the above example, since the pixel Q2 of frame 720 = (P4 + P5 + P6) / 3 (P4, P5, and P6 are consecutive pixels), so for case (1), when the image processing circuit 234 processes the pixels of the first column of the image block A(2,1), it needs the pixel values P4 and P5 of the image block A(1,1); for case (2), when the image processing circuit 234 processes the pixels of the first column of the image block A(2,1), the image processing circuit 234 calculates the calculation result of the pixel values P4 and P5 (that is, (P4 + P5) / 3) and the pixel value P6 at the same time (that is, Q2 = (P4 + P5) / 3 + P6 / 3). The pixel values P4 and P5 and / or the calculation result based on the pixel values P4 and P5 ((P4 + P5) / 3) can be stored in the memory 232 for the image processing circuit 234 to use when processing the pixels of the first column of the image block A(2,1).

[0070] S416: The image processing circuit 234 stores this part of the output image block (B1 or B2) in the memory 210 (more specifically, in the memory block 214). For example, the image processing circuit 234 stores the pixel value Q1 in the memory block 214.

[0071] S420: The image processing circuit 234 determines whether the target image block (A1 or A2) has been completed. When the image processing circuit 234 finishes processing all columns of the target image block (A1 or A2) (the result of S420 is yes), the process proceeds to step S430; otherwise, the image processing circuit 234 continues to process other parts of the target image block (A1 or A2).

[0072] S430: The encoding operation, including sub-steps S432 and S434, is performed by the video signal encoding circuit 236.

[0073] S432: The video signal encoding circuit 236 reads a part of the target image block (A1 or A2) from the memory. The target image block in this step is the same as the target image block (A1 or A2) in step S412; in other words, the same target image block (A1 or A2) will undergo scaling processing and encoding processing.

[0074] S434: The video signal encoding circuit 236 encodes this part of the target image block (A1 or A2) to generate a part of the video signal stream. In some embodiments, the video signal encoding circuit 236 encodes based on the H.264 standard; the H.264 standard is well-known to those of ordinary skill in the art, so it will not be elaborated here.

[0075] S440: The video signal encoding circuit 236 determines whether the target image block (A1 or A2) has been completed. When the video signal encoding circuit 236 finishes processing all pixels of the target image block (the result of S440 is yes), it returns to Figure 4 step S330 or S362; otherwise, the video signal encoding circuit 236 continues to process other parts of the target image block.

[0076] Figure 4 The details of step S380 include Figure 6 step S430 and step S440.

[0077] From the above discussion, it can be seen that the image processing circuit 234 and the video signal encoding circuit 236 operate based on image blocks.

[0078] In different embodiments, Figure 6 step S410 and step S430 can be swapped.

[0079] In some embodiments, the resolutions of source data Din_M (or video signal stream Dout_M), source data Din_S1 (or video signal stream Dout_S1), source data Din_S2 (or video signal stream Dout_S2), etc. are different. For example, the resolution of source data Din_M (or video signal stream Dout_M) is greater than the resolution of source data Din_S1 (or video signal stream Dout_S1), and the resolution of source data Din_S1 (or video signal stream Dout_S1) is greater than the resolution of source data Din_S2 (or video signal stream Dout_S2).

[0080] The processor 220 can control whether to activate the image processing circuit 234 and / or the video signal encoding circuit 236 according to the frame rate Fx of the video signal stream Dout_Sx and the frame rate Fx+1 of the video signal stream Dout_Sx+1, including the following three scenarios.

[0081] Scenario (1): When the frame rate Fx is equal to the frame rate Fx+1, both the image processing circuit 234 and the video signal encoding circuit 236 are activated, that is, both the image processing circuit 234 and the video signal encoding circuit 236 process each frame of the source data Din_Sx (corresponding to Figure 4 and Figure 6 the process).

[0082] Scenario (2): When the frame rate Fx is less than the frame rate Fx+1, the image processing circuit 234 processes a certain frame, and the video signal encoding circuit 236 does not encode this frame. For example, assume that the frame rate Fx is 30 fps (frames per second), and the frame rate Fx+1 is 60 fps. Then the image processing circuit 234 processes each frame of the source data Din_Sx, but the video signal encoding circuit 236 only encodes one of every two consecutive frames (=60 / 30) of the source data Din_Sx and skips the other. In this scenario, Figure 4 steps S320, S360, and S380 of Figure 8A are replaced by steps S320A, S360A, and S380A of Figure 6 respectively, and two steps: S910 and S920 are added to the process of Figure 9 as shown. In step S910, the image processing circuit 234 determines whether to skip the current frame according to a first setting value (generated by the processor 220). If so, the image processing circuit 234 does not perform a scaling operation on this frame. In step S920, the video signal encoding circuit 236 determines whether to skip the current frame according to a second setting value (generated by the processor 220). If so, the video signal encoding circuit 236 does not perform an encoding operation on this frame.

[0083] Scenario (3): When the frame rate Fx is greater than the frame rate Fx+1, the video signal encoding circuit 236 encodes a certain frame, but the image processing circuit 234 does not process this frame. For example, assume that the frame rate Fx is 60 fps and the frame rate Fx+1 is 30 fps. Then the video signal encoding circuit 236 encodes each frame of the source data Din_Sx, but the image processing circuit 234 only processes one of every two ( = 60 / 30) consecutive frames of the source data Din_Sx and skips the other. In this scenario, Figure 4 Steps S320 and S320 are respectively replaced by Figure 8B Steps S320B and S360B, and Figure 6 The process of Figure 9 is replaced by the process of

[0084] Figure 10 Display Figure 3 The internal circuit of the memory 232. Figure 10 And Figure 3 Is basically the same as Figure 10 An embodiment of the display memory 232. In Figure 10 The embodiment, the memory 232 includes a memory block 232a and a memory block 232b. The control circuit 231, the image processing circuit 234, and the video signal encoding circuit 236 are all coupled to the memory block 232a and the memory block 232b. The memory block 232a and the memory block 232b are provided for use by the image processing circuit 234 and the video signal encoding circuit 236 in the form of a double buffer. Figure 11A Shows the flowchart of the control circuit 231 reading data from the memory 210 and writing the data into the memory 232, Figure 11B And Figure 11C Shows the flowchart of the image processing circuit 234 and the video signal encoding circuit 236 reading data from the memory 232, which is described in detail below.

[0085] Figure 11A Includes the following steps.

[0086] Step S1112: The control circuit 231 selects the one with a status of 0 among the memory block 232a and the memory block 232b as the target memory block. The memory block 232a and the memory block 232b have their respective statuses. This step includes the control circuit 231 waiting for the status of the memory block 232a or the memory block 232b to become 0.

[0087] Step S1114: The control circuit 231 sets the status of the target memory block to 1.

[0088] Step S1116: The control circuit 231 reads D1 bits from the memory 210 and writes the D1 bits into the target memory block.

[0089] Step S1118: The control circuit 231 determines whether the number of bits that have been written into the target memory block cumulatively is greater than or equal to a preset value. This preset value can be an integer multiple of the amount of data read / written by the control circuit 231, the image processing circuit 234, and the video signal encoding circuit 236 each time. For example, assuming that the amount of data read or written by the control circuit 231, the image processing circuit 234, and the video signal encoding circuit 236 each time is D1, D2, and D3 respectively, the preset value can be the least common multiple of D1, D2, and D3. In some embodiments, the preset value can be Figure 4 the data volume of the target image block (A1 or A2); in other words, the result of step S1118 being yes means that the control circuit 231 has written the data of a target image block (A1 or A2) into the target memory block.

[0090] Figure 11B comprises the following steps.

[0091] Step S1122: The image processing circuit 234 or the video signal encoding circuit 236 selects the memory block among the memory block 232a and the memory block 232b with a status of 1 as the target memory block. This step includes the image processing circuit 234 or the video signal encoding circuit 236 waiting for the status of the memory block 232a or the memory block 232b to become 1.

[0092] Step S1124: The image processing circuit 234 or the video signal encoding circuit 236 determines whether the unread data in the target memory block is greater than D2 (or D3) bits. If so, step S1126 is executed; if not, it waits for the control circuit 231 to write data.

[0093] Step S1126: The image processing circuit 234 or the video signal encoding circuit 236 reads D2 (or D3) bits from the target memory block.

[0094] Step S1128: The image processing circuit 234 or the video signal encoding circuit 236 determines whether the number of bits read out from the target memory block cumulatively is greater than or equal to the preset value. If so, step S1129 is executed; if not, it returns to step S1124.

[0095] Step S1129: The image processing circuit 234 or the video signal encoding circuit 236 sets the status of the target memory block to 2.

[0096] It can be seen from Figure 11A and Figure 11B that since the memory block with a status of 1 will be written with data by the control circuit 231 at the same time (Figure 11A ) and the data is read by the image processing circuit 234 or the video signal encoding circuit 236 Figure 11B ), so the target memory block is used as a ring buffer.

[0097] Figure 11C The method includes the following steps.

[0098] Step S1132: The image processing circuit 234 or the video signal encoding circuit 236 selects the memory blocks 232a and 232b with the status of 2 as the target memory block. This step includes the image processing circuit 234 or the video signal encoding circuit 236 waiting for the status of the memory block 232a or 232b to become 2.

[0099] Step S1134: The image processing circuit 234 or the video signal encoding circuit 236 reads D2 (or D3) bits from the target memory block.

[0100] Step S1136: The image processing circuit 234 or the video signal encoding circuit 236 determines whether the cumulative number of bits read from the target memory block is greater than or equal to a preset value. If so, step S1138 is executed; if not, it returns to step S1134.

[0101] Step S1138: The image processing circuit 234 or the video signal encoding circuit 236 sets the status of the target memory block to 0.

[0102] One of the image processing circuit 234 and the video signal encoding circuit 236 executes Figure 11B , and the other executes Figure 11C . For example (please refer to Figure 7A ), at a certain time point (the pixel values of the first column of block A(2,1) have been written into the memory block 232a), the control circuit 231 is writing the pixel values of the second column of block A(2,1) into the memory block 232a, the image processing circuit 234 is reading the pixel values of the first column of block A(2,1) from the memory block 232a, and the video signal encoding circuit 236 is reading the pixel values of block A(1,1) from the memory block 232b.

[0103] In Figure 10 's circuit architecture, the image processing circuit 234 and the video signal encoding circuit 236 can work simultaneously to accelerate data processing and output. For example, please refer to Figure 5 , Figure 10The architecture can generate frame M(N) (grid) and frame S1(N) (gray background) faster (i.e., shorten the time length of t7 - t5), and can also generate frame Sx(N) (grid) and frame Sx+1(N) (gray background) faster (e.g., shorten the time length of t9 - t7). In other words, Figure 10 the circuit architecture can make Figure 4 the process proceed more quickly, that is, the image processing system 200 has higher efficiency.

[0104] The video signal processing circuit and the video signal processing method provided by the embodiments of the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A video signal processing circuit, characterized in that, Couple to an external memory which stores partial data of a first frame. The video signal processing circuit generates a video signal stream. The video signal processing circuit includes: A memory; A control circuit for reading a first image block from the external memory and storing the first image block into the memory. The first image block is a part of the first frame; An image processing circuit for reading the first image block from the memory and processing the first image block to generate a second image block. Wherein, the second image block is a part of a second frame, and the second frame is not equal to the first frame; and A video signal encoding circuit for reading the first image block from the memory and encoding the first image block to generate a part of the video signal stream. Before the image processing circuit and the video signal encoding circuit respectively generate the second image block and the part of the video signal stream, the control circuit writes the first image block into the memory only once.

2. The video signal processing circuit according to claim 1, characterized in that The image processing circuit further stores the second image block into the external memory. The control circuit further reads the second image block from the external memory and stores the second image block into the memory.

3. The video signal processing circuit according to claim 2, wherein The video signal stream is a first video signal stream. The video signal processing circuit further sequentially generates a second video signal stream and a third video signal stream. The image processing circuit and the video signal encoding circuit determine whether to process or encode the second image block according to the frame rates of the second video signal stream and the third video signal stream.

4. The video signal processing circuit according to claim 2, wherein, The video signal stream is a first video signal stream. The video signal processing circuit further sequentially generates a second video signal stream and a third video signal stream. When the frame rate of the second video signal stream is less than the frame rate of the third video signal stream, the image processing circuit processes the second image block, but the video signal encoding circuit does not encode the second image block.

5. The video signal processing circuit according to claim 2, wherein The video signal stream is a first video signal stream. The video signal processing circuit further sequentially generates a second video signal stream and a third video signal stream. When the frame rate of the second video signal stream is greater than the frame rate of the third video signal stream, the video signal encoding circuit encodes the second image block, but the image processing circuit does not process the second image block.

6. The video signal processing circuit according to claim 1, wherein The image processing circuit further stores the second image block into the external memory, and the resolution of the first frame is not equal to the resolution of the second frame.

7. The video signal processing circuit according to claim 6, wherein The memory further stores a third image block which is a part of the first frame and adjacent to the first image block. The image processing circuit performs the following operations: Calculate the average value of X pixels of the first image block and Y pixels of the third image block. Both X and Y are positive integers. The X pixels and the Y pixels are consecutive pixels in the same column of the first frame.

8. The video signal processing circuit according to claim 6, wherein The memory also stores a third image block, which is a part of the first frame and adjacent to the first image block, and the image processing circuit performs the following operations: Calculating X pixels of the first image block to generate a calculation result; and Simultaneously calculating the calculation result and Y pixels of the third image block; Wherein, both X and Y are positive integers, and the X pixels and the Y pixels are consecutive pixels in the same column of the first frame.

9. The video signal processing circuit according to claim 6, characterized in that, The first frame is generated by the image processing circuit.

10. The video signal processing circuit according to claim 6, wherein The first frame is not generated by the image processing circuit, and the first frame is the result of a scaling operation.

11. A video signal processing method, characterized in that, The video signal processing method is used to generate a video signal stream according to a first frame, and the video signal processing method includes: Reading a first image block from an external memory and storing the first image block into a memory, where the first image block is a part of the first frame; A scaling operation, which reads the first image block from the memory and processes the first image block to generate a second image block, wherein the second image block is a part of a second frame, and the second frame is not equal to the first frame; and An encoding operation, which reads the first image block from the memory and encodes the first image block to generate a part of the video signal stream; before the scaling operation and the encoding operation respectively generate the second image block and the part of the video signal stream, the first image block is only written into the memory once.

12. The video signal processing method according to claim 11, wherein, The video signal processing method further includes: Storing the second image block into the external memory; Reading the second image block from the external memory; and Storing the second image block into the memory.

13. The video signal processing method according to claim 11, wherein The video signal processing method further includes: Storing the second image block into the external memory; Wherein, the resolution of the first frame is not equal to the resolution of the second frame.

14. The video signal processing method according to claim 13, wherein The memory also stores a third image block, which is a part of the first frame and adjacent to the first image block, and the scaling operation further includes: Calculating the average value of X pixels of the first image block and Y pixels of the third image block, where both X and Y are positive integers, and the X pixels and the Y pixels are consecutive pixels in the same column of the first frame.

15. The video signal processing method according to claim 13, wherein The memory also stores a third image block, which is a part of the first frame and adjacent to the first image block, and the scaling operation further includes: Calculating X pixels of the first image block to generate a calculation result; and Simultaneously calculating the calculation result and Y pixels of the third image block; Wherein, both X and Y are positive integers, and the X pixels and the Y pixels are consecutive pixels in the same column of the first frame.

16. A video signal processing method, characterized in that The video signal processing method is used to generate a first video signal stream and a second video signal stream, and the video signal processing method includes: Read a first image block of a first frame from an external memory and store the first image block in an internal memory; Process the first image block to generate a second image block, the second image block being part of a second frame, the second frame being different from the first frame; Store the second image block in the external memory; Encode the first image block to generate a part of the first video signal stream; Read the second image block from the external memory and store the second image block in the internal memory; and Encode the second image block to generate a part of the second video signal stream; the first image block is only written to the internal memory once before the operations of processing the first image block to generate a second image block and encoding the first image block to generate the part of the first video signal stream respectively generate the second image block and the part of the first video signal stream.

17. The video signal processing method according to claim 16, wherein The resolution of the first frame is different from the resolution of the second frame.

18. The video signal processing method according to claim 16, wherein, The external memory is a dynamic random access memory, and the internal memory is a static random access memory.

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