Semiconductor devices with selective command delay and associated methods and systems

Abstract

Memory devices, systems including memory devices, and methods of operating memory devices are described in which a memory device is configured to add a variable delay to a command. The variable delay can be provided by a test mode of the memory device that can be used by a host device (e.g., a test equipment). Alternatively, the variable delay can be stored in a non-volatile memory (NVM) component of the memory device. In addition, a mode register of the memory device can be set to indicate that the command is associated with the variable delay stored in the NVM component. In addition, the memory device can include a delay component configured to add the variable delay to the command. Such variable delay facilitates staggered execution of the command across multiple memory devices in order to avoid (or mitigate) issues related to instantaneous, large amounts of current drawn from a power supply connected to the memory devices.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 839,371, filed April 3, 2020, and U.S. Provisional Application No. 62 / 955,701, filed December 31, 2019, which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor devices with selective command delays and associated methods and systems. Background Technology

[0004] Memory devices are widely used to store information associated with various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Memory devices are often provided as internal semiconductor integrated circuits and / or external removable devices within computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory, including Random Access Memory (RAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), requires a power source to maintain its data. In contrast, non-volatile memory retains its stored data even when no external power supply is available. Non-volatile memory can be used in various technologies, including flash memory (e.g., NAND and NOR), phase-change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM). Improving memory devices can typically include increasing memory cell density, increasing read / write speeds or otherwise reducing operating latency, improving reliability, increasing data retention, reducing power consumption or manufacturing costs, and other metrics. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an embodiment of a memory device according to the present invention.

[0006] Figure 2 This is a block diagram illustrating, schematically, a command decoder of a memory device according to an embodiment of the present invention.

[0007] Figure 3 A block diagram illustrating a scheme for introducing variable latency into commands of a memory device in a system according to an embodiment of the present invention is shown.

[0008] Figure 4A timing diagram illustrating a scheme for introducing variable latency into commands of a memory device in a system according to an embodiment of the present invention is shown.

[0009] Figure 5 This is a block diagram illustrating an embodiment of a memory system according to the present invention.

[0010] Figure 6 and 7 This is a flowchart illustrating a method for operating a memory device according to an embodiment of the present invention. Detailed Implementation

[0011] Multiple memory devices may be arranged to share a common power supply within a memory module (e.g., a dual in-line memory module (DIMM), a high-bandwidth memory (HBM) module, or a group of memory devices coupled to a test apparatus configured for parallel testing). The number of memory devices sharing a power supply can be increased for various reasons—e.g., to increase the storage capacity of the HBM module, to improve the efficiency of shared resources in a parallel testing environment—and the power supply can be configured to provide a limited amount of power (e.g., a limited amount of current drawn from it) at any given time. Some operations of the memory devices (e.g., operations associated with refresh commands, precharge commands, or activation commands, respectively) can draw a relatively larger amount of current from the power supply compared to other operations (e.g., read operations, write operations). Therefore, when multiple memory devices perform such operations simultaneously, the power supply may not be able to provide the necessary amount of current to each memory device, which may prevent the multiple memory devices from performing their operations properly—e.g., inaccurate speed testing of the memory devices, or the HBM module failing to meet power and / or speed specifications.

[0012] Several embodiments of the present invention relate to memory devices, systems including memory devices, and methods of operating memory devices, wherein the memory devices are configured to introduce variable latency for a selected set of commands. As described herein, a memory device may include a latency component that can be programmed to cause variable latency for commands to be executed at the memory device. A particular amount of latency for a command may be based on several factors, such as the operating environment (e.g., a test environment where additional memory devices and the memory device are tested in parallel, or a native environment where the memory device performs a task requested by a host device (e.g., a memory controller, a processor) together with additional memory devices), the order in which the memory device executes commands relative to other memory devices in the operating environment, the operational characteristics of the commands, the configuration of power supplies coupled to the memory device (and the additional memory devices), etc. Additionally, in some cases, the memory device may bypass (or deactivate) the latency component so as not to introduce any latency for the commands.

[0013] refer to Figure 1 A memory device supporting embodiments of the present invention is described. References Figure 2 A more detailed description of memory devices (e.g., command decoders configured to selectively add variable latency to one or more commands) is provided. Figure 3 A scheme for introducing variable latency into commands for such memory devices that involve an operating environment (e.g., a test environment, a native environment) is described. Figure 4 Various timings for such memory devices based on variable-delay command execution according to embodiments of the present invention are described. References Figure 5 A memory system supporting embodiments of the present invention is described. References Figure 6 and 7 A flowchart illustrating a method for operating a memory device is provided.

[0014] Figure 1 This is a block diagram illustrating a memory device 100 according to an embodiment of the present invention. The memory device 100 may include a memory cell array, such as a memory array 150. The memory array 150 may include a plurality of memory banks (e.g., ...). Figure 1 The memory array 150 comprises memory banks 0-15, each containing multiple word lines (WL), multiple bit lines (BL), and multiple memory cells (e.g., m×n memory cells) arranged at the intersections of word lines (e.g., m word lines, also referred to as rows) and bit lines (e.g., n bit lines, also referred to as columns). The memory cells may contain any of several different memory media types, including capacitive, phase-change, magnetoresistive, ferroelectric, etc. In some embodiments, a portion of the memory array 150 may be configured to store ECC parity bits. Selection of word lines WL may be performed by row decoder 140, and selection of bit lines BL may be performed by column decoder 145. Sensing amplifiers (SAMPs) may be provided for and connected to at least one corresponding local I / O line pair (LIOT / B) for a corresponding bit line BL, which may then be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) that can act as a switch. The memory array 150 may also include board lines and corresponding circuitry for managing its operation.

[0015] The memory device 100 may employ multiple external terminals including command and address terminals coupled to the command bus and address bus to receive command signal CMD and address signal ADDR, respectively. The memory device may further include: a chip select terminal for receiving chip select signal CS; clock terminals for receiving clock signals CK and CKF; data clock terminals for receiving data clock signals WCK and WCKF; data terminals DQ, RDQS, DBI (for data bus transposition function), and DMI (for data mask transposition function); and power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0016] Address signals and memory address signals can be supplied externally to the command and address terminals. The address signals and memory address signals supplied to the address terminals can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive address signals and supply the decoded row address signal (XADD) to the row decoder 140 (which may be called a row driver), and supply the decoded column address signal (YADD) to the column decoder 145 (which may be called a column driver). The address decoder 110 can also receive the memory address portion of the ADDR input and supply the decoded memory address signal (BADD) and the memory address signal to both the row decoder 140 and the column decoder 145.

[0017] Command signal CMD, address signal ADDR, and chip select signal CS can be supplied from the memory controller to the command and address terminals. The command signal can represent various memory commands from the memory controller (e.g., refresh command, activation command, precharge command, access command that may include read and write commands). The select signal CS can be used to select the memory device 100 to respond to commands and addresses provided to the command and address terminals. When an active CS signal is provided to the memory device 100, commands and addresses can be decoded, and memory operations can be performed. The command signal CMD can be provided as an internal command signal ICMD to the command decoder 115 via the command / address input circuit 105.

[0018] Command decoder 115 may include circuitry for decoding internal command signals ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. Other examples of memory operations that memory device 100 may perform based on decoding internal command signals ICMD include refresh commands (e.g., rebuilding full charge in individual memory cells stored in memory array 150), activation commands (e.g., activating rows in a particular memory bank for use in some cases subsequent access operations), or precharge commands (e.g., deactivating activated rows in a particular memory bank). Internal command signals may also include output and input activation commands, such as timing commands CMDCK (…). Figure 1 (Not shown in the image).

[0019] In some embodiments, the command decoder 115 may further include one or more registers 118 for tracking various counts and / or values ​​(e.g., counts of refresh commands received by the memory device 100 or counts of self-refresh operations performed by the memory device 100) and / or for storing various operating conditions of the memory device 100 to perform certain functions, features, and modes (or test modes). Therefore, in some embodiments, register 118 (or a subset of register 118) may be referred to as a mode register. For example, the memory device 100 may be placed in a test mode by programming specific bits of register 118. In some embodiments, this test mode may be used only by the manufacturer of the memory device 100, and not by the end user. Additionally, the memory device 100 may implement such a test mode in conjunction with a design-to-test (DFT) approach (or as part of said approach). In some cases, the DFT approach can facilitate efficient parallel testing of multiple memory devices in a highly parallel test environment. Additionally or alternatively, the DFT approach can mitigate the risks associated with drawing excessive current from a power supply coupled to an HBM module containing multiple memory devices. In this regard, memory device 100 may include test mode (TM) control circuitry 175, which is configured to manage various aspects of test mode operation and / or support DFT methods.

[0020] In some embodiments, the command decoder 115 may include one or more delay components 116 configured to introduce variable delays into certain selected commands—such as refresh commands, precharge commands, and activation commands. The memory device 100 may program the delay components 116 with variable delays based on operating conditions defined by a test mode (or DFT method), such that a selected set of commands can be executed after the variable delay expires.

[0021] In some cases, the manufacturer of memory device 100 may provide different delays for commands (e.g., precharge commands) to different memory devices (e.g., during parallel testing), allowing individual memory devices to execute commands at different times—e.g., interleaving commands across different memory devices 100. In some cases, memory device 100 may store a specific value for the delay for a command (e.g., refresh command) in a non-volatile memory (NVM) component 180 of memory device 100, which may include an array of fuses (or antifuses). The specific value of the delay may have been determined, for example, using test modes and / or DFT methods based on testing memory device 100 together with other memory devices—e.g., in a tester socket configured to test a group of memory devices in parallel—in order to determine the optimal value for the delay for the command. Subsequently, memory device 100 may retrieve the specific value of the delay from NVM component 180 in conjunction with TM control circuitry 175—e.g., during the initialization process of memory device 100—to program the delay component to include the delay. Therefore, memory device 100 can execute commands in an interleaved manner (e.g., multiple memory devices executing commands at different times) in the native environment (e.g., in an HBM module) based on a specific value of latency that has been determined and stored in NVM component 180.

[0022] When a read command is issued to a memory cell with open rows and the column address is supplied in a timely manner as part of the read command, read data can be read from a memory cell in memory array 150 specified by the row address (which may have been provided as part of an activation command to identify the open row) and the column address. The read command can be received by command decoder 115, which can provide internal commands to input / output circuitry 160, such that read data can be output from data terminals DQ, RDQS, DBI, and DMI via read / write amplifier 155 and input / output circuitry 160 according to the RDQS clock signal. Read data can be provided at a time defined by read delay information RL, which can be programmed in memory device 100, for example, in a mode register (e.g., register 118). The read delay information RL can be defined with respect to the clock cycles of the CK clock signal. For example, the read delay information RL can be the number of clock cycles of the CK signal after the read command is received by memory device 100 when the associated read data is provided.

[0023] When a write command is issued to a memory bank with open rows and the column address is supplied in a timely manner as part of the write command, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by a command decoder 115, which can provide an internal command to the input / output circuitry 160 so that the write data can be received by the data receiver in the input / output circuitry 160 and supplied to the memory array 150 via the input / output circuitry 160 and the read / write amplifier 155. The write data can be written to the memory cells specified by the row address and column address. The write data can be supplied to the data terminals at a time defined by write delay information WL. The write delay information WL can be programmed in the memory device 100, for example, in a mode register (e.g., register 118). The write delay information WL can be defined in terms of the clock cycles of the CK clock signal. For example, the write delay information WL can be the number of clock cycles of the CK signal after the memory device 100 receives the write command when the associated write data is received.

[0024] Power supply potentials VDD and VSS can be supplied to the power supply terminals. These power supply potentials VDD and VSS can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the line decoder 140, the internal potentials VOD and VARY can be used in the sense amplifier included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

[0025] A power supply potential VDDQ can also be supplied to the power supply terminals. The power supply potential VDDQ can be supplied together with the power supply potential VSS to the input / output circuit 160. In an embodiment of the invention, the power supply potential VDDQ can be the same potential as the power supply potential VDD. In another embodiment of the invention, the power supply potential VDDQ can be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ can be used for the input / output circuit 160 so that power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0026] External clock signals and complementary external clock signals can be supplied to the clock terminal and data clock terminal. External clock signals CK, CKF, WCK, and WCKF can be supplied to the clock input circuit 120. CK and CKF signals can be complementary, and WCK and WCKF signals can also be complementary. Complementary clock signals can simultaneously have transitions between relative clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and vice versa.

[0027] The input buffer included in clock input circuit 120 can receive external clock signals. For example, when enabled by the CKE signal from command decoder 115, the input buffer can receive CK and CKF signals as well as WCK and WCKF signals. Clock input circuit 120 can receive external clock signals to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 130. Internal clock circuit 130 can provide various phase and frequency-controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from command decoder 115. For example, internal clock circuit 130 can include a clock path that receives the internal clock signal ICLK and provides various clock signals to command decoder 115. Figure 1 (Not shown in the image). The internal clock circuit 130 can further provide input / output (I / O) clock signals. The I / O clock signals can be supplied to the input / output circuit 160 and can be used as timing signals to determine the output timing for reading data and the input timing for writing data. Multiple clock frequencies can be provided for the I / O clock signals to allow data to be output from and input to the memory device 100 at different data rates. Higher clock frequencies are desirable when high memory speed is desired. Lower clock frequencies are desirable when lower power consumption is desired. The internal clock signal ICLK can also be supplied to the timing generator 135, and thus various internal clock signals can be generated.

[0028] The memory device 100 can be connected to any of several electronic devices or components thereof capable of using the memory to temporarily or permanently store information. For example, the host device of the memory device 100 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device can be a networking device (e.g., a switch, router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of several other products. In one embodiment, the host device can be directly connected to the memory device 100, but in other embodiments, the host device can be indirectly connected to the memory device (e.g., via a network connection or through an intermediary device).

[0029] Figure 2 This is a block diagram 200 schematically illustrating a command decoder for a memory device (e.g., memory device 100) according to an embodiment of the present invention. Diagram 200 includes a command decoder 215, which may be referenced. Figure 1 The described command decoder 115 is an example of or includes aspects of the command decoder. Command decoder 215 is configured to selectively add latency to commands relating to memory devices. Command decoder 215 receives various input signals 220 (e.g., signals 220a to 220k), such as row address strobe (RAS), column address strobe (CAS), write enable (WE), and reference... Figure 1 The described CMD, ADDR, CS, CK, and CKE. In some embodiments, input signal 220 relates to a command generated by a host device (e.g., a memory module controller, test equipment) coupled to the memory device. Figure 200 also illustrates enable signals (e.g., En_1 235a, En_2 235b) coupled to command decoder 215. In some embodiments, memory device 100 provides enable signals in conjunction with test mode components (e.g., TM control circuitry 175) that manage the operation of memory device 100 in test mode. In some cases, memory device 100 provides enable signals based on operating conditions defined in a mode register (e.g., register 118).

[0030] Command decoder 215 can be configured to decode input signal 220 to identify commands involving memory devices (e.g., Command_1 225a, Command_2 225b, Command_3 225c). The decoded command can be split into two branches in command decoder 215: a first command signal without delay (e.g., Command_1_ND 225a-1) and a second command signal with delay (e.g., Command_1_YD 225a-2). That is, Command_1_ND 225a-1 bypasses delay component 230a, while Command_1_YD 225a-2 includes the delay inserted by the delay component (e.g., delay component 230a).

[0031] The delay component can be configured to delay a command (e.g., Command_1 225a) when activated by an enable signal (e.g., En_1 235a). In some embodiments, the delay component 230 may include one or more logic components arranged in series (e.g., logic gates configured to perform a logic function, such as AND, OR, XOR, etc.) such that a variable delay can be programmed into the delay component 230.

[0032] Forked command signals (e.g., no-delay commands, delayed commands) are coupled to a multiplexing component (e.g., multiplexing component 240a, which may be referred to as a multiplexer), which is configured to output one of the forked command signals (e.g., Command_1_ND 225a-1, Command_1_YD225a-2) to a command path (e.g., command path 245a) based on the state of an enable signal (e.g., En_1 235a).

[0033] For example, when a test mode is activated for a memory device (e.g., via a test program executed by a tester), delay component 230 (e.g., delay component 230a) can be programmed with a delay—e.g., via TM control circuitry 175. Additionally, in test mode, TM control circuitry 175 can activate enable signal 235 (e.g., En_1 235a). Subsequently, when the memory device receives a command relating to the memory device using input signal 220 (e.g., an input signal from the tester), command decoder 215 can decode input signal 220 to determine that input signal 220 corresponds to Command_1 (e.g., a refresh command). Delay component 230a activated by En_1 235a can delay the refresh command, which is fed to multiplexing component 240a. Therefore, multiplexing component 240a activated by En_1 235a outputs a refresh command including the delay to command path 245a for execution by the memory device. In other words, when En_1 235a is activated in test mode, the delay programmed in the delay component 230a can be added to the refresh command path 245a.

[0034] For reference Figure 4 In more detail, this delay avoids instantaneous, large current draws from the power source (e.g., the power supply of the tester, the power supply coupled to a memory module containing multiple memory devices). In some cases, when a memory device executes a command (e.g., a refresh command) before any other memory device sharing a power source—that is, the memory device is the first memory device to execute the refresh command—the delay component 230a can be programmed or deactivated with zero delay.

[0035] In some cases, the delay component 230a can be programmed with a delay when the test mode for the memory device is not activated. For example, the mode register of the memory device in the HBM module (e.g., reference...) Figure 1 The described register 118 may have been programmed to associate certain commands (e.g., refresh commands) with latency. A specific value for the latency of latency component 230a may have been determined and stored in a non-volatile memory component of the memory device (e.g., reference 118). Figure 1 The NVM component 180 described herein.

[0036] During initialization, the memory device can retrieve a specific value of the delay from the NVM component and program the delay component 230a associated with a refresh command based on a mode register indication. Additionally, an enable signal (e.g., En_1235a) can be activated, allowing the specific value of the delay in the delay component 230a to be added to the refresh command. In this way, an optimal delay can be determined for the memory device (e.g., when testing the memory device in test mode) and stored in the NVM component, and when the memory device operates in a native environment (e.g., within a memory module containing the memory device), the optimal delay can be added to certain commands (e.g., refresh commands) based on a mode register indication.

[0037] As described above, certain enable signals of the memory device (e.g., En_1 235a) can be activated based on two or more operating modes of the memory device—for example, when a test mode is activated, or when a mode register indicates that certain commands are associated with latency. In some embodiments, the memory device also includes other enable signals (e.g., En_2 235b) that can be activated based on a single operating mode of the memory device—for example, when a test mode is activated. That is, when the test mode of the memory device is activated to enable latency components 230b and 230c and multiplexing components 240b and 240c, latency can be added to certain commands (e.g., Command_2, Command_3).

[0038] For example, when a test mode is activated for a memory device, two enable signals (e.g., En_1 235a and En_2 235b) can be activated, allowing delay components 230a to 230c to be programmed with certain delays (e.g., via a test program executed by a test device). Command decoder 215 can then receive and decode input signal 220 to determine that the memory device has received one of Command_1, Command_2, and Command_3 for execution. Due to the activation of the two enable signals (e.g., En_1 235a and En_2 235b), command decoder 215 can add the delays programmed in delay components 230a, 230b, and 230c to Command_1 (e.g., a refresh command), Command_2 (e.g., an activation command), and Command_3 (e.g., a precharge command), respectively.

[0039] Conversely, when the test mode is not activated (e.g., when the memory device is operating in the memory module), En_2 235b may not be activated. Therefore, command decoder 215 may not add a delay to Command_2 (e.g., activation command) and / or Command_3 (e.g., precharge command). However, the memory device's mode register may be configured to associate Command_1 (e.g., refresh command) with a delay. Based on the mode register indication, the memory device may activate En_1 235a and retrieve a delay from the NVM component to program a delay component (e.g., delay component 230a) with the delay. When command decoder 215 receives Command_1 (e.g., refresh command), it adds the delay programmed in delay component 230a to Command_1 (e.g., refresh command).

[0040] For reference Figure 3 and 4 In more detail, the latency can be varied based on the operating environment of the memory device (therefore, it is a variable latency). In some cases, the latency may correspond to zero (i.e., no latency for the command). In some cases, the latency associated with a command (e.g., Command_1) may be different from the latency associated with other commands (e.g., Command_2 and / or Command_3). In some cases, the same latency can be added to two or more commands (e.g., Command_1, Command_2, and Command_3).

[0041] Figure 3 A block diagram 300 illustrating a scheme for introducing variable latency into commands for memory devices in a system according to embodiments of the present invention is shown. Figure 300 includes a host device 310, which may be a test apparatus configured to test multiple groups of memory devices in parallel, or a controller (e.g., a memory controller) for a memory module (e.g., a DIMM, HBM module) containing two or more memory devices. Figure 300 also illustrates memory groups 315, each containing multiple memory devices 320. For example, memory group 315a contains n memory devices 320a-0 to 320a-(n-1). In some cases, individual memory groups 315 represent respective sockets of the test apparatus configured to test multiple memory devices 320 in parallel. Memory devices may be referred to as devices under test (DUTs). In some cases, one of the memory groups 315 may represent a memory module (e.g., a DIMM, HBM module) containing multiple memory devices 320.

[0042] Individual memory device 320 may include delay component 325 (e.g., reference 325). Figure 2The memory device 100 described (description of delay component 230) is an example of or includes aspects of said memory device. For clarity of the overall features and principles of the invention, other details of the memory device 320 are omitted in Figure 300, for example, referring to... Figure 2 The described command decoder (e.g., command decoder 215) and associated components (e.g., multiplexing component 240) and signals (e.g., input signal 220, enable signal 235) are described. Additionally, each memory group 315 is coupled to a power supply 335, which supplies current (and / or voltage) to the memory devices 320 within each memory group 315. For example, memory group 315a is coupled to power supply 335a such that individual memory devices 320a within memory group 315a are connected to power supply 335a.

[0043] In highly parallel testing environments, one or more test resources can be shared among multiple DUTs to increase the number of DUTs being tested in parallel. Such test resources may include clock pins and / or corresponding channels, command / address (C / A) pins and / or corresponding channels, etc. Figure 300 illustrates one or more channels 330 shared by two or more memory groups 315. For example, a set of C / A signals generated by the host device 310 may be shared with memory groups 315a to 315j via channel 330. Additionally, the set of C / A signals can be simultaneously supplied to all DUTs within memory group 315—for example, DUTs 320a-0 to 320a-(n-1) within memory group 315a simultaneously receive the set of C / A signals.

[0044] Therefore, in the absence of delay component 325 (or a variable delay programmed therein), individual DUTs in the memory group (e.g., memory group 315a) simultaneously execute commands (e.g., activation commands) contained in the C / A signal set. In some embodiments, individual power supplies 335 may not be able to supply the total current required for the n DUTs in the corresponding memory group 315, which simultaneously execute commands (e.g., activation commands). Consequently, suboptimal or inaccurate testing of the n DUTs may result—for example, test errors due to unmet timing requirements, thereby unnecessarily reducing DUT yield by identifying one or more good DUTs as faulty. In some cases, it may be necessary to reduce the number of DUTs 320 within the memory group 315 to alleviate problems associated with instantaneous, high-current (or power) requirements.

[0045] The present invention mitigates such problems by introducing variable delays into commands arriving simultaneously at individual DUTs 320. Each DUT 320 includes one or more delay components 325, which can be programmed to produce variable delays for commands when a test mode is activated. In this way, the execution of commands by the DUTs 320 in the memory group 315 can be staggered in time—for example, one or more DUTs 320 execute commands at different times than other DUTs 320. For example, a host device 310 (e.g., a tester in a highly parallel test environment or a test program run by the tester) can activate (e.g., latch) a test mode of a DUT 320, such that an individual DUT 320 can activate an enable signal (e.g., En_1 235a, En_2 235b). Additionally, the host device 310 (or the DUT 320 in conjunction with the host device 310) can program the delay component 325 in each DUT to have different delays for commands—for example, programming the delay component 325a-0 with delay Δ0, programming the delay component 325a-1 with delay Δ1, programming the delay component 325a-2 with delay Δ2, etc.

[0046] In this way, when DUTs 320 in memory group 315 (e.g., memory group 315a) simultaneously receive commands (e.g., precharge commands), individual DUTs 320 can execute the commands (e.g., precharge commands) at different times according to delays programmed in delay component 325. Therefore, individual DUTs can draw the necessary amount of current from a common power source (e.g., power source 335a) at different times, such that the total current required by the common power source to supply to the DUTs 320 at any given time remains within the limitations of the common power source.

[0047] Referring again to Figure 300, when the memory device 320 is assembled into a memory module (e.g., a DIMM, HBM module), the present invention can also utilize the delay component 325 to implement variable delays for commands relating to the memory device 320. For example, a memory group (e.g., memory group 315a) may correspond to an HBM module containing a plurality of memory devices 320a (e.g., memory devices 320a-0 to 320a-(n-1)). Additionally, the host device 310 may be a memory controller or processor coupled to the HBM module (e.g., memory group 315a). Each individual memory device 320a of the HBM module includes a delay component 325 and an NVM component configured to store the delay of the delay component 325.

[0048] In some cases, the latency of memory device 320 can be determined during testing of memory device 320. In other cases, the latency can be determined based on the configuration of the HBM module—e.g., the amount of memory devices 320 in the HBM module, the sequence of memory devices 320 executing commands within the HBM module. Additionally, the mode register of memory device 320 can be programmed to indicate that commands are associated with latency. During the initialization of memory device 320 (e.g., when the HBM module is powered on), individual memory device 320 can activate an enable signal (e.g., En_1235a) based on an instruction programmed in the mode register. Furthermore, each individual memory device 320 can retrieve the corresponding latency for a command from its NVM component to program the latency component 325 to include the corresponding latency.

[0049] When memory devices 320 in the HBM module simultaneously receive a set of C / A signals from a memory controller (e.g., host device 310) via channel 330, memory devices 320 can decode commands (e.g., refresh commands) from the set of C / A signals and determine the associated delay based on mode register indications. Therefore, individual memory devices 320 (or some memory devices 320 in memory group 315) can execute commands (e.g., refresh commands) at different times based on delays programmed into the delay component 325—for example, executing commands interleaved across different memory devices 320 in their native environment (within the HBM module).

[0050] In some embodiments, the memory device 320 may operate in a mode in which one or more commands involving the memory device 320 (e.g., refresh command, precharge command, activation command) are associated with latency. The memory device 320 may determine the set of signals received at the memory device 320 from the host device (e.g., references...). Figure 2 The described signal 220 contains at least one of such commands. Subsequently, the memory device 320 may execute the command after a delay based on the mode (i.e., the mode in which one or more commands are associated with the delay). In some embodiments, the memory device 320 may set a mode register (e.g., register 118, register 507) to indicate the mode. Additionally, the memory device 320 may delay-program a delay component (e.g., delay component 230, delay component 325) such that the delay component can hold the command unexecuted until the delay expires.

[0051] Figure 4 A timing diagram 400 illustrating a scheme for introducing variable latency into commands of a memory device in a system according to an embodiment of the present invention is shown. Figure 400 depicts a reference... Figure 3 The diagram 300 describes various signals and / or activities of the memory device 320. Diagram 400 includes a waveform 410 corresponding to a command received at a memory group (e.g., memory group 315a) comprising multiple memory devices (e.g., memory device 320a). In some cases, waveform 410 may represent a voltage coupled to a C / A pin of memory group 315 when a set of C / A signals arrives at memory group 315 via channel 330, the C / A pin being connected to the multiple memory devices 320.

[0052] Figure 400 also illustrates waveforms 415 (e.g., waveforms 415a-0 to 415a-(n-1)) associated with corresponding memory devices (e.g., the DUT in memory group 315a or memory devices 320a-0 to 320a-(n-1)). Waveform 415 symbolically represents a period of time during which the corresponding memory device can perform various operations associated with a command, and may not correspond to any specific voltage or current level of a particular pin of memory device 320. For example, an upward transition in waveform 415 may indicate that the memory device initiates a first operation in response to receiving a command, and a downward transition in waveform 415 may indicate that the memory device completes the final operation associated with the command. That is, the duration between the upward and downward transitions in waveform 415 may correspond to a period of time during which memory device 320 is active to execute commands.

[0053] Additionally, Figure 400 depicts waveforms 420 (e.g., waveforms 420a-0 to 420a-(n-1)) associated with a corresponding memory device (e.g., memory devices 320a-1 to 320a-(n-1)). In some cases, waveform 420 corresponds to the amount of current drawn by memory device 320 from a common power source (e.g., power supply 335) while executing a command. Waveform 415 includes a peak current I (e.g., peak current I0 to I...). n-1 This may occur during one or more stages of executing a command. For example, an activation command may require the memory device 320 to bring the voltage of the word lines of the memory array to a target value. In some cases, word lines may be coupled to a large number of memory cells (e.g., 1,024 memory cells) and extend over a considerable distance. Therefore, in some cases, the voltage increase of the word lines may cause a peak current I drawn from the power supply due to the inherent and / or parasitic capacitances associated with the word lines. Once the word lines establish the target voltage value, the memory device 320 can proceed to subsequent stages of the activation command, which may not draw as much current as the peak current I.

[0054] Figure 400 illustrates the variable delay (e.g., Δ0 to Δ) added to the command when the individual memory device 320 executes the command. n-1 The variable delay can be designed so that the peak current I required by the individual memory device 320 can be distributed in a timely manner. In this way, problems associated with power supply limitations (e.g., the inability of power supply 335a to supply instantaneous, large currents) can be mitigated.

[0055] For example, waveform 415a-0 may represent memory device 320a-0 initiating operation without delay when it receives a command (e.g., an activation command) at time T0—e.g., a Δ0 corresponding to zero relative to T0. Thereafter, a peak current I0 appears after T0, as indicated in waveform 420a-0. In this respect, memory device 320a-0 may be the first memory device to execute a command (e.g., an activation command) before any other memory device (e.g., memory devices 320a-1 to 320a-(n-1)). In some cases, when the memory device is one of the memory devices in a memory group that executes a command before other memory devices in the memory group, a delay component of the memory device may be deactivated to prevent delay (e.g., equivalent to having a Δ0 corresponding to zero).

[0056] Similarly, waveform 415a-1 can represent memory device 320a-1 starting operation at time T1 after a delay relative to time T0 (e.g., Δ1 corresponding to a duration greater than zero) – for example, Δ1 corresponding to a non-zero value relative to T0. Thereafter, peak current I1 appears after T1, as indicated in waveform 420a-1. That is, memory device 320a-1 executes a command after the elapsed duration (e.g., the duration corresponding to the delay Δ1). In this way, commands (e.g., activation commands) can be interleaved (e.g., distributed) in time by introducing variable delays into the commands, such that the power supply may not need to support the two or more peak currents required by the two or more memory devices 320 at any given time when executing a command (e.g., activation command).

[0057] As described herein, a host device may provide a variable latency to memory device 320 for certain commands (e.g., activation command, precharge command, refresh command), such that individual memory devices 320 can then program corresponding latency components 325 according to the variable latency for said command. For example, a test device in a parallel test environment may activate a test mode for memory devices 320a of memory group 310a and provide a variable latency for a command (e.g., activation command)—e.g., Δ0 corresponding to 0 nsec, Δ1 corresponding to 25 nsec, Δ2 corresponding to 50 nsec, etc.—so that memory devices 320a can be programmed accordingly with corresponding latency components 325a. Subsequently, when memory group 315a receives a command (e.g., an activation command) at time T0, memory device 320a-0 executes the command without delay (e.g., Δ0 corresponding to 0 nsec), memory device 320a-1 executes the command 25 nsec after T0 (e.g., Δ1 corresponding to 25 nsec), and memory device 320a-2 executes the command 50 nsec after T0 (e.g., Δ2 corresponding to 50 nsec).

[0058] As described herein, variable delays for certain commands (e.g., refresh commands) may be stored in the NVM component (e.g., NVM component 180) of the memory device 320 (e.g., DIMM and / or HBM modules delivered to the end user). Additionally, a mode register (e.g., register 118) of the memory device 320 may be configured to indicate that a command is associated with a variable delay stored in the NVM component—that is, the memory device 320 may store an operating mode for certain commands. Therefore, in some cases, the memory device 320 may program a corresponding delay component (e.g., delay component 230a configured to generate a delay for refresh commands) based on the variable delays stored in its NVM component—for example, as part of the initialization process of the memory device 320.

[0059] For example, memory device 320a-0 may be programmed to execute one of such commands (e.g., refresh commands) without any delay (e.g., Δ0 corresponding to 0 nsec) based on a variable delay stored in its NVM component; memory device 320a-1 may be programmed to execute the command after 25 nsec (e.g., Δ1 corresponding to 25 nsec); memory device 320a-2 may be programmed to execute the command after 50 nsec (e.g., Δ2 corresponding to 50 nsec); and so on. In this way, when a memory controller for a memory module (which may be unaware of the variable delay programmed in the delay component) issues one of such commands (e.g., refresh commands) to the memory module, individual memory devices in the memory module execute the command (e.g., refresh command) based on the corresponding variable delay programmed in the delay component—for example, memory device 320a-1 executes the refresh command 25 nsec after receiving the command (e.g., Δ1 corresponding to 25 nsec), memory device 320a-2 executes the refresh command 50 nsec after receiving the command (e.g., Δ2 corresponding to 50 nsec), and so on.

[0060] The variable delay can be determined based on several factors, such as the current delivery capability of the power supply 335 coupled to the memory group 315 containing multiple memory devices 320, the timing and / or magnitude of the peak current that may occur for different commands, the nature of the commands that may or may not allow the introduction of delay, and so on. For example, when the power supply is able to provide the sum of three (3) peak currents for a command (e.g., a precharge command) at any given time, a group of three (3) delays can be implemented—for example, the first group of three (3) memory devices executes the precharge command with Δ0 corresponding to 0 nsec, the second group of three (3) memory devices executes the precharge command with Δ1 corresponding to 25 nsec, and so on. In such instances, a specific number of memory devices with the same delay in the first and / or second groups can differ based on the magnitude of the peak current of the command—for example, the activation command may contain a larger peak current than the precharge command, which may require reducing the number of memory devices in each group (e.g., two (2) memory devices instead of three (3)).

[0061] In some cases, the latency may differ for different commands. For example, a precharge command may trigger a sequence of Δ0 corresponding to 0 nsec, Δ1 corresponding to 25 nsec, Δ2 corresponding to 50 nsec, etc., while a refresh command (which may include a peak current occurring at a later timing than the precharge command) may trigger a different latency sequence, such as Δ0 corresponding to 0 nsec, Δ1 corresponding to 40 nsec, Δ2 corresponding to 80 nsec, etc. Alternatively, some commands may be configured to include variable latency in both the test environment and the end-user environment (e.g., a refresh command for which the memory device 320 may have some flexibility regarding when to execute the refresh command based on the history of previous refresh commands). In contrast, some commands may only include variable latency in the test environment (e.g., activation commands and / or precharge commands typically preceding read and / or write commands), because the memory device needs to meet certain speed and / or bandwidth requirements expected by the host device.

[0062] Several embodiments of the present invention relate to adding variable latency to certain commands involving a memory device, but the present invention is not limited thereto. For example, Figure 3 The DUT described herein may include other types of semiconductor devices, such as processors, microcontrollers, application-specific integrated circuits (ASICs), etc. Additionally, Figure 2 Delay components associated with commands (e.g., delay component 230a associated with Command_1225a, delay component 230b associated with Command_225b, etc.) are described, but in some embodiments, delay components may be configured to add delays to two or more commands.

[0063] Figure 5 This is a block diagram of a system 501 having one or more memory devices 500 configured according to embodiments of the present invention. The memory device 500 may be a reference. Figure 1 The described memory device 100 may be an example or include aspects of the memory device. As shown, the memory device 500 includes a main memory 502 (e.g., DRAM, NAND flash, NOR flash, FeRAM, PCM, etc.) and a control circuitry 506 operatively coupled to a host device 508 (e.g., an upstream central processing unit (CPU)). The main memory 502 may be a reference. Figure 1 The described memory array 150 is an example of or includes aspects of said memory array. Additionally, the control circuitry 506 includes references. Figure 1 The various components described herein. For example, control circuit system 506 may include aspects such as command / address input circuitry 105, command decoder 115, and TM control circuitry 175.

[0064] Main memory 502 includes a plurality of memory cells 520, each containing a plurality of memory information cells. Memory cells 520 may be individual memory dies, memory planes within a single memory die, stacks of memory dies vertically connected by through-silicon vias (TSVs), etc. For example, in one embodiment, each of the memory cells 520 may be formed from a semiconductor die and arranged in a single device package with other memory cell dies. In other embodiments, the plurality of memory cells 520 may be juxtaposed on a single die and / or distributed across multiple device packages. In some embodiments, memory cells 520 may also be subdivided into memory regions 528 (e.g., memory banks, memory rows, channels, blocks, pages, etc.).

[0065] Memory cells may include, for example, floating gates, charge traps, phase-change, capacitive, ferroelectric, magnetoresistive, and / or other suitable storage elements configured to permanently or semi-permanently store data. Main memory 502 and / or individual memory cells 520 may also include other circuit components, such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / data input registers, etc., for accessing and / or programming (e.g., writing) memory cells and other functions, such as processing information and / or communicating with control circuitry 506 or host device 508. Although a certain number of memory cells, rows, columns, areas, and memory cells are shown in the illustrated embodiments for illustrative purposes, the number of memory cells, rows, columns, areas, and memory cells may vary, and in other embodiments, may be larger or smaller in scale than shown in the illustrated examples. For example, in some embodiments, memory device 500 may include only one memory cell 520. Alternatively, the memory device 500 may include two, three, four, eight, ten, or more (e.g., 16, 32, 64, or more) memory cells 520. Although the memory cells 520 are... Figure 5 The diagram shows each memory cell 520 containing four memory regions 528, but in other embodiments, each memory cell 520 may contain one, two, three, eight or more (e.g., 16, 32, 64, 100, 128, 256 or more) memory regions.

[0066] In some embodiments, memory device 500 may include register 507 (which may also be referred to as a mode register), which may be configured to store operating modes relating to commands of main memory 502. Register 507 may be a reference Figure 1The described register 118 may be an instance or include aspects of the register. The operating mode may indicate that a command is associated with a delay—for example, a refresh command associated with a delay Δ2. In some cases, register 507 may be set (e.g., by programming one or more bits of register 507) to indicate that a delay can be added to a command, such that the command can be executed after the delay. In some embodiments, memory device 500 may also include a delay component 515, which may be referenced... Figure 2 and 3 The described delay component 230 and / or delay component 325 may be instances of or include aspects of the delay components. Delay component 515 may be configured to prevent command execution until the delay expires. Therefore, the operational mode for storing commands may be based on programming delay component 515 to include a delay.

[0067] In some embodiments, the memory device 500 may further include an NVM component 516, which may be an instance of the NVM component 180 or include aspects of the NVM component. In some cases, the NVM component includes a fuse (or antifuse) array configured to store various information for the memory device 500 when the memory device 500 is disconnected from power. In some cases, the delay may be stored in the NVM component 516. The memory device 500 (in conjunction 506) may retrieve the delay from the NVM component 516 based on the operating mode of a command, such that the memory device 500 can program the delay component 325 with the delay. Subsequently, when the memory device 500 receives a command, the memory device 500 may execute the command after the delay already programmed in the delay component 325 has expired.

[0068] In some embodiments, the memory device 500 may be a set of memory devices of a multi-chip module (e.g., an HBM module). Figure 5 (Not shown in the image). In some cases, when memory device 500 executes a command after one or more memory devices in a set of memory devices, the delay may be a duration greater than zero (e.g., 25 nsec, 50 nsec, 75 nsec, etc.). In some cases, the delay may differ from another delay stored in at least one memory device in a set of memory devices—for example, commands are executed in time-interleaved between memory devices in a set of memory devices. In some cases, when memory device executes a command before other memory devices in a set of memory devices, the delay may correspond to zero (e.g., no delay). Additionally, when memory device executes a command before other memory devices in a set of memory devices, the delay component 515 may be deactivated so that no delay can be added to the command.

[0069] In one embodiment, the control circuitry 506 may be located on the same die as the main memory 502 (e.g., including command / address / clock input circuitry, decoders, voltage and timing generators, input / output circuitry, etc.). In another embodiment, the control circuitry 506 may be a microcontroller, a special-purpose logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a control circuitry on the memory die, etc.), or other suitable processor. In one embodiment, the control circuitry 506 may include a processor configured to execute instructions stored in memory to perform various processes, logic flows, and routines for controlling the operation of the memory device 500, including managing the main memory 502 and handling communication between the memory device 500 and the host device 508. In some embodiments, the control circuitry 506 may include embedded memory having memory registers for storing, for example, row counters, bank counters, memory pointers, fetched data, etc. In another embodiment of the invention, the memory device 500 may not include a control circuit system and may actually rely on external control (e.g., provided by the host device 508 or by a processor or controller separate from the memory device 500).

[0070] Host device 508 can be any of several electronic devices or components thereof capable of using memory for temporary or permanent storage of information. For example, host device 508 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). Host device 508 can be a networking device (e.g., a switch, router, etc.) or a recorder of digital images, audio and / or video, a vehicle, an appliance, a toy, or any of several other products. In one embodiment, host device 508 may be directly connected to memory device 500, but in other embodiments, host device 508 may be indirectly connected to memory device (e.g., via a network connection or through an intermediary device).

[0071] In operation, the control circuitry 506 can directly write to or otherwise program (e.g., erase) various memory areas of the main memory 502. The control circuitry 506 communicates with the host device 508 via a host device bus or interface 510. In some embodiments, the host device 508 and the control circuitry 506 can communicate via a dedicated memory bus (e.g., a DRAM bus). In other embodiments, the host device 508 and the control circuitry 506 can communicate via a serial interface, such as a serially attached SCSI (SAS), a serial AT accessory (SATA) interface, a peripheral component interconnect high speed (PCIe), or other suitable interfaces (e.g., a parallel interface). The host device 508 can send various requests (in the form of, for example, packets or packet streams) to the control circuitry 506. Requests may include commands to read, write, erase, return information, and / or perform specific operations (e.g., refresh operations, trim operations, precharge operations, activation operations, wear leveling operations, garbage collection operations, etc.). In some cases, a set of signals (e.g., signals from the command / address (C / A) pin and / or the corresponding channel) can be used to transmit this command, and the control circuitry 506 can decode the set of signals (e.g., using command decoder 115 or 215) to determine which command the memory device 500 has received.

[0072] Figure 6 This is a flowchart 600 illustrating a method for operating a memory device according to an embodiment of the present invention. Flowchart 600 may be as shown in the reference... Figures 1 to 5 Examples of methods that can be performed by the described memory device 100 (e.g., command / address input circuitry 105, command decoder 115, TM control circuitry 175, or combinations thereof) and / or memory device 500 (e.g., control circuitry system 506 of memory device 500) or include aspects of the methods.

[0073] The method includes receiving a duration associated with a command relating to a memory device from a host device (block 610). According to one aspect of the invention, this can be achieved by referring to... Figure 1 and 5 The described control circuit system (e.g., Figure 5 Control circuit system 506) or command / address input circuit ( Figure 5 The command / address input circuit 105) executes the receiving feature of block 610.

[0074] The method further includes programming a delay component of the memory device using a duration, wherein the delay component is configured to retain no command during the duration in which the programming is performed (block 615). According to one aspect of the invention, it can be achieved by referring to... Figure 1 and 5The described control circuit system (e.g., Figure 5 Control circuit system 506) or command decoder ( Figure 1 Command decoder 115) and / or test mode control circuitry (e.g., Figure 1 The test mode control circuit 175) executes the programming features of block 615.

[0075] The method further includes receiving a command from the host device after programming the delay component using a duration (block 620). According to one aspect of the invention, it can be achieved by referring to... Figure 1 and 5 The described control circuit system (e.g., Figure 5 Control circuit system 506) or command / address input circuit ( Figure 5 The command / address input circuit 105) executes the receiving feature of block 620.

[0076] The method further includes executing a command at the memory device after the duration has elapsed (block 625). According to one aspect of the invention, in some cases, it may be achieved by, as referenced... Figure 1 and 5 The described control circuit system (e.g., Figure 5 Control circuit system 506) or command decoder ( Figure 1 Command decoder 115) combined Figure 1 The address decoder 110 and / or line decoder 140 execute the execution features of box 625.

[0077] In some embodiments, a group of memory devices includes memory devices, and individual memory devices in the group of memory devices are coupled to a common power source (e.g., Figure 3 The power supply 335) is configured to receive commands simultaneously. In some embodiments, the method may further include deactivating a delay component when the memory device is one of a set of memory devices that executes a command before other memory devices in the set of memory devices. In some embodiments, the duration differs from one or more durations associated with a command relating to one or more other memory devices in the set of memory devices. In some embodiments, the delay components of individual memory devices in the set of memory devices are programmed with corresponding durations that are different from each other, wherein the corresponding durations relate to the command.

[0078] Figure 7 This is a flowchart 700 illustrating a method for operating a memory device according to an embodiment of the present invention. Flowchart 700 may be as shown in the reference... Figures 1 to 5Examples of methods that can be performed by the described memory device 100 (e.g., command / address input circuitry 105, command decoder 115, TM control circuitry 175, or combinations thereof) and / or memory device 500 (e.g., control circuitry system 506 of memory device 500) or include aspects of the methods.

[0079] The method includes operating the memory device (block 710) in a mode where one or more commands relating to the memory device are associated with latency. According to one aspect of the invention, it can be achieved by referring to... Figure 1 and 5 The described control circuit system (e.g., Figure 5 The control circuit system 506) or command decoder (e.g., Figure 1 Command decoder 115 Figure 2 Command decoder 215) and / or test mode control circuitry (e.g., Figure 1 The test mode control circuit 175) executes the operation features of block 710.

[0080] The method further includes determining that the set of signals received from the host device at the memory device contains at least one of the commands (block 715). According to one aspect of the invention, it can be achieved by referring to... Figure 1 and 5 The described control circuit system (e.g., Figure 5 The control circuit system 506) or command decoder (e.g., Figure 1 Command decoder 115 Figure 2 The command decoder 215) executes the determination feature of box 715.

[0081] The method further comprises executing commands at the memory device after a delay, at least in part, based on operating the memory device in one or more command-delay-associated modes (block 720). According to one aspect of the invention, in some cases, it may be achieved by, as referenced... Figure 1 and 5 The described control circuit system (e.g., Figure 5 The control circuit system 506) or command decoder (e.g., Figure 1 Command decoder 115 Figure 2 Command decoder 215) combined Figure 1 The address decoder 110 and / or line decoder 140 execute the execution features of the execution box 720.

[0082] In some embodiments, the method may further include setting a mode register of the memory device to indicate a mode in which one or more commands are associated with a delay. In some embodiments, the method may further include programming a delay component of the memory device with a delay, the delay component being configured to keep a command from being executed until the delay expires. In some embodiments, the memory device is included in a set of memory devices of a multi-chip module, and the delay corresponds to a duration greater than zero when the memory device executes a command after one or more memory devices in the set of memory devices executing the command. In some embodiments, the memory device is included in a set of memory devices of a multi-chip module, and the delay is different from another delay stored in at least one memory device in the set of memory devices.

[0083] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the methods described can be combined.

[0084] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0085] The devices containing memory devices discussed herein can be formed on semiconductor substrates or dies such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0086] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be physically located in various locations, including distributions such that portions of the functionality are implemented in different physical locations.

[0087] As used herein and contained in the claims, the word "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list of inclusion, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Similarly, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0088] As should be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details have been set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the invention. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the technology. Generally, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are within the scope of the invention.

Claims

1. A semiconductor memory device, comprising: Memory array; A first delay component stores a first delay and is configured to generate the first delay in response to a first command involving the memory array; as well as Peripheral circuitry coupled to the memory array and the first delay component, the peripheral circuitry being configured to: Receive the first command from the host device; Determine whether the test mode of the semiconductor memory device is activated or deactivated; as well as The first delay component is enabled when the test mode is activated and bypassed when the test mode is deactivated, wherein enabling the first delay component includes activating an enable signal that enables the first delay component configured to have the first delay and causes the multiplexer to select between a non-delayed version of a command that bypasses the first delay component and a delayed version of the command output by the first delay component, and wherein the first delay is different from a second delay configured at a second delay component in a second semiconductor memory device coupled to the same power supply.

2. The semiconductor memory device of claim 1, wherein when the test mode is activated, the peripheral circuit executes the first command after the first delay stored in the first delay component expires.

3. The semiconductor memory device of claim 1, wherein when the test mode is deactivated, the peripheral circuit executes the first command without delay.

4. The semiconductor memory device of claim 1, wherein the first delay component comprises one or more logic components arranged in series.

5. The semiconductor memory device of claim 1, wherein the first command corresponds to a precharge command, an activation command, or a refresh command.

6. The semiconductor memory device according to claim 1, further comprising: A third delay component is configured to store the first delay or the second delay, and is configured to generate the first delay or the second delay in response to a second command relating to the memory array, wherein the second delay is stored in a non-volatile memory component of the semiconductor memory device.

7. The semiconductor memory device of claim 6, wherein the peripheral circuitry is further configured to: When the test mode is deactivated, determine whether the second command is associated with the second delay; and The second delay component is activated when the second command is associated with the second delay, and bypassed when the second command is not associated with the second delay.

8. The semiconductor memory device of claim 7, wherein when the test mode is deactivated and the second command is associated with the second delay, the peripheral circuitry executes the second command after the second delay expires.

9. The semiconductor memory device of claim 7, wherein when the test mode is deactivated and the second command is not associated with the second delay, the peripheral circuitry executes the second command without delay.

10. The semiconductor memory device of claim 6, wherein the second command corresponds to a refresh command.

11. A method of operating a memory device, comprising: The duration for receiving commands associated with the memory device from the host device; The delay component of the memory device is programmed using a delay equal to the duration. The command is received from the host device after the delay component has been programmed using the delay. The delay component is enabled when the mode of the memory device is activated, and bypassed when the mode of the memory device is deactivated. Enabling the delay component includes activating an enable signal that enables the delay component and causes a multiplexer to select between a non-delayed version of the command bypassing the delay component and a delayed version of the command output by the delay component. The delay is different from a second delay programmed at a second delay component in a second memory device, which is coupled to a common power supply with the memory device. The command is executed at the memory device after the duration has elapsed, at least in part based on the activation of the delay component.

12. The method of claim 11, wherein a plurality of memory devices include the memory devices, and wherein individual memory devices of the plurality of memory devices are coupled to the common power supply and configured to simultaneously receive the command.

13. The method of claim 12, further comprising: The delay component is deactivated when the memory device is one of the plurality of memory devices that executes the command before other memory devices among the plurality of memory devices.

14. The method of claim 12, wherein the duration is different from one or more durations associated with the command relating to one or more other memory devices among the plurality of memory devices.

15. The method of claim 12, wherein delay components of individual memory devices among the plurality of memory devices are programmed using corresponding durations that differ from each other, the corresponding durations relating to the command.

16. A method of operating a memory device, comprising: The memory device is operated in a mode in which commands relating to the memory device are associated with latency; Determine that the set of signals received from the host device at the memory device contains the command; The delay component is enabled when the mode of the memory device is activated, and bypassed when the mode of the memory device is deactivated. Enabling the delay component includes activating an enable signal that enables the delay component configured to have the delay, and causes a multiplexer to select between a non-delayed version of the command bypassing the delay component and a delayed version of the command output by the delay component. The delay is different from a second delay programmed at a second delay component in a second memory device, which is coupled to a common power supply with the memory device. The command is executed at the memory device after the delay, at least in part, based on the activation of the delay component.

17. The method of claim 16, further comprising: The mode register of the memory device is set to indicate the mode in which the command is associated with the latency.

18. The method of claim 16, further comprising: The delay component of the memory device is programmed using the delay, and the delay component is configured to keep the command from being executed until the delay expires.

19. The method of claim 16, wherein the memory device is included in a plurality of memory devices of a multi-chip module, and wherein when the memory device executes the command after one or more of the plurality of memory devices executing the command, the delay corresponds to a duration greater than zero.

20. The method of claim 16, wherein the memory device is included in a plurality of memory devices of a multi-chip module.

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