A multiple-input computing unit based on split-gate flash transistor and a computing method thereof

Abstract

The application discloses a multi-input computing unit based on a split-gate flash transistor and a computing method thereof, and belongs to the technical field of integrated circuits.The application realizes the multiplication of a storage variable and three input variables based on a single split-gate flash transistor, and realizes the mapping of a network core algorithm based on a complementary device array.Compared with a traditional neural network hardware which realizes nonlinear transformation by using a neuron activation circuit, the application realizes nonlinear transformation by using the intrinsic nonlinearity of a device, thereby effectively reducing the design complexity and optimizing the area and power consumption of a system peripheral circuit.In addition, the application realizes complex matrix-vector operation by using a mature memory structure, and has important significance for the design of a high-performance artificial intelligence computing system.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor, artificial intelligence and complementary metal-oxide-semiconductor (CMOS) hybrid integrated circuit, and particularly relates to a multi-input computing unit based on a split-gate flash transistor and a computing method thereof. BACKGROUND

[0002] With the popularity of mobile terminal devices, the ability of human beings to obtain information has been greatly improved in the twenty-first century. Timely storage and rapid processing of massive information bring new challenges to electronic computing systems. Existing computer systems mainly follow the von Neumann computing mode, that is, data stored in the memory is transported to the arithmetic unit for calculation by using a bus system, and the returned results are sent back to the memory after the calculation is completed. This computing mode has very high requirements for the bus bandwidth, and the data transmission speed often becomes the speed bottleneck of the computing system, that is, the so-called "memory wall" problem. This problem is particularly evident when the system performs a large number of repeated data calculations, and there are often a large number of matrix-vector multiplication operations in neural network algorithms. Therefore, the traditional von Neumann computing system is difficult to efficiently complete neural network computation.

[0003] The storage-computing integrated system based on the new device uses the device eigen equation to perform multiplication calculation, can realize in-memory computing, and can alleviate the "memory wall" problem to a certain extent. However, this type of scheme also has certain deficiencies. On the one hand, the computing unit based on the two-terminal linear device array can only realize linear transformation of data, and the nonlinear activation function still needs to be completed by external circuits or other types of devices. This not only increases the area of the entire system, but also increases the design and manufacturing difficulty of the system. On the other hand, the computing unit based on the two-terminal device can only realize simple two-variable multiplication operation, and cannot realize multi-variable multiplication calculation, limiting the use of the array. For some computing tasks that require matrix multiplication with multiple vectors, the two-terminal device array will be difficult to complete. SUMMARY

[0004] To realize the computing task of matrix multiplication with multiple vectors and reduce the hardware overhead generated by external functional circuits, the application provides a multi-input computing unit based on a split-gate flash transistor and a computing method thereof.

[0005] The application can complete multi-element multiplication operation through the device eigen equation, can realize multiplication calculation of the storage matrix with multiple vectors, and finally realize nonlinear transformation from input to output. This scheme not only eliminates the additional nonlinear activation circuit between layers, reduces the complexity of system design, but also realizes multiplication operation of the storage matrix with multiple signal vectors, and expands the application scenario of the computing unit.

[0006] To solve the above technical problems, the technical solutions adopted by the present application are as follows:

[0007] A multi-input operation unit based on a split gate flash transistor array, in which the drain electrodes of split gate flash transistors in the same column are connected by a bit line (BL); the selection gate and the coupling gate of split gate flash transistors in the same row are connected by a word line (WL) and a coupling line (CL), respectively; and the source electrodes of split gate flash transistors are connected by a source line (SL), so that a single split gate flash transistor can complete the calculation of the multi-element product of its stored information (w FG ij ) and three input information (V WL j , V CL j , and V BL i ), and the writing and reading of the split gate transistor are completed by a coupling gate (CG) and a selection gate (SG).

[0008] A method for implementing matrix-multiple vector multiplication operation based on a split gate flash transistor array, characterized in that the current is summed up at the source line to implement current summation operation, and the operation matrix is as follows:

[0009] I SL = W FG V BL ⊙V CL ⊙V WL

[0010] Wherein, the storage matrix W FG of the split gate flash transistor array first performs inner product with the input vector V BL , and the obtained result is then subjected to element product with two input vectors V CL and V WL , so as to finally obtain the current vector I SL of the source line.

[0011] Taking a dendritic network as an example, I SL , W FG , V BL , and V WL are subjected to element product with A i+1 , W, and A iWhen A0 is one-to-one mapped, the operation of the single-layer dendritic network can be realized. When multiple arrays are cascaded through the interface circuit, the entire network can be mapped to hardware to accelerate its operation. The positive and negative weights in the dendritic network are realized by complementary split-gate flash transistor arrays. The positive weight array and the negative weight array share the input and obtain source line currents I SL + and I SL - The final source line current I SL is obtained by subtracting the two. Through the mode of complementary array current subtraction, the positive and negative weight arrays will cancel each other out between the first phase and zero term components in the device current.

[0012] The present application realizes the multi-element multiplication of a storage variable and three input variables based on a single split-gate flash transistor, and realizes the mapping of the core algorithm of the network based on complementary device arrays. Compared with the traditional neural network hardware that realizes nonlinear transformation by using neuron activation circuit, the present application realizes nonlinear transformation by using the intrinsic nonlinearity of the device, effectively reducing the design complexity and optimizing the area and power consumption of the system peripheral circuit. In addition, the present application realizes complex matrix-vector operation by using mature memory structure, which is of great significance to the design of high-performance artificial intelligence computing system. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 The split-gate transistor of the specific embodiment of the present application changes its storage information w FG to adjust the transconductance. (a) is the influence of the device storage state (floating gate charge) on the select gate transfer curve; (b) is the influence of the device storage state on the select gate transconductance. When the device changes from state 0 to state 7, the select gate transconductance gradually decreases.

[0014] Figure 2 The split-gate transistor of the specific embodiment of the present application changes its drain voltage V ds to adjust the transconductance. (a) is the influence of the device source-drain voltage (V ds ) on the select gate transfer curve; (b) is the influence of the device source-drain voltage on the select gate transconductance. When the device source-drain voltage increases from V ds0 to V ds7 , the select gate transconductance gradually increases.

[0015] Figure 3 The split-gate transistor of the specific embodiment of the present application changes its coupling gate voltage V CG to adjust the transconductance. (a) is the influence of the device coupling gate voltage (V CG ) on the select gate transfer curve; (b) is the influence of the device coupling gate voltage on the select gate transconductance. When the device coupling gate voltage increases from V CG0V CG7 The select gate transconductance gradually increases.

[0016] Figure 4 A separate gate flash transistor array structure of an embodiment of the present application;

[0017] Figure 5 A matrix-vector operation schematic diagram of positive and negative weights realized by a complementary device array of an embodiment of the present application;

[0018] Figure 6 A dendritic network hardware schematic diagram of an embodiment of the present application;

[0019] Figure 7 A recognition accuracy schematic diagram of a dendritic network on a MNIST data set of an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the above features and advantages of the present application more obvious and easy to understand, the present application is further described below in combination with the drawings and specific embodiments.

[0021] A structure schematic diagram of a separate gate flash transistor is shown in Figure 1 (b), when the erasing gate (EG) is floating or the level is 0V, the select gate transconductance g m_SG is determined by the product of two factors, i.e. g m_SG = w x V ds , wherein the coefficient w represents the control ability of the select gate to the channel, V ds represents the potential difference between the drain and the source, and w and V ds are controlled respectively. Thus, the select gate transconductance of the device can be controlled. In the separate gate flash transistor, w is determined by the floating gate (FG) charge state w FG and the coupling gate voltage V CG , i.e. w = w FG x V CG Therefore, the expression of the select gate transconductance is g m_SG = w FG x V CG x V ds In the embodiment, electrical tests are performed under the conditions of separately changing w FG , V ds and V CG , and the transconductance change conditions of the separate gate flash transistor are shown in Figure 1 (b), Figure 2 (b) and Figure 3 (b) respectively. The experimental results show that w FG , V ds and V CGAll for selected gate transconductance g m_SG It has regulatory capabilities (the figure shows the regulation of w respectively). FG V ds and V SG The 8 g produced m_SG (State). The drain current of a device can be represented by the product of the selected gate transconductance and the selected gate voltage: I d =g m_SG ×V SG =w FG ×V CG ×V ds ×V SG According to the above formula, the drain current of the device is the product of four factors, where W FG V represents the device's stored state. CG V ds and V SG All are input signals, w FG V ds and V CG The effects on the selected gate transfer curve are as follows: Figure 1 (a) Figure 2 (a) and Figure 3 As shown in (a). By utilizing the multi-port advantage of split-gate flash memory transistors and combining them with the device's intrinsic equations, a four-element multiplication operation can be achieved, greatly enriching the device's application scenarios.

[0022] In a split-gate flash memory transistor array, the drain electrodes of devices in the same column are connected by bit lines (BL); the select gate and coupling gate of devices in the same row are connected by word lines (WL) and coupling lines (CL), respectively, while the source electrodes are connected by source lines (SL). The array structure is as follows: Figure 4 As shown.

[0023] This invention discloses a method for implementing matrix-multivector multiplication based on a split-gate flash memory transistor array. The method mainly includes input-output mapping, information storage, and calculation using the device's intrinsic equations. Current is fed into the source lines to achieve current summation. When the source line potential is clamped to 0V, the current on each source line can be expressed by the following formula:

[0024]

[0025] Wherein, storage matrix W FG First, with the input vector V BL Perform the inner product, and then multiply the result by the two input vectors V. CL and V WL By performing element-wise product, we can ultimately obtain the current vector I of the source line.SL .

[0026] Where the matrix form of the operation is as follows:

[0027] I SL = W FG V BL ⊙V CL ⊙V WL

[0028] By using the multiple-input computation unit array, the operation between the storage matrix and three vectors can be realized. Taking a neural network algorithm (dendritic network algorithm) as an example, the mapping mode of the algorithm on the array is shown below. When each element in V CL is equal and remains unchanged (V CL = 1), the above formula can be simplified as:

[0029] I SL = W FC V BL ⊙V WL

[0030] The network core iteration formula is as follows:

[0031] A i+1 = WA i ⊙A0

[0032] Therefore, only the one-to-one mapping of I SL , W FG , V BL and V WL with A i+1 , W, A i and A0 in the network can realize the operation of a single-layer network. When multiple arrays are cascaded through the interface circuit, the entire network can be mapped to hardware to accelerate its operation. When V CL is also used as an input variable, the array can realize the operation between the storage matrix and three input signal vectors, and complex matrix vector operations can be realized at a small hardware cost. The positive and negative weights in the network are realized by the complementary split gate flash transistor array. The positive weight array and the negative weight array share the input, and respectively obtain the source line currents I SL + and I SL - , and the final source line current I SL is obtained by subtracting the two. Through the mode of complementary array current subtraction, the first-order and zero-order components in the device currents corresponding to the positive and negative weight arrays will be offset, effectively alleviating the influence of device non-ideal effects on the output result.

[0033] This invention utilizes the nonlinearity of flash memory transistors to achieve nonlinear transformation from input to output, eliminating the need for additional nonlinear activation circuits between layers. Furthermore, leveraging the multi-port advantage of the devices, it implements complex matrix-vector operations. Positive and negative weights are implemented using complementary device arrays, with the positive and negative weight arrays sharing the input to obtain the source line current I. SL + and I SL - Subtracting the two yields the final source line current I. SL ,like Figure 5 As shown; the dendritic network hardware can be divided into three layers: the synaptic layer, the dendritic layer, and the output layer. The dendritic layer is implemented using a discrete-gate flash memory transistor array, such as... Figure 6 As shown, the recognition accuracy of dendritic networks on the MNIST dataset increases with the number of quantized weight states. For a two-layer dendritic network of size 64×64, after quantization to 3 bits, a recognition accuracy of 95.67% can be achieved, which is comparable to that of traditional neural networks. Figure 7 As shown.

[0034] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be determined by the claims.

Claims

1. A method for matrix-multiple vector multiplication computation of a multiple-input arithmetic unit, applied to a dendritic network hardware, the dendritic network hardware is divided into three layers, namely a synapse layer, a dendrite layer and an output layer, characterized in that, The dendritic layer is realized by a split-gate flash transistor array, in which the drain electrodes of the split-gate flash transistors in the same column are connected by a bit line; the select gate and the coupling gate of the split-gate flash transistors in the same row are connected by a word line and a coupling line respectively; and the source electrodes of the split-gate flash transistors are connected by a source line. A single split-gate flash transistor completes the multi-element product calculation between the stored information and three input information. The writing and reading of the split-gate transistor are completed by the coupling gate and the select gate respectively, and the current summation operation is realized by the current converging into the source line. The matrix form of the operation is as follows: The storage matrix W of the separated gate flash transistor array FG First, the input vector V BL is multiplied by the input vector V CL and the input vector V WL to obtain the source line current vector I SL , and the multiple separated gate flash transistor arrays are cascaded through the interface circuit, and I SL , W FG , V BL and V WL are mapped with A i+1 , W, A i and A0 in the network one by one, so that the operation of the single-layer network is realized.

2. The matrix-multiple vector multiplication computation method of claim 1, wherein, The positive and negative weights in the network are implemented by complementary split-gate flash transistor arrays, the positive weight array and the negative weight array share the input, and the source line current I SL + and I SL - , and the final source line current I SL is obtained by subtracting the two.

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