Layout parameter determination method and device of printed circuit board and storage medium

Abstract

The present disclosure provides a layout parameter determination method and device of a printed circuit board, a storage medium and an electronic device. The method comprises: determining a first correlation between a first deformation variable of a shielding layer located in a first region and a distance between two adjacent elements; determining a second correlation between a second deformation variable of the shielding layer located in a second region and a width of the shielding layer in the second region; taking a height difference between the two adjacent elements as the first deformation variable, and determining the distance by combining the first correlation; taking 1 / 2 of the height of an element located at the edge of the printed circuit board as the second deformation variable, and determining the width by combining the second correlation; performing layout design of elements on the printed circuit board according to the distance, and determining the size of the shielding layer according to the width. The present disclosure obtains the element layout distance and the actual size of the shielding layer based on the correlation between the deformation variable of the shielding layer and the layout parameter, thereby avoiding abnormal sound.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of electronic technology, and in particular, to a layout parameter determination method and device of a printed circuit board, a storage medium and an electronic device. BACKGROUND

[0002] In the design process of consumer electronic products (such as tablet computers, notebook computers and the like), especially in the design field of display screens, in order to reduce the electromagnetic interference received by the electronic components punched on the printed circuit board (PCB) and ensure the insulation, an insulating PET layer (polyethylene terephthalate) and an electromagnetic tape layer are sequentially attached to the surface of the components, and the edges of the PET layer and the tape layer are bonded together with the PCB board to ensure complete coverage of the components, so that the electronic product has good signal receiving and transmitting performance.

[0003] However, after applying the above design, when the user presses the whole machine, due to force transmission and load distribution, the tape layer and the PET layer will be stressed, causing the tape layer to produce abnormal noise. The abnormal noise is mainly from three parts: (1) the tape between the components contacts the PCB under the action of external force, and after the external force is removed, the tape rebounds to produce abnormal noise; (2) the transition section of the tape on the edge of the component and not yet contacting the PCB is pasted to the PCB under the action of external force, and after the external force is removed, the glue layer separates from the PCB to produce abnormal noise; (3) the transition section of the tape on the edge of the component cannot contact the PCB to form support under the action of external force, so as to drive the edge tape that has been bonded to be raised and produce abnormal noise.

[0004] The above abnormal noise problem is a design defect of the product itself, which reduces the quality of the product and affects the experience of consumers. SUMMARY

[0005] The purpose of the embodiments of the present disclosure is to provide a layout parameter determination method and device of a printed circuit board, a storage medium and an electronic device, to solve the problem of abnormal noise of the electromagnetic tape layer after being stressed in the prior art.

[0006] An embodiment of the present disclosure adopts the following technical solution: a method for determining layout parameters of a printed circuit board, wherein a plurality of components are provided on a surface of the printed circuit board, and a shielding layer is applied to a side of the component away from the printed circuit board, the shielding layer covers all the components and has a bonding area with the printed circuit board. The layout parameter determination method includes: determining a first correlation between a first deformation amount of the shielding layer located in a first area and a spacing between two adjacent components, wherein the first area is an area where the shielding layer covers all the components; determining a second correlation between a second deformation amount of the shielding layer located in a second area and a width of the shielding layer in the second area, wherein the second area is an area of ​​the shielding layer excluding the first area and the bonding area; taking the height difference between the two adjacent components as the first deformation amount, and determining the spacing in combination with the first correlation; taking 1 / 2 of the height of the component located at the edge of the printed circuit board as the second deformation amount, and determining the width in combination with the second correlation; designing the layout of the components on the printed circuit board according to the spacing, and determining the size of the shielding layer according to the width.

[0007] In some embodiments, determining the first correlation between the first deformation amount of the shielding layer located in the first area and the spacing between two adjacent elements includes: establishing a first equivalent model of the shielding layer in the first area; and deriving the first equivalent model based on a simply supported beam model to determine the first correlation.

[0008] In some embodiments, the first association relationship is expressed based on the following formula:

[0009] δ1=k1F1d 3 (1)

[0010] Wherein, δ1 is the first deformation amount, k1 is the deformation coefficient, F1 is the external force received by the shielding layer in the first area, and d is the distance.

[0011] In some embodiments, determining the second correlation between the second deformation amount of the shielding layer located in the second area and the width of the shielding layer in the second area includes: establishing a second equivalent model of the shielding layer in the second area; deriving the second equivalent model based on finite element analysis to determine a third correlation between the second deformation amount and the projection value of the width of the shielding layer in the second area on the printed circuit board; and determining the second correlation based on the Pythagorean theorem and the third correlation.

[0012] In some embodiments, the third association relationship is expressed based on the following formula:

[0013] δ2=(k2L 4 +k3L 3 +k4L 2 +k5L+k6)F2 (2)

[0014] Wherein, δ2 is the second deformation amount, F2 is the external force received by the shielding layer in the second region, k2, k3, k4, k5 and k6 are deformation coefficients, and L is the projection value; the second association relationship is expressed based on the following formula:

[0015]

[0016] Wherein, c is the width.

[0017] In some embodiments, taking 1 / 2 of the height of the component located at the edge of the printed circuit board as the second deformation variable and determining the width in combination with the second association relationship includes: determining the value of the deformation coefficient based on the finite element analysis; forming an association function curve between the second deformation variable and the projection value based on the value of the deformation coefficient, and when the second deformation variable is 1 / 2 of the height of the component located at the edge of the printed circuit board, determining the value of the projection value according to the association function curve; substituting the value of the projection value and the second deformation variable into formula (3) to determine the value of the width.

[0018] In some embodiments, the shielding layer includes an insulating layer and an electromagnetic layer arranged in sequence, wherein the insulating layer is arranged on a side of the component away from the printed circuit board, and the electromagnetic layer is arranged on a side of the insulating layer away from the component.

[0019] An embodiment of the present disclosure further provides a device for determining layout parameters of a printed circuit board, wherein a plurality of components are provided on a surface of the printed circuit board, and a shielding layer is applied to a side of the component away from the printed circuit board, the shielding layer covering all the components and having an adhesive region with the printed circuit board. The device comprises: a first determination module for determining a first correlation between a first deformation of the shielding layer located in a first region and a spacing between two adjacent components, wherein the first region is a region where the shielding layer covers all the components; a second determination module for determining a second correlation between a second deformation of the shielding layer located in a second region and a width of the shielding layer in the second region, wherein the second region is a region of the shielding layer excluding the first region and the adhesive region; a spacing determination module for taking the height difference between two adjacent components as the first deformation and determining the spacing in combination with the first correlation; a width determination module for taking 1 / 2 of the height of a component located at an edge of the printed circuit board as the second deformation and determining the width in combination with the second correlation; and a layout module for designing the layout of the components on the printed circuit board according to the spacing and determining the size of the shielding layer according to the width.

[0020] An embodiment of the present disclosure further provides a storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-mentioned method for determining layout parameters of a printed circuit board.

[0021] An embodiment of the present disclosure also provides an electronic device, comprising at least a memory and a processor, wherein a computer program is stored in the memory, and wherein the processor implements the steps of the above-mentioned method for determining the layout parameters of a printed circuit board when executing the computer program in the memory.

[0022] The beneficial effects of the embodiments of the present disclosure are: based on the correlation between the deformation of the shielding layer and the various layout parameters on the printed circuit board, combined with the actual physical dimensions of the components on the current printed circuit board, the component layout spacing on the printed circuit board and the actual dimensions of the shielding layer are obtained, so that the problem of abnormal noise caused by the printed circuit board under the action of external force is solved based on the changes in the layout design achieved by the above parameters, thereby improving the quality of the product and providing consumers with a better experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0024] Figure 1 Schematic diagram of the layout design of the PCB board in the first embodiment of the present disclosure;

[0025] Figure 2 This is a flow chart of a method for determining layout parameters of a printed circuit board in the first embodiment of the present disclosure;

[0026] Figure 3 This is a schematic diagram of the first equivalent model in the first embodiment of the present disclosure;

[0027] Figure 4 This is a schematic diagram of the second equivalent model in the first embodiment of the present disclosure;

[0028] Figure 5 is a correlation function curve between the second deformation amount and the projection value in the first embodiment of the present disclosure;

[0029] Figure 6 Schematic diagram of the structure of a device for determining layout parameters of a printed circuit board in a second embodiment of the present disclosure;

[0030] Figure 7 Schematic diagram of the structure of an electronic device in the fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Various aspects and features of the present disclosure are described herein with reference to the accompanying drawings.

[0032] It should be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the above description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope and spirit of the present disclosure will occur to those skilled in the art.

[0033] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0034] These and other characteristics of the present disclosure will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0035] It should also be understood that, while the disclosure has been described above with reference to particular embodiments, work perfectly skilled in the art will be able to ascertain many other equivalent forms of the disclosure, which have features as claimed and which are therefore within the scope of the protection defined by the claims.

[0036] The above and other aspects, features, and advantages of the disclosure will become more apparent from the following detailed description, when taken in conjunction with the accompanying drawings, which illustrate a specific embodiment of the disclosure.

[0037] Hereinafter, specific embodiments of the disclosure are described with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of the disclosure, which can be implemented in various ways. Well-known and / or repetitive functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the disclosure. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but are only used as a basis for the claims and a representative basis for teaching those skilled in the art to use the disclosure in a variety of essentially any suitable detailed structures.

[0038] The specification can use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which can refer to one or more of the same or different embodiments of the disclosure.

[0039] In the design process of consumer electronics products (such as tablet computers, notebook computers and the like), especially in the design field of display screens, in order to reduce the electromagnetic interference received by the electronic components punched on the PCB and ensure the insulation, an insulating PET layer and an electromagnetic tape layer are usually attached to the surface of the components in turn, and the edges of the PET layer and the tape layer are bonded together with the PCB, ensuring complete coverage of the components, so that the electronic product has good signal receiving and transmitting performance.

[0040] However, after applying the above design, when the user presses the whole machine, due to force transmission and load distribution, the tape layer and the PET layer will be stressed, causing the tape layer to produce abnormal noise. The abnormal noise is mainly from three parts: (1) the tape between the components contacts the PCB under the action of external force, and the tape rebounds to produce abnormal noise after the external force is removed; (2) the transition section of the tape at the edge of the component and not yet contacting the PCB is pasted to the PCB under the action of external force, and the glue layer separates from the PCB to produce abnormal noise after the external force is removed; (3) the transition section of the tape at the edge of the component cannot contact the PCB to form support under the action of external force, so as to drive the edge tape that has been bonded to be raised, causing abnormal noise. The above abnormal noise problem is a design defect of the product itself, which reduces the quality of the product and affects the experience of consumers.

[0041] In order to solve the above problems, the first embodiment of the present disclosure provides a method for determining the layout parameters of a printed circuit board, and then, by determining the layout parameters of the PCB board, the optimized design of the component layout on the PCB board and the optimized adjustment of the shielding layer size are achieved, so as to achieve the purpose of avoiding the generation of abnormal noise.

[0042] like Figure 1 As shown in FIG. 1 , one side of the printed circuit board for which layout parameter design is to be performed in this embodiment is used to manufacture a plurality of electronic components. Adjacent components are spaced a certain distance apart. A shielding layer is attached to the side of the component away from the PCB surface. The shielding layer covers all components to reduce electronic interference received by the components and ensure insulation performance. While covering all components, the shielding layer is also bonded to the surface of the PCB at the same time. The area where the shielding layer is bonded to the PCB is the bonding area (e.g., Figure 1 The shielding layer described in this embodiment may include an insulating PET layer and an electromagnetic tape layer arranged in sequence, wherein the PET layer is arranged on a side of the component away from the PCB board, and the tape layer is arranged on a side of the PET layer away from the component, that is, the tape layer is arranged above the PET layer.

[0043] Figure 2 The flowchart of the method for determining layout parameters of this embodiment is shown, which mainly includes steps S10 to S50:

[0044] S10 , determining a first correlation between a first deformation amount of the shielding layer located in a first region and a distance between two adjacent components.

[0045] The shielding layer located in the first area is the part of the shielding layer used to cover the component, such as Figure 1 The position shown in the dotted box is where the shielding layer directly contacts the top surface of the component. During the design process, to prevent the shielding layer from rebounding and making unusual noises after being subjected to force and contacting the PCB board between two adjacent components, this embodiment first determines a first correlation between the first deformation of the shielding layer in the first region and the spacing between two adjacent components. The spacing between the components is then determined by limiting the magnitude of the first deformation to ensure that the deformation of the shielding layer covering the top of the component when subjected to force does not exceed the pre-set limit when the component is set according to the aforementioned spacing. This prevents the shielding layer from rebounding and making unusual noises after being subjected to force and contacting the PCB board between two adjacent components.

[0046] Specifically, when determining the first association relationship, a first equivalent model of the shielding layer in the first region may be established to represent the positional relationship and size limitation between the shielding layer and the components supporting the shielding layer, such as: Figure 3As shown, two adjacent components 2 are provided on the PCB board 1, and the spacing between the two components 2 is d. A shielding layer 3 is covered on the component 2. The first deformation variable δ1 is the deformation variable generated by the center point X of the shielding layer located between the two components 2 when subjected to force. The first correlation relationship is to determine the relationship between the first deformation variable δ1 and the spacing d. After the first equivalent model is generated, the positional relationship between the shielding layer 3 and the component 2 is similar to a simply supported beam model. This embodiment derives the first equivalent model based on the simply supported beam model, and finally obtains the first correlation relationship as shown in formula (1):

[0047] δ1=k1F1d 3 (1)

[0048] Wherein, δ1 is the first deformation, k1 is the deformation coefficient, F1 is the external force received by the shielding layer in the first region, and d is the distance.

[0049] S20 , determining a second correlation between a second deformation amount of the shielding layer in the second area and a width of the shielding layer in the second area.

[0050] The shielding layer in the second area is the transition area between the first area and the bonding area, that is, the part extending from the edge of the component at the edge of the PCB but not yet bonded to the PCB (such as Figure 1 (shaded area), since the component has a certain height, the shielding layer in the second area forms an inclined surface when it is set. During the design, in order to avoid abnormal noise when the shielding layer in the second area is subjected to force, this embodiment first determines the second correlation between the second deformation of the shielding layer in the second area and the width of the shielding layer in the area. It should be noted that the width of the shielding layer in the area refers to the width of the inclined surface formed by the shielding layer, which is actually the extension dimension of the shielding layer extending out of the first area. After the second correlation is determined, the width of the shielding layer in the second area is determined by limiting the size of the second deformation to ensure that after the overall size of the shielding layer is calculated based on the above width, the deformation of the portion of the shielding layer located in the second area after being set and implemented according to the size design when subjected to force meets the pre-restricted limit, thereby avoiding the generation of abnormal noise when the shielding layer is subjected to force.

[0051] Specifically, when determining the second association relationship, a second equivalent model of the shielding layer in the second region may be established first to represent the positional relationship and size limitations between the shielding layer and the components connected at both ends and the PCB board, such as Figure 4As shown, the edge portion of the PCB board 1 is provided with an element 2, the shielding layer 3 covers the top surface of the element 2 and is bent downward at the edge A point of the element 2 to extend to the connection with the PCB board 1 at B point, then the distance c between A and B is the width of the shielding layer in the second area, the height of the element 2 is H, the second deformation amount δ2 is the deformation amount of the center point Y of the shielding layer in the second area when being stressed, and the second correlation is the relationship between the second deformation amount δ2 and the width c.

[0052] In the process of determining the second correlation in the embodiment, the projection value (i.e., the corresponding Figure 4 L in the formula (1)) of the width (i.e., the AB segment) of the shielding layer in the second area on the PCB board can be used as a correlation parameter to correlate the width c and the second deformation amount δ2. For example, the second equivalent model can be derived by means of finite element analysis, and first, a third correlation between the second deformation amount δ2 and the projection value L is determined, as shown in the formula (2):

[0053] δ2=(k2L 4 +k3L 3 +k4L 2 +k5L+k6)F2 (2)

[0054] Wherein, δ2 is the second deformation amount, F2 is the external force received by the shielding layer in the second area, j2, j3, k4, k5 and k6 are deformation coefficients, and L represents the projection value.

[0055] After the third correlation is determined, the formula (3) for representing the second correlation can be obtained according to the Pythagorean theorem and the third correlation as follows:

[0056]

[0057] S30, the height difference between the two adjacent elements is taken as the first deformation amount, and the distance is determined in combination with the first correlation.

[0058] In actual implementation, the stress value F can be set according to the actual stress condition, and is usually set to 10N. The deformation coefficient k1 can be obtained based on finite element analysis. According to the correlation relationship presented by the formula (1), the distance size between the elements meeting the first deformation amount requirement can be determined by limiting the value of the first deformation amount δ1. In the embodiment, the first deformation amount can be limited to the height difference h between the two adjacent elements, that is, the deformation amount of the center point X of the shielding layer between the two elements when being stressed does not exceed h, so as to avoid the shielding layer contacting the PCB board between the elements, and also to limit the shielding layer from contacting the edge of the element with lower height when being deformed, thereby causing abnormal sound at the edge position.

[0059] In actual calculation, δ1≤h can be substituted into formula (1) to obtain formula (4) as follows:

[0060]

[0061] Substituting h = 0.1, F1 = 10N, and the value of k1 obtained through finite element analysis into formula (4) can determine the value of spacing d. When setting components, the maximum spacing during component layout can be determined based on the value of d to avoid abnormal noise. However, it should be noted that a certain safe distance should be maintained between adjacent components to avoid mutual influence between components that may cause PCB board functional failure. The specific setting of d can be based on the actual component characteristics, functional requirements, and the value of d determined based on formula (4).

[0062] S40 , taking half of the height of the component located at the edge of the printed circuit board as the second deformation amount, and determining the width in combination with the second association relationship.

[0063] In actual implementation, the force value F can be set according to the actual force situation, usually set to 10N. The deformation coefficients k2 to k6 can be obtained based on finite element analysis. According to the correlation relationship presented by formula (2), the value of the AB segment projection value L can be determined by limiting the value of the second deformation variable δ2. Based on formula (3), the width of the shielding layer in the second area that meets the second deformation variable requirements can be determined to avoid abnormal noise when the shielding layer in the second area is subjected to force.

[0064] Specifically, the value of the second deformation amount δ2 is usually limited to half of the height H of the edge element, that is, H / 2. Referring to the cause of the abnormal noise of the shielding layer in the second area, it is usually because the shielding layer itself is not deformed enough to contact the PCB board to form support after being stressed, thereby causing the shielding layer in the bonding area to warp and produce abnormal noise. Therefore, combined with Figure 4 In the second equivalent model shown, if the deformation of the center point Y of segment AB exceeds H / 2 (based on the principle of similar triangles, point Y is the midpoint of segment AB, and the vertical distance between point Y and the PCB is half the vertical distance between point A and the PCB, that is, H / 2), then the center point of segment AB will contact the PCB when subjected to force, providing support, preventing the shielding layer from warping in the bonding area and thus avoiding the occurrence of abnormal noise.

[0065] Furthermore, the steps for solving the L value by substituting the force value F, deformation coefficients k2 to k6, and the second deformation variable δ2 ≥ H / 2 into formula (2) are relatively complicated. Therefore, in actual calculation, the correlation function curve between the second deformation variable and L can be fitted by the image method first, as shown in the following example: Figure 5 As shown, then based on Figure 5The correlation function curve presented in [1] determines the value of L when δ2 ≥ H / 2. Finally, the value of L and the second deformation variable δ2 ≥ H / 2 are substituted into formula (3) to determine the range of c. It should be noted that, considering the requirements of exposed copper areas on the PCB board during actual layout, it is necessary to ensure the size limit of the area covered by the shielding layer. When determining the value of c, it can be set according to the critical value allowed by the size.

[0066] S50, designing the layout of components on the printed circuit board according to the spacing, and determining the size of the shielding layer according to the width.

[0067] After determining the spacing d between components and the width c of the shielding layer's extended area, the component layout design and shielding layer dimensions can be determined based on actual needs. It should be noted that in addition to considering the spacing d during component design, the safety clearance between components, the type and number of components actually required, or the actual size of the PCB board should also be considered. When determining the size of the shielding layer, the height H of components located at different edge positions may be different, resulting in different calculated shielding layer extension dimensions. For example, if multiple components form a rectangular component array area, and the height of the components located on the long side of the rectangle is different from the height of the components located on the short side of the rectangle, the shielding layer dimensions of the second areas extending from different positions will also be different. In actual calculations, the shielding layer extension dimensions of multiple second areas can be calculated based on the component dimensions at different directional positions. When determining the overall shielding layer dimensions, the shielding layer dimensions of the first area can be combined with the shielding layer extension dimensions of the multiple second areas.

[0068] This embodiment is based on the correlation between the deformation of the shielding layer and the various layout parameters on the printed circuit board, combined with the actual physical dimensions of the components on the current printed circuit board, to obtain the component layout spacing on the printed circuit board and the actual dimensions of the shielding layer. This solves the abnormal noise problem caused by the printed circuit board under the action of external force based on the layout design changes achieved by the above parameters, thereby improving the quality of the product and providing consumers with a better experience. At the same time, the method provided by this embodiment can avoid the continuous trial and error verification of designers in the process of designing PCB boards, reduce human resource costs, improve product design quality and design efficiency, and achieve the purpose of reducing product development costs.

[0069] It should be noted that, when actually executing the layout parameter determination method provided in this embodiment, steps S10 and S20 may be executed in a different order or simultaneously, and the same applies to steps S30 and S40 , which are not specifically limited here.

[0070] The second embodiment of the present disclosure provides a device for determining layout parameters of a printed circuit board. The device can be installed in any electronic device for designing a PCB board. The schematic diagram of the structure is shown in FIG. Figure 6 As shown, the system mainly includes a first determination module 10, a second determination module 20, a spacing determination module 30, a width determination module 40, and a layout module 50. The first determination module 10 is used to determine a first correlation between a first deformation of the shielding layer located in a first region and a spacing between two adjacent components, wherein the first region is the region where the shielding layer covers all components; the second determination module 20 is used to determine a second correlation between a second deformation of the shielding layer located in a second region and a width of the shielding layer in the second region, wherein the second region is the region of the shielding layer excluding the first region and the bonding region; the spacing determination module 30 is used to determine the spacing based on the first correlation using the height difference between two adjacent components as the first deformation; the width determination module 40 is used to determine the width based on the second correlation using 1 / 2 of the height of the component located at the edge of the printed circuit board as the second deformation; and the layout module 50 is used to design the layout of components on the printed circuit board based on the spacing and to determine the size of the shielding layer based on the width.

[0071] In some embodiments, the first determination module 10 is specifically configured to establish a first equivalent model of the shielding layer within the first region; and derive the first equivalent model based on a simply supported beam model to determine a first correlation relationship. Specifically, the first correlation relationship is expressed based on the following formula:

[0072] δ1=k1F1d 3 (1)

[0073] Wherein, δ1 is the first deformation, k1 is the deformation coefficient, F1 is the external force received by the shielding layer in the first region, and d is the distance.

[0074] In some embodiments, the second determination module 20 is specifically configured to establish a second equivalent model of the shielding layer within the second region; derive the second equivalent model based on finite element analysis to determine a third correlation between the second deformation amount and the projection value of the width of the shielding layer within the second region on the printed circuit board; and determine the second correlation based on the Pythagorean theorem and the third correlation. Specifically, the third correlation is expressed based on the following formula:

[0075] δ2=(k2L 4 +k3L 3 +k4L 2 +k5L+k6)F2 (2)

[0076] Wherein, δ2 is the second deformation, F2 is the external force received by the shielding layer in the second region, k2, k3, k4, k5 and k6 are deformation coefficients, and L is the projection value;

[0077] The second correlation relationship is represented based on the following formula:

[0078]

[0079] wherein c is the width.

[0080] In some embodiments, the width determining module 40 is specifically configured to determine the value of the deformation coefficient based on the finite element analysis; form a correlation function curve between the second deformation variable and the projection value based on the value of the deformation coefficient, and determine the value of the projection value according to the correlation function curve in the case that the second deformation variable is 1 / 2 of the height of the element located at the edge of the printed circuit board; and substitute the value of the projection value and the second deformation variable into formula (3) to determine the value of the width.

[0081] In some embodiments, the shielding layer comprises an insulating layer and an electromagnetic layer arranged in sequence, wherein the insulating layer is arranged on the side of the element away from the printed circuit board, and the electromagnetic layer is arranged on the side of the insulating layer away from the element.

[0082] The embodiment is based on the correlation relationship between the deformation variable of the shielding layer and each layout parameter on the printed circuit board, and the actual physical size of the element on the printed circuit board is combined to obtain the element layout spacing on the printed circuit board and the actual size of the shielding layer, so that the abnormal sound problem of the printed circuit board under the action of external force is solved based on the change of the layout design realized based on the above parameters, thereby improving the quality of the product and providing consumers with a better experience. At the same time, through the way provided by the embodiment, the designers can avoid the trial and error verification in the process of designing the PCB board, reduce the human resource cost, improve the design quality and design efficiency of the product, and achieve the purpose of reducing the product development.

[0083] The third embodiment of the present disclosure provides a storage medium which can be installed in any electronic device for PCB board design, specifically a computer readable medium, and stores a computer program which is executed by a processor to realize the method provided by any embodiment of the present disclosure, including the following steps S31 to S35:

[0084] S31, determining a first correlation relationship between a first deformation variable of the shielding layer located in a first region and a spacing between two adjacent elements, wherein the first region is a region in which the shielding layer covers all the elements;

[0085] S32, determining a second correlation relationship between a second deformation variable of the shielding layer located in a second region and a width of the shielding layer in the second region, wherein the second region is a region of the shielding layer except the first region and the bonding area;

[0086] S33, taking the height difference between two adjacent elements as the first deformation amount, and determining the spacing in combination with the first association relationship;

[0087] S34, taking half of the height of the component located at the edge of the printed circuit board as the second deformation amount, and determining the width in combination with the second association relationship;

[0088] S35 , designing a layout of the components on the printed circuit board according to the spacing, and determining a size of the shielding layer according to the width.

[0089] When the computer program is executed by the processor to determine the first correlation between the first deformation of the shielding layer located in the first area and the distance between two adjacent elements, the processor specifically performs the following steps: establishing a first equivalent model of the shielding layer in the first area; deriving the first equivalent model based on the simply supported beam model to determine the first correlation.

[0090] Specifically, the first association relationship is expressed based on the following formula:

[0091] δ1=k1F1d 3 (1)

[0092] Wherein, δ1 is the first deformation amount, k1 is the deformation coefficient, F1 is the external force received by the shielding layer in the first area, and d is the distance.

[0093] When the computer program is executed by the processor to determine the second correlation between the second deformation amount of the shielding layer located in the second area and the width of the shielding layer in the second area, the processor specifically performs the following steps: establishing a second equivalent model of the shielding layer in the second area; deriving the second equivalent model based on finite element analysis to determine a third correlation between the second deformation amount and the projection value of the width of the shielding layer in the second area on the printed circuit board; and determining the second correlation based on the Pythagorean theorem and the third correlation.

[0094] Specifically, the third association relationship is expressed based on the following formula:

[0095] δ2=(k2L 4 +k3L 3 +k4L 2 +k5L+k6)F2 (2)

[0096] Wherein, δ2 is the second deformation amount, F2 is the external force received by the shielding layer in the second region, k2, k3, k4, k5 and k6 are deformation coefficients, and L is the projection value; the second association relationship is expressed based on the following formula:

[0097]

[0098] Wherein, c is the width.

[0099] When the computer program is executed by the processor and takes 1 / 2 of the height of the component located at the edge of the printed circuit board as the second deformation variable and determines the width in combination with the second association relationship, the processor specifically performs the following steps: determining the value of the deformation coefficient based on the finite element analysis; forming a correlation function curve between the second deformation variable and the projection value based on the value of the deformation coefficient, and when the second deformation variable is 1 / 2 of the height of the component located at the edge of the printed circuit board, determining the value of the projection value according to the correlation function curve; substituting the value of the projection value and the second deformation variable into formula (3) to determine the value of the width.

[0100] This embodiment is based on the correlation between the deformation of the shielding layer and the various layout parameters on the printed circuit board, combined with the actual physical dimensions of the components on the current printed circuit board, to obtain the component layout spacing on the printed circuit board and the actual dimensions of the shielding layer. This solves the abnormal noise problem caused by the printed circuit board under the action of external force based on the layout design changes achieved by the above parameters, thereby improving the quality of the product and providing consumers with a better experience. At the same time, the method provided by this embodiment can avoid the continuous trial and error verification of designers in the process of designing PCB boards, reduce human resource costs, improve product design quality and design efficiency, and achieve the purpose of reducing product development costs.

[0101] The fourth embodiment of the present disclosure provides an electronic device, which can be any electronic device used for PCB board design, and its structural diagram is shown in FIG. Figure 7 As shown, the electronic device at least includes a memory 100 and a processor 200. The memory 100 stores a computer program. The processor 200 implements the method provided by any embodiment of the present disclosure when executing the computer program on the memory 100. Exemplarily, the electronic device computer program steps are as follows S41 to S45:

[0102] S41, determining a first correlation between a first deformation amount of the shielding layer located in a first region and a distance between two adjacent components, wherein the first region is a region where the shielding layer covers all the components;

[0103] S42, determining a second correlation between a second deformation amount of the shielding layer located in a second area and a width of the shielding layer in the second area, wherein the second area is an area of ​​the shielding layer excluding the first area and the bonding area;

[0104] S43, taking the height difference between two adjacent elements as the first deformation amount, and determining the spacing in combination with the first association relationship;

[0105] S44, taking half the height of the component located at the edge of the printed circuit board as the second deformation amount, and determining the width in combination with the second association relationship;

[0106] S45 , designing a layout of the components on the printed circuit board according to the spacing, and determining a size of the shielding layer according to the width.

[0107] When the processor executes the first correlation relationship between the first deformation amount of the shielding layer located in the first area and the distance between two adjacent elements stored in the execution memory, it specifically executes the following computer program: establishing a first equivalent model of the shielding layer in the first area; deriving the first equivalent model based on the simply supported beam model to determine the first correlation relationship.

[0108] Specifically, the first association relationship is expressed based on the following formula:

[0109] δ1=k1F1d 3 (1)

[0110] Wherein, δ1 is the first deformation amount, k1 is the deformation coefficient, F1 is the external force received by the shielding layer in the first area, and d is the distance.

[0111] When the processor executes the second correlation relationship between the second deformation amount of the shielding layer located in the second area and the width of the shielding layer in the second area stored in the execution memory, it specifically executes the following computer program: establishing a second equivalent model of the shielding layer in the second area; deriving the second equivalent model based on finite element analysis to determine the third correlation relationship between the second deformation amount and the projection value of the width of the shielding layer in the second area on the printed circuit board; and determining the second correlation relationship based on the Pythagorean theorem and the third correlation relationship.

[0112] Specifically, the third association relationship is expressed based on the following formula:

[0113] δ2=(k2L 4 +k3L 3 +k4L 2 +k5L+k6)F2 (2)

[0114] Wherein, δ2 is the second deformation amount, F2 is the external force received by the shielding layer in the second region, k2, k3, k4, k5 and k6 are deformation coefficients, and L is the projection value; the second association relationship is expressed based on the following formula:

[0115]

[0116] Wherein, c is the width.

[0117] When the processor determines the width by taking 1 / 2 of the height of the component located at the edge of the printed circuit board as the second deformation variable and combining the second association relationship stored in the execution memory, the processor specifically executes the following computer program: determining the value of the deformation coefficient based on the finite element analysis; forming a correlation function curve between the second deformation variable and the projection value based on the value of the deformation coefficient, and when the second deformation variable is 1 / 2 of the height of the component located at the edge of the printed circuit board, determining the value of the projection value according to the correlation function curve; substituting the value of the projection value and the second deformation variable into formula (3) to determine the value of the width.

[0118] This embodiment is based on the correlation between the deformation of the shielding layer and the various layout parameters on the printed circuit board, combined with the actual physical dimensions of the components on the current printed circuit board, to obtain the component layout spacing on the printed circuit board and the actual dimensions of the shielding layer. This solves the abnormal noise problem caused by the printed circuit board under the action of external force based on the layout design changes achieved by the above parameters, thereby improving the quality of the product and providing consumers with a better experience. At the same time, the method provided by this embodiment can avoid the continuous trial and error verification of designers in the process of designing PCB boards, reduce human resource costs, improve product design quality and design efficiency, and achieve the purpose of reducing product development costs.

[0119] The above describes in detail multiple embodiments of the present disclosure, but the present disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concepts of the present disclosure, and these variations and modifications should all fall within the scope of protection claimed by the present disclosure.

Claims

1. A method for determining layout parameters of a printed circuit board, wherein a plurality of components are arranged on a surface of the printed circuit board, a shielding layer is applied to a side of the components away from the printed circuit board, the shielding layer covers all the components and has a bonding area with the printed circuit board, characterized in that: The layout parameter determination method includes: Determining a first correlation between a first deformation amount of the shielding layer located in a first area and a distance between two adjacent elements, wherein the first area is an area where the shielding layer covers all the elements; Determining a second correlation between a second deformation amount of the shielding layer in a second area and a width of the shielding layer in the second area, wherein the second area is an area of ​​the shielding layer excluding the first area and the bonding area; Taking the height difference between two adjacent elements as the first deformation amount, and determining the spacing in combination with the first association relationship; Taking half of the height of the component located at the edge of the printed circuit board as the second deformation amount, and determining the width in combination with the second association relationship; The layout of the components on the printed circuit board is designed according to the spacing, and the size of the shielding layer is determined according to the width.

2. The layout parameter determination method according to claim 1, characterized in that: Determining a first correlation between a first deformation amount of the shielding layer located in the first area and a distance between two adjacent elements includes: establishing a first equivalent model of the shielding layer within the first region; The first equivalent model is derived based on a simply supported beam model to determine the first association relationship.

3. The layout parameter determination method according to claim 2, characterized in that: The first association relationship is expressed based on the following formula: δ1=k1F1d 3 (1) Wherein, δ1 is the first deformation amount, k1 is the deformation coefficient, F1 is the external force received by the shielding layer in the first area, and d is the distance.

4. The method for determining layout parameters according to claim 1, wherein: Determining a second correlation between a second deformation amount of the shielding layer in the second area and a width of the shielding layer in the second area includes: establishing a second equivalent model of the shielding layer in the second region; Derivation of the second equivalent model based on finite element analysis to determine a third correlation relationship between the second deformation amount and a projection value of the width of the shielding layer in the second region on the printed circuit board; Based on the Pythagorean theorem and the third association relationship, the second association relationship is determined.

5. The layout parameter determination method according to claim 4, characterized in that: The third association relationship is expressed based on the following formula: δ2=(k2L 4 +k3L 3 +k4L 2 +k5L+k6)F2 (2) Wherein, δ2 is the second deformation amount, F2 is the external force received by the shielding layer in the second region, k2, k3, k4, k5 and k6 are deformation coefficients, and L is the projection value; The second association relationship is expressed based on the following formula: Wherein, c is the width.

6. The method for determining layout parameters according to claim 5, wherein: The method of using half of the height of the component located at the edge of the printed circuit board as the second deformation amount and determining the width in combination with the second association relationship includes: determining a value of the deformation coefficient based on the finite element analysis; forming a correlation function curve between the second deformation amount and the projection value based on the value of the deformation coefficient, and determining the value of the projection value according to the correlation function curve when the second deformation amount is 1 / 2 of the height of the component located at the edge of the printed circuit board; The value of the projection value and the second deformation amount are substituted into formula (3) to determine the value of the width.

7. The layout parameter determination method according to any one of claims 1 to 6, characterized in that: The shielding layer includes an insulating layer and an electromagnetic layer which are arranged in sequence, wherein the insulating layer is arranged on a side of the component away from the printed circuit board, and the electromagnetic layer is arranged on a side of the insulating layer away from the component.

8. A device for determining layout parameters of a printed circuit board, wherein a plurality of components are arranged on a surface of the printed circuit board, a shielding layer is applied to a side of the components away from the printed circuit board, the shielding layer covers all the components and has an adhesive area between the shielding layer and the printed circuit board, characterized in that: The device comprises: a first determining module, configured to determine a first correlation between a first deformation amount of the shielding layer located in a first area and a distance between two adjacent components, wherein the first area is an area where the shielding layer covers all the components; a second determining module, configured to determine a second correlation between a second deformation amount of the shielding layer located in a second area and a width of the shielding layer in the second area, wherein the second area is an area of ​​the shielding layer excluding the first area and the bonding area; a spacing determination module, configured to determine the spacing by taking the height difference between two adjacent elements as the first deformation amount and combining the first association relationship; a width determination module, configured to determine the width by taking half of the height of the component located at the edge of the printed circuit board as the second deformation amount and combining the second association relationship; A layout module is used to design the layout of the components on the printed circuit board according to the spacing, and to determine the size of the shielding layer according to the width.

9. A storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method for determining layout parameters of a printed circuit board according to any one of claims 1 to 6 are implemented.

10. An electronic device comprising at least a memory and a processor, wherein a computer program is stored in the memory, wherein: When executing the computer program on the memory, the processor implements the steps of the method for determining layout parameters of a printed circuit board according to any one of claims 1 to 6.

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