Semiconductor memory devices

Abstract

One embodiment of the present invention can suppress the increase in the area of ​​the voltage generation circuit and the increase in the current consumed by the voltage generation circuit. A semiconductor memory device according to one embodiment includes: a first memory cell; and a voltage generation circuit comprising a first charge pump having a first characteristic and a second charge pump having a second characteristic, supplying a voltage to the first memory cell. In a first operation of supplying a first voltage to the first memory cell, the voltage generation circuit electrically disconnects the first charge pump and the second charge pump; in a second operation of supplying a second voltage higher than the first voltage to the first memory cell, the voltage generation circuit electrically connects the output terminal of the first charge pump and the input terminal of the second charge pump.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-10010 (filed on January 26, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation relates to a semiconductor memory device. Background Technology

[0004] As a semiconductor memory device, NAND (NotAND) type flash memory is known to perform operations such as writing, reading, and deleting data. NAND type flash memory includes a voltage generation circuit. This voltage generation circuit generates the voltage used to perform write, read, and delete operations. Summary of the Invention

[0005] One embodiment of the present invention can suppress the increase in the area of ​​the voltage generating circuit and the increase in the current consumed by the voltage generating circuit.

[0006] One embodiment of a semiconductor memory device includes: a first memory cell; and a voltage generation circuit comprising a first charge pump having a first characteristic and a second charge pump having a second characteristic, supplying a voltage to the first memory cell, wherein each of the first and second charge pumps has an input terminal and an output terminal. In a first operation of supplying a first voltage to the first memory cell, the voltage generation circuit electrically disconnects the first and second charge pumps; in a second operation of supplying a second voltage higher than the first voltage to the first memory cell, the voltage generation circuit electrically connects the output terminal of the first charge pump to the input terminal of the second charge pump. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system and a host device that includes a semiconductor memory device with an implementation method.

[0008] Figure 2 This is a block diagram illustrating an example of the configuration of a semiconductor memory device according to an implementation method.

[0009] Figure 3 This is a circuit diagram illustrating an example of the configuration of a memory cell array in a semiconductor memory device according to an embodiment.

[0010] Figure 4 This is a cross-sectional view illustrating an example of the structure of a memory cell array in a semiconductor memory device according to an embodiment.

[0011] Figure 5This is a circuit diagram illustrating an example of the configuration of the voltage generation circuit in an embodiment.

[0012] Figure 6 This is a circuit diagram illustrating an example of the configuration of a charge pump included in a voltage generation circuit of an embodiment.

[0013] Figure 7 This is a circuit diagram illustrating an example of the configuration of a charge pump included in a voltage generation circuit of an embodiment.

[0014] Figure 8 This is a timing diagram illustrating an example of the voltages of the bit line, word line, source line, and select gate line when the delete voltage is applied during the delete operation of a semiconductor memory device in an embodiment of the present invention.

[0015] Figure 9 This diagram illustrates the rebalancing operation of the voltage generation circuit when the deletion voltage is applied during the deletion operation of a semiconductor memory device in an embodiment of the application method.

[0016] Figure 10 This is a timing diagram illustrating an example of the voltages of the bit lines, word lines, source lines, and select gate lines when a semiconductor memory device performing a programming operation during a write operation is executed using an embodiment.

[0017] Figure 11 This diagram illustrates the rebalancing action of the voltage generation circuit when a semiconductor memory device performs a programming operation during a write operation in an embodiment of the application.

[0018] Figure 12 This is a timing diagram illustrating an example of the voltages of the bit line, word line, and select gate line when a semiconductor memory device using this embodiment performs a read operation.

[0019] Figure 13 This diagram illustrates the rebalancing operation of the voltage generation circuit when a semiconductor memory device performs a read operation according to an embodiment. Detailed Implementation

[0020] The embodiments will now be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same function and structure are labeled with common reference numerals.

[0021] 1. Implementation Method

[0022] The semiconductor memory device according to the embodiment will now be described. Hereinafter, NAND flash memory will be used as an example of a semiconductor memory device for description.

[0023] 1.1 Composition

[0024] The configuration of the semiconductor memory device according to the embodiment will be described.

[0025] 1.1.1 Memory System

[0026] First, use Figure 1 An example of the configuration of a memory system will be described. Figure 1 This is a block diagram illustrating an example of the configuration of a memory system and a host device that includes a semiconductor memory device with an implementation method.

[0027] The memory system 3 communicates with, for example, an external host device 4. The memory system 3 stores data from the host device 4 and reads data from the host device 4. The memory system 3 is, for example, an SSD (solid-state drive) or SD card. TM Cards, etc.

[0028] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0029] Semiconductor memory device 1 has multiple memory cells and stores data non-volatilely. Semiconductor memory device 1 is connected to memory controller 2 via a NAND bus.

[0030] The NAND bus transmits and receives signals conforming to the NAND interface standard, namely / CE, CLE, ALE, / WE, / RE, RE, / WP, / RB, DQ<7:0>, DQS, and / DQ, via individual signal lines. The / CE signal is the Chip Enable signal, used to start the semiconductor memory device 1. The CLE signal is the Command Latch Enable signal, informing the semiconductor memory device 1 that the signal DQ<7:0> flowing to the semiconductor memory device 1 during the "H" level of the CLE signal is an instruction. The ALE signal is the Address Latch Enable signal, informing the semiconductor memory device 1 that the signal DQ<7:0> flowing to the semiconductor memory device 1 during the "H" level of the ALE signal is an address. The / WE signal is the Write Enable signal, instructing the semiconductor memory device 1 to fetch the signal DQ<7:0>. For example, at Single Data Rate (SDR), the rising edge of the / WE signal instructs the semiconductor memory device 1 to fetch the signal DQ<7:0> as an instruction, address, or data. Similarly, at Double Data Rate (DDR), the rising edge of the / WE signal instructs the semiconductor memory device 1 to fetch the signal DQ<7:0> as an instruction or address. The / RE signal is the Read Enable signal, instructing the semiconductor memory device 1 to output the signal DQ<7:0>. For example, at Single Data Rate, the falling edge of the / RE signal instructs the semiconductor memory device 1 to output the signal DQ<7:0> as data. At Double Data Rate, the falling and rising edges of the / RE signal instruct the semiconductor memory device 1 to output the signal DQ<7:0> as data. The RE signal is the complementary signal to the / RE signal. The / WP signal is the Write Protect signal, which instructs semiconductor memory device 1 to prohibit writing and deleting data. The / RB signal is the Ready Busy signal, indicating whether semiconductor memory device 1 is in a ready state (accepting commands from the outside) or a busy state (not accepting commands from the outside). The DQ<7:0> signal is, for example, an 8-bit signal. The DQS signal is the Data Strobe signal, used to control the timing of the operation of semiconductor memory device 1 affected by the DQ<7:0> signal. For example, at double data rate, the falling and rising edges of the DQS signal instruct semiconductor memory device 1 to fetch the DQ<7:0> signal as data.Furthermore, at double data rate, the signal DQS is generated based on the falling and rising edges of the signal / RE, and is output from semiconductor memory device 1 along with the signal DQ<7:0>, which is data. The signal / DQS is the complementary signal to the signal DQS.

[0031] Signals DQ<7:0> are transmitted and received between semiconductor memory device 1 and memory controller 2, and include instructions CMD, addresses ADD, and data DAT. Instructions CMD may include, for example, instructions that cause semiconductor memory device 1 to perform a delete operation (delete instruction), instructions that cause semiconductor memory device 1 to perform a write operation (write instruction), and instructions that cause semiconductor memory device 1 to perform a read operation (read instruction). Data DAT includes read data and write data.

[0032] The storage controller 2 receives commands from the host device 4 and controls the semiconductor storage device 1 based on the received commands. Specifically, the storage controller 2 writes the data to be written to the semiconductor storage device 1 based on the write command received from the host device 4. In addition, the storage controller 2 sends the data to be read from the semiconductor storage device 1 to the read host device 4 based on the read command received from the host device 4.

[0033] Examples of host devices 4 that use the memory system 3 described above include digital cameras, personal computers, and servers in data centers.

[0034] 1.1.2 Storage Controller

[0035] like Figure 1 As shown, the memory controller 2 includes a CPU (Central Processing Unit) 20, built-in memory 21, buffer memory 22, NAND I / F (NAND interface circuit) 23, and host I / F (host interface circuit) 24. The memory controller 2 is configured, for example, as a SoC (System-on-a-chip).

[0036] CPU 20 controls the overall operation of memory controller 2. CPU 20 issues instructions, for example, to instruct semiconductor memory device 1 to perform various operations such as write, read, and delete operations.

[0037] The built-in memory 21 is, for example, a semiconductor memory such as DRAM (Dynamic Random Access Memory), and is used as the operating area of ​​the CPU 20. The built-in memory 21 stores firmware used to manage the semiconductor memory device 1, as well as various management tables, etc.

[0038] The buffer memory 22 temporarily stores write data received from the host device 4 and read data received by the storage controller 2 from the semiconductor storage device 1.

[0039] NAND interface circuit 23 is connected to semiconductor memory device 1 via NAND bus and is responsible for communication with semiconductor memory device 1. NAND interface circuit 23 sends instruction CMD, address ADD, and write data to semiconductor memory device 1 according to the instructions of CPU 20. In addition, NAND interface circuit 23 receives read data from semiconductor memory device 1.

[0040] The host interface circuit 24 is connected to the host device 4 via the host bus and is responsible for communication between the storage controller 2 and the host device 4. For example, the host interface circuit 24 transmits commands and data received from the host device 4 to the CPU 20 and the buffer memory 22, respectively.

[0041] 1.1.3 Semiconductor memory devices

[0042] Next, use Figure 2 An example of the configuration of the semiconductor memory device 1 according to the embodiment will be described. Figure 2 This is a block diagram illustrating an example of the configuration of a semiconductor memory device 1 according to an embodiment.

[0043] Semiconductor memory device 1 includes a memory cell array 10, an input / output circuit 11, a logic control circuit 12, a register 13, a sequencer 14, a voltage generation circuit 15, a row decoder 16, a sense amplifier module 17, and a source line driver 18. Register 13 includes an address register 13-1 and an instruction register 13-2.

[0044] The memory cell array 10 comprises multiple blocks BLK0 to BLKm (where m is an integer greater than or equal to 1). Each BLK is a collection of multiple memory cell transistors capable of non-volatile data storage, serving as a data deletion unit, for example. That is, the data stored in the memory cell transistors within the same BLK is deleted all at once. Detailed configuration of the memory cell array 10 is described below.

[0045] The input / output circuit 11 transmits and receives signals DQ<7:0> with the storage controller 2. The input / output circuit 11 transmits the address ADD and instruction CMD within the signal DQ<7:0> to the address register 13-1 and instruction register 13-2, respectively. In addition, the input / output circuit 11 transmits and receives data DAT with the sense amplifier module 17.

[0046] The logic control circuit 12 receives signals such as / CE, CLE, ALE, / WE, / RE, RE, / WP, DQS, and / DQS from the memory controller 2, and controls the input / output circuit 11 based on the received signals. Additionally, the logic control circuit 12 generates the signal / RB and sends it to the memory controller 2.

[0047] Register 13 stores various signals. Address register 13-1 stores the address ADD transmitted from input / output circuit 11. Address register 13-1 transmits the stored address ADD to line decoder 16 and sense amplifier module 17. Instruction register 13-2 stores the instruction CMD transmitted from input / output circuit 11. Instruction register 13-2 transmits the stored instruction CMD to sequencer 14.

[0048] The sequencer 14 receives instructions CMD from the instruction register 13-2 and controls the entire semiconductor memory device 1 according to the sequence obtained based on the received instructions CMD. For example, when the sequencer 14 receives a delete instruction, a write instruction, and a read instruction, it instructs the voltage generation circuit 15 to generate the voltage used in the corresponding operation.

[0049] The voltage generation circuit 15 generates the voltage used in the delete, write and read operations based on the instruction from the sequencer 14, and supplies the generated voltage to the line decoder 16, the sense amplifier module 17 and the source line driver 18, etc.

[0050] The line decoder 16 receives the block address from the address register 13-1 within the address ADD, and selects one of the blocks BLK0 to BLKm (where m is an integer greater than or equal to 1) based on the block address. The line decoder 16 applies, for example, the voltage supplied from the voltage generation circuit 15 to the selected block BLK.

[0051] The sense amplifier module 17 receives the column address in address ADD from address register 13-1, and based on this column address, transmits data DAT between the memory controller 2 and the memory cell array 10. More specifically, when performing a write operation, the sense amplifier module 17 receives write data from the input / output circuit 11 and transmits the received write data to the memory cell array 10. Additionally, when performing a read operation, the sense amplifier module 17 senses the threshold voltage of the memory cell transistors within the memory cell array 10 that are the targets of the read operation, generates read data, and transmits the generated read data to the input / output circuit 11.

[0052] The source line driver 18 applies a voltage supplied from the voltage generation circuit 15 to the memory cell array 10.

[0053] 1.1.4 Storage Cell Array

[0054] Next, use Figure 3 The configuration of the memory cell array 10 of the semiconductor memory device 1 according to the embodiment will be described. Figure 3 This is an example of a circuit diagram illustrating the configuration of the memory cell array 10 of the semiconductor memory device 1 in the embodiment.

[0055] A block BLK may contain, for example, four string units SU (SU0, SU1, SU2, and SU3). Each string unit SU contains multiple NAND strings NS.

[0056] Each NAND string (NS) has, for example, eight memory cell transistors (MT0 to MT7) and select transistors (ST1 and ST2). Furthermore, the number of memory cell transistors (MT) in each NAND string (NS) is not limited to eight; it can also be 16, 32, 48, 64, 96, 128, etc., with no limit on the number. That is, the number of word lines (WL) contained in the block BLK is not limited to eight; it can also be 16, 32, 48, 64, 96, 128, etc., with no limit on the number. The memory cell transistors (MT) have a stacked gate that includes a control gate and a charge storage layer. Each memory cell transistor (MT) is connected in series between select transistors (ST1 and ST2).

[0057] Within a certain BLK, the gates of the selection transistors ST1 for serial cells SU0 to SU3 are respectively connected to selection gate lines SGD0 to SGD3. Additionally, the gates of the selection transistors ST2 for serial cells SU within the BLK are all connected to the selection gate line SGS. Furthermore, similarly to the selection gate line SGD, the gates of the selection transistors ST2 for serial cells SU0 to SU3 are connected to selection gate lines SGS0 to SGS3 (not shown). The control gates of the memory cell transistors MT0 to MT7 within the same BLK are respectively connected to word lines WL0 to WL7. That is, the word line WL and the selection gate line SGS are all connected to the serial cells SU0 to SU3 within the same BLK. On the other hand, the selection gate line SGD is connected to one serial cell SU within the same BLK.

[0058] Furthermore, in the matrix-arranged NAND strings NS within the memory cell array 10, the other end of the selection transistor ST1 of the NAND string NS located in the same row is connected to any one of the n (n is an integer greater than 2) bit lines BL (BL0 to BL(n-1)). Additionally, the bit lines BL are all connected to the same column of NAND strings NS in multiple blocks BLK.

[0059] Additionally, the other end of the select transistor ST2 is connected to the source line SL. The source line SL is shared by multiple NAND strings NS across multiple blocks BLK.

[0060] As described above, the deletion operation is performed once on a memory cell transistor MT located within the same BLK. On the other hand, the write and read operations can be performed once on multiple memory cell transistors MT that are commonly connected to a word line WL in any string of cells SU of any BLK. A group of memory cell transistors MT that share a word line WL within a string of cells SU is, for example, called a memory cell group MU. That is, a memory cell group MU is a group of memory cell transistors MT that can be written to or read from at once.

[0061] In a memory cell group MU, the unit of a data sequence containing 1 bit of data stored by each of the multiple memory cell transistors MT is defined as a "page". For example, a single memory cell transistor MT can store 2 bits of data. These 2 bits are referred to as the lower bit and the upper bit, starting from the lowest bit. In this case, the memory cell group MU stores 2 pages of data. The set of lower bits stored by each memory cell transistor MT in the memory cell group MU is called the lower page, and the set of upper bits is called the upper page. Furthermore, the memory cell transistor MT is not limited to 2 bits; it can also be configured to store more than 3 bits of data.

[0062] Figure 4 This is a cross-sectional view of a portion of the BLK block. Figure 4 In the diagram, the X direction is the extension direction of the gate line, the Y direction, which is orthogonal to the X direction in the horizontal plane, is the extension direction of the bit line, and the Z direction is the stacking direction.

[0063] A p-well region 30 is provided within the semiconductor layer. Multiple NAND strings NS are disposed on the p-well region 30. That is, on the p-well region 30, a wiring layer 31 functioning as the select gate line (SGS), an 8-layer wiring layer 32 functioning as word lines WL0 to WL7, and a wiring layer 33 functioning as the select gate line (SGD) are sequentially stacked, separated by multiple insulating layers. The accompanying drawing omits illustrations of the multiple insulating layers between the stacked wiring layers to avoid complexity.

[0064] The memory via 34 penetrates the wiring layers 31, 32, and 33 to reach the p-type well region 30. A columnar semiconductor layer (semiconductor pillar) 35 is disposed within the memory via 34. A gate insulating film 36, a charge storage layer (insulating film) 37, and a barrier insulating film 38 are sequentially disposed on the sides of the semiconductor pillar 35. These form the memory cell transistor MT and the select transistors ST1 and ST2. The semiconductor pillar 35 functions as the current path for the NAND string NS, providing the channel for forming each transistor. The upper end of the semiconductor pillar 35 is connected via a contact plug 39 to the metal wiring layer 40, which functions as the bit line BL.

[0065] In the surface region of the p-type well region 30, an n-type impurity with a high concentration of n-type impurities is introduced. + Type diffusion region 41. n + A contact plug 42 is provided on the p-type diffusion region 41, and the contact plug 42 is connected to the metal wiring layer 43, which functions as the source line SL. Furthermore, in the surface region of the p-type well region 30, a p-type impurity-rich material is provided. + Type diffusion region 44. p + A contact plug 45 is provided on the p-type diffusion region 44, and the contact plug 45 is connected to the metal wiring layer 46, which functions as a well wiring CPWELL. The well wiring CPWELL is a wiring used to apply voltage to the semiconductor pillar 35 via the p-type well region 30.

[0066] exist Figure 4 The paper is composed of multiple NAND strings arranged in the depth direction (X direction), and the string unit SU is composed of a set of multiple NAND strings NS arranged along the X direction.

[0067] 1.1.5 Structure of the Voltage Generation Circuit

[0068] Next, use Figure 5 The configuration of the voltage generation circuit 15 of the semiconductor memory device 1 in the embodiment will be described. Figure 5 This is a circuit diagram illustrating an example of the configuration of the voltage generation circuit 15 in the embodiment. Figure 5 An example of the configuration of voltage generation circuit 15 and sequencer 14 is shown.

[0069] The voltage generation circuit 15 is configured to, after receiving the input voltage VIN, output a voltage VOUTL higher than the voltage VIN from the first output terminal and a voltage VOUTH higher than the voltage VOUTL from the second output terminal, based on operations such as data writing, reading, and deletion. The voltage VIN is, for example, a voltage supplied from a voltage source (not shown) inside the semiconductor memory device 1.

[0070] The voltage VOUTL includes, for example, voltages VREAD and VPASS. Voltage VREAD is the voltage applied to the word line WL connected to the memory cell transistor MT other than the read target during a read operation. Voltage VPASS is the voltage applied to the word line WL connected to the memory cell transistor MT other than the write target during a write operation.

[0071] The voltage VOUTH includes, for example, voltages VPGM and VERA. VPGM is the voltage applied to the word line WL, which is connected to the transistor MT of the memory cell being written, during a write operation. VERA is the voltage applied to the source line SL, which is connected to the block BLK being deleted, during an erase operation.

[0072] In the following description, the word line WL connected to the memory cell transistor MT other than the read target and the word line WL connected to the memory cell transistor MT other than the write target are called non-select word lines WL. Conversely, the word line WL connected to the memory cell transistor MT of the read target and the word line WL connected to the memory cell transistor MT of the write target are called select word lines WL.

[0073] The voltage generation circuit 15 includes four charge pumps CP1 (CP1-1, CP1-2, CP1-3, and CP1-4), four charge pumps CP2 (CP2-1, CP2-2, CP2-3, and CP2-4), and transistors T1 to T19. Charge pump CP1 has a higher current supply capability than charge pump CP2. That is, it is configured such that, for a given output voltage, charge pump CP1 can output more current than charge pump CP2. In other words, the maximum value of the current output from the output terminal of charge pump CP1 (maximum output current) is greater than the maximum output current of charge pump CP2. Therefore, for the same output voltage, charge pump CP1 can rapidly raise the voltage of the connected wiring to the voltage output from charge pump CP1 compared to charge pump CP2.

[0074] Charge pump CP1 and charge pump CP2 each have an input terminal and an output terminal. Charge pump CP1 increases the voltage input to its input terminal and outputs it from its output terminal. Charge pump CP2 increases the voltage input to its input terminal and outputs it from its output terminal.

[0075] Transistors T1 to T19 are, for example, each an N-type transistor.

[0076] Input voltage VIN to the input terminal of charge pump CP1-1. The output terminal of charge pump CP1-1 is connected to node N1.

[0077] Terminal 1 of transistor T1 is connected to node N1. Terminal 2 of transistor T1 is connected to node N2.

[0078] Terminal 1 of transistor T2 is connected to node N1. Terminal 2 of transistor T2 is connected to node N3.

[0079] A voltage VIN is input to terminal 1 of transistor T3. Terminal 2 of transistor T3 is connected to node N2.

[0080] The input terminal of charge pump CP1-2 is connected to node N2. The output terminal of charge pump CP1-2 is connected to node N3.

[0081] Input voltage VIN to the input terminal of charge pump CP1-3. The output terminal of charge pump CP1-3 is connected to node N4.

[0082] Terminal 1 of transistor T4 is connected to node N4. Terminal 2 of transistor T4 is connected to node N5.

[0083] Terminal 1 of transistor T5 is connected to node N4. Terminal 2 of transistor T5 is connected to node N6.

[0084] A voltage VIN is input to terminal 1 of transistor T6. Terminal 2 of transistor T6 is connected to node N5.

[0085] The input terminal of charge pump CP1-4 is connected to node N5. The output terminal of charge pump CP1-4 is connected to node N6.

[0086] Terminal 1 of transistor T7 is connected to node N3. Terminal 2 of transistor T7 is connected to node N6.

[0087] Terminal 1 of transistor T8 is connected to node N6. Terminal 2 of transistor T8 is configured to be connected to line decoder 16, for example. Voltage VOUTL is output from terminal 2 of transistor T8.

[0088] A voltage VIN is input to terminal 1 of transistor T9. Terminal 2 of transistor T9 is connected to node N7.

[0089] The input terminal of charge pump CP2-1 is connected to node N7. The output terminal of charge pump CP2-1 is connected to node N8.

[0090] Terminal 1 of transistor T10 is connected to node N8. Terminal 2 of transistor T10 is connected to node N9.

[0091] Terminal 1 of transistor T11 is connected to node N8. Terminal 2 of transistor T11 is connected to node N10. Node N10 is configured, for example, to be connected to the line decoder 16, the sense amplifier module 17, and the source line driver 18. The output voltage VOUTH is from node N10.

[0092] The input of charge pump CP2-2 is connected to node N9. The output of charge pump CP2-2 is connected to node N11.

[0093] Terminal 1 of transistor T12 is connected to node N11. Terminal 2 of transistor T12 is connected to node N12.

[0094] Terminal 1 of transistor T13 is connected to node N11. Terminal 2 of transistor T13 is connected to node N10.

[0095] The input terminal of charge pump CP2-3 is connected to node N12. The output terminal of charge pump CP2-3 is connected to node N13.

[0096] Terminal 1 of transistor T14 is connected to node N13. Terminal 2 of transistor T14 is connected to node N14.

[0097] Terminal 1 of transistor T15 is connected to node N13. Terminal 2 of transistor T15 is connected to node N10.

[0098] The input of charge pump CP2-4 is connected to node N14. The output of charge pump CP2-4 is connected to node N10.

[0099] Terminal 1 of transistor T16 is connected to node N3. Terminal 2 of transistor T16 is connected to node N7.

[0100] Terminal 1 of transistor T17 is connected to node N3. Terminal 2 of transistor T17 is connected to node N9.

[0101] Terminal 1 of transistor T18 is connected to node N6. Terminal 2 of transistor T18 is connected to node N12.

[0102] Terminal 1 of transistor T19 is connected to node N6. Terminal 2 of transistor T19 is connected to node N14.

[0103] The sequencer 14 is configured to control transistors T1 to T19 independently according to the deletion operation, the write operation and the read operation.

[0104] In other words, the voltage generation circuit 15 is configured to change the electrical connections of charge pumps CP1-1 to CP1-4 and CP2-1 to CP2-4 under the control of the sequencer 14, thereby outputting voltages VOUTL and VOUTH corresponding to the delete, write, and read operations. Furthermore, in the following description, the operation of the sequencer 14 controlling transistors T1 to T19 to change the electrical connections of charge pumps CP1-1 to CP1-4 and CP2-1 to CP2-4 is also referred to as a resetting operation. Details regarding the resetting operation are described below.

[0105] 1.1.6 Composition of a charge pump

[0106] An example of the configuration of charge pump CP1 and charge pump CP2 included in voltage generation circuit 15 will be described.

[0107] (charge pump CP1)

[0108] First, use Figure 6 The structure of charge pump CP1 will be explained. Figure 6 This is a circuit diagram illustrating an example of the configuration of the charge pump CP1 in the implementation method.

[0109] The charge pump CP1 includes, for example, transistors DT (DT1 to DT5) and capacitors DC (DC1 to DC4).

[0110] Transistors DT1 to DT5 are, for example, each an N-type transistor.

[0111] A voltage VIN1 is input to terminal 1 and gate of transistor DT1. Terminal 2 of transistor DT1 is connected to node ND1.

[0112] Terminal 1 and gate of transistor DT2 are connected to node ND1. Terminal 2 of transistor DT2 is connected to node ND2.

[0113] Terminal 1 and gate of transistor DT3 are connected to node ND2. Terminal 2 of transistor DT3 is connected to node ND3.

[0114] Terminal 1 and gate of transistor DT4 are connected to node ND3. Terminal 2 of transistor DT4 is connected to node ND4.

[0115] Terminal 1 and gate of transistor DT5 are connected to node ND4. A voltage VOUT1 higher than voltage VIN1 is output from terminal 2 of transistor DT5.

[0116] Terminal 1 of capacitor DC1 is connected to node ND1. A clock signal CLKD is input to terminal 2 of capacitor DC1.

[0117] Terminal 1 of capacitor DC2 is connected to node ND2. A clock signal / CLKD is input to terminal 2 of capacitor DC2.

[0118] Terminal 1 of capacitor DC3 is connected to node ND3. A clock signal CLKD is input to terminal 2 of capacitor DC3.

[0119] Terminal 1 of capacitor DC4 is connected to node ND4. A clock signal / CLKD is input to terminal 2 of capacitor DC4.

[0120] The clock signal / CLKD is, for example, the inverted signal of the clock signal CLKD. During the period when the clock signal CLKD is at a "H" level, nodes ND1 and ND3 (terminals 1 and 1 of capacitor DC1 and capacitor DC3) are boosted. During the period when the clock signal / CLKD is at a "H" level, nodes ND2 and ND4 (terminals 1 and 1 of capacitor DC2 and capacitor DC4) are boosted.

[0121] In the charge pump CP1 described above, the configuration comprising one transistor DTi (i being an integer between 1 and 4) and one capacitor DCi is referred to as stage Stg1 (Stg1-1 to Stg1-4). In stage Stg1-i, the potential of the second terminal of transistor DTi rises due to the charging of capacitor DCi. Consequently, when i is an integer between 1 and 3, the potential of the first terminal of transistor DT(i+1) in the next stage Stg1-(i+1) rises. Furthermore, when i is 4, the potential of the first terminal of transistor DT5 rises to the voltage (VOUT1+Vth) obtained by adding voltage VOUT1 and threshold voltage Vth of transistor DT5. Thus, stage Stg1 functions as a unit for raising the voltage input to charge pump CP1.

[0122] The output voltage VOUT1 from the second terminal of transistor DT5 is reduced due to the threshold voltage Vth of transistor DT5.

[0123] Furthermore, although the charge pump CP1 in this embodiment includes four steps Stg1-1 to Stg1-4, the number of steps Stg1 included in the charge pump CP1 in this embodiment is not limited to this. The number of steps Stg1 can also be two, three, or five or more, and can be varied according to the target value of the rising voltage, etc. In this case, a clock signal CLKD is input to the second terminal of the capacitor DCia (where ia is an odd number of 1 or more). Additionally, a clock signal / CLKD is input to the second terminal of the capacitor DCib (where ib is an even number of 2 or more).

[0124] Regarding the charge pump CP1 with the above configuration, the boost gain VOUT1 / VIN1 may change depending on the voltage VIN1 input to the charge pump CP1. For example, the higher the voltage VIN1 input to the charge pump CP1, the lower the boost gain VOUT1 / VIN1 of the charge pump CP1 will be.

[0125] More specifically, in each Stg1 stage of charge pump CP1, a voltage drop occurs due to the threshold voltage of transistor DTi. Therefore, if the number of Stg1 stages of charge pump CP1 is increased in order to increase voltage VOUT1, the effect of the voltage drop caused by the threshold voltage of transistor DTi will become greater due to the increased number of transistors DTi.

[0126] Furthermore, for example, if the potential at the second terminal of transistor DTi in charge pump CP1 becomes higher, the threshold voltage of each transistor DTi will become higher due to the substrate bias effect. Therefore, if voltage VOUT1 is set to a high voltage, the voltage drop caused by the threshold voltage of each transistor DTi will also become greater.

[0127] Therefore, on the high-voltage side, the voltage drop caused by the threshold voltage of transistor DTi becomes more significant, making it difficult for charge pump CP1 to output voltages higher than, for example, voltage VOUTL. In other words, for example, if voltage VOUT1 is higher than voltage VOUTL, the boost gain VOUT1 / VIN1 of charge pump CP1 will be significantly reduced, making it difficult to generate voltage efficiently.

[0128] (charge pump CP2)

[0129] Secondly, use Figure 7 The structure of charge pump CP2 will be explained. Figure 7 This is a circuit diagram illustrating an example of the configuration of the charge pump CP2 in the implementation method.

[0130] The charge pump CP2 includes, for example, transistors VtT (VtT1 to VtT6 and VtTa to VtTc) and capacitors VtC (VtC1 to VtC4 and VtCa).

[0131] Transistors VtT1~VtT6 and VtTa~VtTc are, for example, each an N-type transistor.

[0132] A voltage VIN2 is input to terminal 1 of transistor VtT1. Terminal 2 of transistor VtT1 is connected to node NV1. The gate of transistor VtT1 is connected to node NV2.

[0133] A voltage VIN2 is input to terminal 1 of transistor VtT2. Terminal 2 of transistor VtT2 is connected to node NV2. The gate of transistor VtT2 is connected to node NV1.

[0134] A voltage VIN2 is input to the first terminal and gate of transistor VtT3. The second terminal of transistor VtT3 is connected to node NV2.

[0135] Terminal 1 of capacitor VtC1 is connected to node NV1. Clock signal CLKV1 is input to terminal 2 of capacitor VtC1.

[0136] Terminal 1 of capacitor VtC2 is connected to node NV2. Clock signal CLKV2 is input to terminal 2 of capacitor VtC2.

[0137] Terminal 1 of transistor VtT4 is connected to node NV1. Terminal 2 of transistor VtT4 is connected to node NV3. The gate of transistor VtT4 is connected to node NV4.

[0138] Terminal 1 of transistor VtT5 is connected to node NV1. Terminal 2 of transistor VtT5 is connected to node NV4. The gate of transistor VtT5 is connected to terminal 2 of transistor VtT4.

[0139] Terminal 1 and gate of transistor VtT6 are connected to node NV1. Terminal 2 of transistor VtT6 is connected to node NV4.

[0140] Terminal 1 of capacitor VtC3 is connected to node NV3. Clock signal CLKV3 is input to terminal 2 of capacitor VtC3.

[0141] Terminal 1 of capacitor VtC4 is connected to node NV4. Clock signal CLKV4 is input to terminal 2 of capacitor VtC4.

[0142] Terminal 1 of transistor VtTa is connected to node NV3. Terminal 2 of transistor VtTa outputs a voltage VOUT2 that is higher than voltage VIN2. The gate of transistor VtTa is connected to node NVa.

[0143] Terminal 1 of transistor VtTb is connected to node NV3. Terminal 2 of transistor VtTb is connected to node NVa. The gate of transistor VtTb is connected to terminal 2 of transistor VtTa.

[0144] Terminal 1 and gate of transistor VtTc are connected to node NV3. Terminal 2 of transistor VtTc is connected to node NVa.

[0145] Terminal 1 of capacitor VtCa is connected to node NVa. Clock signal CLKV5 is input to terminal 2 of capacitor VtCa.

[0146] Clock signal CLKV3 is, for example, the inverted signal of clock signal CLKV1. Clock signal CLKV4 becomes an "H" level signal for a shorter period than the clock period of clock signal CLKV1 during the period when clock signal CLKV1 is at an "H" level. Clock signal CLKV5 becomes an "H" level signal for a shorter period than the clock period of clock signal CLKV3 during the period when clock signal CLKV3 is at an "H" level. Clock signal CLKV2 is, for example, the same signal as clock signal CLKV5. During the period when clock signal CLKV1 is at an "H" level, terminal 1 of capacitor VtC1 (node ​​NV1) is boosted. During the period when clock signal CLKV2 is at an "H" level, terminal 1 of capacitor VtC2 (node ​​NV2) is boosted. During the period when clock signal CLKV3 is at an "H" level, terminal 1 of capacitor VtC3 (node ​​NV3) is boosted. During the period when clock signal CLKV4 is at the "H" level, terminal 1 of capacitor VtC4 (node ​​NV4) is boosted. During the period when clock signal CLKV5 is at the "H" level, terminal 1 of capacitor VtCa (node ​​NVa) is boosted.

[0147] In the charge pump CP2 described above, the configuration comprising three transistors VtT(3j-2), VtT(3j-1), and VtT(3j) (j being 1 or 2), and two capacitors VtC(2j-1) and VtC(2j) is called order Stg2 (Stg2-1 and Stg2-2). In order Stg2-j, the charge (voltage) at the first terminal of the boosted capacitor VtC(2j-1) is boosted by the first terminal of the capacitor VtC(2(j+1)) of the next order Stg2-(j+1), and then transferred to node NV(2j+1) via the transistor VtT(3j+1) of the next order Stg2-(j+1). Furthermore, in step Stg2-1, the voltage VIN2, which has been input to the first terminals of transistors VtT1, VtT2, and VtT3, is boosted by the first terminal of capacitor VtC2 and then transferred to node NV1 via transistor VtT1. Additionally, in step Stg2-2, the charge (voltage VOUT2) at the first terminal of capacitor VtC3, after being boosted, is output from charge pump CP2 via transistor VtTa by the first terminal of capacitor VtCa. Here, unlike charge pump CP1, the voltage drop caused by the threshold voltages of transistors VtT(3j+1), VtT1, and VtTa is essentially negligible. Thus, step Stg2 functions as a unit for boosting the voltage input to charge pump CP2.

[0148] The voltage VOUT2 at the first terminal of transistor VtTa, boosted in the manner described above, is output from the second terminal of transistor VtTa through the boosting effect of the first terminal of capacitor VtCa.

[0149] Furthermore, although the charge pump CP2 in this embodiment includes two Stg2 steps, the number of Stg2 steps included in the charge pump CP2 in this embodiment is not limited to this. The number of Stg2 steps can also be three or more, and can be varied according to the target value of the rising voltage, etc. In this case, a clock signal CLKV1 is input to the second terminal of the capacitor VtC(2ja-1) (ja is an odd number of 1 or more). In addition, a clock signal CLKV1 is input to the second terminal of the capacitor VtC(2ja). In addition, a clock signal CLKV3 is input to the second terminal of the capacitor VtC(2jb-1) (jb is an even number of 2 or more). In addition, a clock signal CLKV4 is input to the second terminal of the capacitor VtC(2jb).

[0150] Regarding the charge pump CP2 with the above configuration, as mentioned above, unlike charge pump CP1, the voltage drop caused by the transistor's threshold voltage can be ignored. Therefore, even if the output voltage VOUT2 of charge pump CP2 is, for example, higher than the voltage VOUTL, it can efficiently increase the voltage, resulting in an output voltage VOUT2 that is higher than the voltage VOUT1 of charge pump CP1. For example, when the voltage VOUT2 output from charge pump CP2 is higher than the voltage VOUTL, the boost gain VOUT2 / VIN2 of charge pump CP2 is greater than the boost gain VOUT1 / VIN1 of charge pump CP1 when the voltage VOUT1 output from charge pump CP1 is higher than the voltage VOUTL.

[0151] Thus, while charge pump CP1, with its simple structure, offers high current supply capability at low voltages, its boost gain at high voltages is small due to the voltage drop caused by the threshold voltage of the transistor CT at each Stg1 stage. On the other hand, charge pump CP2, with its more complex circuitry than charge pump CP1, offers lower current supply capability, but its boost gain is large even at high voltages because the voltage drop caused by the transistor threshold voltage is practically negligible. The voltage generation circuit 15, by combining these two charge pumps CP1 and CP2 with their different characteristics, can efficiently generate the voltage required for various operations.

[0152] 1.2 Actions

[0153] Next, the operations performed using the semiconductor memory device 1 of this embodiment will be described. Examples of deletion, writing, and reading operations will be described below.

[0154] Furthermore, in the following description, the word line WL and string cell SU corresponding to the memory cell transistor MT that is the target of a write operation or a read operation will be referred to as the selected word line WL and the selected string cell SU, respectively. Additionally, the word line WL and string cell SU corresponding to the memory cell transistor MT that is not the target of a write operation or a read operation will be referred to as the non-selected word line WL and the non-selected string cell SU, respectively.

[0155] Here, when the number of word lines WL contained in the block BLK is set to n (e.g., 8, 16, 32, 48, 64, 96, 128, etc.), the selected word line in the write or read operation becomes 1, and the non-selected word line becomes n-1.

[0156] 1.2.1 Deletion Action

[0157] First, an example of the deletion operation in this embodiment will be described. The deletion operation includes: applying a voltage to the source line SL and the bit line BL to lower the threshold voltage of the memory cell transistor MT (hereinafter also referred to as the deletion voltage application operation); and a deletion verification operation, which determines whether the threshold voltage of the memory cell transistor MT has become lower than the target voltage after the deletion voltage application operation. The semiconductor memory device 1 makes the threshold voltage of the memory cell transistor MT lower than the target voltage by repeatedly combining the deletion voltage application operation and the deletion verification operation.

[0158] Furthermore, in the following description, the explanation of the verification action of deletion is omitted, and the example of performing one deletion voltage application action and the voltage supplied by the voltage generation circuit 15 when performing the deletion voltage application action are mainly described.

[0159] 1.2.1.1 Voltage of each wiring line when performing the voltage deletion action

[0160] use Figure 8 An example of the deletion voltage application operation in this embodiment will be described. Figure 8 This is a timing diagram representing an example of the voltage across each wiring when the voltage removal operation is performed.

[0161] At time t11, the source line driver 18 applies a voltage VERA to the source line SL.

[0162] In addition, the sensing amplifier module 17 applies a voltage VERA to the bit line BL contained in the block BLK, which is the target of the deletion action.

[0163] Additionally, the line decoder 16 applies a voltage VWLE to the word lines WL contained in the block BLK, which is the target of the deletion operation. The voltage VWLE is, for example, a voltage higher than VSS and lower than VRA. However, it is not limited to this; the voltage VWLE can also be a voltage lower than VSS.

[0164] At time t12, the line decoder 16 applies voltage VSGE to the select gate lines SGS and SGD of the block BLK, which is the target of the deletion operation. Voltage VSGE is a voltage higher than voltage VWLE but lower than voltage VERA.

[0165] Through these actions, electron hole pairs are generated in the selection transistors ST1 and ST2 contained in the block BLK, which is the target of the deletion action, by utilizing GIDL (Gate-Induced Drain Leakage).

[0166] More specifically, on the select transistor ST1 side of the NAND string NS, a GIDL current (hereinafter also referred to as BL-side GIDL current) flows from the bit line BL to the select transistor ST1 through the voltage VERA already applied to the bit line BL. Additionally, on the select transistor ST2 side of the NAND string NS, a GIDL current (hereinafter also referred to as SL-side GIDL current) flows from the source line SL to the select transistor ST2. Through these GIDL currents, the electrons of the generated electron-hole pairs move towards the outer side of the NAND string NS channel, i.e., the source line SL and the bit line BL, while the holes move towards the inner side of the NAND string NS channel.

[0167] Semiconductor memory device 1 injects holes into the charge storage layer by raising the potential within the channels of the NAND string NS through holes generated in the manner described above. Semiconductor memory device 1 then causes the injected holes to recombine with electrons already injected into the charge storage layer of the memory cell transistor MT via write operations, thereby causing the electrons to disappear from the charge storage layer of the NAND string's memory cell transistor MT. As a result, the threshold voltage of the NAND string's memory cell transistor MT decreases.

[0168] At time t13, the line decoder 16 applies voltage VSS to the word line WL, as well as the select gate lines SGS and SGD.

[0169] In addition, the sensing amplifier module 17 applies a voltage VSS to the bit line BL.

[0170] Additionally, the source line driver 18 applies a voltage VSS to the source line SL.

[0171] At this point, the voltage application removal process is complete.

[0172] Furthermore, although the description refers to the case where voltage VSGE is applied to the select gate lines SGS and SGD at time t12, it is not limited to this. The voltages applied to the select gate lines SGS and SGD can be any voltage that allows the GIDL current to flow, and they can also be different voltages.

[0173] 1.2.1.2 Remove the resetting action in the voltage application process.

[0174] use Figure 9 The generation of the voltage VERA applied to the source line SL and bit line BL during the execution of the deletion voltage application operation is explained. Figure 9 This diagram illustrates the rebalancing operation of the voltage generation circuit 15 when the deletion voltage is applied during the deletion operation of the semiconductor memory device 1 in the embodiment of the application method.

[0175] Furthermore, in the following description, the voltages output from charge pumps CP1-1, CP1-2, CP1-3, and CP1-4 will be referred to as voltages VOUT1-1, VOUT1-2, VOUT1-3, and VOUT1-4, respectively. Additionally, the voltages output from charge pumps CP2-1, CP2-2, CP2-3, and CP2-4 will be referred to as voltages VOUT2-1, VOUT2-2, VOUT2-3, and VOUT2-4, respectively.

[0176] During the resetting operation when the deletion voltage is applied, sequencer 14 turns on transistors T1, T4, T11, T13, T15, T16, T17, T18, and T19, and turns off transistors T2, T3, T5, T6, T7, T8, T9, T10, T12, and T14. Figure 9 In the diagram, transistors that will be in the ON state are marked with an "〇" symbol, and transistors that will be in the OFF state are marked with an "×" symbol.

[0177] Through the above rebalancing process, in the voltage generation circuit 15, charge pumps CP1-1 and CP1-2 are connected in series. Charge pumps CP2-1 and CP2-2 are connected in parallel to the output terminal of charge pump CP1-2.

[0178] In addition, charge pumps CP1-3 and CP1-4 are connected in series. Charge pumps CP2-3 and CP2-4 are connected in parallel to the output terminal of charge pump CP1-4.

[0179] The output terminals of charge pumps CP2-1, CP2-2, CP2-3 and CP2-4 are connected in a common manner.

[0180] A voltage VIN is input to the input terminal of charge pump CP1-1. Charge pump CP1-1 raises the input voltage VIN to voltage VOUT1-1 and outputs it to the input terminal of charge pump CP1-2. Charge pump CP1-2 raises the input voltage VOUT1-1 to voltage VOUT1-2 and outputs it to the respective input terminals of charge pumps CP2-1 and CP2-2. Charge pumps CP2-1 and CP2-2 raise the voltage VOUT1-2, which has been input to their respective input terminals, to voltages VOUT2-1 and VOUT2-2, respectively, and output them to node N10.

[0181] Additionally, a voltage VIN is input to the input terminal of charge pump CP1-3. Charge pump CP1-3 raises the input voltage VIN to voltage VOUT1-3 and outputs it to the input terminal of charge pump CP1-4. Charge pump CP1-4 raises the input voltage VOUT1-3 to voltage VOUT1-4 and outputs it to the respective input terminals of charge pumps CP2-3 and CP2-4. Charge pumps CP2-3 and CP2-4 raise the voltage VOUT1-4, which has been input to the respective input terminals of charge pumps CP2-3 and CP2-4, to voltages VOUT2-3 and VOUT2-4, respectively, and output them to node N10. From node N10, a voltage VERA (VOUTH) based on voltages VOUT2-1, VOUT2-2, VOUT2-3, and VOUT2-4 is output to the sense amplifier module 17 and the source line driver 18.

[0182] In the manner described above, the sequencer 14 controls the supply of voltage VERA to the source line SL and the bit line BL contained in the block BLK which is the target of the deletion operation.

[0183] 1.2.2 Write Action

[0184] Next, a brief explanation of an example of the writing operation in this embodiment will be given.

[0185] The write operation includes a programming operation and a write verification operation. The programming operation is the process of increasing the threshold voltage by injecting electrons into the charge storage layer (or maintaining the threshold voltage by inhibiting electron injection). The write verification operation is the process of reading data after the programming operation and determining whether the threshold voltage of the memory cell transistor MT has reached the target voltage. The semiconductor memory device 1 increases the threshold voltage of the memory cell transistor MT to the target voltage by repeatedly performing the programming operation and the write verification operation.

[0186] In the following description, the verification action related to the write is omitted, and the example of performing one programming action is mainly described, as well as the voltage supplied by the voltage generation circuit 15 when the programming action is performed.

[0187] 1.2.2.1 Programming Actions

[0188] use Figure 10 The programming actions in this implementation method will be explained. Figure 10 This is a timing diagram illustrating an example of the voltage of each wiring when a semiconductor memory device using the implementation method performs a programming operation.

[0189] Hereinafter, the action that raises the threshold voltage of the memory cell transistor MT will be called the "'0' programming action", and the action that maintains the threshold voltage of the memory cell transistor MT will be called the "'1' programming action".

[0190] exist Figure 10 In the voltage of bit line BL shown in the upper section, the solid line corresponds to the bit line BL (hereinafter referred to as bit line BL("1")) corresponding to the memory cell transistor MT which is programmed as "1". The dashed line corresponds to the bit line BL (hereinafter referred to as bit line BL("0")) corresponding to the memory cell transistor MT which is programmed as "0".

[0191] At time t21, the sensing amplifier module 17 applies voltage VBL to bit line BL (“1”) to precharge BL. On the other hand, voltage VSS is applied to bit line BL (“0”).

[0192] Furthermore, the line decoder 16 selects any one block BLK from multiple block BLKs, and then selects any one string unit SU from multiple string units SU. Then, the line decoder 16 applies a selection gate line SGD ( Figure 10 A voltage VSD1 is applied to the selection gate line SGD (selection SGD). If the threshold voltage of the selection transistor ST1 is set to Vtsg, then the voltage VSD1 is a voltage greater than "VBL + Vtsg", which is the voltage that turns the selection transistor ST1 on. On the other hand, the line decoder 16 applies a voltage VSD1 to the selection gate line SGD (selection gate line of the non-selection string unit SU). Figure 10 A voltage VSS is applied to the non-select SGD, causing the corresponding selection transistor ST1 to be turned off. Additionally, the line decoder 16 applies a voltage VSS to the selection gate line SGS, causing the selection transistor ST2 to be turned off.

[0193] In addition, the source line driver 18 applies a voltage VSL (>VSS) to the source line SL.

[0194] At time t22, the line decoder 16 reduces the voltage applied to the select gate line SGD of the select string unit SU from voltage VSD1 to voltage VSD2. Voltage VSD2 is lower than voltage VSD1 and voltage VBL, which is the voltage that turns on the select transistor ST1 for bit line BL when voltage VSS is applied, but turns off the select transistor ST1 for bit line BL when voltage VBL is applied. Therefore, the channel of the NAND string NS corresponding to bit line BL ("1") becomes a floating state electrically isolated from bit line BL and source line SL.

[0195] By changing the voltage of bit line BL in the manner described, a "0" programming action and a "1" programming action can be set for each bit line BL in the same programming action.

[0196] At time t23, line decoder 16 selects any word line WL from selection block BLK, and performs a selection on word line WL ( Figure 10Apply voltage VPGM to select word line WL, and apply voltage VPGM to other non-select word lines WL. Figure 10 The voltage VPASS is applied to the non-selected WL.

[0197] In the NAND string NS corresponding to bit line BL (“0”), the select transistor ST1 is turned on. Then, the channel potential of the memory cell transistor MT connected to the select word line WL becomes VSS. As a result, the potential difference (VPGM - VSS) between the control gate and the channel increases, and as a result, electrons are injected into the charge storage layer, and the threshold voltage of the memory cell transistor MT rises.

[0198] In the NAND string NS corresponding to bit line BL (“1”), the select transistor ST1 becomes off. Therefore, the channel of the memory cell transistor MT connected to the select word line WL becomes floating. Then, through capacitive coupling between the channel and word line WL, the channel potential rises. As a result, the potential difference between the control gate and the channel decreases, and consequently, almost no electrons are injected into the charge storage layer, and the threshold voltage of the memory cell transistor MT remains unchanged.

[0199] At time t24, the line decoder 16 applies voltage VSS to the select word line WL and the non-select word line WL. This completes the charge injection into the charge storage layer.

[0200] At time t25, the line decoder 16 applies voltage VSS to the select gate line SGD.

[0201] In addition, the sensing amplifier module 17 applies a voltage VSS to the bit line BL.

[0202] Additionally, the source line driver 18 applies a voltage VSS to the source line SL.

[0203] The programming process is now complete.

[0204] also, Figure 10 Ultimately, this is merely one example of the timing diagram for the programming operations in this embodiment. The magnitudes of the voltages applied to the bit line BL, word line WL, source line SL, and select gate lines SGS and SGD may not necessarily correspond to the actual implementation. Figure 10 The magnitudes of the voltages shown are consistent. For example, Figure 10 The diagram is presented with voltages VBL and VSD2 being equal, but voltages VBL and VSD2 can also be different.

[0205] 1.2.2.2 Reorganization Action in Programming Actions

[0206] use Figure 11 The generation of voltages VPASS and VPGM applied to the word line WL during programming operations is explained. Figure 11This diagram illustrates the rebalancing operation of the voltage generation circuit 15 when the semiconductor memory device 1 performs a programming operation during a write operation in an embodiment of the application.

[0207] During the resetting operation when executing programming actions, sequencer 14 turns on transistors T2, T3, T5, T6, T7, T8, T9, T10, T12, and T14, and turns off transistors T1, T4, T11, T13, T15, T16, T17, T18, and T19. Figure 11 In the diagram, transistors that will be in the ON state are marked with an "〇" symbol, and transistors that will be in the OFF state are marked with an "×" symbol.

[0208] Through the above rebalancing process, in the voltage generation circuit 15, charge pumps CP1-1, CP1-2, CP1-3, and CP1-4 are connected in parallel. The output terminals of each charge pump CP1-1, CP1-2, CP1-3, and CP1-4 are connected in common.

[0209] In addition, in the voltage generation circuit 15, charge pumps CP2-1, CP2-2, CP2-3 and CP2-4 are connected in series in sequence.

[0210] A voltage VIN is input to the respective input terminals of charge pumps CP1-1 to CP1-4. Charge pumps CP1-1 to CP1-4 raise the input voltage VIN to voltages VOUT1-1 to VOUT1-4, and output them to terminal 1 of transistor T8. A voltage VPASS (VOUTL) based on voltages VOUT1-1 to VOUT1-4 is supplied to the line decoder 16 from terminal 2 of transistor T8.

[0211] Additionally, a voltage VIN is input to the input terminal of charge pump CP2-1 via transistor T9. Charge pump CP2-1 raises the input voltage VIN to voltage VOUT2-1 and outputs it to the input terminal of charge pump CP2-2. Charge pump CP2-2 raises the input voltage VOUT2-1 to voltage VOUT2-2 and outputs it to the input terminal of charge pump CP2-3. Charge pump CP2-3 raises the input voltage VOUT2-2 to voltage VOUT2-3 and outputs it to the input terminal of charge pump CP2-4. Charge pump CP2-4 raises the input voltage VOUT2-3 to voltage VPGM(VOUTH) and outputs it to the line decoder 16.

[0212] In the manner described above, the sequencer 14 controls the supply of voltage VPGM to the select word line WL and voltage VPASS to the non-select word line WL.

[0213] 1.2.3 Reading Action

[0214] First, an example of the read operation in this embodiment will be described. Furthermore, for the sake of simplicity, the following description will focus on the case where 1 bit of data is read in a single read operation.

[0215] 1.2.3.1 Voltage of each wiring line during the readout operation

[0216] use Figure 12 The voltage of each wiring is explained when the read operation is performed. Figure 12 This is a timing diagram showing an example of the voltage across each wiring line during a readout operation.

[0217] At time t31, the line decoder 16 pairs of selection gate lines SGD (corresponding to the selection string unit SU) are executed. Figure 12 The voltage VSGD is applied to the selection gate line (SGD) corresponding to the non-selected string unit SU. Additionally, the line decoder 16 applies a voltage VSGD to the selection gate line (SGD) corresponding to the non-selected string unit SU. Figure 12 The non-selection SGD is connected to a voltage VSS. Additionally, the line decoder 16 applies a voltage equal to VSGD to the selection gate line SGS. VSGD is the voltage applied to the selection gate lines SGD and SGS during readout, causing the corresponding selection transistors ST1 and ST2 to be turned on. Consequently, selection transistors ST1 and ST2 of the selection string unit SU are turned on, while selection transistor ST1 of the non-selection string unit SU is turned off.

[0218] Additionally, the line decoder has 16 pairs of non-select word lines WL ( Figure 12 Apply voltage VREAD to the non-select word line WL, and apply voltage VREAD to the select word line WL. Figure 12 A voltage VCGRV is applied to the non-select word line WL during a read operation. The voltage VREAD is higher than VCGRV (VREAD > VCGRV). VREAD is the voltage applied to the non-select word line WL during a read operation, causing the corresponding memory cell transistor MT to be turned on. VCGRV is the voltage corresponding to the threshold voltage of the memory cell transistor MT targeted for the read operation. More specifically, for example, if the threshold voltage of the memory cell transistor MT targeted for the read operation is higher than VCGRV, the memory cell transistor MT is turned off; if the threshold voltage is lower than VCGRV, the memory cell transistor MT is turned on.

[0219] At time t32, the sensing amplifier module 17 makes the potential of the bit line BL a voltage VBL. The voltage VBL is, for example, a voltage lower than the voltage VCGRV (VCGRV > VBL).

[0220] At time t33, the line decoder 16 applies voltage VSS to the select gate line SGD and select gate line SGS corresponding to the select word line WL and non-select word line WL, select string unit SU and non-select string unit SU.

[0221] In addition, the sensing amplifier module 17 applies a voltage VSS to the bit line BL.

[0222] Through the above actions, data is read from the memory cell transistor MT corresponding to the selection word line WL of the selection string unit SU.

[0223] also, Figure 12 Ultimately, this is merely one example of the timing diagram for the readout operation in this embodiment, and the magnitudes of the voltages applied to the bit line BL, word line WL, source line SL, and select gate line SGD may not necessarily correspond to the actual implementation. Figure 12 The magnitudes of the voltages shown are consistent. For example, Figure 12 The diagram is drawn with voltages VREAD and VSGD being equal, but voltages VREAD and VSGD can also be different.

[0224] 1.2.3.2 Generation of voltage applied to the word line during read operation

[0225] use Figure 13 The generation of the voltage VREAD applied to the word line WL during the read operation is explained. Figure 13 This diagram illustrates the generation of voltage VREAD by voltage generation circuit 15 when the semiconductor memory device 1 performs a read operation according to the usage embodiment.

[0226] During the resetting operation when performing the readout action, sequencer 14 turns on transistors T2, T3, T5, T6, T7, and T8, and turns off transistors T1, T4, and T9 to T19. Figure 13 In the diagram, transistors that will be in the ON state are marked with an "〇" symbol, and transistors that will be in the OFF state are marked with an "×" symbol.

[0227] Through the above rebalancing process, in the voltage generation circuit 15, charge pumps CP1-1, CP1-2, CP1-3, and CP1-4 are connected in parallel. The output terminals of each charge pump CP1-1, CP1-2, CP1-3, and CP1-4 are connected in common.

[0228] In addition, charge pumps CP2-1 to CP2-4 are electrically insulated from the voltage source supplying voltage VIN and charge pump CP1.

[0229] A voltage VIN is input to the respective input terminals of charge pumps CP1-1 to CP1-4. Charge pumps CP1-1 to CP1-4 raise the input voltage VIN to voltages VOUT1-1 to VOUT1-4, respectively, and output them to terminal 1 of transistor T8. From terminal 2 of transistor T8, a voltage VREAD (VOUTL) based on voltages VOUT1-1 to VOUT1-4 is output to the line decoder 16.

[0230] In addition, when performing a read operation, the slave node N10 does not output voltage VOUTH.

[0231] In the manner described above, the sequencer 14 controls the supply of voltage VREAD to the non-selection word line WL.

[0232] 1.3 Effects

[0233] According to this embodiment, the increase in the area of ​​the voltage generating circuit 15 and the increase in the current consumed by the voltage generating circuit 15 can be suppressed. The effects of the embodiment will be explained below.

[0234] The voltage generation circuit 15 is configured to electrically disconnect charge pump CP1 and charge pump CP2 during read and write operations. Specifically, charge pump CP1 is primarily used to generate the voltages VREAD and VPASS supplied to the n-1 non-select word lines WL within the n word lines (e.g., 8, 16, 32, 48, 64, 96, 128, etc.) contained in the block BLK. Additionally, charge pump CP2 is primarily used to generate the voltage VPGM supplied to the single select word line WL. This allows for efficient voltage generation.

[0235] To elaborate, charge pump CP1, due to the voltage drop caused by the threshold voltages of each transistor's current transformer (CT), has a lower boost gain in the high-voltage region compared to charge pump CP2, but it has a higher current supply capability in the low-voltage region. Therefore, it is advantageous for generating voltages like VREAD and VPASS, which, although relatively low, have a large capacitive load on the charged object. On the other hand, charge pump CP2, with its more complex structure than charge pump CP1, has a lower current supply capability than charge pump CP1, but since the voltage drop caused by the threshold voltages of each transistor's current transformer (VtT) is practically negligible, it has a higher boost gain in the high-voltage region than charge pump CP1. Therefore, it is advantageous for generating voltages like VPGM, which, although relatively high, have a small capacitive load on the charged object.

[0236] According to this embodiment, the voltage generation circuit 15 uses charge pump CP1 and charge pump CP2 separately during the read and write operations to generate voltages that conform to their respective characteristics. This suppresses the increase in current consumption and circuit area of ​​the voltage generation circuit 15.

[0237] Furthermore, the voltage generation circuit 15 is configured such that, during the deletion operation, the output terminal of charge pump CP1 is electrically connected to the input terminal of charge pump CP2. Specifically, during the deletion operation, the voltage generation circuit 15 uses charge pump CP1 for boosting in the low-voltage region and charge pump CP2 for boosting in the high-voltage region, and combines them to generate voltage VERA. Thus, by connecting charge pump CP1 and charge pump CP2 in series, a high current supply capability of charge pump CP1 can be obtained in the high-voltage region (when generating voltage VERA). Therefore, a high voltage, namely voltage VERA, can be supplied to the object being charged, given its large capacitive load. Additionally, charge pumps CP1 and CP2 used in the write and read operations can be utilized. Therefore, the potential reduction in boost gain when using charge pump CP1 for boosting in the high-voltage region can be avoided. Consequently, the increase in current consumption and circuit area of ​​the voltage generation circuit 15 can be suppressed.

[0238] Furthermore, when performing the deletion operation, the voltage generation circuit 15 connects the input terminals of charge pumps CP2-1 and CP2-2 together to the output terminal of charge pump CP1-2. Similarly, when performing the deletion operation, the voltage generation circuit 15 connects the input terminals of charge pumps CP2-3 and CP2-4 together to the output terminal of charge pump CP1-4. By connecting the input terminals of two charge pumps CP2 in parallel to the output terminal of one charge pump CP1, a higher current supply capability can be obtained (compensating for the low current supply capability of charge pump CP2) compared to connecting only one charge pump CP2 to the output terminal of charge pump CP1.

[0239] 2 Other

[0240] Furthermore, the configurations of charge pumps CP1 and CP2 are not limited to the examples described in the embodiments. For example, as charge pump CP1, a charge pump with a higher current supply capability than charge pump CP2 can be used. In addition, as charge pump CP2, a charge pump that does not significantly change the boost gain when the output voltage is below VERA can be used, for example.

[0241] More specifically, the charge pump CP1 may also include, for example, a transistor with a three-layer structure, which includes a P-type substrate, an N-type embedding layer embedded in the substrate, and a P-type well formed in the embedding layer.

[0242] When using a transistor with a three-layer structure for boosting in high-voltage regions, the substrate thickness may need to be increased to suppress leakage current, such as that flowing from the N-type embedding layer to the outside of the substrate. However, the increase in substrate thickness is limited by the semiconductor memory device 1 that increases with storage capacity, and is therefore not preferred.

[0243] According to this embodiment, during the deletion operation, the charge pump CP1 can be used for boosting in the low-voltage region. Therefore, the generation of leakage current can be substantially ignored, thereby suppressing the increase in substrate thickness. In addition, by using a transistor with a 3-layer structure, the effect of voltage drop caused by the substrate potential surface on the transistor's threshold voltage can be suppressed, thus suppressing the reduction in boost gain of the charge pump CP1.

[0244] In addition, the charge pumps CP1 and CP2 in the embodiment can be respectively located in physically different areas within the voltage generation circuit 15.

[0245] Furthermore, the embodiments described above are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

[0246] [Explanation of Symbols]

[0247] 1. Semiconductor memory device

[0248] 2 Storage Controller

[0249] 3. Memory System

[0250] 4. Main unit

[0251] 10-cell array

[0252] 11 Input / Output Circuit

[0253] 12 Logic Control Circuit

[0254] 13 Registers

[0255] 13-1 Address Register

[0256] 13-2 Instruction Register

[0257] 14 Sequencer

[0258] 15 Voltage Generation Circuit

[0259] 16-line decoder

[0260] 17. Sensing Amplifier Module

[0261] 18 Source Line Drivers

[0262] 20 CPU

[0263] 21. Built-in memory

[0264] 22 Buffer memory

[0265] 23 NAND I / F

[0266] 24 Host I / F

[0267] WL lettering

[0268] MT memory cell transistor

[0269] ST Select Transistor

[0270] NS NAND string

[0271] MU storage unit group

[0272] SU string unit

[0273] CP1, CP1-1~CP1-4, CP2, CP2-1~CP2-4 Charge pumps

[0274] Transistors T1~T19, DT1~DT5, VtT1~VtT6

[0275] DC1~DC4, VtC1~VtC4 capacitors.

Claims

1. A semiconductor memory device comprising: a first memory cell; and a voltage generation circuit including a first charge pump having a first characteristic and a second charge pump having a second characteristic, which supplies a voltage to the first memory cell, wherein the first charge pump and the second charge pump each have an input terminal and an output terminal; and wherein, as the voltage generation circuit, in a first operation of supplying a first voltage to the first memory cell, the first charge pump and the second charge pump are electrically disconnected from each other, in a second operation of supplying a second voltage higher than the first voltage to the first memory cell, the output terminal of the first charge pump and the input terminal of the second charge pump are electrically connected to each other; the first characteristic includes an amount of current supplied from the output terminal of the first charge pump being a first amount of current; the second characteristic includes an amount of current supplied from the output terminal of the second charge pump being a second amount of current; the first amount of current is greater than the second amount of current; in a case where the second voltage is output from the output terminal of the first charge pump, a ratio of the second voltage to a voltage that has been input to the input terminal of the first charge pump becomes a first ratio; the second characteristic includes, in a case where the second voltage is output from the output terminal of the second charge pump, a ratio of the second voltage to a voltage that has been input to the input terminal of the second charge pump becoming a second ratio; and the first ratio is lower than the second ratio.

2. The semiconductor memory device according to claim 1, wherein in a case where the first voltage is output from the output terminal of the first charge pump, a ratio of the first voltage to a voltage that has been input to the input terminal of the first charge pump becomes a third ratio; and the first ratio is lower than the third ratio.

3. The semiconductor memory device according to claim 1, wherein in a case where a maximum voltage that can be input to the input terminal of the first charge pump has been input to the input terminal of the first charge pump, the first charge pump outputs a voltage lower than the second voltage.

4. The semiconductor memory device according to claim 1, wherein in the first operation, the voltage generation circuit supplies the first voltage to the first memory cell using the first charge pump.

5. The semiconductor memory device according to claim 4, wherein the semiconductor memory device further comprises a second memory cell connected in series to the first memory cell, and in the first operation, the voltage generation circuit supplies a third voltage higher than the first voltage to the second memory cell using the second charge pump.

6. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises a plurality of memory cells connected in series to each other including the first memory cell, and in the second operation, the voltage generation circuit supplies the second voltage to at least one end of the plurality of memory cells.

7. The semiconductor memory device according to claim 1, wherein the voltage generation circuit further comprises a third charge pump having an input terminal and an output terminal, and in a case where the second voltage is output from the output terminal of the first charge pump, the output terminal of the third charge pump and the input terminal of the second charge pump are electrically connected to each other. ​ ​ The first characteristic includes: ​ ​ ​ ​ The first property includes: ​ ​ ​ The first property includes: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ In the second action, an input terminal of the second charge pump and an input terminal of the third charge pump are commonly connected to an output terminal of the first charge pump.

8. The semiconductor memory device according to claim 7, wherein The third charge pump has the second characteristic.

9. The semiconductor memory device according to claim 7, wherein The first charge pump is provided in a first region, The second charge pump and the third charge pump are provided in a second region.

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