Memory device and method of operating the same

Abstract

The present disclosure relates to a memory device and a method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to perform an incremental step pulse programming (ISPP) on the plurality of memory cells. The control logic is configured to control the peripheral circuit to perform the ISPP using a bit line voltage set based on different bit line step voltages according to a target program state among a plurality of program states for each memory cell of the plurality of memory cells.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0010361, filed on January 25, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to electronic devices, and more specifically, to memory devices and methods of operating such memory devices. Background Technology

[0004] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores the data therein and a memory controller that controls the memory device. The memory device may be a volatile memory device or a non-volatile memory device.

[0005] Volatile memory devices are devices that store data only while power is supplied and lose the stored data when power is cut off. Volatile memory devices can include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are devices that do not lose data even when power is cut off. Non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, etc. Summary of the Invention

[0007] Embodiments of this disclosure relate to a memory device having improved programming speed and a method of operating the memory device.

[0008] According to one embodiment of this disclosure, a memory device includes a plurality of memory cells, peripheral circuitry, and control logic. The peripheral circuitry is capable of, and in one embodiment is configured to, perform incremental step pulse programming (ISPP) on the plurality of memory cells. The control logic is capable of, and in one embodiment is configured to, control the peripheral circuitry to perform ISPP using bit line voltages set based on different bit line step voltages, according to a target programming state of each of the plurality of memory cells among a plurality of programming states.

[0009] According to one embodiment of this disclosure, a method for operating a memory device to perform incremental step pulse programming (ISPP) on a plurality of memory cells includes: setting a bit line voltage based on different bit line step voltages according to a target programming state of each of the plurality of memory cells in a plurality of programming states; applying the set bit line voltage to a bit line connected to the plurality of memory cells; and applying a programming voltage to a word line connected to a selected memory cell among the plurality of memory cells.

[0010] Based on the proposed technology, a memory device with improved programming speed and a method for operating the memory device are disclosed. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0012] Figure 2 It is a diagram. Figure 1 A diagram of the structure of a memory device.

[0013] Figure 3 It is a diagram. Figure 2 A diagram of a memory cell array.

[0014] Figure 4 It is a diagram. Figure 2 A diagram of another embodiment of the memory cell array.

[0015] Figure 5 It is a diagram. Figure 4 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0016] Figure 6 It is a diagram. Figure 4 A circuit diagram of another embodiment of memory block BLKb among memory blocks BLK1 to BLKz.

[0017] Figure 7 This is a diagram illustrating Incremental Step Pulse Programming (ISPP).

[0018] Figure 8 This is a diagram illustrating the distribution of threshold voltages in memory cells as the programming cycle count increases in an ISPP, according to one embodiment.

[0019] Figure 9 This is a diagram illustrating the distribution of threshold voltages in memory cells as the programming cycle count increases in an ISPP, according to one embodiment.

[0020] Figure 10This is a diagram illustrating the completion time points of programming operations for each programming state according to one embodiment.

[0021] Figure 11 It is a diagram and Figure 10 A diagram showing the programming settings related to programming operations.

[0022] Figure 12 This is a diagram illustrating the completion time points of programming operations for each programming state according to one embodiment.

[0023] Figure 13 It is a diagram and Figure 12 A diagram showing the programming settings related to programming operations.

[0024] Figure 14 This is a diagram illustrating the completion time points of programming operations for each programming state according to one embodiment.

[0025] Figure 15 It is a diagram and Figure 14 A diagram showing the programming settings related to programming operations.

[0026] Figure 16 This is a flowchart illustrating programming operations of a memory device according to one embodiment. Detailed Implementation

[0027] The specific structural or functional descriptions of embodiments based on the concepts of this disclosure disclosed in this specification or application are illustrative and are for the purpose of describing embodiments based on the concepts of this disclosure only. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0028] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0029] refer to Figure 1 Storage device 50 may include memory device 100 and memory controller 200 for controlling the operation of memory device. Storage device 50 is a device that stores data under the control of a host, such as a cellular phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0030] Depending on the host interface, which serves as the method of communication with the host, storage device 50 can be manufactured as one of various types of storage devices. For example, storage device 50 can be configured as any of various types of storage devices, such as SSDs, multimedia cards (in the form of MMC, eMMC, RS-MMC, and micro MMC), secure digital cards (in the form of SD, mini SD, and micro SD), universal serial bus (USB) storage devices, universal flash storage (UFS) devices, PCMCIA card type storage devices, peripheral component interconnect (PCI) card type storage devices, PCI Express (PCI-E) card type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0031] Storage device 50 can be manufactured in any of various package types. For example, storage device 50 can be manufactured in any of various package types, such as package-on-package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0032] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data.

[0033] Each memory cell in the memory unit can be configured as: a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a three-level cell (TLC) storing three data bits, or a four-level cell (QLC) storing four data bits.

[0034] A memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0035] A memory block can be a unit used for erasing data. In one embodiment, memory device 100 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin-Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, it is assumed that memory device 100 includes NAND flash memory.

[0036] Memory device 100 is configured to receive commands and addresses from memory controller 200 and access address-selected regions in the memory cell array. That is, memory device 100 can perform operations instructed by commands on address-selected regions. For example, memory device 100 can perform write operations (programming operations), read operations, or erase operations. During a programming operation, memory device 100 can program data into the address-selected region. During a read operation, memory device 100 can read data from the address-selected region. During an erase operation, memory device 100 can erase data stored in the address-selected region.

[0037] The memory controller 200 controls the overall operation of the storage device 50.

[0038] When power is applied to storage device 50, memory controller 200 can execute firmware (FW). When storage device 100 is a flash memory device, memory controller 200 can operate firmware such as flash translation layer (FTL) to control communication between the host and storage device 100.

[0039] In one embodiment, the memory controller 200 may receive data and logical block addresses (LBAs) from a host and translate the LBAs into physical block addresses (PBAs), which indicate the addresses of memory cells in which data included in the memory device 100 is to be stored.

[0040] The memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations in response to a request from the host. During a programming operation, the memory controller 200 can provide the memory device 100 with write commands, a PBA, and data. During a read operation, the memory controller 200 can provide the memory device 100 with read commands and a PBA. During an erase operation, the memory controller 200 can provide the memory device 100 with erase commands and a PBA.

[0041] In one embodiment, memory controller 200 can generate commands, addresses, and data, and transmit these commands, addresses, and data to memory device 100 regardless of requests from a host. For example, memory controller 200 can provide commands, addresses, and data to memory device 100 to perform background operations such as programming operations for wear leveling and programming operations for garbage collection.

[0042] In one embodiment, the memory controller 200 can control at least two memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving method to improve operational performance. The interleaving method can be an operational method for overlapping the operation periods of at least two memory devices 100.

[0043] The host can communicate with the storage device 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Away DIMM (LRDIMM).

[0044] Figure 2 It is a diagram. Figure 1 A diagram of the structure of a memory device.

[0045] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0046] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to address decoder 121 via row lines RL. The multiple memory blocks BLK1 to BLKz are connected to read and write circuitry 123 via bit lines BL1 to BLm. Each memory block among the multiple memory blocks BLK1 to BLKz includes multiple memory cells. As an embodiment, these multiple memory cells are non-volatile memory cells. Memory cells connected to the same word line among the multiple memory cells are defined as a physical page. That is, memory cell array 110 is configured with multiple physical pages. According to one embodiment of this disclosure, each memory block among the multiple memory blocks BLK1 to BLKz included in memory cell array 110 may include multiple dummy cells. At least one dummy cell may be connected in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0047] Each memory cell in the memory unit of the memory device 100 can be configured as an SLC storing one data bit, an MLC storing two data bits, a TLC storing three data bits, or a QLC storing four data bits.

[0048] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0049] Peripheral circuitry 120 drives memory cell array 110. For example, peripheral circuitry 120 can drive memory cell array 110 to perform programming operations, read operations, and erase operations.

[0050] Address decoder 121 is connected to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to one embodiment of this disclosure, word lines may include normal word lines and dummy word lines. According to one embodiment of this disclosure, row lines RL may also include pipe select lines.

[0051] Address decoder 121 is configured to operate in response to control of control logic 130. Address decoder 121 receives address ADDR from control logic 130.

[0052] Address decoder 121 is configured to decode the block address of the received address ADDR. Address decoder 121 selects at least one memory block from BLK1 to BLKz based on the decoded block address. Address decoder 121 is also configured to decode the row address of the received address ADDR. Address decoder 121 can select at least one word line from the word lines of the selected memory block based on the decoded row address. Address decoder 121 can apply an operating voltage Vop supplied from voltage generator 122 to the selected word line.

[0053] During programming operations, address decoder 121 may apply a programming voltage to the selected word line and a pass voltage to the unselected word line, the pass voltage level being lower than the programming voltage level. During programming verification operations, address decoder 121 may apply a verification voltage to the selected word line and a verification pass voltage to the unselected word line, the verification pass voltage level being higher than the verification voltage level.

[0054] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and a read pass voltage to the unselected word line, wherein the level of the read pass voltage is greater than the level of the read voltage.

[0055] According to one embodiment of this disclosure, an erase operation on memory device 100 is performed on a block-by-block basis. The address ADDR input to memory device 100 during the erase operation includes a block address. Address decoder 121 can decode the block address and select at least one memory block based on the decoded block address. During the erase operation, address decoder 121 can apply a ground voltage to the word lines input to the selected memory block.

[0056] According to one embodiment of this disclosure, address decoder 121 can be configured to decode the column address of the transmitted address ADDR. The decoded column address can be transmitted to read and write circuitry 123. As an example, address decoder 121 may include components such as row decoders, column decoders, and address buffers.

[0057] Voltage generator 122 is configured to generate multiple operating voltages Vop using an external power supply voltage supplied to memory device 100. Voltage generator 122 operates in response to control of control logic 130.

[0058] As one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 is used as the operating voltage of memory device 100.

[0059] As one embodiment, voltage generator 122 can use an external power supply voltage or an internal power supply voltage to generate multiple operating voltages Vop. Voltage generator 122 can be configured to generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0060] To generate multiple operating voltages Vop with various voltage levels, voltage generator 122 may include multiple pump capacitors that receive internal voltages and selectively activate the multiple pump capacitors in response to control logic 130 to generate multiple operating voltages Vop.

[0061] Multiple generated operating voltages Vop can be supplied to the memory cell array 110 via address decoder 121.

[0062] The read and write circuit 123 includes first page buffers PB1 to m-th page buffers PBm. First page buffers PB1 to m-th page buffers PBm are connected to the memory cell array 110 via first bit line BL1 to m-th bit line BLm, respectively. First page buffers PB1 to m-th page buffers PBm operate in response to control logic 130.

[0063] Page buffers PB1 through PBm (page m) communicate data DATA with data input / output circuit 124. During programming, page buffers PB1 through PBm receive the data DATA to be stored through data input / output circuit 124 and data line DL.

[0064] During programming operations, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transfer the data DATA to be stored (i.e., the data DATA received via the data input / output circuit 124) to the selected memory cell via bit lines BL1 to BLm. The memory cell of the selected page is programmed according to the transferred data DATA. Memory cells connected to the bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells connected to the bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm read the data DATA stored in the memory cell from the selected memory cell via bit lines BL1 to BLm.

[0065] During a read operation, the read and write circuit 123 can read data DATA from the memory cell of the selected page via bit lines BL1 to BLm, and store the read data DATA in the first page buffer PB1 to the m-th page buffer PBm.

[0066] During the erase operation, the read and write circuitry 123 can float bit lines BL1 to BLm. As one embodiment, the read and write circuitry 123 may include column select circuitry.

[0067] The data input / output circuit 124 is connected to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 operates in response to the control logic 130.

[0068] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives data DATA to be stored from an external controller (not shown). During read operations, the data input / output circuit 124 outputs normal data DATA to the external controller, which is transmitted from the first page buffer PB1 to the m-th page buffer PBm included in the read and write circuit 123.

[0069] During a read or verification operation, the sensing circuit 125 may generate a reference current in response to the signal of the enable bit VRYBIT generated by the control logic 130, and may compare the sensed voltage VPB received from the read and write circuit 123 with the reference voltage generated by the reference current to output a pass signal or a failure signal to the control logic 130.

[0070] Control logic 130 can be connected to address decoder 121, voltage generator 122, read and write circuitry 123, data input / output circuitry 124, and sensing circuitry 125. Control logic 130 can be configured to control all operations of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices. Control logic 130 can be implemented in hardware, software, or a combination of both. For example, control logic 130 can be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0071] Control logic 130 can generate various signals in response to command CMD and address ADDR to control peripheral circuitry 120. For example, control logic 130 can generate operation signal OPSIG, address ADDR, read and write circuit control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, address ADDR to address decoder 121, read and write control signals to read and write circuitry 123, and enable bit VRYBIT to sensing circuitry 125. Furthermore, control logic 130 can determine whether the verification operation has passed or failed in response to pass signal PASS or failure signal FAIL output by sensing circuitry 125.

[0072] In one embodiment, the peripheral circuitry 120 can perform incremental step pulse programming (ISPP) on multiple memory cells.

[0073] Control logic 130 can set the bit line voltage based on different bit line step voltages, according to the target programming state of each memory cell in multiple programming states. Control logic 130 can control peripheral circuitry 120 to perform ISPP using the bit line voltages set based on the different bit line step voltages.

[0074] In one embodiment, control logic 130 may include a programming settings table storage device 131 and a programming operation controller 132.

[0075] The programming setup table storage device 131 can store information about bit line step voltages corresponding to multiple corresponding programming states. The programming setup table storage device 131 can represent programming setup table storage circuitry or a device. In one embodiment, as the target programming state is higher, the amplitude of the bit line step voltage corresponding to the target programming state can be set to be lower. As the target programming state is higher, the amplitude of the programming step voltage corresponding to the target programming state can be set to be higher. The amplitude of the programming step voltage can be the difference between the word line step voltage and the bit line step voltage corresponding to the target programming state.

[0076] The programming configuration table storage device 131 can update information about bit line step voltages based on requests from the host. The programming configuration table storage device 131 can also update information about bit line step voltages based on the lifetime of the memory device 100. The lifetime of the memory device 100 can be determined based on the erase and write counts of memory blocks.

[0077] The programming operation controller 132 can control the peripheral circuitry 120 to perform ISPP based on information about the bit line step voltage. As the programming cycle count increases, the programming operation controller 132 can control the peripheral circuitry 120 to increase the bit line voltage by the corresponding bit line step voltage. The programming operation controller 132 can complete programming operations on at least two or more programming states out of multiple programming states within the same programming cycle. The programming operation controller 132 can complete programming operations on each of the multiple programming states in the final programming cycle.

[0078] Figure 3 It is a diagram. Figure 2 A diagram of the memory cell array 110.

[0079] refer to Figure 3 The first memory block BLK1 to the z-th memory block BLKz are all connected to the first bit line BL1 to the m-th bit line BLm. Figure 3 For ease of description, the elements included in the first memory block BLK1 of the plurality of memory blocks BLK1 to BLKz are shown, and the elements included in each of the remaining memory blocks BLK2 to BLKz are omitted. It will be understood that each of the remaining memory blocks BLK2 to BLKz is configured similarly to the first memory block BLK1.

[0080] The memory block BLK1 may include multiple cell strings CS1_1 to CS1_m (m is a positive integer). The first cell string CS1_1 to the m-th cell string CS1_m are respectively connected to the first bit line BL1 to the m-th bit line BLm. Each cell string in the first cell string CS1_1 to the m-th cell string CS1_m includes a drain selection transistor DST, multiple memory cells MC1 to MCn (n is a positive integer) connected in series, and a source selection transistor SST.

[0081] The gate terminal of the drain select transistor DST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the drain select line DSL1. The gate terminal of each of the first memory cells MC1 to the n-th memory cells MCn included in each of the first unit strings CS1_1 to the n-th word lines WL1 to WLn is connected to the first word line WL1 to the n-th word line WLn. The gate terminal of the source select transistor SST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m is connected to the source select line SSL1.

[0082] For ease of description, the structure of the unit strings is described based on the first unit string CS1_1 among multiple unit strings CS1_1 to CS1_m. However, it can be understood that each of the remaining unit strings CS1_2 to CS1_m is configured similarly to the first unit string CS1_1.

[0083] The drain terminal of the drain select transistor DST included in the first cell string CS1_1 is connected to the first bit line BL1. The source terminal of the drain select transistor DST included in the first cell string CS1_1 is connected to the drain terminal of the first memory cell MC1 included in the first cell string CS1_1. The first memory cells MC1 to the nth memory cell MCn are connected in series with each other. The drain terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the source terminal of the nth memory cell MCn included in the first cell string CS1_1. The source terminal of the source select transistor SST included in the first cell string CS1_1 is connected to the common source line CSL. As an embodiment, the common source line CSL can be connected to the first memory block BLK1 to the zth memory block BLKz.

[0084] Drain select line DSL1, first word lines WL1 to nth word lines WLn, and source select line SSL1 are included. Figure 2 In the row line RL, the drain selection line DSL1, the first word lines WL1 to the nth word lines WLn, and the source selection line SSL1 are controlled by the address decoder 121. The common source line CSL is controlled by the control logic 130. The first bit line BL1 to the mth bit line BLm are controlled by the read and write circuit 123.

[0085] Figure 4 It is a diagram. Figure 2 A diagram of another embodiment of the memory cell array 110.

[0086] refer to Figure 4 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions. (Reference) Figure 5 and Figure 6 The structure of each memory block is described in more detail.

[0087] Figure 5 It is a diagram. Figure 4 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0088] refer to Figure 5The memory block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. As an example, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed in a 'U' shape. In the memory block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). Figure 5 In this diagram, two unit strings are arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0089] In one embodiment, a memory block may include multiple sub-blocks. A sub-block may include a string of cells arranged in a 'U' shape in a column.

[0090] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0091] The selection transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. As one embodiment, each of the selection transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. As one embodiment, a pillar for providing the channel layer may be provided in each cell string. As one embodiment, a pillar may be provided in each cell string for providing at least one of the channel layer, tunneling insulating film, charge storage film, and barrier insulating film.

[0092] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0093] As one embodiment, source selection transistors of cell strings arranged in the same row are connected to source selection lines extending in the row direction, and source selection transistors of cell strings arranged in different rows are connected to different source selection lines. Figure 5 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0094] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0095] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0096] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp, and the (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp are arranged sequentially in the direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn are arranged sequentially in the +Z direction and are connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn are connected to each other through the channel transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0097] The gate of the pipe transistor PT in each cell string is connected to the pipe line.

[0098] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0099] The cell string arranged in the column direction is connected to the bit line extending in the column direction. Figure 5 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0100] Memory cells connected to the same word line in a cell string arranged in a row direction are configured as one page. For example, memory cells in cell strings CS11 to CS1m in the first row that are connected to the first word line WL1 are configured as one page. Memory cells in cell strings CS21 to CS2m in the second row that are connected to the first word line WL1 are configured as another page. A cell string arranged in a row direction can be selected by selecting either the drain select line DSL1 or DSL2. A page of the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0101] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0102] As one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. With more dummy memory cells provided, the reliability of operation for memory block BLKa is improved; however, the size of memory block BLKa increases. With fewer memory cells provided, the size of memory block BLKa can be reduced; however, the reliability of operation for memory block BLKa may decrease.

[0103] To efficiently control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after a programming operation, the dummy memory cells can have the required threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0104] Figure 6 It is a diagram. Figure 4 A circuit diagram of another embodiment of memory block BLKb among memory blocks BLK1 to BLKz.

[0105] refer to Figure 6 The memory block BLKb includes multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' includes, stacked on a substrate (not shown) beneath the memory block BLKb: at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST.

[0106] In one embodiment, a memory block may include multiple sub-blocks. A sub-block may include a string of cells arranged in an 'I' shape in a column.

[0107] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. The source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. As another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' can be connected to a single source select line.

[0108] The first memory cell MC1 to the nth memory cell MCn in each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0109] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0110] As a result, in addition to excluding the pipe transistor PT from each cell string, Figure 6 The memory block BLKb has the same Figure 5 The equivalent circuit of the memory block BLKa is similar to the equivalent circuit.

[0111] As another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Furthermore, even-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be connected to the even-numbered bit lines, and odd-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be connected to the odd-numbered bit lines.

[0112] As one embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. With more dummy memory cells provided, the reliability of operation for memory block BLKb is improved; however, the size of memory block BLKb increases. With fewer dummy memory cells provided, the size of memory block BLKb can be reduced; however, the reliability of operation for memory block BLKb may decrease.

[0113] To efficiently control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cells can have the required threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0114] Figure 7 This is a diagram illustrating Incremental Step Pulse Programming (ISPP).

[0115] exist Figure 7 For ease of description, it is assumed that the memory cell is an MLC that stores 2 bits of data. However, the scope of this disclosure is not limited to this, and the memory cell can be a TLC that stores 3 bits of data or a QLC that stores 4 bits of data. The number of data bits stored in the memory cell can be one or more.

[0116] The memory device can execute multiple programming cycles PL1 to PLn to program the selected memory cell to have a threshold voltage corresponding to any one of the multiple programming states P1, P2 and P3.

[0117] Each of the multiple programming cycles PL1 to PLn may include: a programming voltage application step PGM Step, which applies a programming voltage to a selected word line connected to the selected memory cell, and a programming verification step Verify Step, which determines whether the memory cell has been programmed by applying a verification voltage.

[0118] For example, during the execution of the first programming cycle PL1, after applying the first programming voltage Vpgm1, the first verification voltage V_vfy1 to the third verification voltage V_vfy3 are applied sequentially to verify the programming state of the selected memory cell. At this time, the verification of the memory cell whose target programming state is the first programming state P1 can be performed using the first verification voltage V_vfy1, the verification of the memory cell whose target programming state is the second programming state P2 can be performed using the second verification voltage V_vfy2, and the verification of the memory cell whose target programming state is the third programming state P3 can be performed using the third verification voltage V_vfy3.

[0119] Memory cells that have passed verification by verification voltages V_vfy1 to V_vfy3 can be identified as having a target programming state, and then programming of these memory cells can be disabled in the second programming cycle PL2. In other words, from the second programming cycle PL2, a programming disable voltage can be applied to a bit line connected to the verified memory cell.

[0120] In the second programming cycle PL2, a second programming voltage Vpgm2, which is a unit voltage ΔVpgm higher than the first programming voltage Vpgm1, is applied to the selected word line to program the remaining memory cells except those where programming is disabled. Thereafter, a verification operation is performed in the same manner as in the first programming cycle PL1. For example, a verification pass indication indicates that the memory cell is read as a disabled cell by the corresponding verification voltage.

[0121] As described above, when the memory device programs a 2-bit MLC, the memory device uses a first verification voltage V_vfy1 to a third verification voltage V_vfy3 to verify each memory cell in the memory cell that has changed from the programming state to the target programming state.

[0122] During the verification operation, a verification voltage is applied to the selected word line, which is the word line connected to the selected memory cell. Figure 2 The page buffer can determine whether the memory cell has passed verification based on the current flowing through the bit line connected to the selected memory cell or the voltage applied to that bit line.

[0123] In the case of ISPP, because a programming verification operation is performed for each programming cycle, the threshold voltage distribution of the memory cells can be formed with high accuracy. Based on the results of the programming verification operation, the timing at which the programming inhibit voltage is applied to the bit lines connected to the memory cells can be determined.

[0124] Figure 8This is a diagram illustrating the distribution of threshold voltages in memory cells as the programming cycle count increases in an ISPP, according to one embodiment.

[0125] refer to Figure 8 As the number of programming loops executed in ISPP increases, the threshold voltage distribution of the memory cell can change from s1 to s4. Figure 8 In this embodiment, the memory cell can be a TLC that stores three data bits. The number of data bits stored in the memory cell is not limited to this embodiment. The memory cell can be programmed to any one of the programming states from the first programming state P1 to the seventh programming state P7.

[0126] At s1, all memory cells can be in the erase state E.

[0127] At s2, the memory cells that are to be programmed to the first programming state P1 to the seventh programming state P7 can be being programmed.

[0128] At s3, memory cells that are to be programmed to the first programming state P1 through the fourth programming state P4 can be in the programming completed state. Memory cells that are to be programmed to the fifth programming state P5 through the seventh programming state P7 can be in the process of being programmed.

[0129] At s4, all memory cells in the memory cell that are to be programmed to the first programming state P1 to the seventh programming state P7 can be in the programming completed state.

[0130] exist Figure 8 In the process, as the ISPP programming cycle count increases, programming operations can be completed sequentially from low programming state to high programming state. The timing of programming operation completion and related programming settings will be discussed later. Figure 10 and Figure 11 Describe it.

[0131] Figure 9 This is a diagram illustrating the distribution of threshold voltages in memory cells as the programming cycle count increases in an ISPP, according to one embodiment.

[0132] refer to Figure 9 As the number of programming loops executed in ISPP increases, the threshold voltage distribution of the memory cell can be changed from s1' to s4'. The memory cell can be programmed into any of the programming states from the first programming state P1 to the seventh programming state P7.

[0133] At s1', all memory cells can be in the erase state E.

[0134] In s2' and s3', the memory cells that are to be programmed to the first programming state P1 to the seventh programming state P7 can be being programmed.

[0135] At s4', all memory cells in the memory cell that are to be programmed to the first programming state P1 to the seventh programming state P7 can be in the programming completed state.

[0136] exist Figure 9 In this process, even as the ISPP loop count increases, programming operations across multiple programming states can be completed in the final programming loop, regardless of the programming state. The timing of programming operation completion and related programming settings will be discussed later. Figure 12 and Figure 13 Describe it.

[0137] In various embodiments, programming operations corresponding to at least two or more programming states out of a plurality of programming states can be completed within the same programming loop. The timing of the programming operation completion and the programming settings associated with the programming operation will be discussed later. Figure 14 and Figure 15 Describe it.

[0138] Figure 10 This is a diagram illustrating the completion time points of programming operations for each programming state according to one embodiment.

[0139] refer to Figure 10 As the programming loop count increases, programming operations can be completed sequentially from low programming state to high programming state.

[0140] exist Figure 10 In this process, after completing the programming operation on the memory cell to be programmed to the first programming state P1, the programming operation on the memory cell to be programmed to the second programming state P2 can be completed. Following a similar sequence, after completing the programming operation on the memory cell to be programmed to the sixth programming state P6, the programming operation on the memory cell to be programmed to the seventh programming state P7 can be completed.

[0141] Figure 11 It is a diagram and Figure 10 A diagram showing the programming settings related to programming operations.

[0142] refer to Figure 11 The programming setting table stored in the programming setting table storage device 131 may include setting values ​​for the operating voltage related to programming operations. Figure 11 In this embodiment, programming operations can be performed during the first to thirteenth programming cycles. However, the number of programming cycles executed in the programming operation and the timing of completing the programming operation for each programming state are not limited to this embodiment.

[0143] exist Figure 11 In the programming cycle, as the count increases, the word line voltage can be increased by a step voltage ΔVWL from the initial voltage VWL.

[0144] A programming enable voltage Vgnd can be applied to the bit line connected to the memory cell being programmed, one of the memory cells to be programmed into multiple programming states P1 to P7. The programming enable voltage Vgnd can be a ground voltage level. A programming disable voltage Vinh can be applied to the bit line connected to the memory cell that has been programmed, one of the memory cells to be programmed into multiple programming states P1 to P7. A programming disable voltage Vinh can be applied to the bit line connected to a programming disable memory cell. The programming disable memory cell can be a memory cell in an erase state E.

[0145] The programming step voltage Vps can be the difference between the word line step voltage ΔVWL and the bit line step voltage ΔVBL. Figure 11 In all programming states, the bit line step voltage ΔVBL can be the same as 0V.

[0146] The programming operations of memory cells to be programmed to the first programming state P1 to the seventh programming state P7 can be completed in different programming cycles.

[0147] For example, the programming operation of a memory cell to be programmed into the first programming state P1 can begin in the first programming loop and be completed in the fourth programming loop.

[0148] The programming operation of the memory cell to be programmed to the second programming state P2 can begin in the first programming loop and be completed in the fifth programming loop.

[0149] The programming operation for the memory cell to be programmed to the third programming state P3 can begin in the first programming loop and be completed in the sixth programming loop.

[0150] The programming operation for the memory cell to be programmed to the fourth programming state P4 can begin in the first programming cycle and be completed in the eighth programming cycle.

[0151] The programming operation for the memory cell to be programmed to the fifth programming state P5 can begin in the first programming cycle and be completed in the ninth programming cycle.

[0152] The programming operation for the memory cell to be programmed to the sixth programming state P6 can begin in the first programming loop and be completed in the eleventh programming loop.

[0153] The programming operation for the memory cell to be programmed to the seventh programming state P7 can begin in the first programming loop and be completed in the thirteenth programming loop.

[0154] Figure 12 This is a diagram illustrating the completion time points of programming operations for each programming state according to one embodiment.

[0155] refer to Figure 12 It can perform programming operations for all programming states simultaneously, regardless of the programming loop count.

[0156] exist Figure 12 In this process, the programming operations of memory cells to be programmed to the first programming state P1 to the sixth programming state P6 can be completed in the same programming loop as the programming operations of memory cells to be programmed to the seventh programming state P7 (which is the highest programming state).

[0157] Figure 13 It is a diagram and Figure 12 A diagram showing the programming settings related to programming operations.

[0158] refer to Figure 13 Programming operations can be performed during the first to eighth programming cycles. However, the number of programming cycles executed in the programming operation and the timing of completing the programming operation for each programming state are not limited to this embodiment.

[0159] exist Figure 13 In this programming loop, as the count increases, the word line voltage can be increased by a word line step voltage ΔVWL_a from the word line start voltage VWL. The bit line voltage can be set according to different bit line step voltages for each of the multiple programming states, based on the target programming state. The bit line step voltage can be different for each programming state.

[0160] The bit line step voltage corresponding to each programming state from the first programming state P1 to the sixth programming state P6 can be the first bit line step voltage ΔVBL1_a to the sixth bit line step voltage ΔVBL6_a. The bit line step voltage corresponding to the seventh programming state P7 (which is the highest programming state) can be 0V, which is the ground voltage.

[0161] As the corresponding target programming state increases, the amplitude of the bit line step voltage can be set to a lower value. Therefore, following the order from the first bit line step voltage ΔVBL1_a to the sixth bit line step voltage ΔVBL6_a, the voltage amplitude can be set to a low value.

[0162] As the programming cycle count increases, the bit line voltage can be increased from the bit line start voltage corresponding to each programming state to the bit line step voltage corresponding to that state. The bit line start voltage and bit line step voltage can be set differently for each programming state.

[0163] For example, each time the programming cycle count increases, the bit line voltage applied to the bit line connected to the memory cell to be programmed to the first programming state can be increased by a bit line step voltage ΔVBL1_a from the bit line start voltage VBL1_a. Each time the programming cycle count increases, the bit line voltage applied to the bit line connected to the memory cell to be programmed to the second programming state can be increased by a bit line step voltage ΔVBL2_a from the bit line start voltage VBL2_a. Similarly, each time the programming cycle count increases, the bit line voltage applied to the bit line connected to the memory cell to be programmed to the sixth programming state can be increased by a bit line step voltage ΔVBL6_a from the bit line start voltage VBL6_a. The bit line voltage applied to the bit line connected to the memory cell to be programmed to the seventh programming state (which is the highest programming state) can be the programming enable voltage Vgnd.

[0164] The programming disable voltage Vinh_a can be applied to the bit lines connected to the memory cells that are to be programmed into multiple programming states P1 to P7, where the programmed memory cells have been programmed. The programming disable voltage Vinh_a can also be applied to the bit lines connected to a programming disable memory cell. The programming disable memory cell can be a memory cell in an erase state E.

[0165] The programming step voltage Vps can be the difference between the word line step voltage ΔVWL_a and the bit line step voltage ΔVBL. Figure 13 In the programming state P1, the programming step voltage Vps1_a can be the difference between the word line step voltage ΔVWL_a and the first bit line step voltage ΔVBL1_a. Similarly, the programming step voltage Vps2_a corresponding to the second programming state P2 can be the difference between the word line step voltage ΔVWL_a and the second bit line step voltage ΔVBL2_a. Likewise, the programming step voltage Vps6_a corresponding to the sixth programming state P6 can be the difference between the word line step voltage ΔVWL_a and the sixth bit line step voltage ΔVBL6_a.

[0166] The programming step voltage Vps7_a corresponding to the seventh programming state P7 (which is the highest programming state) can be the word line step voltage ΔVWL_a, because the seventh bit line step voltage is the ground voltage.

[0167] The programming operations of memory cells to be programmed to the first programming state P1 to the seventh programming state P7 can be completed in the same programming cycle.

[0168] For example, all programming operations on memory cells to be programmed to the first programming state P1 through the seventh programming state P7 can begin in the first programming cycle and be completed in the eighth programming cycle.

[0169] exist Figure 13 In this system, the bit line start voltage and bit line step voltage can be set differently for each programming state. Because the bit line voltage is adjusted differently for each programming state and for each programming cycle count, programming operations for all programming states can be completed within the same programming cycle.

[0170] In one embodiment, although Figure 13 The word line step voltage ΔVWL_a is set to be greater than Figure 11 The word line step voltage ΔVWL is adjusted differently for each programming state and for each programming cycle count, and thus the programming operation can be performed normally. Because Figure 13 The step voltage ΔVWL_a of the word line is greater than Figure 11 The word line step voltage ΔVWL, therefore, can be compared to Figure 11 The programming operations are completed in an earlier programming loop. Figure 13 Programming operations. Can be compared to Figure 11 The programming operations are executed faster. Figure 13 Programming operations.

[0171] Figure 14 This is a diagram illustrating the completion time points of programming operations for each programming state according to one embodiment.

[0172] refer to Figure 14 It is possible to complete programming operations for at least two or more programming states within the same programming loop.

[0173] After programming the memory cell to be programmed to the first programming state P1, programming the memory cell to be programmed to the second programming state P2 can be completed. After programming the memory cell to be programmed to the second programming state P2, programming the memory cell to be programmed to the third programming state P3 can be completed. After programming the memory cell to be programmed to the third programming state P3, programming the memory cells to be programmed to the fourth programming state P4 through the seventh programming state P7 can be completed in the same programming cycle.

[0174] Figure 15 It is a diagram and Figure 14 A diagram showing the programming settings related to programming operations.

[0175] refer to Figure 15Programming operations can be performed during the first to ninth programming cycles.

[0176] Programming operations on memory cells to be programmed to the first programming state P1 through the third programming state P3 can be completed in different programming loops. Programming operations on memory cells to be programmed to the fourth programming state P4 through the seventh programming state P7 can be completed in the same programming loop.

[0177] For example, the programming operation of a memory cell to be programmed into the first programming state P1 can begin in the first programming loop and be completed in the sixth programming loop.

[0178] The programming operation of the memory cell to be programmed to the second programming state P2 can begin in the first programming loop and be completed in the seventh programming loop.

[0179] The programming operation of the memory cell to be programmed to the third programming state P3 can begin in the first programming loop and be completed in the eighth programming loop.

[0180] Programming operations on memory cells to be programmed to the fourth programming state P4 through the seventh programming state P7 can begin in the first programming cycle and be completed in the ninth programming cycle.

[0181] The programming disable voltage Vinh_b can be applied to the bit lines connected to the memory cells that are to be programmed into multiple programming states P1 to P7, where the programmed memory cells have been programmed. The programming disable voltage Vinh_b can also be applied to the bit lines connected to programming disable memory cells. A programming disable memory cell can be a memory cell in an erase state E.

[0182] and Figure 13 In comparison, the word line step voltage ΔVWL_b can be set to be less than the word line step voltage ΔVWL_a. The bit line start voltage VBL_b can be set to be less than the bit line start voltage VBL_a. The bit line step voltage ΔVBL_b can be set to be less than the bit line step voltage ΔVBL_a.

[0183] Because the word line step voltage ΔVWL_b is less than the word line step voltage ΔVWL_a, therefore in comparison Figure 13 The programming operations are executed later in the programming loop. Figure 15 The programming operation. However, because the programming disable voltage Vinh_b (which is the maximum voltage applied to the bit line) is set lower than the programming disable voltage Vinh_a, interference effects between bit lines can be reduced.

[0184] Figure 16 This is a flowchart illustrating programming operations of a memory device according to one embodiment.

[0185] refer to Figure 16 In step S1601, the memory device can set a bit line voltage corresponding to the target programming state based on different bit line step voltages, according to the target programming state of each memory cell in multiple programming states.

[0186] In step S1603, the memory device may apply a set bit line voltage to the bit lines connected to the plurality of memory cells.

[0187] In step S1605, the memory device may apply a programming voltage to a word line connected to a selected memory cell among a plurality of memory cells.

[0188] Through steps S1601 to S1605, for each programming state, the memory device can perform a programming operation using bit line voltages set based on different bit line step voltages. By adjusting the bit line voltages differently for each programming state and each programming cycle count, programming operations can be performed in fewer programming cycles. That is, programming operations can be completed in a shorter time.

Claims

1. A memory device, comprising: Multiple memory units; The peripheral circuitry is configured to perform incremental step pulse programming (ISPP) on a selected memory cell among the plurality of memory cells to achieve a target programming state among the plurality of programming states. as well as The control logic is configured to: store a programming setting table of bit line step voltages corresponding to the plurality of programming states, and control the peripheral circuitry to execute the ISPP using the bit line voltages set based on the target programming state and the programming setting table. In the programming settings table, the bit line step voltages have different values ​​depending on the corresponding programming state.

2. The memory device according to claim 1, wherein the control logic includes: A programming setting table storage device is configured to store the programming setting table, which includes information about the bit line step voltage; as well as The programmable controller is configured to control the peripheral circuitry to execute the ISPP based on the information regarding the bit line step voltage.

3. The memory device of claim 2, wherein the programming settings table storage device updates the information regarding the bit line step voltage according to a request from the host or the lifetime of the memory device.

4. The memory device of claim 3, wherein as the target programming state increases, the magnitude of the bit line step voltage corresponding to the target programming state is set to be lower.

5. The memory device of claim 4, wherein as the target programming state increases, the amplitude of the programming step voltage corresponding to the target programming state is set to increase.

6. The memory device of claim 5, wherein the amplitude of the programming step voltage corresponding to the target programming state is the difference between the word line step voltage and the bit line step voltage corresponding to the target programming state.

7. The memory device of claim 3, wherein as the programming cycle count increases, the programming operation controller controls the peripheral circuitry to increase the bit line voltage by a corresponding bit line step voltage.

8. The memory device of claim 3, wherein, in the same programming cycle, the programming operation controller performs programming operations for at least two or more of the plurality of programming states.

9. The memory device of claim 3, wherein in the final programming cycle, the programming operation controller performs programming operations for each of the plurality of programming states.

10. The memory device of claim 1, wherein the bit line voltage corresponding to the highest programming state among the plurality of programming states is set to a ground voltage level.

11. A method of operating a memory device, the memory device performing incremental step pulse programming (ISPP) on a selected memory cell among a plurality of memory cells to achieve a target programming state among a plurality of programming states, the method comprising: The bit line voltage is set based on the target programming state and the programming setting table for the bit line step voltage corresponding to the plurality of programming states respectively. The set bit line voltage is applied to the bit line connected to the selected memory cell; as well as A programming voltage is applied to the word line connected to the selected memory cell among the plurality of memory cells. In the programming settings table, the bit line step voltages have different values ​​depending on the corresponding programming state.

12. The method of claim 11, wherein setting the bit line voltage comprises: As the programming loop count increases, the bit line voltage is increased by the corresponding bit line step voltage.

13. The method of claim 12, wherein increasing the bit line voltage comprises: Set the bit line voltage corresponding to the highest programming state among the plurality of programming states to the ground voltage level.

14. The method of claim 11, further comprising: In the ISPP, programming operations for at least two or more of the plurality of programming states are completed within the same programming loop.

15. The method of claim 11, further comprising: In the ISPP, in the final programming loop, programming operations are performed for each of the plurality of programming states.

16. The method of claim 11, further comprising: As the target programming state becomes higher, the amplitude of the bit line step voltage corresponding to the target programming state is set to be lower.

17. The method of claim 16, further comprising: As the target programming state becomes higher, the amplitude of the programming step voltage corresponding to the target programming state is set to be higher.

18. The method of claim 17, wherein the magnitude of the programming step voltage corresponding to the target programming state is the difference between the word line step voltage and the bit line step voltage corresponding to the target programming state.

19. The method of claim 11, further comprising: The programming settings table regarding the bit line step voltage is updated based on a request from the host or the lifetime of the memory device.

20. The method of claim 11, further comprising: Based on the target programming state, programming operations are performed on at least one of the plurality of programming states in different programming loops.

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