Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region, the first region including a first peripheral region and a first core region, a first dummy gate structure being disposed on the first peripheral region, and a second dummy gate structure being disposed on the first core region; forming a first sacrificial layer that exposes the first region; using the first sacrificial layer as a mask to form a first source / drain opening and a second source / drain opening in the first region; using the first sacrificial layer as a mask to form a first lightly doped region on sidewalls and a bottom surface of the first source / drain opening. By means of the first sacrificial layer, the manufacturing processes of the first source / drain opening, the second source / drain opening, and the first lightly doped region can be completed simultaneously, effectively reducing the number of sacrificial layers, thereby reducing production costs and improving production efficiency. In addition, the first lightly doped region is formed after the first source / drain opening is formed. Due to the reduction of the barrier in the first peripheral region, the ion implantation energy, dose, and ion implantation time during the formation of the first lightly doped region can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As the channel length of semiconductor devices shrinks, in order to obtain the required drive current and suppress the short-channel effect, semiconductor substrates and source / drain electrodes with better concentration doping are usually used, so as to generate a high electric field in the depletion region of the source / drain electrodes. When a high-voltage input / output device operates in the saturation current state, the inversion layer charges are accelerated by the transverse electric field on the channel surface and collide with the lattice to generate a large number of hot carriers (electron-hole pairs). Hot electrons and hot holes can cross the interface barrier and emit into the gate dielectric layer, forming the hot-carrier injection effect (Hot-Carrier Injection, HCI). The hot carriers entering the gate dielectric layer have the following effects: the increase of the threshold voltage, the decrease of the saturation drive current, and the decrease of the carrier mobility; at the same time, hot electrons or hot holes can also enter the substrate under the action of the junction electric field to form substrate leakage current. The above results caused by hot carriers will seriously affect the device working characteristics and reliability.

[0003] Currently, in the industry, to improve the hot-carrier injection effect problem of NMOS transistors, LDD (Lightly Doped Drain) ion implantation is usually used for optimization. By reducing the dose of LDD ion implantation and increasing the LDD implantation energy, the performance of semiconductor devices is improved.

[0004] However, there are still many problems in the LDD ion implantation process in the prior art. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, which can effectively improve production efficiency and save production costs.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region, the first region including a first peripheral region and a first core region, the first peripheral region having a plurality of first dummy gate structures arranged in parallel, a first dimension being between adjacent first dummy gate structures, the first core region having a plurality of second dummy gate structures arranged in parallel, a second dimension being between adjacent second dummy gate structures, the second dimension being smaller than the first dimension; forming a first sacrificial layer on the substrate to expose the first region; using the first sacrificial layer as a mask to form a plurality of first source / drain openings in the first peripheral region, the first source / drain openings being located between adjacent first dummy gate structures, and forming a plurality of second source / drain openings in the first core region, the second source / drain openings being located between adjacent second dummy gate structures; after forming the first source / drain openings and the second source / drain openings, using the first sacrificial layer as a mask to perform an ion tilt implantation process on the first region, and forming a first lightly doped region on the sidewall and bottom surface of the first source / drain openings, the first lightly doped region having a first ion.

[0007] Optionally, after forming the first lightly doped region, using the first sacrificial layer as a mask to form a first source / drain doped layer in the first source / drain openings and a second source / drain doped layer in the second source / drain openings, the first source / drain doped layer and the second source / drain doped layer having a second ion.

[0008] Optionally, the substrate includes a second region, the second region including a second peripheral region and a second core region, the second peripheral region having a plurality of third dummy gate structures arranged in parallel, a third dimension being between adjacent third dummy gate structures, the second core region having a plurality of fourth dummy gate structures arranged in parallel, a fourth dimension being between adjacent fourth dummy gate structures, the fourth dimension being smaller than the third dimension.

[0009] Optionally, after forming the first source / drain doped layer and the second source / drain doped layer, further comprising: removing the first sacrificial layer; forming a second sacrificial layer on the substrate to expose the second region; using the second sacrificial layer as a mask to form a plurality of third source / drain openings in the second peripheral region, the third source / drain openings being located between adjacent third dummy gate structures, and forming a plurality of fourth source / drain openings in the second core region, the fourth source / drain openings being located between adjacent fourth dummy gate structures; after forming the third source / drain openings and the fourth source / drain openings, using the second sacrificial layer as a mask to perform an ion tilt implantation process on the second region, and forming a second lightly doped region on the sidewall and bottom surface of the third source / drain openings, the second lightly doped region having a third ion, the third ion having an electrical type opposite to that of the first ion.

[0010] Optionally, after forming the second lightly doped region, the method further includes: using the second sacrificial layer as a mask to form a third source / drain doped layer in the third source / drain opening and a fourth source / drain doped layer in the fourth source / drain opening, where the third source / drain doped layer and the fourth source / drain doped layer contain a fourth ion, and the electrical type of the fourth ion is opposite to that of the second ion.

[0011] Optionally, the method for forming the first source / drain opening and the second source / drain opening includes: using the first sacrificial layer, the first pseudo-gate structure, and the second pseudo-gate structure as masks to etch the first peripheral region and the first core region to form the first source / drain opening and the second source / drain opening.

[0012] Optionally, the method for forming the third source / drain opening and the fourth source / drain opening includes: using the second sacrificial layer, the third pseudo-gate structure, and the fourth pseudo-gate structure as masks to etch the second peripheral region and the second core region to form the third source / drain opening and the fourth source / drain opening.

[0013] Optionally, the first ion includes: an N-type ion or a P-type ion; the third ion includes: a P-type ion or an N-type ion.

[0014] Optionally, the second ion includes: an N-type ion or a P-type ion; the fourth ion includes: a P-type ion or an N-type ion.

[0015] Optionally, the method for forming the first sacrificial layer includes: forming an initial first sacrificial layer on the substrate, where the initial first sacrificial layer covers the first region and the second region; using a patterning process to remove the initial first sacrificial layer located on the first region to form the first sacrificial layer.

[0016] Optionally, the method for forming the second sacrificial layer includes: forming an initial second sacrificial layer on the substrate, where the initial second sacrificial layer covers the first region and the second region; using a patterning process to remove the initial second sacrificial layer located on the second region to form the second sacrificial layer.

[0017] Optionally, after forming the third source / drain doped layer and the fourth source / drain doped layer, the method further includes: removing the second sacrificial layer; forming a dielectric layer on the substrate, where the dielectric layer covers the sidewalls of the first pseudo-gate structure, the second pseudo-gate structure, the third pseudo-gate structure, and the fourth pseudo-gate structure.

[0018] Optionally, after forming the dielectric layer, it also includes: removing the first dummy gate structure to form a first gate opening in the dielectric layer; removing the second dummy gate structure to form a second gate opening in the dielectric layer; removing the third dummy gate structure to form a third gate opening in the dielectric layer; removing the fourth dummy gate structure to form a fourth gate opening in the dielectric layer; forming a first gate structure in the first gate opening; forming a second gate structure in the second gate opening; forming a third gate structure in the third gate opening; and forming a fourth gate structure in the fourth gate opening.

[0019] Optionally, the substrate includes: a base and a plurality of first fins located on the base, and the first dummy gate structure and the second dummy gate structure respectively cross the first fins.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] In the formation method of the technical solution of the present invention, a first sacrificial layer exposing the first region is formed on the substrate, and the first source and drain openings and the second source and drain openings are formed using the first sacrificial layer as a mask; after the first source and drain openings and the second source and drain openings are formed, the first sacrificial layer is continued to be used as a mask for ion tilt implantation, and only the sidewalls and bottom surfaces of the first source and drain openings are formed with the first sacrificial layer. The first source and drain openings, the second source and drain openings, and the ion tilt implantation process can be completed simultaneously through the first sacrificial layer, which can effectively reduce the number of sacrificial layers, thereby reducing production costs and improving production efficiency. In addition, the first lightly doped region is formed after the first source and drain openings are formed. Since the first peripheral region and the blocking are reduced, the ion implantation energy, dose, and ion implantation time when the first lightly doped region is formed can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 4 It is a schematic diagram of the formation process of a semiconductor structure;

[0023] Figures 5 to 15 It is a schematic diagram of the structures of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0024] As described in the background art, the LDD ion implantation process in the prior art still has many problems, which will be described in detail below with reference to the accompanying drawings.

[0025] Figures 1 to 4 It is a schematic diagram of the formation process of a semiconductor structure.

[0026] Please refer to Figure 1, a substrate 100 is provided. The substrate 100 includes a first region I and a second region II. A plurality of first dummy gate structures 101 arranged in parallel are provided on the first region I, and a plurality of second dummy gate structures 102 arranged in parallel are provided on the second region II; a first sacrificial layer 103 is formed on the second region II, and the first sacrificial layer 103 covers the second dummy gate structures 102; a plurality of initial first lightly doped regions 104 are formed in the first region I, and the initial first lightly doped regions 104 are located between adjacent first dummy gate structures 101.

[0027] Please refer to Figure 2 , after forming the initial first lightly doped regions 104, the first sacrificial layer 103 is removed, and a second sacrificial layer 105 is formed on the first region I. The second sacrificial layer 105 covers the first dummy gate structures 101; a plurality of initial second lightly doped regions 106 are formed in the second region II, and the initial second lightly doped regions 106 are located between adjacent second dummy gate structures 102.

[0028] Please refer to Figure 3 , after forming the second lightly doped regions 106, the second sacrificial layer 105 is removed, and a third sacrificial layer 107 is formed on the second region II. The third sacrificial layer 107 covers the second dummy gate structures 102; a part of the initial first lightly doped regions 104 is removed to form the first lightly doped regions 108 and first source / drain openings; a first source / drain doping layer 109 is formed in the first source / drain openings.

[0029] Please refer to Figure 4 , after forming the first source / drain doping layer 109, the third sacrificial layer 107 is removed, and a fourth sacrificial layer 110 is formed on the first region I. The fourth sacrificial layer 110 covers the first dummy gate structures 101; a part of the initial second lightly doped regions 106 is removed to form the second lightly doped regions 111 and second source / drain openings; a second source / drain doping layer 112 is formed in the second source / drain openings.

[0030] In this embodiment, since the formation process of the first lightly doped regions 108 and the second lightly doped regions 111 is to first form the initial first lightly doped regions 104 and the initial second lightly doped regions 106, and then by removing a part of the initial first lightly doped regions 104 and a part of the initial second lightly doped regions 106, thereby forming the first lightly doped regions 108 and the second lightly doped regions 111. This process requires the consumption of the first sacrificial layer 103 and the second sacrificial layer 105. In the subsequent process of forming the first source / drain openings and the second source / drain openings, the third sacrificial layer 107 and the fourth sacrificial layer 110 also need to be consumed. This process sequence will not only increase the manufacturing cost but also reduce the production efficiency.

[0031] In addition, when forming the initial first lightly doped region 104 and the initial second lightly doped region 106, since it is necessary to ensure the depths and ion concentrations of the finally formed first lightly doped region 108 and second lightly doped region 111, the ion implantation energy, dose, and ion implantation time required for forming the initial first lightly doped region 104 and the initial second lightly doped region 106 will also increase.

[0032] On this basis, the present invention provides a method for forming a semiconductor structure. A first sacrificial layer exposing the first region is formed on the substrate, and using the first sacrificial layer as a mask, the first source-drain opening and the second source-drain opening are formed; after forming the first source-drain opening and the second source-drain opening, an ion tilt implantation process is continued using the first sacrificial layer as a mask, and a first lightly doped region is formed only on the sidewalls and bottom surface of the first source-drain opening. Through this manufacturing process, the number of sacrificial layers can be effectively reduced, thereby reducing the production cost and improving the production efficiency. In addition, the first lightly doped region is formed after forming the first source-drain opening. Since the blockage of the first peripheral region and the like is reduced, the ion implantation energy, dose, and ion implantation time for forming the first lightly doped region can be effectively reduced.

[0033] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0034] Figures 5 to 15 It is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0035] Please refer to Figure 5 , a substrate 200 is provided. The substrate 200 includes a first region I. The first region I includes a first peripheral region A1 and a first core region B1. A plurality of first pseudo-gate structures 201 are arranged in parallel on the first peripheral region A1. There is a first dimension d1 between adjacent first pseudo-gate structures 201. A plurality of second pseudo-gate structures 202 are arranged in parallel on the first core region B1. There is a second dimension d2 between adjacent second pseudo-gate structures 202. The second dimension d2 is smaller than the first dimension d1.

[0036] In this embodiment, the substrate 200 includes a second region II. The second region II includes a second peripheral region A2 and a second core region B2. A plurality of third pseudo-gate structures 203 are arranged in parallel on the second peripheral region A2. There is a third dimension d3 between adjacent third pseudo-gate structures 203. A plurality of fourth pseudo-gate structures 204 are arranged in parallel on the second core region B2. There is a fourth dimension d4 between adjacent fourth pseudo-gate structures 204. The fourth dimension d4 is smaller than the third dimension d3.

[0037] In this embodiment, the substrate 200 includes a base and a plurality of first fin portions (not labeled) located on the base, and the first dummy gate structure 201 and the second dummy gate structure 202 respectively straddle the first fin portions.

[0038] In this embodiment, the substrate 200 further includes a plurality of second fin portions (not labeled) located on the base, and the third dummy gate structure 203 and the fourth dummy gate structure 204 respectively straddle the second fin portions.

[0039] In this embodiment, the first region I and the second region II are used to form different types of transistor structures, and the transistor structures formed on the first peripheral region A1 and the second peripheral region A2 operate in a high-voltage state. Therefore, in order to overcome the hot carrier injection effect of the transistors, it is necessary to form lightly doped drain (LDD) regions in the transistor structures of the first peripheral region A1 and the second peripheral region A2.

[0040] Please refer to Figure 6 , a first sacrificial layer 217 exposing the first region I is formed on the substrate 200.

[0041] In this embodiment, the method for forming the first sacrificial layer 217 includes: forming an initial first sacrificial layer (not shown) on the substrate 200, the initial first sacrificial layer covering the first region I and the second region II; using a patterning process to remove the initial first sacrificial layer located on the first region I to form the first sacrificial layer 217.

[0042] In this embodiment, the formation process of the first sacrificial layer 217 adopts an atomic layer deposition process.

[0043] Please refer to Figure 7 , using the first sacrificial layer 217 as a mask, a plurality of first source / drain openings 205 are formed in the first peripheral region A1, the first source / drain openings 205 are located between adjacent first dummy gate structures 201, and a plurality of second source / drain openings 206 are formed in the first core region B1, the second source / drain openings 206 are located between adjacent second dummy gate structures 202.

[0044] In this embodiment, the method for forming the first source / drain openings 205 and the second source / drain openings 206 includes: etching the first peripheral region A1 and the first core region B1 using the first sacrificial layer 217, the first dummy gate structure 201 and the second dummy gate structure 202 as masks to form the first source / drain openings 205 and the second source / drain openings 206.

[0045] Please refer to Figure 8, after forming the first source / drain opening 205 and the second source / drain opening 206, using the first sacrificial layer 217 as a mask, performing an ion tilt implantation process on the first region I to form a first lightly doped region 207 on the sidewall and bottom surface of the first source / drain opening 205, and the first lightly doped region 207 contains first ions.

[0046] In this embodiment, a first sacrificial layer 217 exposing the first region I is formed on the substrate 200, using the first sacrificial layer 217 as a mask, forming the first source / drain opening 205 and the second source / drain opening 206; after forming the first source / drain opening 205 and the second source / drain opening 206, continuing to perform an ion tilt implantation process using the first sacrificial layer 217 as a mask, and only forming a first lightly doped region 207 on the sidewall and bottom surface of the first source / drain opening 205. Through the first sacrificial layer 217, the manufacturing processes of the first source / drain opening 205, the second source / drain opening 206, and the ion tilt implantation process can be completed simultaneously, which can effectively reduce the number of sacrificial layers, thereby reducing the production cost and improving the production efficiency. In addition, the first lightly doped region 207 is formed after forming the first source / drain opening 205. Due to the reduction of the blockage of the first peripheral region A1, the ion implantation energy, dose, and ion implantation time when forming the first lightly doped region 207 can be effectively reduced.

[0047] In this embodiment, since the density of the transistor structures in the first peripheral region A1 is less than the density of the transistor structures in the first core region B1, an ion tilt implantation process can be used to ensure that only a first lightly doped region 207 is formed on the sidewall and bottom surface of the first source / drain opening 205.

[0048] In this embodiment, the implantation angle for performing the ion tilt implantation process on the first region I is related to the first dimension d1, the second dimension d2, the height h1 of the first dummy gate structure 201, the height h2 of the second dummy gate structure 202, the aspect ratio of the first source / drain opening 205, and the aspect ratio of the second source / drain opening 206. Utilizing the shadowing effect of ion tilt implantation, finally only a first lightly doped region 207 is formed on the sidewall and bottom surface of the first source / drain opening 205.

[0049] Please refer to Figure 9 , after forming the first lightly doped region 207, using the first sacrificial layer 217 as a mask, forming a first source / drain doped layer 208 in the first source / drain opening 205 and forming a second source / drain doped layer 209 in the second source / drain opening 206, and the first source / drain doped layer 208 and the second source / drain doped layer 209 contain second ions.

[0050] In this embodiment, the forming method of the first source / drain doping layer 208 and the second source / drain doping layer 209 includes: forming a first epitaxial layer (not shown) in the first source / drain opening 205 by using an epitaxial growth process, and forming a second epitaxial layer (not shown) in the second source / drain opening 206; during the formation of the first epitaxial layer, doping the second ions into the first epitaxial layer by using an in-situ doping process to form the first source / drain doping layer 208; during the formation of the second epitaxial layer, doping the second ions into the second epitaxial layer by using an in-situ doping process to form the second source / drain doping layer 209.

[0051] Please refer to Figure 10 , after the formation of the first source / drain doping layer 208 and the second source / drain doping layer 209, removing the first sacrificial layer 217; forming a second sacrificial layer 210 on the substrate 200 to expose the second region II.

[0052] In this embodiment, the forming method of the second sacrificial layer 210 includes: forming an initial second sacrificial layer (not shown) on the substrate 200, the initial second sacrificial layer covering the first region I and the second region II; using a patterning process to remove the initial second sacrificial layer located on the second region II to form the second sacrificial layer 210.

[0053] In this embodiment, the forming process of the second sacrificial layer 210 adopts an atomic layer deposition process.

[0054] Please refer to Figure 11 , using the second sacrificial layer 210 as a mask, forming a plurality of third source / drain openings 211 in the second peripheral region A2, the third source / drain openings 211 being located between adjacent third pseudo-gate structures 203, and forming a plurality of fourth source / drain openings 212 in the second core region B2, the fourth source / drain openings 212 being located between adjacent fourth pseudo-gate structures 204.

[0055] In this embodiment, the forming method of the third source / drain openings 211 and the fourth source / drain openings 212 includes: etching the second peripheral region A2 and the second core region B2 by using the second sacrificial layer 210, the third pseudo-gate structures 203 and the fourth pseudo-gate structures 204 as masks to form the third source / drain openings 211 and the fourth source / drain openings 212.

[0056] Please refer to Figure 12, after forming the third source / drain opening 211 and the fourth source / drain opening 212, using the second sacrificial layer 210 as a mask, performing an ion tilt implantation process on the second region II to form a second lightly doped region 213 on the sidewall and bottom surface of the third source / drain opening 211. The second lightly doped region 213 contains a third ion, and the electrical type of the third ion is opposite to that of the first ion.

[0057] In this embodiment, since the density of the transistor structures in the second peripheral region A2 is less than the density of the transistor structures in the second core region B2, an ion tilt implantation process can be used to ensure that the second lightly doped region 213 is formed only on the sidewall and bottom surface of the third source / drain opening 211.

[0058] In this embodiment, the implantation angle for performing the ion tilt implantation process on the second region II is related to the third dimension d3, the fourth dimension d4, the height h3 of the third dummy gate structure 203, the height h4 of the fourth dummy gate structure 204, the aspect ratio of the third source / drain opening 211, and the aspect ratio of the fourth source / drain opening 212. Utilizing the shadowing effect of ion tilt implantation, finally, the second lightly doped region 213 is formed only on the sidewall and bottom surface of the third source / drain opening 211.

[0059] In this embodiment, the first ion is an N-type ion and the third ion is a P-type ion; in other embodiments, the first ion can also be a P-type ion and the third ion is an N-type ion.

[0060] Please refer to Figure 13 , after forming the second lightly doped region 213, using the second sacrificial layer 210 as a mask, forming a third source / drain doped layer 214 in the third source / drain opening 211 and forming a fourth source / drain doped layer 215 in the fourth source / drain opening 212. The third source / drain doped layer 214 and the fourth source / drain doped layer 215 contain a fourth ion, and the electrical type of the fourth ion is opposite to that of the second ion.

[0061] In this embodiment, the forming method of the third source / drain doped layer 214 and the fourth source / drain doped layer 215 includes: forming a third epitaxial layer (not shown) in the third source / drain opening 211 and forming a fourth epitaxial layer (not shown) in the fourth source / drain opening 212 by using an epitaxial growth process; during the process of forming the third epitaxial layer, doping the fourth ion into the third epitaxial layer by using an in-situ doping process to form the third source / drain doped layer 214; during the process of forming the fourth epitaxial layer, doping the fourth ion into the fourth epitaxial layer by using an in-situ doping process to form the fourth source / drain doped layer 215.

[0062] In this embodiment, the second ions are N-type ions and the fourth ions are P-type ions; in other embodiments, the second ions may also be P-type ions and the fourth ions are N-type ions.

[0063] Please refer to Figure 14 , after forming the third source / drain doping layer 214 and the fourth source / drain doping layer 215, remove the second sacrificial layer 210; form a dielectric layer 216 on the substrate 200, and the dielectric layer 216 covers the sidewalls of the first dummy gate structure 201, the second dummy gate structure 202, the third dummy gate structure 203, and the fourth dummy gate structure 204.

[0064] In this embodiment, the material of the dielectric layer 216 is silicon oxide; in other embodiments, the material of the dielectric layer may also be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0065] Please refer to Figure 15 , after forming the dielectric layer 216, form a first gate structure 221, a second gate structure 218, a third gate structure 219, and a fourth gate structure 220 in the dielectric layer 210.

[0066] In this embodiment, the forming method of the first gate structure 221, the second gate structure 218, the third gate structure 219, and the fourth gate structure 220 includes: removing the first dummy gate structure 201 to form a first gate opening (not labeled) in the dielectric layer 216; removing the second dummy gate structure 202 to form a second gate opening (not labeled) in the dielectric layer 216; removing the third dummy gate structure 203 to form a third gate opening (not labeled) in the dielectric layer 216; removing the fourth dummy gate structure 204 to form a fourth gate opening (not labeled) in the dielectric layer 216; forming the first gate structure 221 in the first gate opening; forming the second gate structure 218 in the second gate opening; forming the third gate structure 219 in the third gate opening; forming the fourth gate structure 220 in the fourth gate opening.

[0067] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a first region, the first region including a first peripheral region and a first core region, a plurality of first dummy gate structures arranged in parallel on the first peripheral region, a first dimension being between adjacent first dummy gate structures, a plurality of second dummy gate structures arranged in parallel on the first core region, a second dimension being between adjacent second dummy gate structures, and the second dimension being smaller than the first dimension; Forming a first sacrificial layer on the substrate to expose the first region; Using the first sacrificial layer as a mask, forming a plurality of first source / drain openings in the first peripheral region, the first source / drain openings being located between adjacent first dummy gate structures, and forming a plurality of second source / drain openings in the first core region, the second source / drain openings being located between adjacent second dummy gate structures; After forming the first source / drain openings and the second source / drain openings, using the first sacrificial layer as a mask, performing an ion tilt implantation process on the first region by using the shadow effect of ion tilt implantation, and forming a first lightly doped region on the sidewall and bottom surface of the first source / drain openings, the first lightly doped region having first ions.

2. The method for forming a semiconductor structure according to claim 1, wherein After forming the first lightly doped region, further including: using the first sacrificial layer as a mask, forming a first source / drain doped layer in the first source / drain openings, forming a second source / drain doped layer in the second source / drain openings, and the first source / drain doped layer and the second source / drain doped layer having second ions.

3. The method for forming a semiconductor structure as described in claim 2, wherein, The substrate includes a second region, the second region including a second peripheral region and a second core region, a plurality of third dummy gate structures arranged in parallel on the second peripheral region, a third dimension being between adjacent third dummy gate structures, a plurality of fourth dummy gate structures arranged in parallel on the second core region, a fourth dimension being between adjacent fourth dummy gate structures, and the fourth dimension being smaller than the third dimension.

4. The method for forming a semiconductor structure according to claim 3, wherein After forming the first source / drain doped layer and the second source / drain doped layer, further including: removing the first sacrificial layer; forming a second sacrificial layer on the substrate to expose the second region; using the second sacrificial layer as a mask, forming a plurality of third source / drain openings in the second peripheral region, the third source / drain openings being located between adjacent third dummy gate structures, forming a plurality of fourth source / drain openings in the second core region, the fourth source / drain openings being located between adjacent fourth dummy gate structures; after forming the third source / drain openings and the fourth source / drain openings, using the second sacrificial layer as a mask, performing an ion tilt implantation process on the second region by using the shadow effect of ion tilt implantation, and forming a second lightly doped region on the sidewall and bottom surface of the third source / drain openings, the second lightly doped region having third ions, and the electrical type of the third ions being opposite to that of the first ions.

5. The method for forming the semiconductor structure according to claim 4, wherein, After forming the second lightly doped region, further including: using the second sacrificial layer as a mask, forming a third source / drain doped layer in the third source / drain openings, forming a fourth source / drain doped layer in the fourth source / drain openings, and the third source / drain doped layer and the fourth source / drain doped layer having fourth ions, and the electrical type of the fourth ions being opposite to that of the second ions.

6. The method for forming a semiconductor structure according to claim 1, wherein The forming method of the first source-drain opening and the second source-drain opening includes: etching the first peripheral region and the first core region by using the first sacrificial layer, the first pseudo-gate structure, and the second pseudo-gate structure as masks to form the first source-drain opening and the second source-drain opening.

7. The method for forming the semiconductor structure according to claim 4, wherein The forming method of the third source-drain opening and the fourth source-drain opening includes: etching the second peripheral region and the second core region by using the second sacrificial layer, the third pseudo-gate structure, and the fourth pseudo-gate structure as masks to form the third source-drain opening and the fourth source-drain opening.

8. The method for forming a semiconductor structure according to claim 4, wherein The first ion includes: an N-type ion or a P-type ion; the third ion includes: a P-type ion or an N-type ion.

9. The method for forming the semiconductor structure as described in claim 5, wherein, The second ion includes: an N-type ion or a P-type ion; the fourth ion includes: a P-type ion or an N-type ion.

10. The method for forming a semiconductor structure as claimed in claim 3, wherein, The forming method of the first sacrificial layer includes: forming an initial first sacrificial layer on the substrate, the initial first sacrificial layer covering the first region and the second region; using a patterning process to remove the initial first sacrificial layer located on the first region to form the first sacrificial layer.

11. The method for forming a semiconductor structure according to claim 4, wherein, The forming method of the second sacrificial layer includes: forming an initial second sacrificial layer on the substrate, the initial second sacrificial layer covering the first region and the second region; using a patterning process to remove the initial second sacrificial layer located on the second region to form the second sacrificial layer.

12. The method for forming a semiconductor structure as described in claim 5, wherein After forming the third source-drain doping layer and the fourth source-drain doping layer, it further includes: removing the second sacrificial layer; forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the first pseudo-gate structure, the second pseudo-gate structure, the third pseudo-gate structure, and the fourth pseudo-gate structure.

13. The method for forming the semiconductor structure according to claim 12, wherein, After forming the dielectric layer, it further includes: removing the first pseudo-gate structure to form a first gate opening in the dielectric layer; removing the second pseudo-gate structure to form a second gate opening in the dielectric layer; removing the third pseudo-gate structure to form a third gate opening in the dielectric layer; removing the fourth pseudo-gate structure to form a fourth gate opening in the dielectric layer; forming a first gate structure in the first gate opening; forming a second gate structure in the second gate opening; forming a third gate structure in the third gate opening; forming a fourth gate structure in the fourth gate opening.

14. The method for forming a semiconductor structure according to claim 1, wherein, The substrate includes: a substrate and a plurality of first fins located on the substrate, the first pseudo-gate structure and the second pseudo-gate structure respectively straddling the first fins.

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