Nanowire transistor and method of making the same

Abstract

A nanowire transistor and a method for fabricating the same are disclosed. The method for fabricating the nanowire transistor includes forming a channel structure on a substrate, wherein the channel structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, forming a gate structure on the channel structure, and forming a source / drain structure beside the gate structure, wherein the source / drain structure includes graphene.

Description

TECHNICAL FIELD

[0001] The present application relates to a nanowire transistor and a method for fabricating the same, and more particularly to a nanowire transistor with graphene as a source / drain structure or a contact plug and a method for fabricating the same. BACKGROUND

[0002] In recent years, the semiconductor industry has been trying to scale down the size of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to achieve higher operation speed and higher device density. However, the device size cannot be scaled down indefinitely. When the device size is scaled down to below 30 nm, serious short channel effects and gate dielectric thickness-induced leakage current increase the static power consumption of the device and even make the device completely lose its function. One-dimensional devices constructed from nanowires or nanotubes are considered to have the greatest chance of replacing the existing silicon technology because of their lower technical risk. Among them, nanowire transistors have higher channel carrier mobility, and quantum effects can further enhance the mobility of carriers. In addition, the use of high-dielectric-constant dielectric layers can further improve the control ability of the gate, so they are quite promising transistor devices. SUMMARY

[0003] One embodiment of the present application discloses a method for fabricating a nanowire transistor. First, a channel structure is formed on a substrate, wherein the channel structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, then a gate structure is formed on the channel structure, and a source / drain structure is formed beside the gate structure, wherein the source / drain structure comprises graphene.

[0004] Another embodiment of the present application discloses a nanowire transistor, which mainly comprises a channel structure disposed on a substrate, a gate structure disposed on the channel structure and surrounding the channel structure, and a source / drain structure disposed on both sides of the gate structure, wherein the source / drain structure comprises graphene.

[0005] Still another embodiment of the present application discloses a nanowire transistor, which mainly comprises a channel structure disposed on a substrate, a gate structure disposed on the channel structure and surrounding the channel structure, a source / drain structure disposed on both sides of the gate structure, an interlayer dielectric layer surrounding the gate structure, and a contact plug disposed in the interlayer dielectric layer and electrically connected to the source / drain structure, wherein the contact plug comprises graphene. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1 to 8 A schematic diagram of a method for fabricating a nanowire transistor according to one embodiment of the present application;

[0007] Figure 9 Structure of a nanowire transistor according to an embodiment of the application.

[0008] Figure 10 Structure of a nanowire transistor according to an embodiment of the application.

[0009] Main element symbol explanation

[0010] 12: substrate

[0011] 14: channel structure

[0012] 16: first semiconductor layer

[0013] 18: first semiconductor layer

[0014] 20: first semiconductor layer

[0015] 22: second semiconductor layer

[0016] 24: second semiconductor layer

[0017] 26: second semiconductor layer

[0018] 28: gate structure

[0019] 30: dielectric layer

[0020] 32: hard mask

[0021] 34: spacer

[0022] 36: spacer

[0023] 40: source / drain structure

[0024] 44: opening

[0025] 46: opening

[0026] 48: high-k dielectric layer

[0027] 50: work function metal layer

[0028] 52: low impedance metal layer

[0029] 54: gate structure

[0030] 56: first portion

[0031] 58: second portion

[0032] 60: interlayer dielectric layer

[0033] 62: contact plug

[0034] 64: barrier layer

[0035] 66: Metal layer

[0036] 68: First Barrier Layer

[0037] 70: Siliconized metal layer

[0038] 72: Graphene layer

[0039] 74: Second Barrier Layer

[0040] 76: Metal layer

[0041] 82: NMOS region

[0042] 84: PMOS region Detailed Implementation

[0043] Please refer to Figures 1 to 8 , Figures 1 to 8 This is a schematic diagram illustrating a method for fabricating a nanowire transistor according to an embodiment of the present invention. Figure 1 As shown, a substrate 12, such as a silicon substrate, is first provided, and then a stacked structure or channel structure 14 is formed on the substrate 12. In this embodiment, the channel structure 14 is preferably formed by alternating stacking of multiple first semiconductor layers 16, 18, 20 and second semiconductor layers 22, 24, 26. The first semiconductor layers 16, 18, 20 and the second semiconductor layers 22, 24, 26 preferably contain different materials or different lattice constants, and the first semiconductor layers 16, 18, 20 and the second semiconductor layers 22, 24, 26 can all be selected from the group consisting of silicon, germanium, doped silicon, doped germanium, and silicon germanide. It should be noted that although the stacked structure disclosed in this embodiment uses three first semiconductor layers 16, 18, 20 alternating with three second semiconductor layers 22, 24, 26 as an example, the number of first semiconductor layers 16, 18, 20 and second semiconductor layers 22, 24, 26 is not limited to this and can be arbitrarily adjusted according to the manufacturing process or product requirements.

[0044] like Figure 2 As shown, a photolithography and etching process is then performed, for example, using a patterned photoresist (not shown) as a mask to remove part of the channel structure 14 and part of the substrate 12 to form a groove (not shown) on the substrate 12. Then, a dielectric layer 30 is formed in the groove on the portion of the substrate 12 to electrically isolate the patterned channel structure 14, and the upper surface of the dielectric layer 30 is flush with the lower surface of the bottommost first semiconductor layer 16. In this embodiment, the dielectric layer 30 may be made of silicon oxide, but is not limited to this.

[0045] Subsequently, as Figure 3As shown, a gate structure 28 and a hard mask 32 are formed across the channel structure 14, and then a spacer 34 is formed on the sidewalls of the gate structure 28 and the hard mask 32. In this embodiment, the gate structure 28 can be composed of polysilicon, the hard mask 32 can include silicon nitride, and the spacer 34 can be selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and silicon carbon nitride, but is not limited thereto. It should be noted that the spacer 34 in this embodiment is a single-layer spacer, but can also be a composite spacer according to process requirements. For example, the spacer 34 can further include one or more spacers, and the composite spacers can be of the same or different materials. According to an embodiment of the present application, the composite spacer can include, for example, a double-layer composite spacer composed of silicon dioxide and silicon nitride, or a three-layer composite spacer composed of silicon oxide-silicon nitride-silicon oxide, which are all within the scope of the present application.

[0046] Please refer to Figure 4 and Figure 5 , wherein Figure 5 is followed by Figure 4 a cross-sectional view along the tangent AA'. As shown in Figure 4 and Figure 5 , a photolithography and etching process is performed or the hard mask 32 is directly used as a mask to remove the channel structure 14 on both sides of the spacer 34 to form a groove (not shown). Then the hard mask 32 and part of the first semiconductor layers 16, 18, and 20 are removed, and another spacer 36 is formed beside the first semiconductor layers 16, 18, and 20, and the sidewalls of the spacer 36 are preferably cut flush with the sidewalls of the second semiconductor layers 22, 24, and 26 and the sidewalls of the spacer 34 above. In this embodiment, the spacer 34 and the spacer 36 can include the same or different materials, such as silicon dioxide and silicon nitride, which are all within the scope of the present application.

[0047] Then a source / drain structure 40 is formed on the substrate 12 on both sides of the spacer 36, wherein the source / drain structure 40 is preferably composed of graphene. In this embodiment, the source / drain structure 40 can be prepared by first forming an epitaxial layer composed of, for example, silicon carbide on the substrate on both sides of the spacer 36 using an epitaxial growth method, and then performing a heating process to thermally decompose or sublimate the silicon atoms in the epitaxial layer at a temperature of about 700-800 degrees Celsius to form the source / drain structure 40 composed of graphene.

[0048] Subsequently as shown in Figure 6As shown, an etching process is first performed to remove the hard mask 32 and the gate structure 28 to form an opening 44, and then another selective etching process is performed to remove the first semiconductor layers 16, 18, and 20 to form multiple openings 46. Since the first semiconductor layers 16, 18, and 20 and the second semiconductor layers 22, 24, and 26 are made of different materials and there is a predetermined etching selectivity between them, in this embodiment, it is preferable that the etching removal of the first semiconductor layers 16, 18, and 20 does not damage any of the second semiconductor layers 22, 24, and 26.

[0049] According to one embodiment of the present invention, the first semiconductor layers 16, 18, 20 and the gate structure 28 can be made of the same material, for example, all containing polycrystalline silicon, while the second semiconductor layers 22, 24, 26 can be selected from the group consisting of single-crystal silicon, germanium, doped silicon, doped germanium, and silicon germanide. In this way, the hard mask 32 and the first semiconductor layers 16, 18, 20 can be removed simultaneously using an etching process. This embodiment is also within the scope of the present invention. Alternatively, after removing the first semiconductor layers 16, 18, 20 by etching, a portion of the second semiconductor layers 22, 24, 26 can be selectively removed by oxidation or another etching process, etching the originally approximately cubic second semiconductor layers 22, 24, 26 into an approximately arc shape to form the nanowire channel structure 14. This embodiment is also within the scope of the present invention.

[0050] Then as Figure 7 As shown, a high-dielectric-constant dielectric layer 48, a work-function metal layer 50, and a low-impedance metal layer 52 are sequentially formed within openings 44 and 46, and then planarized to form a gate structure 54. In this embodiment, the gate structure 54 preferably comprises two parts, wherein the first part 56 is disposed directly above the second semiconductor layers 22, 24, and 26, and the second part 58 is staggered with the second semiconductor layers 22, 24, and 26. From another perspective, the high-dielectric-constant dielectric layer 48 and the work-function metal layer 50 cover the second semiconductor layers 22, 24, and 26, while the low-impedance metal layer 52 fills the openings 44 and 46.

[0051] In this embodiment, the high-k dielectric layer 48 comprises a dielectric material having a dielectric constant greater than 4, such as selected from the group consisting of hafnium oxide (Hf02), hafnium silicon oxide (HfSi04), hafnium silicon oxynitride (HfSiON), aluminum oxide (AI2O3), lanthanum oxide (La203), tantalum oxide (Ta205), yttrium oxide (Y203), zirconium oxide (Zr02), strontium titanate oxide (SrTi03), zirconium silicon oxide (ZrSi04), hafnium zirconium oxide (HfZr04), strontium bismuth tantalate (SrBi2Ta20g, SBT), lead zirconate titanate (PbZrTi03, PZT), barium strontium titanate (BaSrTi03, BST), or combinations thereof. x Ti 1-xO3 ,PZT), barium strontium titanate (Ba x Sr 1- x Ti03, BST), or combinations thereof.

[0052] The work function metal layer 50 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 50 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 50 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 50 and the low impedance metal layer 52. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 52 may be selected from low-resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof. Since converting a dummy gate into a metal gate using a metal gate replacement fabrication process is a well-known technique in the art, it will not be described further here. Subsequently, a portion of the high dielectric constant dielectric layer 48, a portion of the work function metal layer 50, and a portion of the low impedance metal layer 52 may be removed to form a groove (not shown).

[0053] Then as Figure 8 As shown, an interlayer dielectric layer 60 is formed on the source / drain structure 40 and fills the groove. In this embodiment, the interlayer dielectric layer 60 can be made of any insulating material containing oxides, such as an oxide layer made of tetraethyl orthosilicate (TEOS), but is not limited thereto. Then, a contact plug fabrication process is performed to form a contact plug 62 that electrically connects to the source / drain structure 40. In this embodiment, the contact plug 62 can be formed by first using an etching process to completely remove part of the interlayer dielectric layer 60 to form a contact hole (not shown) and expose the surface of the source / drain structure 40, then sequentially depositing a barrier layer 64 and a metal layer 66 in the contact hole and filling the contact hole, and then using a planarization process, such as a CMP process, to remove part of the metal layer 66 and part of the barrier layer 64 to form the contact plug 62 in the opening, wherein the upper surface of the contact plug 62 is preferably flush with the upper surface of the interlayer dielectric layer 60. In this embodiment, the barrier layer 64 is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride, and tungsten nitride, and the metal layer 66 is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum, and copper, but is not limited thereto. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention.

[0054] Referring back to Figure 9 , Figure 9 A schematic diagram of a nanowire transistor according to an embodiment of the present application is shown. As shown, in contrast to the aforementioned embodiments in which a contact hole is formed and then filled with a barrier layer 64 and a metal layer 66 to form a contact plug 62, the present embodiment further comprises a first barrier layer 68 deposited in the contact hole after the contact hole is formed, wherein the first barrier layer 68 is preferably formed conformally on the surface of the source / drain structure 40 and the inner sidewall of the contact hole. In the present embodiment, the first barrier layer 68 is preferably selected from the group consisting of titanium, cobalt, nickel and platinum, and is most preferably titanium. Then a first thermal treatment fabrication process and a second thermal treatment fabrication process are performed in sequence to form a metal silicide layer 70 on the surface of the source / drain structure 40. In the present embodiment, the first thermal treatment fabrication process comprises a soak anneal fabrication process, which is preferably performed at a temperature of 500-600 °C, and most preferably at 550 °C, and for a time period of 10-60 seconds, and most preferably for 30 seconds. The second thermal treatment fabrication process comprises a spike anneal fabrication process, which is preferably performed at a temperature of 600-950 °C, and most preferably at 600 °C, and for a time period of 100 milliseconds to 5 seconds, and most preferably for 5 seconds.

[0055] A graphene layer 72 is then formed on the surface of the metal silicide layer 70 in a manner similar to that described above for forming the source / drain structure 40, and a second barrier layer 74 and a metal layer 76 are then selectively formed on the graphene layer 72 and filled into the contact hole, wherein the second barrier layer 74 preferably comprises a metal compound such as titanium nitride or tantalum nitride, and the metal layer 76 preferably comprises tungsten, but is not limited thereto. Finally, a planarization fabrication process is performed to partially remove portions of the metal layer 76, the second barrier layer 74, the graphene layer 72 and the first barrier layer 68, and if necessary, portions of the ILD layer 60, to form the contact plug 62 electrically connected to the source / drain structure 40.

[0056] Referring back to Figure 10 , Figure 10 A schematic diagram of a nanowire transistor according to an embodiment of the present application is shown. As shown, in contrast to the aforementioned embodiments in which a contact hole is formed and then filled with a barrier layer 64 and a metal layer 66 to form a contact plug 62, the present embodiment further comprises a first barrier layer 68 deposited in the contact hole after the contact hole is formed, wherein the first barrier layer 68 is preferably formed conformally on the surface of the source / drain structure 40 and the inner sidewall of the contact hole. In the present embodiment, the first barrier layer 68 is preferably selected from the group consisting of titanium, cobalt, nickel and platinum, and is most preferably titanium. Then a first thermal treatment fabrication process and a second thermal treatment fabrication process are performed in sequence to form a metal silicide layer 70 on the surface of the source / drain structure 40. In the present embodiment, the first thermal treatment fabrication process comprises a soak anneal fabrication process, which is preferably performed at a temperature of 500-600 °C, and most preferably at 550 °C, and for a time period of 10-60 seconds, and most preferably for 30 seconds. The second thermal treatment fabrication process comprises a spike anneal fabrication process, which is preferably performed at a temperature of 600-950 °C, and most preferably at 600 °C, and for a time period of 100 milliseconds to 5 seconds, and most preferably for 5 seconds. Figure 10 Figure 8 Figure 9 As shown, in contrast to the aforementioned embodiments in which only a single conductivity type of transistor is fabricated, the present embodiment further comprises applying the embodiment of the present application in which a graphene layer is used to form the source / drain structure 40 in Figures 1 to 8 or the embodiment of the present application in which a graphene layer is used to simultaneously form the source / drain structure 40 and the contact plug 62 to the fabrication of a complementary nanowire transistor element. For example, an NMOS region 82 and a PMOS region 84 can first be defined on the substrate 12, and then the aforementioned​​Figures 1 to 8 The fabrication process of the graphene source / drain structure 40 and / or the contact plug 62 in the NMOS region 82 and the PMOS region 84 is performed respectively.

[0057] It is worth noting that, compared with the final channel structure of the nanowire transistor in the foregoing embodiments, the final channel structure of the nanowire transistor in the present embodiment can be selected from the group consisting of silicon, germanium, doped silicon, doped germanium, and silicon germanide. Before the work function metal layer of the NMOS region 82 and the PMOS region 84 is prepared, the first semiconductor layers 16, 18, and 20 of the NMOS region 82 and the second semiconductor layers 22, 24, and 26 of the PMOS region 84 can be removed, but the second semiconductor layers 22, 24, and 26 of the NMOS region 82 and the first semiconductor layers 16, 18, and 20 of the PMOS region 84 are retained as the channel structure 14 of each region. In other words, the channel structure 14 of the NMOS region 82 and the channel structure 14 of the PMOS region 84 preferably comprise different materials, for example, the channel structure 14 of the NMOS region 82 preferably comprises silicon, and the channel structure 14 of the PMOS region 84 preferably comprises silicon germanide.

[0058] In summary, the present application mainly integrates graphene into the source / drain structure and / or the contact plug of the nanowire transistor, and uses the zero bandgap characteristic of graphene to reduce the resistance between the source / drain structure and the contact plug, thereby improving the performance of the element.

[0059] The above description is only the preferred embodiment of the present application, and any equivalent changes and modifications made according to the claims of the present application should be included in the scope of the present application.

Claims

1. A method of fabricating a nanowire transistor, comprising: comprising: forming a channel structure on a substrate, wherein the channel structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers interleaved stacked; forming a gate structure on the channel structure; forming a source / drain structure beside the gate structure, wherein the source / drain structure comprises graphene; forming an interlayer dielectric layer around the gate structure; forming a contact hole in the interlayer dielectric layer; forming a first barrier layer on a surface of the source / drain structure and an inner sidewall of the contact hole; forming a metal silicide layer in the contact hole and directly contacting the source / drain structure; forming a graphene layer on the metal silicide layer; forming a second barrier layer on the graphene layer, wherein the first barrier layer, the graphene layer, and the second barrier layer are sequentially stacked on the inner sidewall of the contact hole; forming a metal layer on the second barrier layer; and planarizing the metal layer, the barrier layer, and the graphene layer to form a contact plug in the interlayer dielectric layer and electrically connecting the source / drain structure.

2. The method of claim 1, further comprising: forming a first spacer beside the gate structure; removing portions of the plurality of first semiconductor layers; forming a second spacer beside the plurality of first semiconductor layers; forming the source / drain structure beside the second spacer and the plurality of second semiconductor layers; removing the gate structure to form a first recess; removing the plurality of first semiconductor layers to form a second recess between the plurality of second semiconductor layers; and forming a functional metal layer in the first recess and the second recess.

3. The method of claim 2, wherein the first spacer sidewall is aligned with the second spacer sidewall.

4. The method of claim 2, wherein the first spacer sidewall is aligned with the plurality of second semiconductor layers sidewall.

5. The method of claim 2, wherein the contact plug comprises graphene. comprising: a channel structure on a substrate and comprising a plurality of semiconductor layers; 6. A nanowire transistor, characterized by a gate structure on the channel structure and surrounding the channel structure, wherein the gate structure comprises a first portion disposed directly above the plurality of semiconductor layers and a second portion disposed below the first portion, the second portion interleaved with the plurality of semiconductor layers; a source / drain structure on both sides of the gate structure, wherein the source / drain structure comprises graphene, an interlayer dielectric layer surrounding the gate structure; and a contact plug in a contact hole of the interlayer dielectric layer and electrically connecting the source / drain structure, wherein the contact plug comprises: a first barrier layer disposed on an inner sidewall of the contact hole of the interlayer dielectric layer; a metal silicide layer disposed on the source / drain structure; a graphene layer disposed on the metal silicide layer; a second barrier layer disposed on the graphene layer, wherein the first barrier layer, the graphene layer, and the second barrier layer are sequentially stacked on the inner sidewall of the contact hole; and a metal layer disposed on the barrier layer.

7. The nanowire transistor of claim 6, wherein the channel structure is selected from the group consisting of silicon, germanium, doped silicon, doped germanium, and silicon-germanium. ​ ​ ​ 8. The nanowire transistor of claim 6, further comprising a spacer adjacent to the gate structure, wherein the spacer sidewalls trim the channel structure sidewalls.

9. A nanowire transistor, characterized in that, Comprising: a channel structure disposed on a substrate; a gate structure disposed on and surrounding the channel structure; a source / drain structure disposed on both sides of the gate structure, wherein the source / drain structure comprises graphene; an interlayer dielectric layer surrounding the gate structure; and a contact plug disposed in a contact hole of the interlayer dielectric layer and electrically connected to the source / drain structure, wherein the contact plug comprises: a first barrier layer disposed on the inner sidewalls of the contact hole of the interlayer dielectric layer; a metal silicide layer disposed on the source / drain structure; a graphene layer disposed on the metal silicide layer; a second barrier layer disposed on the graphene layer, wherein the first barrier layer, the graphene layer, and the second barrier layer are sequentially stacked on the inner sidewalls of the contact hole; and a metal layer disposed on the barrier layer.

10. The nanowire transistor of claim 9, wherein the source / drain structure comprises an epitaxial layer.

11. The nanowire transistor of claim 9, wherein the channel structure is selected from the group consisting of silicon, germanium, doped silicon, doped germanium, and silicon- germanium.

12. The nanowire transistor of claim 9, further comprising a spacer adjacent to the gate structure, wherein the spacer sidewalls trim the channel structure sidewalls.

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