Nanowire transistor and method of making the same

By introducing graphene source/drain structures and contact plugs into nanowire transistors, combined with a high dielectric constant dielectric layer, the short-channel effect and leakage current problem of miniaturized semiconductor devices are solved, improving carrier mobility and device efficiency, making them suitable for high-density, high-speed semiconductor devices.

CN114792682BActive Publication Date: 2025-12-09UNITED MICROELECTRONICS CORP
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Patent Information

Application Number
CN202110101854.9
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-01-26
Publication Date
2025-12-09
Estimated Expiration
2041-06-11

AI Technical Summary

Technical Problem

When existing semiconductor devices are shrunk to below 30 nanometers, the short-channel effect and leakage current increase, leading to increased static power consumption and even loss of function. Traditional silicon-based devices face technical bottlenecks.

Method used

Graphene is used as the source/drain structure or contact plug of nanowire transistors. Combined with a high dielectric constant dielectric layer, the gate control capability is improved. A nanowire channel structure is formed through a specific process. The zero bandgap characteristic of graphene is used to reduce the resistance between the source/drain structure and the contact plug.

Benefits of technology

It improves the channel carrier mobility of nanowire transistors, reduces the resistance between the source/drain structure and the contact plug, and enhances the device's efficiency and gate control capability, making it suitable for high-density and high-speed semiconductor devices.

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Abstract

A nanowire transistor and a method for fabricating the same are disclosed. The method for fabricating the nanowire transistor includes forming a channel structure on a substrate, wherein the channel structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, forming a gate structure on the channel structure, and forming a source / drain structure beside the gate structure, wherein the source / drain structure includes graphene.
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