Improved semiconductor structures and power semiconductor devices

Abstract

The present invention provides an improved semiconductor structure and a power semiconductor device. On the basis of the existing semiconductor cell structure, a metal-like field plate formed of a high dielectric constant medium is added next to the drift region. The metal-like field plate modulates the conductivity of the on-state drift region and the high-voltage blocking electric field distribution in the off-state, thereby obtaining a higher breakdown voltage. At the same time, its process is easier to implement than other existing high-voltage and low-drift region on-resistance semiconductor cell structures, reducing the loss caused by charge mismatch at the same voltage, including the mismatch caused by the charge of the dielectric layer. This has great redundancy and benefits in reducing the difficulty of process implementation and process capability requirements, and improving the yield rate, while also improving the stability of the structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices and integrated circuits, and in particular to an improved semiconductor structure and a power semiconductor device. Background Art

[0002] Semiconductor devices, especially high-voltage silicon power devices, face a complex and conflicting relationship between the breakdown voltage and on-resistance of their drift region, which bears the withstand voltage. Achieving a high breakdown voltage generally makes it difficult to achieve a low on-resistance. This, of course, excludes situations where the withstand voltage drift region experiences large minority carrier or unbalanced double-carrier injection modulation when the device is on, as in devices such as insulated gate bipolar transistors (IGBTs), PIN diodes (PINs), and gate-controlled thyristors (GTOs). Generally, in high-voltage silicon semiconductor devices above 300V, a portion of the on-resistance is taken up by the device's high-voltage drift region. This situation becomes increasingly severe with increasing operating voltage. This is the most well-known silicon theoretical limitation of non-minority carrier-modulated power devices: the breakdown voltage to the power of 2.5 is proportional to the on-resistance of the drift region.

[0003] In order to reduce the on-resistance of the drift region of non-minority carrier modulation power devices under high voltage conditions, in the past decade or so, the industry has proposed some methods and device cell structures to reduce the on-resistance while maintaining the breakdown voltage unchanged for traditional device cell structures. The most famous is the super junction structure device based on the two-dimensional electric field principle of semiconductor PN junction RESURF and the charge balance principle.

[0004] In addition, there are many new implementation methods and equivalent structural technical solutions based on superjunction theory in the existing technology. Among these technologies, the solutions that can be industrially implemented are mainly structures and methods characterized by deep trenches. Among them, the inclined injection and epitaxial filling after the deep trenches are particularly close to the superjunction theory and are relatively easy to implement.

[0005] In general, the core of all existing technologies is based on the two-dimensional theory of superjunctions and also conforms to the RESURF principle. The core requirement is that if a two-dimensional semiconductor is to withstand a voltage higher than that of a parallel-plane junction in a certain direction while also reducing the on-resistance of the drift region, a PN junction must be formed on the side of the semiconductor parallel to the current flow direction. Furthermore, when the device is subjected to high voltage, both sides of this PN junction must be fully depleted and charge balance must be achieved. At the same time, the impurity concentration or the charge in the space depletion layer must meet the RESURF condition. In rare cases, fixed uniform charge in an insulator such as an oxide layer can be used to replace the charge in the space depletion layer on the side of the PN junction that does not participate in conduction.

[0006] by Figure 1 Take for example, to comprehensively explain the characteristics of existing technologies and the problems or shortcomings faced in their implementation. Figure 1 This is a highly summarized schematic diagram of a high-voltage, low-conductivity cell structure in the prior art. As shown in the figure, region 1 in the figure is the drift region that withstands high voltage when the device is turned off, and is also the current channel when the device is turned on; region 6 is the device active region, which can be the gate and channel region of VDMOS, or simply the main functional region of the device such as the Schottky or high-voltage PN junction diode junction region; region 7 is the device high-voltage and highly doped region, which can be the drain region of VMDOS, or a high-voltage electrode region with high doping and low resistance as a Schottky or PN junction diode.

[0007] It can be seen that Figure 1 The active region (i.e., region 6), drift region (i.e., region 1) and high-voltage electrode region (and region 7) constitute the basic functional elements of this type of high-voltage power device. They are the basic core structure that can work independently based on ordinary one-dimensional parallel plane PN junction high-voltage devices. The drift region 1 is the focus of the contradiction between high voltage and low on-resistance in this type of device, because this drift region withstands high voltage in reverse and becomes the inevitable path of current in forward conduction.

[0008] In order to further improve the performance of the device, that is, the performance of higher voltage and lower on-resistance, the existing technologies basically adopt the RESURF principle and the superjunction charge balance two-dimensional effect mechanism. Figure 1 Adding a region 2 with an opposite impurity type to the drift region 1 on the current side, and forming a so-called super junction with the device drift region 1 is the basic solution. This solution is based on the super junction theory and breaks through the theoretical limitations of the 2.5 power of the parallel plane PN junction on-resistance and withstand voltage. CoolMOS is the first generation of high-voltage power semiconductor devices. TM It is a typical example of this structure and has been commercially implemented.

[0009] In addition, a few existing technical solutions also propose to use the charge in the insulating medium to be equivalent to and replace area 2, such as Figure 1 The charge in the insulating medium is 3. Figure 1 In addition to regions 1, 2, and 3, some prior art device cell structures also have some minor additional structures, such as Figure 1 Regions 4 and 5 are often formed by semi-insulating layers such as polycrystalline and oxide layers, insulating layers such as silicon nitride, etc., alone or in combination. In most cases, region 4 is formed by a process technology characterized by deep trenches, and region 5 is generally a deformation of some structures at the bottom of deep trenches 4. In most cases, there is only region 4, and region 5 is not present or is not needed.

[0010] However, the above-mentioned existing technical solutions have the following difficulties or deficiencies in the process implementation of the device structure:

[0011] 1) For the device cell structure technology solution without region 4 and region 5, the charge balance between region 1 and region 2 is difficult to control. Generally, according to the RESURF principle, in the voltage range of 100V to 10000V, the charge density required for charge balance between region 1 and region 2 is 1×10 12 cm -2 ~2×10 12 cm -2 Within the range, the higher the voltage, the stricter the requirements, and a 10% change is only 1×10 11 cm -2 ~2×10 11 cm -2 Semiconductor technicians in the industry understand the difficulty of controlling this type of charge. This change, for a super-junction device operating at around 800V, will result in a change of approximately 150V. Therefore, commercialized devices generally must compromise on-state performance to balance breakdown and conduction characteristics. Considering the impact of variations in layout CD during the manufacturing process also increases the difficulty of implementing super-junction devices.

[0012] 2) For the device cell structure scheme with regions 4 and 5, similar to the case without regions 4 and 5, there is still the problem of difficult to control the charge balance between regions 1 and 2. Moreover, when there is an insulating medium in regions 4 and (or) 5, it is generally inevitable to introduce the interface charge of the insulating medium layer or the fixed charge in the insulating medium, typically such as the fixed oxide charge in the oxide layer. For thinner oxide layers, the fixed charge is relatively small. For thermal oxide layers of 20nm and above, the oxide charge is generally around 3×10 10 cm -2 ~2×10 11 cm -2 Of course, when the process control level is good, this charge is controllable and repeatable. Even so, for high-voltage power devices, their operating environment is generally relatively harsh, and they are inevitably subject to spike voltage interference, which can easily cause charge injection or degradation of the oxide layer, causing the superjunction to lose charge balance and affecting the stability of the high-voltage device.

[0013] 3) For the very few cases where charge substitution is used in the insulating layer Figure 1 When the middle region 2 forms a superjunction with the active functional region 1, the aforementioned uncertain charge influence unique to the conventional insulating layer still exists. On the other hand, the insulating layer charge currently used on the insulating layer is generally made of metal cesium (Cesium), which belongs to the alkali metal family and has poor compatibility with semiconductor silicon processes.

[0014] 4) In addition, there are two methods in the existing technology that are relatively easy to implement with deep trenches as process features, namely large tilt angle ion implantation and direct epitaxy. Large tilt angle can take advantage of the better dose accuracy of ion implantation, but the accuracy of tilt angle and equivalent impurity surface density of 1×10 10 cm -2 ~1×10 11 cm -2 The precision is also quite challenging. How to meet the requirements of modern planar integration process and close the deep trench without causing charge fluctuations in the superjunction structure system is also a difficult problem in process implementation. If a dielectric layer is used for sealing, the control of the charge of the dielectric insulating layer is a difficult point, and the excess injected impurity charge at the bottom of the deep trench also needs to be handled carefully. If polycrystalline or single crystal semiconductor epitaxy is used, the spatial depletion layer or single crystal defects need to be well controlled, otherwise it will cause serious reverse leakage. The direct epitaxial method requires precise control of the doping dose, with an absolute control accuracy of 1 to 2×10 11 cm -2 On the other hand, how to perfectly seal the deep trench without forming defects by epitaxially growing single crystals within the deep trench is also a difficult problem, otherwise it will also cause serious reverse leakage.

[0015] Therefore, there is an urgent need for a high-voltage silicon power device with high withstand voltage, low on-resistance and simple and easy-to-implement process. Summary of the Invention

[0016] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an improved semiconductor cell structure and a power semiconductor device for solving the above-mentioned technical problems.

[0017] To achieve the above-mentioned and other related objectives, the present invention provides an improved semiconductor structure, comprising at least:

[0018] a highly doped semiconductor material region;

[0019] an epitaxial layer, disposed on the highly doped semiconductor material region, wherein a deep trench is formed therein, and the deep trench vertically enters the highly doped semiconductor material region;

[0020] an active device region, disposed on the epitaxial layer;

[0021] a dielectric insulating layer, disposed on the sidewalls and bottom of the deep trench;

[0022] A high dielectric constant medium is arranged to fill the deep trench and contact the dielectric insulating layer;

[0023] A first electrode is disposed above the high dielectric constant medium and in contact with the high dielectric constant medium;

[0024] Among them, the criterion for the depth of the deep trench extending vertically into the highly doped semiconductor material region is: to make the highest electric field before breakdown at the interface between the active device region and the epitaxial layer equal to the highest electric field on one side of the epitaxial layer at the intersection of the epitaxial layer, the dielectric insulating layer and the highly doped semiconductor material region.

[0025] Optionally, the dielectric constant of the high dielectric constant medium is greater than 200.

[0026] Optionally, the highly doped semiconductor material region and the epitaxial layer are of the same conductive impurity type.

[0027] Optionally, the impurity concentration of the epitaxial layer is higher than the impurity concentration of the drift region corresponding to the parallel plane junction at the same operating voltage.

[0028] Optionally, the dielectric insulating layer includes a single-layer dielectric or a multi-layer dielectric.

[0029] Optionally, the semiconductor improved structure further includes:

[0030] The second electrode is arranged above the active device area and contacts the active device area, serving as a low-voltage electrode of the semiconductor improved structure, and the highly doped semiconductor material area corresponds to a high-voltage electrode of the semiconductor improved structure.

[0031] Optionally, the high voltage electrode includes a negative high voltage electrode.

[0032] To achieve the above-mentioned and other related objectives, the present invention further provides an improved semiconductor structure, comprising at least:

[0033] a highly doped semiconductor material region;

[0034] an epitaxial layer, disposed on the highly doped semiconductor material region, wherein a deep trench is formed therein, and the deep trench vertically enters the highly doped semiconductor material region;

[0035] an active device region, disposed on the epitaxial layer;

[0036] A high dielectric constant medium is arranged to fill the deep groove;

[0037] A first electrode is disposed above the high dielectric constant medium and in contact with the high dielectric constant medium;

[0038] Among them, the criterion for the depth of the deep trench extending vertically into the highly doped semiconductor material region is: to make the highest electric field before breakdown at the interface between the active device region and the epitaxial layer equal to the highest electric field on one side of the epitaxial layer at the intersection of the epitaxial layer, the high dielectric constant medium, and the highly doped semiconductor material region.

[0039] Optionally, the dielectric constant of the high dielectric constant medium is greater than 200.

[0040] Optionally, the semiconductor improved structure further includes:

[0041] The second electrode is arranged above the active device area and contacts the active device area, serving as a low-voltage electrode of the semiconductor improved structure, and the highly doped semiconductor material area corresponds to a high-voltage electrode of the semiconductor improved structure.

[0042] Optionally, the high voltage electrode includes a negative high voltage electrode.

[0043] To achieve the above objectives and other related objectives, the present invention further provides a power semiconductor device, which includes any one of the above-mentioned improved semiconductor structures.

[0044] As described above, the improved semiconductor structure and power semiconductor device of the present invention have at least the following beneficial effects:

[0045] 1) The process is easier to implement than other existing high-voltage and low-drift region on-resistance semiconductor cell structures;

[0046] 2) Because its working principle is that the potential distribution of the inclined field plate formed by the high dielectric constant medium modulates the electric field distribution in the drift region, it has a better suppression effect on the charge in the dielectric layer;

[0047] 3) The difficulty of implementing existing common superjunction charge balance process technology is reduced. The same voltage loss caused by charge mismatch, including mismatch caused by dielectric layer charge, has great redundancy and benefits in reducing process implementation difficulty and process capability requirements, improving yield, and also improving the stability of the structure.

[0048] 4) Compared with existing high-k structures, the breakdown voltage can be improved at the same drift region thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Shown is a schematic diagram of a conventional high-voltage, low on-resistance semiconductor cell structure.

[0050] Figure 2 Shown is a schematic diagram of the improved semiconductor structure in Example 1 of the present invention.

[0051] Figure 3-Figure 5 Shown is a process flow chart of the improved semiconductor structure in Example 1 of the present invention.

[0052] Figure 6 Shown is a schematic diagram of the improved semiconductor structure in the second embodiment of the present invention.

[0053] Explanation of Figure Numbers

[0054] 100—oxide layer, 101—highly doped semiconductor material region, 102—epitaxial layer, 103—active device region, 104—dielectric insulating layer, 105—high dielectric constant dielectric, 106—first electrode, 107—second electrode, T—deep trench, M—mirror. DETAILED DESCRIPTION

[0055] The inventors have discovered that, in current power semiconductor devices, the optimization of the contradictory relationship between the breakdown voltage and on-resistance of the devices has reached a bottleneck, and the corresponding process requirements are becoming increasingly stringent.

[0056] Based on this, the present invention proposes a technical solution for improving the semiconductor cellular structure: on the basis of the existing semiconductor cellular structure, a metal-like field plate formed of a high dielectric constant dielectric material is added next to the drift region, and the metal-like field plate is used to modulate the conductivity of the on-state drift region and the off-state high-voltage blocking electric field distribution to obtain a higher breakdown voltage.

[0057] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] See also Figures 2 to 6 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the diagrams only show the components related to the present invention rather than being drawn according to the number, shape and size of the components during actual implementation. During actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated. The structure, proportion, size, etc. shown in the diagrams attached to this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed in the present invention without affecting the efficacy and purpose that can be achieved by the present invention.

[0059] Example 1

[0060] like Figure 2 As shown, an embodiment of the present invention provides an improved semiconductor cell structure with a high voltage and low drift region on-resistance (hereinafter referred to as a semiconductor improved structure), the semiconductor improved structure comprising:

[0061] Highly doped semiconductor material region 101;

[0062] The epitaxial layer 102 is disposed on the highly doped semiconductor material region 101 and has a deep trench formed therein, the deep trench vertically extending into the highly doped semiconductor material region 101;

[0063] An active device region 103 is provided on the epitaxial layer 102;

[0064] A dielectric insulating layer 104 is provided on the sidewalls and bottom of the deep trench;

[0065] A high dielectric constant dielectric 105 is provided to fill the deep trench and contact the dielectric insulating layer 104;

[0066] A first electrode 106 is disposed above the high-permittivity dielectric 105 and in contact with the high-permittivity dielectric 105;

[0067] Among them, the criterion for the depth of the deep trench extending vertically into the highly doped semiconductor material region 101 is: to make the highest electric field before breakdown at position A below the interface between the active device region 103 and the epitaxial layer 102 equal to the highest electric field at position B on the epitaxial layer 102 side of the intersection of the epitaxial layer 102, the dielectric insulating layer 104, and the highly doped semiconductor material region 101.

[0068] In a specific implementation, the highly doped semiconductor material region 101 and the epitaxial layer 102 may be of the same conductive impurity type. This is because, generally speaking, only the same conductive impurity type should be used. If they are different, minority carrier injection will generally cause carrier modulation effects in the epitaxial layer, reducing the effectiveness of the present invention.

[0069] In practice, the impurity concentration of epitaxial layer 102 is higher than the impurity concentration in the drift region of a parallel-plane junction at the same operating voltage. Otherwise, this structure will not achieve the desired reduction in on-resistance. This is common knowledge in the art and will not be further elaborated upon here. Theoretically, this impurity concentration can be as high as the maximum solubility of the impurities in the semiconductor material. The actual concentration depends on the process technology capabilities of the cell structure.

[0070] In a specific implementation, the dielectric insulating layer 104 may be composed of a single dielectric layer or a multi-layer dielectric layer. The vertical surface of the dielectric insulating layer 104 passes through the epitaxial layer 102 , and the bottom thereof extends into the highly doped semiconductor material region 101 .

[0071] In a specific implementation, the high-k dielectric 105 is located on one side of the dielectric insulating layer 104 and vertically extends into the highly doped semiconductor material region 101 along with the dielectric insulating layer 104 .

[0072] Among them, the dielectric constant of the high dielectric constant medium 105 is greater than 200, and the high dielectric constant medium 105 forms a field plate structure. This field plate structure (hereinafter referred to as a metal-like long plate) is similar to a metal field plate, and is a metal inclined field plate with variable dielectric thickness. The electric field distribution of this metal-like field plate can effectively modulate the conductivity of the on-state drift region and the off-state high-voltage blocking electric field distribution to obtain a higher breakdown voltage.

[0073] Specifically, the dielectric insulating layer 104 and the high-k dielectric 105 can be realized by etching a deep trench in the epitaxial layer 102 , forming the dielectric insulating layer 104 on the bottom and sidewalls of the deep trench and filling the deep trench with the high-k dielectric 105 .

[0074] In a specific implementation, the optimal electric field distribution characteristics of the improved semiconductor structure are: when the highest electric field near position A of the active device area 103 under reverse high voltage is approximately equal to the highest electric field at position B on the side of the epitaxial layer 102 at the intersection of the epitaxial layer 102, the dielectric insulating layer 104, and the highly doped semiconductor material area 101, the improved semiconductor structure achieves the best effect, with a higher breakdown voltage and a lower drift region on-resistance.

[0075] In addition, research shows that the high dielectric constant medium 105 penetrates deeper into the highly doped semiconductor material region 101 to a certain depth, which can further improve the breakdown voltage of the device, and the corresponding metal-like field plate has a better modulation effect on the device.

[0076] In a specific implementation, the depth h of the dielectric insulating layer 104 and the high-k dielectric 105 vertically penetrating into the epitaxial layer 102 is related to the thickness t of the dielectric insulating layer 104 .

[0077] In specific implementation, for different operating voltages, the specific optimal cell size structure is calculated and simulated using process simulation software combined with process implementation capabilities.

[0078] Furthermore, if Figure 2 As shown, the improved semiconductor structure further includes:

[0079] The second electrode 107 is disposed above the active device region 103 and in contact with the active device region 103 , serving as a low-voltage electrode of the semiconductor improved structure, while the highly doped semiconductor material region 101 corresponds to a high-voltage electrode of the semiconductor improved structure.

[0080] In a specific implementation, the highly doped semiconductor material region 101 also serves as the high-voltage electrode of the semiconductor improved structure, and its corresponding low-voltage electrodes are the first electrode 106 (the low-voltage electrode at the top of the high dielectric constant medium 105) and the second electrode 107 (the low-voltage electrode at the top of the active device region 103), and the potential of the first electrode 106 and the potential of the second electrode 107 can be the same potential, that is, the first electrode 106 and the second electrode 107 can be the same low-voltage electrode.

[0081] It should be noted that the high voltage here should be understood as positive high voltage or negative high voltage (determined by the doping type of the epitaxial layer 102). The second electrode 107 is generally the lowest voltage when the cell blocks the high voltage. Taking a typical VDMOS as an example, the second electrode 107 is the source electrode or the gate electrode of the cell. When it is turned off, it is in a state of blocking high voltage, or a state of being turned off to withstand high voltage. At this time, the gate electrode can be a turn-off voltage lower than that of the source electrode, or the same voltage as the source electrode voltage. At this time, the cell is still in a state of being turned off to withstand high voltage. Therefore, the first electrode 106 can be connected to the source electrode or to the gate electrode. Generally, for simplicity and reliability, the first electrode 106 is directly connected to the source electrode. If connected to the gate electrode, the load of the gate electrode will increase, affecting the switching speed of the cell structure. However, connecting to the gate electrode has certain benefits for forward conduction during forward conduction, which can further reduce the forward on-resistance, and the performance is basically the same when reversely turned off to withstand high voltage.

[0082] It should also be noted that the Figure 2 The improved semiconductor structure shown is only a half structure with left and right symmetry. Simply make a left and right mirror image (such as Figure 2 As shown, M is a mirror) symmetry to obtain a complete high-voltage and low-drift region on-resistance semiconductor cell improved structure.

[0083] In order to enable those skilled in the art to better understand the above solution, the above solution will be described in detail below by taking examples.

[0084] The implementation of this technical solution is illustrated using the active device region 103 as a simplest 600V withstand voltage PN junction diode cellular structure. Other embodiments other than diodes that possess the characteristics described in this cellular structure should not be considered different cellular structures. The active device region 103 herein can also be a semiconductor cellular structure such as a bipolar transistor, MOSFET, VDMOS, IGBT, or JFET that can utilize this cellular structure to achieve high breakdown voltage and low drift region on-resistance performance. The processes described in the following examples are all existing mature processes and are not described in great detail. These processes are generally understood and appreciated by those skilled in the art.

[0085] The following is a detailed explanation using the simplest silicon diode as an example. The specific steps for its formation are as follows:

[0086] S1. Based on the 600V withstand voltage requirement of the diode and the process implementation capability, the cellular structure simulation was performed using the industry's common semiconductor device simulation tool software. Assuming that the basic process capability can achieve 3μm wide and 40μm deep trench etching, the on-resistance semiconductor cellular structure parameters of this high-voltage, low-drift region are obtained as follows:

[0087] 1) The deep trench has a depth of 40 μm and a width of 3 μm, and a depth h of 3 μm into the highly doped semiconductor material region 101.

[0088] 2) The thickness of the epitaxial layer 102 is 37 μm, and the N-type doping concentration is 2.8×10 15 cm -3 ,

[0089] 3) The lateral width of the epitaxial layer 102 is 5 μm,

[0090] 4) The thickness t of the dielectric insulating layer 104 is 300 nm,

[0091] 5) The resistivity of the highly doped semiconductor material region 101 is 0.02 to 0.001 Ω·cm, N-type <100> Silicon materials,

[0092] At this time, the withstand voltage of the diode cell structure is 630V;

[0093] S2. After the above cell structure design is completed, take 0.02~0.001Ω.cm N type <100> The silicon material (silicon wafer) is formed with photolithography alignment marks using industry-standard methods to facilitate alignment in subsequent process steps. The silicon wafer is also used as the highly doped semiconductor material region 101.

[0094] S3, on the silicon wafer, an N-type epitaxial layer 102 is grown using an industry-standard epitaxial method, and its doping concentration is 2.8×10 15 / cm 3 In the area where surface P-type doping is required, the overprint ion implantation method is used to achieve the desired effect, with a concentration greater than 1×10 19 / cm 3 The PN junction formed with the epitaxial layer 102 has a depth of 0.1μm to 2μm. This PN junction serves as the active device region 103. A 40nm oxide layer is formed using industry-standard thermal oxidation. A 500nm oxide layer is then deposited using LPCVD to form an oxide layer 100, which serves as a hard mask for deep trench etching. A general photolithography method is used to expose and develop the deep trench pattern to be etched, and a highly anisotropic dry etcher is used to etch a deep trench T on the epitaxial layer 102. Figure 3 As shown;

[0095] S4. Clean the silicon wafer using a common cleaning procedure in the industry, and thermally oxidize or deposit an oxide layer on the bottom and sidewalls of the deep trench T using thermal oxidation or CVD. The oxide layer has a thickness of 300 nm to form a dielectric insulating layer 104. Figure 4 As shown;

[0096] S5. Fill the silicon wafer with a high-k dielectric 105 by PVD, CVD, powder, or liquid methods. The deep trench T is sealed or filled with the high-k dielectric 105. If there are gaps in the deep trench T after being filled with the high-k dielectric 105, the cell structure will be slightly affected, but not seriously.

[0097] S6. Planarize the surface of the silicon wafer, remove the surface oxide layer 100, the surface dielectric insulating layer 104 and the surface high dielectric constant medium 105, and form the first electrode 106 and the second electrode 107 by sputtering or evaporation, etc., which are common in the industry. Then, perform alloy treatment commonly used in the industry to finally complete the production of the semiconductor improved structure. Figure 5 shown.

[0098] Finally, we get Figure 2 or Figure 5 The diode cell structure shown, based on the existing diode cell structure, adds a metal-like field plate (slanted field plate) formed by a high dielectric constant medium 105 next to the drift region (i.e., the epitaxial layer 102). By modulating the conductivity of the on-state drift region and the off-state high-voltage blocking electric field distribution through this metal-like field plate, a higher breakdown voltage can be obtained. A large number of experiments have proved that compared with before the improvement, under the same process and design parameter conditions (same drift region thickness), it has a higher withstand voltage, and its withstand voltage reaches 630V, which is an increase of 30V in breakdown withstand voltage.

[0099] In addition, the present invention also provides a power semiconductor device, which includes the above-mentioned semiconductor improved structure. The power semiconductor device based on the above-mentioned semiconductor improved structure can withstand a higher drift region breakdown voltage and has a lower on-resistance, which will not be repeated here.

[0100] Example 2

[0101] In the first embodiment of the present invention, a dielectric insulating layer 104 is provided between the metal-like field plate formed by the high-k dielectric 105 and the drift region (i.e., the epitaxial layer 102). The metal-like field plate structure formed by the high-k dielectric 105 regulates the impurity concentration in the drift region (i.e., the epitaxial layer 102) through the dielectric insulating layer 104, thereby modulating the on-state drift region conductance and the off-state high-voltage blocking electric field distribution, thereby achieving a higher breakdown voltage. In fact, the dielectric insulating layer 104 can be omitted, that is, the high-k dielectric 105 directly contacts the drift region (i.e., the epitaxial layer 102) on the sidewalls of the deep trench T.

[0102] Based on this, Figure 6 As shown, an embodiment of the present invention provides an improved semiconductor structure, which includes:

[0103] Highly doped semiconductor material region 101;

[0104] The epitaxial layer 102 is disposed on the highly doped semiconductor material region 101 and has a deep trench formed therein, the deep trench vertically extending into the highly doped semiconductor material region 101;

[0105] An active device region 103 is provided on the epitaxial layer 102;

[0106] A high dielectric constant medium 105 is provided and filled in the deep groove;

[0107] A first electrode 106 is disposed above the high-permittivity dielectric 105 and in contact with the high-permittivity dielectric 105;

[0108] Among them, the criterion for the depth of the deep trench extending vertically into the highly doped semiconductor material region 101 is: to make the maximum electric field before breakdown at position A below the interface between the active device region 103 and the epitaxial layer 102 equal to the maximum electric field at position B on the epitaxial layer 102 side of the intersection of the epitaxial layer 102, the high dielectric constant medium 105, and the highly doped semiconductor material region 101.

[0109] Likewise, the high-k dielectric 105 has a dielectric constant greater than 200, forming a metal-like field plate.

[0110] Likewise, if Figure 6 As shown, the improved semiconductor structure further includes:

[0111] The second electrode 107 is disposed above the active device region 103 and in contact with the active device region 103 , serving as a low-voltage electrode of the semiconductor improved structure, while the highly doped semiconductor material region 101 corresponds to a high-voltage electrode of the semiconductor improved structure.

[0112] It should be noted that other detailed structures and specific process steps of the improved semiconductor structure in the embodiment of the present invention can be referred to in Example 1 and will not be described in detail here.

[0113] To sum up, the improved semiconductor structure and power semiconductor device provided by the present invention, on the basis of the existing semiconductor cell structure, add a metal-like field plate formed by a high dielectric constant medium next to the drift region, and modulate the on-state drift region conductivity and the off-state high-voltage blocking electric field distribution through the metal-like field plate, so as to obtain a higher breakdown voltage while having a lower on-resistance; at the same time, its process is easier to implement than other existing high-voltage and low-drift region on-resistance semiconductor cell structures, reducing the loss caused by charge mismatch at the same voltage, including the mismatch caused by the charge of the dielectric layer, which has great redundancy and benefits in reducing the difficulty of process implementation and process capability requirements, and improving the yield rate, and also improves the stability of the structure.

[0114] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A semiconductor improved structure, characterized in that: At least: a highly doped semiconductor material region; an epitaxial layer, disposed on the highly doped semiconductor material region, wherein a deep trench is formed therein, and the deep trench vertically enters the highly doped semiconductor material region; an active device region, disposed on the epitaxial layer; a dielectric insulating layer, disposed on the sidewalls and bottom of the deep trench; A high dielectric constant medium is arranged to fill the deep trench and contact the dielectric insulating layer; A first electrode is disposed above the high dielectric constant medium and in contact with the high dielectric constant medium; The depth of the deep trench extending vertically into the highly doped semiconductor material region is determined by: ensuring that the maximum electric field before breakdown at the interface between the active device region and the epitaxial layer is equal to the maximum electric field at a position on one side of the epitaxial layer at the intersection of the epitaxial layer, the dielectric insulating layer, and the highly doped semiconductor material region; Among them, the dielectric constant of the high dielectric constant medium is greater than 200; the high dielectric constant medium forms a field plate structure, and is a metal-like inclined field plate with variable dielectric thickness. The electric field distribution of the metal-like inclined field plate can effectively modulate the conductivity of the on-state drift region and the off-state high-voltage blocking electric field distribution.

2. The improved semiconductor structure according to claim 1, characterized in that: The highly doped semiconductor material region and the epitaxial layer are of the same conductive impurity type.

3. The improved semiconductor structure according to claim 2, characterized in that: The impurity concentration of the epitaxial layer is higher than the impurity concentration of the drift region corresponding to the parallel plane junction under the same operating voltage.

4. The improved semiconductor structure according to claim 3, characterized in that: The dielectric insulating layer includes a single-layer dielectric or a multi-layer dielectric.

5. The semiconductor improved structure according to claim 1 or 4, characterized in that: The semiconductor improved structure further includes: The second electrode is arranged above the active device area and contacts the active device area, serving as a low-voltage electrode of the semiconductor improved structure, and the highly doped semiconductor material area corresponds to a high-voltage electrode of the semiconductor improved structure.

6. The improved semiconductor structure according to claim 5, characterized in that: The high-voltage electrode includes a negative high-voltage electrode.

7. A semiconductor improved structure, characterized in that: At least: a highly doped semiconductor material region; an epitaxial layer, disposed on the highly doped semiconductor material region, wherein a deep trench is formed therein, and the deep trench vertically enters the highly doped semiconductor material region; an active device region, disposed on the epitaxial layer; A high dielectric constant medium is arranged to fill the deep groove; A first electrode is disposed above the high dielectric constant medium and in contact with the high dielectric constant medium; The depth of the deep trench extending vertically into the highly doped semiconductor material region is determined by: ensuring that the maximum electric field before breakdown at the interface between the active device region and the epitaxial layer is equal to the maximum electric field at a position on one side of the epitaxial layer at the intersection of the epitaxial layer, the high-k dielectric, and the highly doped semiconductor material region; Among them, the dielectric constant of the high dielectric constant medium is greater than 200; the high dielectric constant medium forms a field plate structure, and is a metal-like inclined field plate with variable dielectric thickness. The electric field distribution of the metal-like inclined field plate can effectively modulate the conductivity of the on-state drift region and the off-state high-voltage blocking electric field distribution.

8. The improved semiconductor structure according to claim 7, characterized in that: The semiconductor improved structure further includes: The second electrode is arranged above the active device area and contacts the active device area, serving as a low-voltage electrode of the semiconductor improved structure, and the highly doped semiconductor material area corresponds to a high-voltage electrode of the semiconductor improved structure.

9. The improved semiconductor structure according to claim 8, characterized in that: The high-voltage electrode includes a negative high-voltage electrode.

10. A power semiconductor device, characterized in that: The power semiconductor device comprises the improved semiconductor structure according to any one of claims 1 to 9.

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