Air gap structures in auto-doped regions under one or more transistors

Abstract

The present disclosure relates to semiconductor structures, and more particularly to air gap structures in auto-doped regions under one or more transistors and methods of manufacture. The structure includes a semiconductor material including a doped region, one or more sealed air gap structures that disrupt the doped region of the semiconductor material, and a field effect transistor located above the one or more sealed air gap structures and the semiconductor material.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly to air gap structures in auto-doped regions of semiconductor material underlying one or more transistors and methods of fabricating the same. Background Art

[0002] Semiconductor chips can have many different devices fabricated within their active regions. For example, RF CMOS devices can be fabricated on the same chip as bipolar junction transistors (BJTs). BJTs can include both high-performance and high-breakdown devices. However, the manufacturing process for one device can degrade the performance of another device on the same chip. For example, the manufacturing process for a high-breakdown BJT device can degrade the performance of an RF CMOS device.

[0003] More specifically, when manufacturing bipolar junction transistors, and more specifically, high-breakdown NPN bipolar junction transistors, it is necessary to form a subcollector region within the substrate. The subcollector region is an n-well that auto-dopes the epitaxial semiconductor material grown above the substrate material during the growth process. The epitaxial semiconductor material serves as the collector region of the NPN bipolar junction transistor, as well as the channel and source / drain regions of the RF device. However, the auto-doped semiconductor material beneath the RF device degrades the RF performance of the RF CMOS device on the same wafer. To compensate for this performance degradation, isolation is required between the channel and source / drain regions of the RF device and the auto-doped epitaxial semiconductor material. Summary of the Invention

[0004] In one aspect of the present disclosure, a structure includes: a semiconductor material including doped regions; one or more sealed air gap structures that break up the doped regions of the semiconductor material; and a field effect transistor located above the one or more sealed air gap structures and the semiconductor material.

[0005] In one aspect of the present disclosure, a structure includes: a bipolar junction transistor, which includes at least a subcollector located in an underlying substrate; a semiconductor material located above the subcollector, the semiconductor material having a doped region; an active device located above the semiconductor material; and at least one air gap structure located below the active device and within the doped region of the semiconductor material.

[0006] In one aspect of the present disclosure, a method includes forming a semiconductor material including a doped region; forming one or more sealed air-gap structures that disrupt the doped region of the semiconductor material; and forming a field effect transistor over the one or more sealed air-gap structures and the semiconductor material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0008] Figure 1 A substrate having an n-well region and a corresponding fabrication process are shown, among other features, according to some aspects of the present disclosure.

[0009] Figure 2 Shown are, among other features, auto-doping semiconductor materials and corresponding fabrication processes according to aspects of the present disclosure.

[0010] Figure 3 A plurality of air gap structures (eg, cavities) in an autodoped region of a semiconductor material and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0011] Figure 4 Materials and corresponding manufacturing processes for sealed air gap structures according to aspects of the present disclosure, among other features, are shown.

[0012] Figure 5 Shown are, among other features, a shallow trench isolation structure over a sealed air gap structure and a corresponding fabrication process according to aspects of the present disclosure.

[0013] Figure 6 An RF device over a sealed air gap structure and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0014] Figure 7 Contacts to different devices and corresponding fabrication processes are shown, among other features, in accordance with some aspects of the present disclosure.

[0015] Figure 8 An alternative structure having a continuous air gap structure beneath one or more RF devices and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0016] Figure 9 An alternative structure having an air gap structure underneath a high performance bipolar junction device and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0017] Figure 10 An alternative structure having an air gap structure beneath a passive device and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0018] The present disclosure relates to semiconductor structures, and more particularly to air gap structures and methods for fabricating them within an autodoped region of semiconductor material underlying one or more transistors. In a more specific embodiment, among other features, an air gap structure is disposed within an autodoped region of epitaxial semiconductor material underlying one or more radio frequency (RF) devices, such as field effect transistors (FETs). Advantageously, the air gap structure disrupts or eliminates the autodoped region to improve RF isolation and, therefore, RF switching performance.

[0019] In an embodiment, an air gap structure is located below the RF CMOS device in an auto-doped region of epitaxial semiconductor material. The auto-doped region results from the use of an n-type well (sub-collector) below the epitaxial semiconductor material used with the high breakdown NPN bipolar junction transistor. The air gap structure can be continuous or discontinuous below the RF CMOS device (i.e., FET) and can be strategically placed to remove the auto-doped region (i.e., doped epitaxial semiconductor material), or to disrupt the auto-doped region below the RF device, thereby improving RF isolation. An amorphous layer of polysilicon material or semiconductor material can be provided between the air gap structure and the RF CMOS device to further improve the isolation of the RF device. Thus, FETs and high breakdown NPNs and other devices with improved switching isolation can now be used on the same substrate.

[0020] The semiconductor structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, typically, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the semiconductor structures disclosed herein have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a film of material patterned on top of the wafer by a photolithographic process. In particular, the manufacture of semiconductor structures uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film with respect to the mask.

[0021] Figure 1 The substrate and the corresponding manufacturing process are shown, among other features. Figure 1 In structure 10, substrate 12 comprises a bulk semiconductor material, preferably a single-crystal Si material. In embodiments, substrate 12 may be composed of other suitable bulk substrate materials, including but not limited to elemental semiconducting materials (e.g., crystalline germanium), silicon carbide, silicon germanium, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. In preferred embodiments, substrate 12 comprises any suitable crystal orientation (e.g., a (100), (110), (111), or (001) crystal orientation).

[0022] The substrate 12 includes three regions: a high-performance NPN transistor region 100; a high-breakdown NPN transistor region 200; and an RF transistor region 300. As will be understood by those skilled in the art, and as described in greater detail herein, the high-performance NPN transistor region 100 includes one or more high-performance NPN bipolar junction transistors, the high-breakdown NPN transistor region 200 includes one or more high-breakdown NPN bipolar junction transistors, and the RF transistor region 300 includes one or more RF CMOS devices, such as FETs. Furthermore, those skilled in the art will appreciate that other regions or combinations of regions are also contemplated herein.

[0023] Still refer to Figure 1 , a well 14 can be formed in the substrate 12. In an embodiment, the well 14 can be an n-well used as a sub-collector of one or more high breakdown NPN bipolar junction transistors in the high breakdown NPN transistor region 200. In an embodiment, the n-well 14 can be formed by introducing dopants such as arsenic (As), phosphorus (P), or antimony (Sb), by ion implantation in the substrate 12, in addition to other suitable examples. For the n-well 14, the dopant can be implanted through the opening of the implantation mask. The dopant can be activated by an annealing process well known to those skilled in the art, so that the present disclosure is fully understood without further explanation. The implantation mask can be stripped after the ion implantation process.

[0024] In an embodiment, the implantation mask may include a layer of photosensitive material, such as an organic photoresist, applied by a spin-coating process, then pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer. The implantation mask has a thickness and stopping power sufficient to block the masked area from receiving a dose of implanted ions.

[0025] Figure 2 A semiconductor material 16 is shown formed over substrate 12 and n-well 14. In an embodiment, semiconductor material 16 may be a Si material epitaxially grown on substrate 12 and over n-well 14. In an embodiment, a dopant (e.g., As) from n-well 14 autodopes semiconductor material 16, as shown by reference numeral 16a. As examples of autodoping, during the growth of semiconductor material 16, dopant atoms (e.g., As) from n-well 14 may (i) diffuse to the top surface of substrate 12, (ii) evaporate from the surface in a gas phase, (iii) undergo mass transport in a gas phase, and (iv) be adsorbed or incorporated into a growing layer (e.g., semiconductor material 16).

[0026] In an alternative embodiment, n-well 18 can be formed in semiconductor material 16 in high-performance NPN transistor region 100. In an embodiment, n-well 18 can serve as a subcollector for one or more high-performance NPN bipolar junction transistors. It should be appreciated that n-well 18 can be implanted in a similar manner to n-well 14 described above; however, n-well 18 can be provided at a lower dose to remain within semiconductor material 16 and avoid or minimize auto-doping. In an embodiment, n-well 18 can also be closer to the surface of semiconductor material 16 than n-well 14.

[0027] exist Figure 3 In the embodiment of the present invention, a plurality of air gap structures (e.g., cavities) 22 can be formed in the semiconductor material 16 in the RF transistor region 300. More specifically, the plurality of air gap structures 22 are formed in the auto-doped region 16a of the semiconductor material 16. The plurality of air gap structures 22 effectively destroy or eliminate the auto-doped region 16a, thereby providing improved switching isolation for one or more RF CMOS devices in the RF transistor region 300. As further described herein, the plurality of air gap structures 22 can be a single air gap structure (discontinuous) or a single merged air gap structure (continuous).

[0028] In an embodiment, a plurality of air gap structures 22 can be formed by providing a plurality of trenches 20 in substrate 16 using conventional photolithography and etching processes. For example, a resist formed over a pad dielectric film 21 (deposited over semiconductor material 16) can be exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry, such as reactive ion etching (RIE), is used to form one or more trenches through the openings in the resist, through pad film 21, and into semiconductor material 16. The resist can then be removed by a conventional oxygen ashing process or other known strippers.

[0029] A sidewall liner can be formed on the sidewalls of trench 20 by depositing a dielectric material and then performing an anisotropic etching process on the dielectric material from the bottom of the trench and the top planar features of the structure. In an embodiment, the sidewall liner can be any suitable dielectric material, such as an oxide or nitride, or a combination of dielectric layers deposited using any known deposition method, such as chemical vapor deposition (CVD), thermal oxidation of a silicon substrate, atomic layer deposition (ALD), or any combination thereof. The anisotropic etch can include RIE using perfluorocarbon-based chemistries known in the art, which etches material from a planar surface but leaves dielectric material (e.g., a sidewall liner) on the sidewalls of trench 20.

[0030] In an embodiment, the sidewall liner should securely cover the sidewalls of the trench 20 to protect the underlying semiconductor material 16 from subsequent etching processes (for cavity formation). To achieve this secure sidewall coverage, the dielectric material(s) should be thick enough to leave a film on the sidewalls of the trench 20, but not so thick as to pinch off the top opening of the trench 20, which would prevent cavity formation during subsequent cavity etching processes.

[0031] The air gap structure 22 can be formed in the semiconductor material 16 through the bottom of the trench 20 by a substrate etching process. The liner film 21 on the substrate surface and the sidewall lining of the trench 20 protect the semiconductor material 16 from being unintentionally etched during the formation of the air gap structure 22. In an embodiment, before forming the air gap structure, any excess dielectric material at the bottom of the trench 20 can be removed using an optional gas or liquid HF clean, hydrogen plasma, annealing, alkaline or acidic chemical clean known for removing thin or native dielectrics or residual spacers from the semiconductor material 16 (e.g., silicon). The post-sidewall liner etch clean (e.g., anisotropic etching) should leave a strong dielectric liner, such as a sidewall liner, on the top corners and sidewalls of the trench 20 to prevent etching of the semiconductor material 16 through the sidewalls of the trench 20 during cavity formation. In an embodiment, the air gap structure 22 can extend into the underlying semiconductor material 12.

[0032] Removal of the semiconductor materials 12, 16 to form the air gap structure 22 can be achieved by a wet etching process or a dry etching process. For example, the dry etchant can include plasma-based CF4, plasma-based SF6, or gaseous XeF4 silicon etching, while the wet etching process can include KOH and NH4OH. After the air gap structure 22 is formed, the sidewall liner and liner film can be removed from the structure to expose the upper surface of the semiconductor material 16 and the sidewalls of the trench 20. In an embodiment, the sidewall liner and liner film 21 can be removed by performing a conventional etching process that is selective to such materials (e.g., thermal phosphorus) and then performing an HF chemistry reaction, or performing an HF chemistry reaction and then performing a conventional etching process that is selective to such materials (e.g., thermal phosphorus), depending on whether a single dielectric layer or a stack of different dielectric layers is used for the sidewall liner.

[0033] After removing the sidewall liner and liner film 21, the trench 20 can be subjected to an optional annealing process to soften or round (bend) the edges of the trench 20. In an embodiment, the annealing is provided in an H2 or other hydrogen atmosphere to remove any native or other oxides from the surface of the silicon substrate. The annealing can also be provided in other atmospheres, for example, NH3, B2H6, Ph3, AsH2 or other gases combined with hydrogen. For example, after the HF pre-cleaning process, the structure can undergo an annealing process at a temperature range of about 800°C to about 1100°C for up to about 60 seconds. If little or no bending is required, the annealing temperature is reduced, the time or hydrogen-based gas flow is reduced to eliminate or minimize silicon substrate reflow.

[0034] exist Figure 4 In the embodiment, material 24 can be formed on the surface of semiconductor material 16, including the sidewalls of trench 20 and the sidewalls of cavity structure 22. In one embodiment, material 24 can be an epitaxial Ge or SiGe material deposited using ultra-high vacuum CVD (UHVCVD); although other semiconductor materials are also contemplated herein. In one embodiment, the Ge material can be deposited at a temperature of about 600° C. to 750° C., resulting in a thickness of about 5 nm to about 50 nm; although other dimensions are also contemplated depending on the critical dimensions of trench 20.

[0035] like Figure 4 As further shown, the structure is heated to a temperature equal to or greater than the reflow temperature of material 24, causing material 24 to fill the top of trench 20. More specifically, material 24 has a lower reflow temperature than semiconductor materials 12, 16, allowing material 24 to reflow and seal trench 20, thereby forming sealed air gap structure 22a (which would damage or eliminate the auto-doped region 16a below the RF CMOS device). For example, Ge has a lower reflow temperature than Si, allowing Ge to reflow into the opening of trench 20 to seal the top of trench 20 without filling the sealed air gap structure 22a. In an embodiment, the reflow temperature may be approximately 800°C to 1050°C and the reflow time may be any time up to 600 seconds.

[0036] After the material 24 reflows, another semiconductor material 26 can be deposited over the trench 20 and the material 24. In an embodiment, the semiconductor material 26 can be a single crystal Si material, for example, wherein the sealed air gap structure 22a is continuous with the formation of the semiconductor material 26. The semiconductor material 26 can be epitaxially grown over the semiconductor material 16 in a deposition chamber having a temperature of about 850°C to about 1050°C for about 60 seconds to a thickness of 0.4 μm or more. At this temperature, the material 24 can continue to reflow and continue to be attracted or migrate into the upper portion of the trench 20 (e.g., typically at the minimum critical dimension). In an embodiment, the surface of the semiconductor material 26 can be grown in a self-planarizing manner, for example, having a flat surface. In addition, the semiconductor material 26 can be used to further seal the air gap structure 22a.

[0037] exist Figure 5 In the embodiment, shallow trench isolation structures 28 are formed in the semiconductor material 26 in the regions 100, 200, and 300. In an embodiment, the shallow trench isolation structures 28 can isolate the separated devices in different regions 100, 200, and 300. The shallow trench isolation structures 28 can be formed by the conventional photolithography and etching processes described above and subsequent deposition of insulating materials. For example, after etching and resist removal, an insulator material (e.g., SiO2) can be deposited in the shallow trenches formed by the etching process by any conventional deposition process, such as CVD. Any residual material on the surface of the semiconductor material 26 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0038] Figure 5 Further shown is an amorphous semiconductor region 30 formed in semiconductor material 26, located vertically above air gap structure 22a in region 300. In an embodiment, amorphous semiconductor region 30 may be a polysilicon material formed by performing an implantation process using an implantation mask, followed by annealing. For example, the implant may be argon or another inert gas, such as Xe, Kr, etc. In an embodiment, amorphous semiconductor region 30 may be a high-resistance semiconductor region that provides further isolation below the RF device in region 300. Amorphous semiconductor region 30 may be disposed below shallow trench isolation region 28.

[0039] exist Figure 6, bipolar junction transistors 32 and 34 may be formed in respective regions 100 and 200, and an RF switch 36, such as an RF CMOS device, may be formed in region 300. In an embodiment, the RF switch 36 may be located vertically above the amorphous semiconductor region 30 and the air gap structure 22a. In a non-limiting illustrative example, the bipolar junction transistor 32 may be a 5V high-performance transistor, and the bipolar junction transistor 34 may be a 20V high-breakdown transistor (e.g., 20V BVcbo (breakdown voltage, collector-emitter, base open)); however, other parameters are also contemplated herein.

[0040] Although not critical to understanding the present disclosure, the RF switch 36 can be manufactured using standard CMOS or replacement gate processes. In standard CMOS processing, a gate dielectric and polysilicon material are formed (e.g., deposited) on the semiconductor material 26, followed by a patterning process. An insulator material such as a nitride or oxide can be deposited on the patterned material, followed by an anisotropic etching process to form sidewall spacers. The gate dielectric can be a low-k dielectric material, such as a gate oxide, or a high-k dielectric material, such as a hafnium oxide-based material. The source and drain regions of the RF switch 36 can be formed by conventional epitaxial processes for raised source / drain regions, or by ion implantation processes, each of which is well known to those skilled in the art and therefore does not require further explanation herein to fully understand the present disclosure.

[0041] The bipolar junction transistors may be a high-performance bipolar junction transistor 32 in region 100 and a high-breakdown bipolar junction transistor 34 in region 200. It should be understood that the high-performance bipolar junction transistor 32 may be an optional device. In any case, the bipolar junction transistors 32 and 34 may be formed by depositing a base material (e.g., p-doped polysilicon material) and an emitter material (e.g., n-doped Si material or SiGe material) on the semiconductor material 26. The material is then patterned using conventional photolithography and etching processes known in the art. The collector region includes the semiconductor material 26, the n-well 18 is a sub-collector for the high-performance bipolar junction transistor 32, and the n-well 14 is a sub-collector for the high-breakdown bipolar junction transistor 34. It will be understood by those skilled in the art that the n-well 18 should be closer to the surface to increase the frequency, while the n-well 14 should be deeper into the substrate 12 to improve the breakdown.

[0042] like Figure 7As shown, devices 32, 34, and 36 can undergo a silicide process to form silicide contacts 38. As will be understood by those skilled in the art, the silicide process begins by depositing a thin transition metal layer (e.g., nickel, cobalt, or titanium) over the fully formed and patterned semiconductor devices (e.g., the source / drain regions and corresponding active portions of devices 32, 34, and 36). After the material is deposited, the structure is heated, causing the transition metal to react with the exposed silicon (or other semiconductor materials described herein) in the active regions of the devices to form low-resistance transition metal silicide contacts 38. After the reaction, any remaining transition metal can be removed by chemical etching, leaving behind silicide contacts 38. Those skilled in the art will understand that silicide contacts are not required on all features.

[0043] Interlayer dielectric material 40 may be formed over silicide contact 38 and devices 32, 34, 36. In an embodiment, interlayer dielectric material 40 may be an oxide material, such as SiO2, deposited using conventional deposition processes known to those skilled in the art, or a double-layer material stack, such as a nitride material with an undoped insulator material or phosphosilicate (PSG) / boron PSG (BPSG). Contact 42 may be formed by conventional photolithography, etching, and deposition methods known in the art. Contact 42 may be formed to each of devices 32, 34, 36 (e.g., gate structures, silicides, and / or non-silicided NPN structures). Contact 42 may be formed by conventional photolithography, etching, and deposition processes known to those skilled in the art. In an embodiment, contact 42 comprises aluminum, tungsten, or other suitable metal or metal alloy.

[0044] Figure 8 An alternative structure 10a is shown according to some aspects of the present disclosure. In this alternative structure 10a, the air gap structures are merged together to form a single larger air gap structure 22b (i.e., a continuous air gap structure 22b) in region 300. In an embodiment, the single larger air gap structure 22b can be formed by a continuation of the etching process that forms the discrete air gap structures. The single larger air gap structure 22b can eliminate or destroy the auto-doped region 16a, effectively providing additional isolation for the RF device 36 in region 300. The remaining features of the structure 10a are similar to those of the reference 10a. Figure 7 described.

[0045] Figure 9 An alternative structure 10b according to some aspects of the present disclosure is shown. In this alternative structure 10b, an air gap structure 22a is disposed within the auto-doped region 16a in regions 100 and 300. More specifically, in this embodiment, the air gap structure 22a is disposed within the auto-doped region 16a, below the high-performance bipolar junction device 32. The air gap structure 22a is also disposed below the n-well 18. It should be understood that the air gap structure 22a may also be Figure 8The single merged air gap structure shown, and any combination of separate air gap structures (discontinuous) and / or single merged air gap structures (continuous) are contemplated herein. The remaining features of structure 10b are similar to those described with reference to Figure 7 and Figure 8 described.

[0046] Figure 10 An alternative structure 10c is shown in accordance with some aspects of the present disclosure. In this alternative structure 10c, the passive device 41 is formed in the back end of line dielectric material 38. In embodiments, the passive device 41 can be a resistor, inductor, capacitor, etc. formed using conventional CMOS processes, and thus need no further explanation here to fully understand the present disclosure. In this structure 10c, the air gap structure 22a is disposed within the auto-doped region 16a below the passive device 41. It should be recognized that the air gap structure 22a can also be a single merged air gap structure as described in Figure 8 and any combination of air gap structures are contemplated herein. In addition, the amorphous region 30 can extend below the passive device 41 for additional isolation, improving the Q (quality) factor of the passive device 41. The remaining features of structure 10c are similar to those described with reference to Figures 7 to 9 described features.

[0047] These semiconductor structures can be utilized in system on a chip (SoC) technology. Those skilled in the art will appreciate that an SoC is an integrated circuit (also known as a “chip”) that integrates all components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0048] The above-described methods are used in the manufacturing of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricant as raw chips, i.e., as a single wafer having many unpackaged chips, as bare chips, or in packages with a variety of shapes and sizes. In the latter case the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to the main board or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either a

[0049] The description of various embodiments of the present disclosure has been given for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: a semiconductor material including a doped region; one or more sealed air gap structures that disrupt the doped regions of the semiconductor material; a field effect transistor located over the one or more sealed air gap structures and the semiconductor material; as well as An n-well is located in an underlying semiconductor substrate below the doped region of semiconductor material and below the one or more sealed air gap structures. The structure of claim 1 , wherein the doped region comprises an n-type dopant. 3 . The structure of claim 1 , wherein the one or more sealed air gap structures comprises a discontinuous sealed air gap structure located below the field effect transistor. 4 . The structure of claim 1 , wherein the one or more sealed air-gap structures comprise a single continuous sealed air-gap structure located beneath the field effect transistor. 5 . The structure of claim 1 , wherein the one or more sealed air gap structures eliminate the doped region below the field effect transistor. 6 . The structure of claim 1 , further comprising an amorphous semiconductor material vertically located between the field effect transistor and the one or more sealed air gap structures.

7. The structure of claim 6, wherein the amorphous semiconductor material is located below a shallow trench isolation region formed in a second semiconductor material including a source region and a drain region of the field effect transistor.

8. The structure of claim 1, wherein the one or more sealed air gap structures are sealed with another semiconductor material.

9. The structure of claim 1, wherein the one or more sealed air gap structures are located below a passive device.

10. The structure of claim 1, wherein the one or more sealed air gap structures are located beneath a high performance bipolar junction transistor.

11. The structure of claim 1 further comprising a high breakdown bipolar junction transistor comprising the n-well below the doped region of the semiconductor material, the high breakdown bipolar junction transistor being located on one side of the one or more sealed air gap structures.

12. A semiconductor structure comprising: a bipolar junction transistor comprising at least a subcollector located within an underlying substrate, the subcollector comprising an n-well located within the underlying substrate; a semiconductor material located above the subcollector, comprising a doped region, wherein the doped region is located above the subcollector; an active device located above the semiconductor material; as well as At least one air gap structure is located below the active device and within the doped region of the semiconductor material, the at least one air gap structure being away from the subcollector.

13. The structure of claim 12, further comprising polysilicon material vertically located between the at least one air gap structure and the active device.

14. The structure of claim 13, wherein the polysilicon material is located below shallow trench isolation regions formed in a semiconductor layer including source and drain regions of the active device.

15. The structure of claim 12, wherein the at least one air gap structure comprises a discontinuous sealed air gap structure underlying the active device.

16. The structure of claim 12, wherein the at least one air gap structure comprises a single continuous sealed air gap structure underlying the active device.

17. The structure of claim 12, wherein the at least one air gap structure is located below a passive device.

18. The structure of claim 12, wherein the at least one air gap structure is located below a high performance bipolar junction transistor, and the semiconductor material having the doped region comprises the same dopant type as the subcollector.

19. The structure of claim 12, wherein the active device comprises an RF switching device and the bipolar junction transistor comprises a high breakdown bipolar junction transistor having the subcollector and the doped region comprising the same dopant type.

20. A method of forming a semiconductor structure, comprising: forming a semiconductor material including a doped region; forming one or more sealed air gap structures that disrupt the doped regions of the semiconductor material; as well as forming a field effect transistor over the one or more sealed air gap structures and the semiconductor material, An n-well is located in an underlying semiconductor substrate below the doped region of the semiconductor material and below the one or more sealed air gap structures.

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