Switching converter circuit and driving circuit with adaptive dead time therein

Abstract

A switching converter circuit and a driver circuit therein having adaptive dead time. The switching converter circuit is configured to switch the voltage at one end of an inductor therein according to a pulse-width modulation signal to convert an input voltage into an output voltage. The switching converter circuit comprises a driver circuit including an upper bridge driver, a lower bridge driver, an upper bridge sensing circuit, and a lower bridge sensing circuit. The upper bridge sensing circuit is configured to sense the gate-source voltage of the upper bridge metal-oxide semiconductor field-effect transistor and generate a lower bridge enable signal to enable the lower bridge driver to switch the lower bridge metal-oxide semiconductor field-effect transistor according to the pulse-width modulation signal. The lower bridge sensing circuit is configured to sense the gate-source voltage of the lower bridge metal-oxide semiconductor field-effect transistor and generate an upper bridge enable signal to enable the upper bridge driver to switch the upper bridge metal-oxide semiconductor field-effect transistor according to the pulse-width modulation signal.

Description

Technical Field

[0001] The present invention relates to a switching converter circuit, and more particularly to a switching converter circuit having an adaptive dead time and capable of avoiding short-circuit current. The present invention also relates to a driving circuit in the switching converter circuit. Background Art

[0002] Figure 1A A circuit diagram of a conventional switching converter circuit 10 is shown. The switching converter circuit 10 includes a driver circuit 11 and a power stage circuit 12. As shown, the power stage circuit 12 includes a high-bridge switch 121, a low-bridge switch 122, and an inductor 123. The driver circuit 11 generates a high-bridge signal UG and a low-bridge signal LG based on a pulse width modulation (PWM) signal P1. The high-bridge switch 121 and the low-bridge switch 122 operate based on the high-bridge signal UG and the low-bridge signal LG, respectively, to convert an input voltage Vin into an output voltage Vout and generate an inductor current IL that flows through the inductor 123 of the power stage circuit 12.

[0003] like Figure 1A In the illustrated switching converter circuit 10, the power stage circuit 12 is a step-down power stage circuit. During normal operation, the high-bridge switch 121 and the low-bridge switch 122 are alternately turned on to switch the end of the inductor 123 electrically connected to the phase node LX between the input voltage Vin and the ground potential GND. This causes the inductor current IL to alternate between two current paths: one flowing from the input voltage Vin through the high-bridge switch 121 to the phase node LX, then through the inductor L, to the output terminal; and the other flowing from the ground potential GND through the low-bridge switch 122 to the phase node LX, then through the inductor L, to the output terminal. During normal operation, the high-bridge switch 121 and the low-bridge switch 122 must not be turned on at the same time to prevent circuit breakdown and damage. Therefore, a dead time, in which both the high-bridge switch 121 and the low-bridge switch 122 are not turned on, is required to separate the on-times of the high-bridge switch 121 and the low-bridge switch 122.

[0004] Figure 1B The circuit diagram of the driving circuit 11 of the prior art is shown. Figure 1BAs shown, the driver circuit 11 includes latch circuits 111 and 112, a level shift circuit 113, an inverter 114, delay circuits 115 and 116, and multiple other inverters. The PWM signal P1 serves as a reset signal for the latch circuit 111. When the PWM signal P1 is low, the latch circuit 111 outputs a high signal. After passing through the level shift circuit 113 and three inverters, the generated high-side signal UG is low, turning off the high-side switch 121. When the PWM signal P1 goes high, the output signal of the delay circuit 116 determines whether the high-side signal UG goes high, turning on the high-side switch 121.

[0005] On the other hand, PWM signal P1 passes through inverter 114, and its inverted signal serves as a reset signal for latch circuit 112. When PWM signal P1 is high, latch circuit 112 outputs a high voltage. Passing through three inverters, the resulting low-bridge signal LG is low, turning off low-bridge switch 122. When PWM signal P1 goes low, the output signal of delay circuit 115 determines whether to cause low-bridge signal LG to go high, turning on high-bridge switch 121.

[0006] The output signal of latch circuit 111 is delayed by a predetermined upper-bridge delay time through delay circuit 115 and then input to latch circuit 112 as a set signal for latch circuit 112, thereby enabling latch circuit 112 to generate lower-bridge signal LG based on the inverted signal of PWM signal P1. Conversely, the output signal of latch circuit 112 is delayed by a predetermined lower-bridge delay time through delay circuit 116 and then input to latch circuit 111 as a set signal for latch circuit 111, thereby enabling latch circuit 111 to generate upper-bridge signal UG based on PWM signal P1.

[0007] The high-bridge delay time must be long enough to cover the dead time after the high-bridge switch 121 stops conducting, and the low-bridge delay time must be long enough to cover the dead time after the low-bridge switch 122 stops conducting, to prevent the high-bridge switch 121 and the low-bridge switch 122 from being turned on simultaneously. The driver circuit 11 generates a bootstrap voltage BOOT based on the DC voltage VCC. The level shift circuit 113 level-shifts the PWM signal P1 after passing through the latch circuit 111 to the boot voltage domain.

[0008] See also Figure 1ADuring normal operation of the switching converter circuit 10, the deadtime is a fixed, predetermined period. After the low-bridge switch 122 ceases conducting, the high-bridge switch 121 turns on after a fixed deadtime. During this deadtime, the parasitic diode LD in the low-bridge switch 122 switches from forward bias to reverse bias. During another deadtime, between the high-bridge switch 121 cessation of conduction and the low-bridge switch 122 turning on, the parasitic diode LD in the low-bridge switch 122 switches from reverse bias to forward bias. During this deadtime, the inductor current IL flows solely from ground potential GND through the parasitic diode LD in the low-bridge switch 122 to the phase node LX and then through the inductor L. In other words, during one switching cycle of the high-bridge switch 121 and the low-bridge switch 122, the PN interface of the parasitic diode LD in the low-bridge switch 122 undergoes two bias reversals during the two deadtimes, resulting in energy and time losses in the reverse recovery charge (Qrr).

[0009] During normal operation of a conventional switching converter circuit 10, the deadtime must be preset to a fixed time that is sufficiently long to accommodate varying deadtime requirements due to variations in the electronic components and circuitry of the switching converter circuit 10 during various manufacturing processes. Specifically, the deadtime must be preset to exceed the maximum of the varying deadtime requirements due to various variations in deadtime to prevent the high-bridge switch 121 and the low-bridge switch 122 from being turned on simultaneously. Consequently, for most switching converter circuits 10 that require a shorter deadtime, an excessively long deadtime results in significant reverse recovery charge energy and time losses, as well as significant forward conduction energy losses, resulting in relatively low conversion efficiency.

[0010] Compared to the aforementioned prior art, the present invention proposes a switching converter circuit with adaptive dead time and a driving circuit therein, which can avoid short-circuit current caused by simultaneous conduction of the upper bridge switch and the lower bridge switch, while reducing reverse recovery charge and forward conduction energy loss to improve conversion efficiency. Summary of the Invention

[0011] From one perspective, the present invention provides a switching converter circuit for switching a first end of an inductor between a first voltage and a second voltage according to a pulse width modulation (PWM) signal to convert an input voltage into an output voltage. The switching converter circuit includes: an upper bridge metal oxide semiconductor field effect transistor (MOSFET) coupled between the first voltage and the first end of the inductor; a lower bridge MOSFET coupled between the second voltage and the first end of the inductor; and a driving circuit including: an upper bridge driver for generating an upper bridge driving signal according to the PWM signal to drive the upper bridge MOSFET; a lower bridge driver for generating a lower bridge driving signal according to the PWM signal to drive the lower bridge MOSFET; an upper bridge sensing circuit for sensing the gate-source voltage of the upper bridge MOSFET and sensing the gate-source voltage of the upper bridge MOSFET according to the gate-source voltage of the upper bridge MOSFET. The FET has a gate-source voltage, which generates a lower bridge enable signal to indicate the non-conducting state of the upper bridge MOSFET, wherein the lower bridge enable signal enables the lower bridge driver to switch the lower bridge MOSFET according to the PWM signal; and a lower bridge sensing circuit to sense the gate-source voltage of the lower bridge MOSFET and generate an upper bridge enable signal according to the gate-source voltage of the lower bridge MOSFET to indicate the non-conducting state of the lower bridge MOSFET, wherein the upper bridge enable signal enables the upper bridge driver to switch the upper bridge MOSFET according to the PWM signal.

[0012] From another perspective, the present invention also provides a driving circuit for a switching converter circuit, comprising: an upper bridge driver for generating an upper bridge drive signal according to a PWM signal to drive an upper bridge MOSFET; a lower bridge driver for generating a lower bridge drive signal according to the PWM signal to drive a lower bridge MOSFET; an upper bridge sensing circuit for sensing the gate-source voltage of the upper bridge MOSFET and generating a lower bridge enable signal according to the gate-source voltage of the upper bridge MOSFET to indicate a non-conducting state of the upper bridge MOSFET, wherein the lower bridge enable signal enables the lower bridge driver to switch the lower bridge MOSFET according to the PWM signal; and a lower bridge sensing circuit for sensing the gate-source voltage of the lower bridge MOSFET and generating an upper bridge enable signal according to the gate-source voltage of the lower bridge MOSFET to indicate a non-conducting state of the lower bridge MOSFET, wherein the upper bridge enable signal enables the upper bridge driver to switch the upper bridge MOSFET according to the PWM signal.

[0013] In a preferred embodiment, the lower bridge sensing circuit includes a lower bridge sensing MOSFET having the same conductivity type as the lower bridge MOSFET, and the gate of the lower bridge sensing MOSFET is coupled to the gate of the lower bridge MOSFET, and the source of the lower bridge sensing MOSFET is coupled to the source of the lower bridge MOSFET, so that the lower bridge sensing MOSFET generates the upper bridge enable signal at the drain of the lower bridge sensing MOSFET according to the gate-source voltage of the lower bridge MOSFET.

[0014] In a preferred embodiment, the lower bridge sensing circuit further includes a current source coupled between the upper bridge enable signal and a bootstrap voltage of the upper bridge driver to level shift the multiple logic levels of the upper bridge enable signal to a boot voltage domain, wherein the upper bridge driver includes an enable logic circuit for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge MOSFET according to the PWM signal.

[0015] In a preferred embodiment, the lower bridge sensing circuit further includes a current source coupled between the upper bridge enable signal and a DC voltage, wherein the DC voltage is used to generate a bootstrap voltage for the upper bridge driver, wherein the upper bridge driver includes an enable logic circuit and a level shift circuit coupled to each other to receive the upper bridge enable signal and enable the upper bridge driver to switch the upper bridge MOSFET according to the PWM signal.

[0016] In a preferred embodiment, the lower bridge sensing circuit includes a lower bridge comparator for comparing the gate-source voltage of the lower bridge MOSFET with a lower bridge reference voltage to generate the upper bridge enable signal, wherein the upper bridge driver includes an enable logic circuit and a level shift circuit coupled to each other for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge MOSFET according to the PWM signal.

[0017] In a preferred embodiment, the absolute value of the turn-on threshold voltage of an upper bridge sensing MOSFET of the upper bridge sensing circuit is lower than or equal to the absolute value of the turn-on threshold voltage of the upper bridge MOSFET, and the absolute value of the turn-on threshold voltage of the lower bridge sensing MOSFET is lower than or equal to the absolute value of the turn-on threshold voltage of the lower bridge MOSFET.

[0018] In a preferred embodiment, the upper bridge sensing circuit includes an upper bridge sensing MOSFET having a conductivity type complementary to that of the upper bridge MOSFET, and the gate of the upper bridge sensing MOSFET is coupled to the source of the upper bridge MOSFET, and the source of the upper bridge sensing MOSFET is coupled to the gate of the upper bridge MOSFET, so that the upper bridge sensing MOSFET generates the lower bridge enable signal at the drain of the upper bridge sensing MOSFET according to the gate-source voltage of the upper bridge MOSFET.

[0019] In a preferred embodiment, the high-bridge sensing circuit includes: a high-bridge sensing MOSFET having the same conductivity type as the high-bridge MOSFET; and a high-bridge clamping MOSFET having a conductivity type complementary to the high-bridge MOSFET, wherein the high-bridge clamping MOSFET and the high-bridge sensing MOSFET are coupled in series to a bootstrap voltage of the high-bridge driver; wherein the gate and source of the high-bridge MOSFET are respectively coupled to the gate of the high-bridge sensing MOSFET and the gate of the high-bridge clamping MOSFET, so that the high-bridge clamping MOSFET generates the low-bridge enable signal at the drain of the high-bridge clamping MOSFET according to the gate-source voltage of the high-bridge MOSFET.

[0020] In a preferred embodiment, the high-bridge sensing circuit includes: a high-bridge sensing MOSFET having a conductivity type complementary to that of the high-bridge MOSFET; and a high-bridge clamping MOSFET having a conductivity type complementary to that of the high-bridge MOSFET, wherein the high-bridge clamping MOSFET and the high-bridge sensing MOSFET are coupled in series to a bootstrap voltage of the high-bridge driver; wherein the gate and source of the high-bridge MOSFET are respectively coupled to the gate of the high-bridge sensing MOSFET and the gate of the high-bridge clamping MOSFET, so that the high-bridge clamping MOSFET generates the low-bridge enable signal at the drain of the high-bridge clamping MOSFET according to the gate-source voltage of the high-bridge MOSFET.

[0021] In a preferred embodiment, the upper bridge sensing circuit includes: an upper bridge sensing MOSFET, wherein the absolute value of the turn-on threshold voltage of the upper bridge sensing MOSFET is lower than or equal to the absolute value of the turn-on threshold voltage of the upper bridge MOSFET, and the lower bridge sensing circuit includes a lower bridge sensing MOSFET, wherein the absolute value of the turn-on threshold voltage of the lower bridge sensing MOSFET is lower than or equal to the absolute value of the turn-on threshold voltage of the lower bridge MOSFET.

[0022] In a preferred embodiment, the upper bridge MOSFET has the same conductivity type as the lower bridge MOSFET.

[0023] The following detailed description of specific embodiments will make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A A schematic diagram of a conventional switching converter circuit 10 is shown.

[0025] Figure 1B FIG. 1 is a circuit diagram showing a driving circuit 11 in the prior art.

[0026] Figure 2 A schematic diagram is shown of a switching converter circuit 20 according to the present invention.

[0027] Figure 3 An embodiment of a driving circuit 21 according to the present invention is shown.

[0028] Figure 4 An embodiment of a driving circuit 31 according to the present invention is shown.

[0029] Figure 5 An embodiment of a driving circuit 41 according to the present invention is shown.

[0030] Figure 6 An embodiment of a driving circuit 51 according to the present invention is shown.

[0031] Explanation of symbols in the figure

[0032] 10, 20: Switching converter circuit

[0033] 11, 21, 31, 41, 51: drive circuit

[0034] 12: Power stage circuit

[0035] 23: Load circuit

[0036] 111, 112: Latch circuit

[0037] 113: Level Shift Circuit

[0038] 114: Inverter

[0039] 115, 116: Delay circuit

[0040] 121: Upper bridge switch

[0041] 122: Lower bridge switch

[0042] 123: Inductor

[0043] 211, 311, 411, 511: Upper bridge driver

[0044] 212, 312, 412, 512: Upper bridge sensing circuit

[0045] 213, 313, 413, 513: Lower bridge driver

[0046] 214, 314, 414, 514: Lower bridge sensing circuit

[0047] 221: Upper bridge MOSFET

[0048] 222: Lower bridge MOSFET

[0049] 223: Inductor

[0050] 315, 415, 515, 516: Level shift circuits

[0051] 514: Lower bridge comparator

[0052] 2121, 3121, 4121: Upper bridge sensing MOSFET

[0053] 2122, 2142, 3122, 3142, 4122, 4142: Current Source

[0054] 2141, 3141, 4141: Low-side sensing MOSFET

[0055] 3111, 3131, 4111, 4131, 5111, 5131: Enable logic circuit

[0056] 3123, 4123: High-side clamp MOSFET

[0057] 5121: Upper bridge comparator

[0058] BOOT: bootstrap voltage

[0059] ENH: upper bridge enable signal

[0060] ENL: lower bridge enable signal

[0061] GND: Ground potential

[0062] IL: inductor current

[0063] LD: parasitic diode

[0064] LG: Downbridge signal

[0065] LX: Phase Node

[0066] P1: PWM signal

[0067] SH: upper bridge PWM signal

[0068] SL: lower bridge PWM signal

[0069] VCC: DC voltage

[0070] Vin: input voltage

[0071] Vout: output voltage

[0072] Vref1: upper bridge reference voltage

[0073] Vref2: lower bridge reference voltage

[0074] UG: Up bridge signal DETAILED DESCRIPTION

[0075] The drawings in the present invention are schematic diagrams, mainly intended to illustrate the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale.

[0076] Figure 2 A schematic diagram illustrates a switching converter circuit 20 according to the present invention. Switching converter circuit 20 is configured to switch a first end of an inductor 223 (in this embodiment, the end electrically connected to a phase node LX) between a first voltage (in this embodiment, the input voltage Vin) and a second voltage (in this embodiment, the ground potential GND) according to a pulse width modulation (PWM) signal P1, thereby converting the input voltage Vin into an output voltage Vout to provide power to a load circuit 23. Switching converter circuit 20 includes a high-bridge metal oxide semiconductor field effect transistor (MOSFET) 221, a low-bridge MOSFET 222, and a driver circuit 21.

[0077] In this embodiment, the high-bridge MOSFET is coupled between the input voltage Vin and the phase node LX (the first end of the inductor). The low-bridge MOSFET is coupled between the ground potential GND and the phase node LX (the first end of the inductor). It should be noted that in addition to buck-type power stage circuits, the present invention can also be applied to boost-type power stage circuits and buck-boost-type power stage circuits. Any power stage circuit comprising a high-bridge MOSFET and a low-bridge MOSFET can be applied to improve conversion efficiency and reduce reverse recovery charge loss. Simply by changing the connection point to which the first end of the inductor is coupled and the connection points at which the high-bridge MOSFET and the low-bridge MOSFET are coupled to the input voltage, ground potential, phase node, and output voltage, the present invention can be applied.

[0078] The driver circuit 21 generates a high-bridge drive signal UG and a low-bridge drive signal LG based on a PWM signal P1 related to the output voltage Vout feedback signal. These signals operate the high-bridge MOSFET 221 and the low-bridge MOSFET 222 to switch the first end of the inductor 223 between a first voltage (input voltage Vin) and a second voltage (ground GND). The driver circuit 21 includes a high-bridge driver 211, a low-bridge driver 213, a high-bridge sensing circuit 212, and a low-bridge sensing circuit 214.

[0079] The high-bridge driver 211 is configured to generate a high-bridge drive signal UG based on a PWM signal P1 to drive the high-bridge MOSFET 221. The low-bridge driver 213 is configured to generate a low-bridge drive signal LG based on the PWM signal P1 to drive the low-bridge MOSFET 222. The high-bridge sensing circuit 212 is configured to sense the gate-source voltage of the high-bridge MOSFET 221 and generate a low-bridge enable signal ENL to indicate that the high-bridge MOSFET 221 is in a non-conducting state. The low-bridge enable signal ENL enables the low-bridge driver 213 to switch the low-bridge MOSFET 222 based on the PWM signal P1. The low-bridge sensing circuit 214 is configured to sense the gate-source voltage of the low-bridge MOSFET 222 and generate a high-bridge enable signal ENH to indicate that the low-bridge MOSFET 222 is in a non-conducting state. The high-bridge enable signal ENH enables the high-bridge driver 211 to switch the high-bridge MOSFET 221 based on the PWM signal P1.

[0080] Specifically Figure 2 In the illustrated embodiment, the high-bridge MOSFET 221 is, for example, an N-type MOSFET. The high-bridge sensing circuit 212 senses the gate-source voltage of the high-bridge MOSFET 221. When the absolute value of the gate-source voltage of the high-bridge MOSFET 221 is greater than a first threshold voltage, indicating that the high-bridge MOSFET 221 is conducting or nearly conducting, the high-bridge sensing circuit 212, for example, changes the low-bridge enable signal ENL to a disable level to disable conduction of the low-bridge MOSFET 222. In a preferred embodiment, the first threshold voltage is, for example, a positive value and less than or equal to the conduction threshold voltage of the high-bridge MOSFET 221. This ensures that the enable signal ENL changes to a disable level when the high-bridge MOSFET 221 is conducting. This ensures that the low-bridge MOSFET 222 is non-conducting when the high-bridge MOSFET 221 is conducting. The conduction threshold voltage of the high-bridge MOSFET 221 is, for example, a positive value.

[0081] On the other hand, when the gate-source voltage of the high-bridge MOSFET 221 is lower than the first threshold voltage, which indicates that the high-bridge MOSFET 221 is not conducting, the high-bridge sensing circuit 212 changes the low-bridge enable signal ENL to an enable level, so as to enable the low-bridge driver 213 to switch the low-bridge MOSFET 222 according to the PWM signal P1.

[0082] Similarly, when the high-bridge MOSFET 221 is a P-type MOSFET, the high-bridge sensing circuit 212 senses the gate-source voltage of the high-bridge MOSFET 221. When the absolute value of the gate-source voltage of the high-bridge MOSFET 221 is higher than a first threshold voltage, indicating that the high-bridge MOSFET 221 is conducting or nearly conducting, the high-bridge sensing circuit 212 changes the low-bridge enable signal ENL to a high-disabling level to disable conduction of the low-bridge MOSFET 222. This ensures that when the high-bridge MOSFET 221 is conducting, the low-bridge MOSFET 222 is non-conducting. The high-bridge MOSFET 221 is, for example, a P-type MOSFET, and its conduction threshold voltage is, for example, a negative value, and the first threshold voltage is less than or equal to the absolute value of the conduction threshold voltage of the high-bridge MOSFET 221.

[0083] On the other hand, when the absolute value of the gate-source voltage of the high-bridge MOSFET 221 is lower than the first threshold voltage, that is, when the high-bridge MOSFET 221 is not conducting, the high-bridge sensing circuit 212 changes the low-bridge enable signal ENL to an enable level, so as to enable the low-bridge driver 213 to switch the low-bridge MOSFET 222 according to the PWM signal P1.

[0084] Please continue reading Figure 2 ,like Figure 2 As shown, the lower bridge MOSFET222 is, for example, an N-type MOSFET, and the lower bridge sensing circuit 214 senses the gate-source voltage of the lower bridge MOSFET222. When the absolute value of the gate-source voltage of the lower bridge MOSFET222 is higher than the second threshold voltage, that is, when the lower bridge MOSFET222 is turned on, the lower bridge sensing circuit 214, for example, changes the upper bridge enable signal ENH to a high potential. In a preferred embodiment, the second threshold voltage is, for example, a positive value and is lower than or equal to the turn-on threshold voltage of the lower bridge MOSFET222 to ensure that when the lower bridge MOSFET222 is turned on, the enable signal ENH is changed to a prohibition level. In this way, it can be ensured that when the lower bridge MOSFET222 is turned on, the upper bridge MOSFET221 must be non-conducting. Among them, the turn-on threshold voltage of the lower bridge MOSFET222 is, for example, a positive value. In a preferred embodiment, the upper bridge MOSFET221 has the same conductivity type as the lower bridge MOSFET222, for example Figure 2 Both are N-type MOSFETs.

[0085] On the other hand, when the gate-source voltage of the lower bridge MOSFET 222 is lower than the second threshold voltage, indicating that the lower bridge MOSFET 222 is not conducting, the lower bridge sensing circuit 214, for example, changes the high bridge enable signal ENH to an enable level, thereby enabling the high bridge driver 211 to switch the high bridge MOSFET 221 according to the PWM signal P1. Similarly, if the lower bridge MOSFET 222 is a P-type MOSFET, the lower bridge sensing circuit 214, for example, senses the gate-source voltage of the lower bridge MOSFET 222. When the absolute value of the gate-source voltage of the lower bridge MOSFET 222 is higher than the second threshold voltage, the lower bridge sensing circuit 214 changes the high bridge enable signal ENH to a disable level, indicating that the high bridge MOSFET 221 is not conducting. In this manner, the high bridge MOSFET 221 is not conducting when the lower bridge MOSFET 222 is conducting. The lower bridge MOSFET 222 is, for example, a P-type MOSFET, whose conduction threshold voltage is, for example, negative, and the second threshold voltage is less than or equal to the absolute value of the conduction threshold voltage of the lower bridge MOSFET 222. The actual levels of the enable level and the disable level can be configured according to the requirements of a specific circuit, which will be described in detail later.

[0086] In summary, the high-bridge sensing circuit 212 and the low-bridge sensing circuit 214 respectively sense the gate-source voltage of the high-bridge MOSFET 221 and the gate-source voltage of the low-bridge MOSFET 222. When the high-bridge MOSFET 221 and the low-bridge MOSFET 222 are determined to be non-conducting, the low-bridge driver 213 can be enabled to switch the low-bridge MOSFET 222 and the high-bridge driver 211 can be enabled to switch the high-bridge MOSFET 221 in accordance with the PWM signal P1 in real time. This eliminates the need for the conventional switching converter circuit 10 to use fixed, excessively long high-bridge and low-bridge delay times to separate the conduction times of the high-bridge switch 121 and the low-bridge switch 122. Compared to the conventional technology, the present invention can reduce the energy and time losses of the reverse recovery charge and improve conversion efficiency.

[0087] Figure 3 An embodiment of the driving circuit 21 according to the present invention is shown. Figure 3As shown, the drive circuit 21 includes an upper bridge driver 211, an upper bridge sensing circuit 212, a lower bridge driver 213, and a lower bridge sensing circuit 214. The upper bridge sensing circuit 212, for example, includes an upper bridge sensing MOSFET 2121 and a current source 2122; the lower bridge sensing circuit 214, for example, includes a lower bridge sensing MOSFET 2141 and a current source 2142. The PWM signal P1 is buffered to generate an upper bridge PWM signal SH, where the PWM signal P1 is in phase with the upper bridge PWM signal SH. The PWM signal P1 is then invertered to generate a lower bridge PWM signal SL, where the PWM signal P1 is in phase with the lower bridge PWM signal SL.

[0088] like Figure 3 As shown, the lower bridge sensing MOSFET 2141 has the same conductivity type as the lower bridge MOSFET 222; the lower bridge sensing MOSFET 2141 and the lower bridge MOSFET 222 are both N-type MOSFETs. The gate of the lower bridge sensing MOSFET 2141 is coupled to the gate of the lower bridge MOSFET 222, and the source of the lower bridge sensing MOSFET 2141 is coupled to the source of the lower bridge MOSFET 222, as shown in FIG. Figure 3 As shown, the source of the low-bridge sensing MOSFET 2141 and the source of the low-bridge MOSFET 222 are both electrically connected to the ground potential GND. In this way, the low-bridge sensing MOSFET 2141 generates the high-bridge enable signal ENH at the drain of the low-bridge sensing MOSFET 2141 according to the gate-source voltage of the low-bridge MOSFET 222.

[0089] Please continue reading Figure 3 The lower bridge sensing circuit 214 further includes a current source 2142 coupled between the upper bridge enable signal ENH and the bootstrap voltage BOOT of the upper bridge driver 21, so as to level shift the multiple logic levels of the upper bridge enable signal ENH to the boot voltage domain, so that the upper bridge driver 211 can determine whether the lower bridge MOSFET 222 is not conducting according to the upper bridge enable signal ENH. The upper bridge driver 211 includes an enable logic circuit (such as Figure 3 The level-shifted inverter formed by the P-type MOSFET and the current source, and another inverter and NAND gate coupled thereto are used to receive the high-bridge enable signal ENH to enable the high-bridge driver 211 to switch the high-bridge MOSFET 221 according to the PWM signal P1.

[0090] like Figure 3 As shown, the upper bridge driver 211 includes, for example, a P-type MOSFET, a NAND gate as an enable logic circuit, a current source, and two inverters. The lower bridge driver 213 includes, for example, a NAND gate as an enable logic circuit and two inverters.

[0091] For example, if Figure 3 As shown, the turn-on threshold voltage of low-bridge sensing MOSFET 2141 is equal to the aforementioned second threshold voltage and is lower than or equal to the turn-on threshold voltage of low-bridge MOSFET 222. When low-bridge sensing MOSFET 2141 is turned on, it indicates that low-bridge MOSFET 222 is turned on or nearly on, and also indicates that high-bridge MOSFET 221 should not be turned on. In this case, low-bridge sensing circuit 214 changes high-bridge enable signal ENH to a disable level (low in this embodiment) to disable high-bridge PWM signal SH, ensuring that high-bridge MOSFET 221 is not turned on. Specifically, the level-shifted high-bridge enable signal ENH is input to the gate of the P-type MOSFET in the high-bridge driver 211, turning on the P-type MOSFET and outputting a high potential to the inverter. Consequently, one input terminal of the NAND gate in the high-bridge driver 211 is a low potential representing 0. At this point, regardless of the logic level of the high-bridge PWM signal SH, the output terminal of the NAND gate outputs a high potential representing 1. This high potential then passes through the inverter and outputs a low potential, meaning that the high-bridge drive signal UG is a low potential, and the high-bridge MOSFET 221 is not conducting.

[0092] When the lower bridge sensing MOSFET 2141 is off, it indicates that the lower bridge MOSFET 222 is also off, which also means that the upper bridge MOSFET 221 can now operate according to the upper bridge PWM signal SH. In this case, the lower bridge sensing circuit 214 shifts the upper bridge enable signal ENH to an enable level (high in this embodiment) to enable the upper bridge PWM signal SH. Specifically, the level-shifted upper bridge enable signal ENH is input to the gate of the P-type MOSFET in the upper bridge driver 211, turning the P-type MOSFET off and outputting a low voltage to the inverter. As a result, one input terminal of the NAND gate in the upper bridge driver 211 is a high voltage, representing a 1. When the upper bridge PWM signal SH is a high voltage, representing a 1, the output terminal of the NAND gate is a low voltage, representing a 0. This low voltage is then output through the inverter, resulting in a high voltage. This means that the upper bridge drive signal UG is high, turning the upper bridge MOSFET 221 on. Similarly, when the upper bridge PWM signal SH is a low voltage, representing a 0, the upper bridge drive signal UG is low, turning the upper bridge MOSFET 221 off. That is, when the lower bridge sensing MOSFET 2141 is not conducting, the upper bridge enable signal ENH is at a high level (enabled), and the upper bridge driver 211 switches the upper bridge MOSFET 221 according to the PWM signal P1 .

[0093] Please continue reading Figure 3The upper bridge sensing MOSFET 2121 has a conductivity type complementary to that of the upper bridge MOSFET 221. For example, the upper bridge sensing MOSFET 2121 is a P-type MOSFET, while the upper bridge MOSFET 221 is an N-type MOSFET. The gate of the upper bridge sensing MOSFET 2121 is coupled to the source of the upper bridge MOSFET 221, and the source of the upper bridge sensing MOSFET 2121 is coupled to the gate of the upper bridge MOSFET 221. In this way, the upper bridge sensing MOSFET 2121 generates a lower bridge enable signal ENL at the drain of the upper bridge sensing MOSFET 2121 based on the gate-source voltage of the upper bridge MOSFET 221.

[0094] Please continue reading Figure 3 The upper bridge sensing circuit 212 further includes a current source 2122 coupled between the lower bridge enable signal ENL and the ground potential GND, so that the lower bridge driver 213 can determine whether the upper bridge MOSFET 221 is not conducting according to the lower bridge enable signal ENL. The lower bridge driver 213 includes an enable logic circuit (such as Figure 3 The NAND gate is configured to enable the low-bridge driver 213 to switch the low-bridge MOSFET 222 according to the PWM signal P1 according to the low-bridge enable signal ENL.

[0095] On the other hand, for example, Figure 3 As shown, the turn-on threshold voltage of the upper bridge sensing MOSFET 2121 is equal to the aforementioned first threshold voltage, and its absolute value is lower than or equal to the turn-on threshold voltage of the upper bridge MOSFET 221. When the upper bridge sensing MOSFET 2121 is turned on, it indicates that the upper bridge MOSFET 221 is turned on or nearly turned on, and also indicates that the lower bridge MOSFET 222 should not be turned on. In this case, the upper bridge sensing circuit 212 changes the lower bridge enable signal ENL to a disable level (a high level in this embodiment) to disable the lower bridge PWM signal SL, ensuring that the lower bridge MOSFET 222 is not turned on. Specifically, the high-level lower bridge enable signal ENL is input to the inverter in the lower bridge driver 213. Therefore, one input terminal of the NAND gate in the lower bridge driver 213 is at a low level representing 0. At this time, regardless of the logic level of the lower bridge PWM signal SL, the output terminal of the NAND gate outputs a high level representing 1. This high level is then outputted by the inverter to a low level, which means that the lower bridge drive signal LG is at a low level, and the lower bridge MOSFET 222 is not turned on.

[0096] When the upper bridge sensing MOSFET 2121 is off, it indicates that the upper bridge MOSFET 221 is definitely off, and the lower bridge MOSFET 222 can now operate according to the lower bridge PWM signal SL. In this case, the upper bridge sensing circuit 212 changes the lower bridge enable signal ENL to an enable level (low in this embodiment) to enable the lower bridge PWM signal SL. Specifically, the low lower bridge enable signal ENL is input to the inverter in the lower bridge driver 213. As a result, one input terminal of the NAND gate in the lower bridge driver 213 is at a high level, representing a 1. When the lower bridge PWM signal SL is at a high level, representing a 1, the output terminal of the NAND gate is at a low level, representing a 0. This low level, after passing through the inverter, outputs a high level, which means that the lower bridge drive signal LG is high, turning the lower bridge MOSFET 222 on. Similarly, when the lower bridge PWM signal SL is at a low level, representing a 0, the lower bridge drive signal LG is low, turning the lower bridge MOSFET 222 off. That is, when the upper bridge sensing MOSFET 2121 is off and the lower bridge enable signal ENL is low (enabled), the lower bridge driver 213 switches the lower bridge MOSFET 222 according to the lower bridge PWM signal SL, which is the inverse signal of the PWM signal P1 .

[0097] Figure 4 An embodiment of the driving circuit 31 according to the present invention is shown. Figure 4 As shown, the drive circuit 31 includes an upper bridge driver 311, an upper bridge sensing circuit 312, a lower bridge driver 313, and a lower bridge sensing circuit 314. The upper bridge sensing circuit 312, for example, includes an upper bridge sensing MOSFET 3121, a current source 3122, and an upper bridge clamping MOSFET 3123; the lower bridge sensing circuit 314, for example, includes a lower bridge sensing MOSFET 3141 and a current source 3142. The PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH. The PWM signal P1 is invertered to generate the lower bridge PWM signal SL, where the PWM signal P1 is in phase with the lower bridge PWM signal SL.

[0098] like Figure 4 As shown, the lower bridge sensing MOSFET 3141 has the same conductivity type as the lower bridge MOSFET 222; the lower bridge sensing MOSFET 3141 and the lower bridge MOSFET 222 are both N-type MOSFETs. The gate of the lower bridge sensing MOSFET 3141 is coupled to the gate of the lower bridge MOSFET 222, and the source of the lower bridge sensing MOSFET 3141 is coupled to the source of the lower bridge MOSFET 222, as shown in FIG. Figure 4As shown, the source of the low-bridge sensing MOSFET 3141 and the source of the low-bridge MOSFET 222 are both electrically connected to the ground potential GND. In this way, the low-bridge sensing MOSFET 3141 generates an upper bridge enable signal ENH at its drain according to the gate-source voltage of the low-bridge MOSFET 222.

[0099] Please continue reading Figure 4 The lower bridge sensing circuit 314 further includes a current source 3142 coupled between the upper bridge enable signal ENH and a DC voltage VCC, wherein the DC voltage VCC is used to generate a bootstrap voltage BOOT for the upper bridge driver 311. The upper bridge driver 311 includes an enable logic circuit 3111 and a level shift circuit 315 coupled to each other. The level shift circuit 315 is used to level shift the output signal of the enable logic circuit 3111 upward to a boot voltage domain, so that the upper bridge driver 311 can determine whether the lower bridge MOSFET 222 is off based on the upper bridge enable signal ENH. The enable logic circuit 3111 is used to receive the upper bridge enable signal ENH to enable the upper bridge driver 311 to switch the upper bridge MOSFET 221 based on the PWM signal P1.

[0100] For example, if Figure 4 As shown, the turn-on threshold voltage of the low-bridge sense MOSFET 3141 is lower than or equal to the turn-on threshold voltage of the low-bridge MOSFET 222. When the low-bridge sense MOSFET 3141 is turned on, it indicates that the low-bridge MOSFET 222 is turned on or nearly on, and also indicates that the high-bridge MOSFET 221 should not be turned on. In this case, the low-bridge sense circuit 314 changes the high-bridge enable signal ENH to a disable level (low in this embodiment) to disable the high-bridge PWM signal SH, ensuring that the high-bridge MOSFET 221 is not turned on.

[0101] Specifically, the low potential upper bridge enable signal ENH is input to the inverter in the upper bridge driver 311, and outputs a high potential to the enable logic circuit 3111. The enable logic circuit 3111 is, for example, Figure 4 Therefore, one input terminal of the enable logic circuit 3111, such as the reset pin of the NAND latch circuit, receives the upper bridge PWM signal SH; the other terminal, such as the set pin of the NAND latch circuit, receives the inverted upper bridge enable signal ENH.

[0102] When the high-bridge PWM signal SH is at a low level representing 0, the enable logic circuit 3111 outputs a high level representing 1. This high level then passes through the level shift circuit 315 and then three inverters to generate a low high-bridge drive signal UG, turning off the high-bridge MOSFET 221.

[0103] When the high-bridge PWM signal SH changes from a low level representing 0 to a high level representing 1, the logic level of the high-bridge enable signal ENH is a low level representing 0, and its inverted signal is a high level representing 1. The enable logic circuit 3111 outputs a high level representing 1, the high-bridge drive signal UG is a low level, and the high-bridge MOSFET 221 is also turned off. In other words, when the high-bridge enable signal ENH is a low level (corresponding to disabled in this embodiment), regardless of the logic level of the high-bridge PWM signal SH, the high-bridge drive signal UG is a low level, and the high-bridge MOSFET 221 is turned off.

[0104] On the other hand, when the lower-bridge sensing MOSFET 2141 is off, it indicates that the lower-bridge MOSFET 222 is also off, indicating that the upper-bridge MOSFET 221 can now operate according to the upper-bridge PWM signal SH. In this case, the lower-bridge sensing circuit 314 changes the upper-bridge enable signal ENH to an enable level (a high level in this embodiment) to enable the upper-bridge PWM signal SH. Specifically, the inverted signal of the upper-bridge enable signal ENH is a low level representing 0, which is input to the set pin of the NAND latch circuit. The output signal of the NAND latch circuit is a signal that is in phase with the upper-bridge PWM signal SH. This signal passes through the level shifting circuit 315 and then through three inverters (forming a tapered buffer circuit), thereby aligning the upper-bridge drive signal UG with the upper-bridge PWM signal SH. That is, when the lower bridge sensing MOSFET 3141 is not conducting, indicating that the lower bridge MOSFET 222 is determined to be not conducting, the upper bridge enable signal ENH is high (enabled), and the upper bridge driver 311 switches the upper bridge MOSFET 221 according to the upper bridge PWM signal SH that is the same as the PWM signal P1.

[0105] Please continue reading Figure 4The high-bridge sensing circuit 312 includes a high-bridge sensing MOSFET 3121, a current source 3122, and a high-bridge clamping MOSFET 3123. The high-bridge sensing MOSFET 3121 has the same conductivity type as the high-bridge MOSFET 221; the high-bridge clamping MOSFET 3123 has a complementary conductivity type to the high-bridge MOSFET. The high-bridge clamping MOSFET 3123 and the high-bridge sensing MOSFET 3121 are coupled in series to the bootstrap voltage BOOT of the high-bridge driver 311. The high-bridge sensing MOSFET 3121 and the high-bridge MOSFET 221 are, for example, N-type MOSFETs. The high-bridge clamping MOSFET 3123 is, for example, a P-type MOSFET. The gate and source of the high-bridge MOSFET 221 are respectively coupled to the gate of the high-bridge sensing MOSFET 3121 and the gate of the high-bridge clamping MOSFET 3123, so that the high-bridge sensing MOSFET 3121 and the high-bridge clamping MOSFET 3123 generate a low-bridge enable signal ENL at the drain of the high-bridge clamping MOSFET 3123 according to the gate-source voltage of the high-bridge MOSFET 221.

[0106] Please continue reading Figure 4 The current source 3122 of the upper bridge sensing circuit 312 is coupled between the lower bridge enable signal ENL and the ground potential GND, so that the lower bridge driver 313 can determine whether the upper bridge MOSFET 221 is off based on the lower bridge enable signal ENL. The lower bridge driver 313 includes an enable logic circuit 3131 for receiving the lower bridge enable signal ENL to enable the lower bridge driver 313 to switch the lower bridge MOSFET 222 based on the lower bridge PWM signal SL that is inversely proportional to the PWM signal P1.

[0107] For example, if Figure 4 As shown, when the upper bridge sensing MOSFET 3121 is turned on, it indicates that the upper bridge MOSFET 221 is turned on or nearly turned on, and also indicates that the lower bridge MOSFET 222 should not be turned on. In this case, the upper bridge sensing circuit 312 changes the lower bridge enable signal ENL to a disable level (high in this embodiment) to disable the lower bridge PWM signal SL, ensuring that the lower bridge MOSFET 222 is not turned on.

[0108] Specifically, the high potential lower bridge enable signal ENL is input to the enable logic circuit 3131. The enable logic circuit 3131 is, for example, Figure 4 Therefore, one input terminal of the enable logic circuit 3131 is, for example, a reset pin of the NAND latch circuit, which receives the lower bridge PWM signal SL; the other input terminal is, for example, a set pin of the NAND latch circuit, which receives the lower bridge enable signal ENL.

[0109] When the lower bridge PWM signal SL is a low level representing 0, the enable logic circuit 3131 outputs a high level representing 1. This high level then passes through three inverters to generate a low level lower bridge drive signal LG, and the lower bridge MOSFET 222 is turned off.

[0110] When the low-bridge PWM signal SL changes from a low level (representing 0) to a high level (representing 1), the logic level of the low-bridge enable signal ENL is a high level (representing 1). The enable logic circuit 3131 outputs a high level (representing 1), the low-bridge drive signal LG is a low level, and the low-bridge MOSFET 222 is also turned off. In other words, when the low-bridge enable signal ENL is high (disabled), regardless of the logic level of the low-bridge PWM signal SL, the low-bridge drive signal LG is a low level, and the low-bridge MOSFET 222 is turned off.

[0111] On the other hand, when the high-bridge sensing MOSFET 3121 is off, it indicates that the high-bridge MOSFET 221 is definitely off, which also means that the low-bridge MOSFET 222 can operate according to the low-bridge PWM signal SL. In this case, the high-bridge sensing circuit 312 changes the low-bridge enable signal ENL to an enable level (low in this embodiment) to enable the low-bridge PWM signal SL. Specifically, the low-level low-bridge enable signal ENL is input to the set pin of the NAND latch circuit. The output signal of the NAND latch circuit is a signal that is inversely proportional to the low-bridge PWM signal SL. This signal passes through three inverters, aligning the low-bridge drive signal LG with the low-bridge PWM signal SL. In other words, when the high-bridge sensing MOSFET 3121 is off, indicating that the high-bridge MOSFET 221 is off, the low-bridge enable signal ENL is low (enabled), and the low-bridge driver 313 switches the low-bridge MOSFET 222 according to the low-bridge PWM signal SL, which is inversely proportional to the PWM signal P1.

[0112] Figure 5 An embodiment of the driving circuit 41 according to the present invention is shown. Figure 5As shown, the drive circuit 41 includes an upper bridge driver 411, an upper bridge sensing circuit 412, a lower bridge driver 413, and a lower bridge sensing circuit 414. The upper bridge sensing circuit 412, for example, includes an upper bridge sensing MOSFET 4121, a current source 4122, and an upper bridge clamping MOSFET 4123; the lower bridge sensing circuit 414, for example, includes a lower bridge sensing MOSFET 4141 and a current source 4142. The upper bridge driver 411, for example, includes an enable logic circuit 4111 and a level shift circuit 415 coupled to each other, and four inverters. The lower bridge driver 413, for example, includes an enable logic circuit 4131 and four inverters. The PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH. The PWM signal P1 is generated by the inverter to generate the lower bridge PWM signal SL, indicating that the PWM signal P1 is in phase with the lower bridge PWM signal SL.

[0113] This embodiment and Figure 4 The difference between the embodiment shown is that, in this embodiment, the upper bridge sensing MOSFET 4121 has a conductivity type complementary to that of the upper bridge MOSFET 221. The upper bridge sensing MOSFET 4121 is, for example, a P-type MOSFET. The upper bridge MOSFET 221 is, for example, an N-type MOSFET. Therefore, the lower bridge enable signal ENL of this embodiment is Figure 4 The lower bridge enable signal ENL of the embodiment shown in FIG. is inverted to each other. In this embodiment, the lower bridge enable signal ENL is generated after passing through the inverter. Figure 4 The lower bridge enable signal ENL is the same as the signal of the embodiment shown in FIG. Figure 4 The same embodiment shown, see Figure 4 Description.

[0114] Figure 6 An embodiment of the driving circuit 51 according to the present invention is shown. Figure 6 As shown, the driving circuit 51 includes an upper bridge driver 511, an upper bridge sensing circuit 512, a lower bridge driver 513, and a lower bridge sensing circuit 514. The upper bridge sensing circuit 512, for example, includes an upper bridge comparator 5121 and a level shift circuit 516; the lower bridge sensing circuit, for example, includes a lower bridge comparator 514. The upper bridge driver 511, for example, includes an enable logic circuit 5111 and a level shift circuit 515 coupled to each other, and three inverters. The lower bridge driver 513, for example, includes an enable logic circuit 5131 and three inverters. The PWM signal P1 is the upper bridge PWM signal SH, indicating that the PWM signal P1 is in phase with the upper bridge PWM signal SH. The PWM signal P1 is generated by the inverter to generate the lower bridge PWM signal SL, wherein the PWM signal P1 is in phase with the lower bridge PWM signal SL.

[0115] like Figure 6 As shown, the low-bridge comparator 514 is used to compare the gate-source voltage of the low-bridge MOSFET 222 with the low-bridge reference voltage Vref2 to generate the high-bridge enable signal ENH. In a preferred embodiment, the low-bridge reference voltage Vref2 is lower than or equal to the turn-on threshold voltage of the low-bridge MOSFET 222. As a result, the low-bridge comparator 514 generates the high-bridge enable signal ENH at the output terminal of the low-bridge comparator 514 based on the gate-source voltage of the low-bridge MOSFET 222.

[0116] Please continue reading Figure 6 The enable logic circuit 5111 of the upper bridge driver 511 is configured to receive the upper bridge enable signal ENH to enable the upper bridge driver 511 to switch the upper bridge MOSFET 221 according to the PWM signal P1 .

[0117] For example, if Figure 6 As shown, when the lower bridge MOSFET 222 is turned on or nearly turned on, it means that the upper bridge MOSFET 221 should not be turned on. In this case, the lower bridge comparator 514 changes the upper bridge enable signal ENH to a disable level (high voltage in this embodiment) according to the lower bridge drive signal LG being higher than the lower bridge reference voltage Vref2, thereby disabling the upper bridge PWM signal SH and ensuring that the upper bridge MOSFET 221 is not turned on.

[0118] Specifically, the high potential upper bridge enable signal ENH is input to the enable logic circuit 5111. The enable logic circuit 5111 is, for example, as shown in FIG. Figure 6 Therefore, one input terminal of the enable logic circuit 5111 is, for example, a reset pin of the NAND latch circuit, which receives the upper bridge PWM signal SH; the other input terminal is, for example, a set pin of the NAND latch circuit, which receives the upper bridge enable signal ENH.

[0119] When the high-bridge PWM signal SH is at a low level representing 0, the enable logic circuit 5111 outputs a high level representing 1. This high level then passes through the level shift circuit 515 and then through three inverters. The generated high-bridge drive signal UG is at a low level, and the high-bridge MOSFET 221 is turned off.

[0120] When the high-bridge PWM signal SH transitions from a low level (representing 0) to a high level (representing 1), the logic level of the high-bridge enable signal ENH is a high level (representing 1). The enable logic circuit 5111 outputs a high level (representing 1), the high-bridge drive signal UG is a low level, and the high-bridge MOSFET 221 is also turned off. In other words, when the high-bridge enable signal ENH is high (disabled), regardless of the logic level of the high-bridge PWM signal SH, the high-bridge drive signal UG is a low level, and the high-bridge MOSFET 221 is turned off.

[0121] On the other hand, when the lower-bridge MOSFET 222 is not conducting and its gate-source voltage is lower than the lower-bridge reference voltage Vref2, the upper-bridge MOSFET 221 is capable of operating according to the upper-bridge PWM signal SH. In this case, the lower-bridge comparator 514 changes the upper-bridge enable signal ENH to an enable level (low in this embodiment) to enable the upper-bridge PWM signal SH. Specifically, the low-level upper-bridge enable signal ENH is input to the set pin of the NAND latch circuit in the enable logic circuit 5111. The output signal of the NAND latch circuit is a signal inversely proportional to the upper-bridge PWM signal SH. This signal passes through the level shift circuit 515 and then three inverters, aligning the upper-bridge drive signal UG with the upper-bridge PWM signal SH. That is, when the lower bridge comparator 514 changes the upper bridge enable signal ENH to a low level representing 0, indicating that the lower bridge MOSFET 222 is determined to be non-conductive, the upper bridge enable signal ENH is at a low level (enabled), and the upper bridge driver 511 switches the upper bridge MOSFET 221 according to the upper bridge PWM signal SH that is the same as the PWM signal P1.

[0122] Please continue reading Figure 6 The high-bridge comparator 5121 and the level shift circuit 516 of the high-bridge sensing circuit 512 use the gate-source voltage of the high-bridge MOSFET 221 and the high-bridge reference voltage Vref1 to enable the low-bridge driver 513 to determine whether the high-bridge MOSFET 221 is turned off based on the low-bridge enable signal ENL. In a preferred embodiment, the high-bridge reference voltage Vref1 is lower than or equal to the turn-on threshold voltage of the high-bridge MOSFET 221. The low-bridge driver 513 includes an enable logic circuit 5131 for enabling the low-bridge driver 513 to switch the low-bridge MOSFET 222 based on the low-bridge PWM signal SL that is inversely proportional to the PWM signal P1 based on the low-bridge enable signal ENL.

[0123] For example, if Figure 6 As shown, when the high-bridge MOSFET 221 is turned on or nearly on, it also indicates that the low-bridge MOSFET 222 should not be turned on. In this case, the high-bridge comparator 5121 changes the low-bridge enable signal ENL to a disable level (high in this embodiment) based on the high-bridge drive signal UG being higher than the high-bridge reference voltage Vref1, thereby disabling the low-bridge PWM signal SL and ensuring that the low-bridge MOSFET 222 is not turned on. Specifically, the high-level low-bridge enable signal ENL is input to the enable logic circuit 3131. The level shift circuit 516 shifts the level of the output signal of the high-bridge comparator 5121 downward and inputs it to the enable logic circuit 5131. This allows the enable logic circuit 5131 to determine whether to enable the low-bridge driver 513 to operate the low-bridge MOSFET 222 according to the PWM signal P1 based on the low-bridge enable signal ENL.

[0124] The enabling logic circuit 5131 is, for example, Figure 6 Therefore, one input terminal of the enable logic circuit 5131, such as the reset pin of the NAND latch circuit, receives the low-bridge PWM signal SL; the other input terminal, such as the set pin of the NAND latch circuit, receives the low-bridge enable signal ENL after the level is shifted down.

[0125] When the lower bridge PWM signal SL is a low level representing 0, the enable logic circuit 5131 outputs a high level representing 1. This high level then passes through three inverters to generate a low level lower bridge drive signal LG, and the lower bridge MOSFET 222 is not turned on.

[0126] When the low-bridge PWM signal SL changes from a low level (representing 0) to a high level (representing 1), the logic level of the low-bridge enable signal ENL is a high level (representing 1). The enable logic circuit 5131 outputs a high level (representing 1), the low-bridge drive signal LG is a low level, and the low-bridge MOSFET 222 is also turned off. In other words, when the low-bridge enable signal ENL is high (disabled), regardless of the logic level of the low-bridge PWM signal SL, the low-bridge drive signal LG is a low level, and the low-bridge MOSFET 222 is turned off.

[0127] On the other hand, when high-bridge MOSFET 221 is off and its gate-source voltage is lower than high-bridge reference voltage Vref1, low-bridge MOSFET 222 can operate according to low-bridge PWM signal SL. In this case, high-bridge comparator 5121 changes low-bridge enable signal ENL to an enable level (low in this embodiment) based on the fact that high-bridge drive signal UG is lower than high-bridge reference voltage Vref1, thereby enabling low-bridge PWM signal SL. Specifically, the output signal of high-bridge comparator 5121 is shifted downward by level shift circuit 516 and then input to the set pin of the NAND latch circuit of enable logic circuit 5131. The output signal of the NAND latch circuit is then in phase with low-bridge PWM signal SL. This signal, after passing through three inverters, synchronizes low-bridge drive signal LG with low-bridge PWM signal SL. That is, when the upper bridge comparator 5121 changes the lower bridge enable signal ENL to a low voltage (enabled) representing 0, indicating that the upper bridge MOSFET 221 is determined to be non-conductive, the lower bridge driver 513 switches the lower bridge MOSFET 222 according to the lower bridge PWM signal SL which is inverse to the PWM signal P1.

[0128] The present invention has been described above with respect to the preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention and is not intended to limit the scope of the rights of the present invention. The various embodiments described are not limited to individual applications, but can also be applied in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, performing voltage-current conversion, current-voltage conversion, and / or ratio conversion on the signal, and then processing or calculating the converted signal to generate an output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed here one by one. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A switching converter circuit for switching a first terminal of an inductor between a first voltage and a second voltage according to a pulse width modulation signal to convert an input voltage into an output voltage, the switching converter circuit comprising: an upper bridge metal oxide semiconductor field effect transistor coupled between the first voltage and the first end of the inductor; a low-bridge metal-oxide-semiconductor field-effect transistor coupled between the second voltage and the first end of the inductor; as well as A driving circuit comprising: an upper bridge driver for generating an upper bridge driving signal according to the pulse width modulation signal to drive the upper bridge metal oxide semiconductor field effect transistor; a lower bridge driver for generating a lower bridge driving signal according to the pulse width modulation signal to drive the lower bridge metal oxide semiconductor field effect transistor; an upper bridge sensing circuit configured to sense a gate-source voltage of the upper bridge MOSFET and generate a lower bridge enable signal based on the gate-source voltage of the upper bridge MOSFET to indicate a non-conducting state of the upper bridge MOSFET, wherein the lower bridge enable signal enables the lower bridge driver to switch the lower bridge MOSFET according to the pulse width modulation signal; and A lower bridge sensing circuit is configured to sense a gate-source voltage of the lower bridge metal oxide semiconductor field effect transistor and generate an upper bridge enable signal according to the gate-source voltage of the lower bridge metal oxide semiconductor field effect transistor to indicate a non-conducting state of the lower bridge metal oxide semiconductor field effect transistor, wherein the upper bridge enable signal enables the upper bridge driver to switch the upper bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal. The lower bridge sensing circuit includes a lower bridge sensing metal oxide semiconductor field effect transistor having the same conductivity type as the lower bridge metal oxide semiconductor field effect transistor, and the gate of the lower bridge sensing metal oxide semiconductor field effect transistor is coupled to the gate of the lower bridge metal oxide semiconductor field effect transistor, and the source of the lower bridge sensing metal oxide semiconductor field effect transistor is coupled to the source of the lower bridge metal oxide semiconductor field effect transistor, so that the lower bridge sensing metal oxide semiconductor field effect transistor generates the upper bridge enable signal at the drain of the lower bridge sensing metal oxide semiconductor field effect transistor according to the gate-source voltage of the lower bridge metal oxide semiconductor field effect transistor.

2. The switching converter circuit of claim 1 , wherein: The lower bridge sensing circuit also includes a current source coupled between the upper bridge enable signal and a bootstrap voltage of the upper bridge driver to shift the multiple logic levels of the upper bridge enable signal to a starting voltage range, wherein the upper bridge driver includes an enable logic circuit for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal.

3. The switching converter circuit of claim 1 , wherein: The lower bridge sensing circuit further includes a current source coupled between the upper bridge enable signal and a DC voltage, wherein the DC voltage is used to generate a bootstrap voltage for the upper bridge driver. The upper bridge driver includes an enable logic circuit and a level shift circuit coupled to each other to receive the upper bridge enable signal and enable the upper bridge driver to switch the upper bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal.

4. The switching converter circuit of claim 1 , wherein: An absolute value of a turn-on threshold voltage of an upper-bridge sensing metal-oxide-semiconductor field-effect transistor of the upper-bridge sensing circuit is lower than or equal to an absolute value of a turn-on threshold voltage of the upper-bridge metal-oxide-semiconductor field-effect transistor, and an absolute value of a turn-on threshold voltage of the lower-bridge sensing metal-oxide-semiconductor field-effect transistor is lower than or equal to an absolute value of a turn-on threshold voltage of the lower-bridge metal-oxide-semiconductor field-effect transistor.

5. The switching converter circuit of claim 1 , wherein: The upper bridge sensing circuit includes an upper bridge sensing metal oxide semiconductor field effect transistor having a conductivity type complementary to that of the upper bridge metal oxide semiconductor field effect transistor. The gate of the upper bridge sensing metal oxide semiconductor field effect transistor is coupled to the source of the upper bridge metal oxide semiconductor field effect transistor, and the source of the upper bridge sensing metal oxide semiconductor field effect transistor is coupled to the gate of the upper bridge metal oxide semiconductor field effect transistor, so that the upper bridge sensing metal oxide semiconductor field effect transistor generates the lower bridge enable signal at the drain of the upper bridge sensing metal oxide semiconductor field effect transistor according to the gate-source voltage of the upper bridge metal oxide semiconductor field effect transistor.

6. The switching converter circuit of claim 1 , wherein: The upper bridge sensing circuit includes: an upper bridge sensing MOSFET having the same conductivity type as the upper bridge MOSFET; and a high-bridge clamping MOSFET having a conductivity type complementary to that of the high-bridge MOSFET, wherein the high-bridge clamping MOSFET and the high-bridge sensing MOSFET are coupled in series to a bootstrap voltage of the high-bridge driver; The gate and source of the high-bridge MOSFET are respectively coupled to the gate of the high-bridge sensing MOSFET and the gate of the high-bridge clamping MOSFET, so that the high-bridge clamping MOSFET generates the low-bridge enable signal at the drain of the high-bridge clamping MOSFET according to the gate-source voltage of the high-bridge MOSFET.

7. The switching converter circuit of claim 1 , wherein: The upper bridge sensing circuit includes: an upper bridge sensing MOSFET having a conductivity type complementary to that of the upper bridge MOSFET; and a high-bridge clamping MOSFET having a conductivity type complementary to that of the high-bridge MOSFET, wherein the high-bridge clamping MOSFET and the high-bridge sensing MOSFET are coupled in series to a bootstrap voltage of the high-bridge driver; The gate and source of the high-bridge MOSFET are respectively coupled to the gate of the high-bridge sensing MOSFET and the gate of the high-bridge clamping MOSFET, so that the high-bridge clamping MOSFET generates the low-bridge enable signal at the drain of the high-bridge clamping MOSFET according to the gate-source voltage of the high-bridge MOSFET.

8. The switching converter circuit of claim 1 , wherein: The upper bridge sensing circuit includes: an upper bridge comparator for comparing the gate-source voltage of the upper bridge metal oxide semiconductor field effect transistor with an upper bridge reference voltage, and generating the lower bridge enable signal according to the voltage of the first end of the inductor; and a level shift circuit for shifting the level of the lower bridge enable signal downward; The lower bridge driver includes an enabling logic circuit for receiving the lower bridge enabling signal with a level shifted downward, so as to enable the lower bridge driver to switch the lower bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal.

9. The switching converter circuit of claim 1 , wherein: The upper bridge MOSFET has the same conductivity type as that of the lower bridge MOSFET.

10. A driving circuit for a switching converter circuit, comprising: An upper bridge driver, for generating an upper bridge driving signal according to a pulse width modulation signal, to drive an upper bridge metal oxide semiconductor field effect transistor; a lower bridge driver for generating a lower bridge driving signal according to the pulse width modulation signal to drive a lower bridge metal oxide semiconductor field effect transistor; an upper bridge sensing circuit configured to sense a gate-source voltage of the upper bridge MOSFET and generate a lower bridge enable signal based on the gate-source voltage of the upper bridge MOSFET to indicate a non-conducting state of the upper bridge MOSFET, wherein the lower bridge enable signal enables the lower bridge driver to switch the lower bridge MOSFET according to the pulse width modulation signal; and A lower bridge sensing circuit is configured to sense a gate-source voltage of the lower bridge metal oxide semiconductor field effect transistor and generate an upper bridge enable signal according to the gate-source voltage of the lower bridge metal oxide semiconductor field effect transistor to indicate a non-conducting state of the lower bridge metal oxide semiconductor field effect transistor, wherein the upper bridge enable signal enables the upper bridge driver to switch the upper bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal. The lower bridge sensing circuit includes a lower bridge sensing metal oxide semiconductor field effect transistor having the same conductivity type as the lower bridge metal oxide semiconductor field effect transistor, and the gate of the lower bridge sensing metal oxide semiconductor field effect transistor is coupled to the gate of the lower bridge metal oxide semiconductor field effect transistor, and the source of the lower bridge sensing metal oxide semiconductor field effect transistor is coupled to the source of the lower bridge metal oxide semiconductor field effect transistor, so that the lower bridge sensing metal oxide semiconductor field effect transistor generates the upper bridge enable signal at the drain of the lower bridge sensing metal oxide semiconductor field effect transistor according to the gate-source voltage of the lower bridge metal oxide semiconductor field effect transistor.

11. The driving circuit according to claim 10, wherein: The lower bridge sensing circuit also includes a current source coupled between the upper bridge enable signal and a bootstrap voltage of the upper bridge driver to shift the multiple logic levels of the upper bridge enable signal to a starting voltage range, wherein the upper bridge driver includes an enable logic circuit for receiving the upper bridge enable signal to enable the upper bridge driver to switch the upper bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal.

12. The driving circuit according to claim 10, wherein: The lower bridge sensing circuit further includes a current source coupled between the upper bridge enable signal and a DC voltage, wherein the DC voltage is used to generate a bootstrap voltage for the upper bridge driver. The upper bridge driver includes an enable logic circuit and a level shift circuit coupled to each other to receive the upper bridge enable signal and enable the upper bridge driver to switch the upper bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal.

13. The driving circuit according to claim 10, wherein: An absolute value of a turn-on threshold voltage of an upper-bridge sensing metal-oxide-semiconductor field-effect transistor of the upper-bridge sensing circuit is lower than or equal to an absolute value of a turn-on threshold voltage of the upper-bridge metal-oxide-semiconductor field-effect transistor, and an absolute value of a turn-on threshold voltage of the lower-bridge sensing metal-oxide-semiconductor field-effect transistor is lower than or equal to an absolute value of a turn-on threshold voltage of the lower-bridge metal-oxide-semiconductor field-effect transistor.

14. The driving circuit according to claim 10, wherein: The upper bridge sensing circuit includes an upper bridge sensing metal oxide semiconductor field effect transistor having a conductivity type complementary to that of the upper bridge metal oxide semiconductor field effect transistor. The gate of the upper bridge sensing metal oxide semiconductor field effect transistor is coupled to the source of the upper bridge metal oxide semiconductor field effect transistor, and the source of the upper bridge sensing metal oxide semiconductor field effect transistor is coupled to the gate of the upper bridge metal oxide semiconductor field effect transistor, so that the upper bridge sensing metal oxide semiconductor field effect transistor generates the lower bridge enable signal at the drain of the upper bridge sensing metal oxide semiconductor field effect transistor according to the gate-source voltage of the upper bridge metal oxide semiconductor field effect transistor.

15. The driving circuit according to claim 10, wherein: The upper bridge sensing circuit includes: an upper bridge sensing MOSFET having the same conductivity type as the upper bridge MOSFET; and a high-bridge clamping MOSFET having a conductivity type complementary to that of the high-bridge MOSFET, wherein the high-bridge clamping MOSFET and the high-bridge sensing MOSFET are coupled in series to a bootstrap voltage of the high-bridge driver; The gate and source of the high-bridge MOSFET are respectively coupled to the gate of the high-bridge sensing MOSFET and the gate of the high-bridge clamping MOSFET, so that the high-bridge clamping MOSFET generates the low-bridge enable signal at the drain of the high-bridge clamping MOSFET according to the gate-source voltage of the high-bridge MOSFET.

16. The driving circuit according to claim 10, wherein: The upper bridge sensing circuit includes: an upper bridge sensing MOSFET having a conductivity type complementary to that of the upper bridge MOSFET; and a high-bridge clamping MOSFET having a conductivity type complementary to that of the high-bridge MOSFET, wherein the high-bridge clamping MOSFET and the high-bridge sensing MOSFET are coupled in series to a bootstrap voltage of the high-bridge driver; The gate and source of the high-bridge MOSFET are respectively coupled to the gate of the high-bridge sensing MOSFET and the gate of the high-bridge clamping MOSFET, so that the high-bridge clamping MOSFET generates the low-bridge enable signal at the drain of the high-bridge clamping MOSFET according to the gate-source voltage of the high-bridge MOSFET.

17. The driving circuit according to claim 10, wherein: The upper bridge sensing circuit includes: an upper bridge comparator for comparing the gate-source voltage of the upper bridge metal oxide semiconductor field effect transistor with an upper bridge reference voltage, and generating the lower bridge enable signal according to the voltage of a first terminal of an inductor; and a level shift circuit for shifting the level of the lower bridge enable signal downward; The lower bridge driver includes an enabling logic circuit for receiving the lower bridge enabling signal with a level shifted downward, so as to enable the lower bridge driver to switch the lower bridge metal oxide semiconductor field effect transistor according to the pulse width modulation signal.

18. The driving circuit according to claim 10, wherein: The upper bridge MOSFET driven by the driving circuit has the same conductivity type as the lower bridge MOSFET driven by the driving circuit.

Images