Multi-path parallel clock generation system, clock generation circuit and clock generation method

Abstract

The application relates to the field of switching power supplies, and discloses a multi-path parallel clock generation system, a clock generation circuit and a clock generation method, wherein the clock generation circuit is composed of a parallel number detection circuit, a reference voltage selection circuit and an interleaved clock generation circuit; after the parallel number detection circuit detects the parallel number, the clock generation circuit automatically generates interleaved phases, realizes phase interleaving through series connection control from a master circuit to a slave circuit, realizes parallel high frequency, and reduces output ripple and input peak current.

Description

Technical Field

[0001] This invention relates to the field of switching power supplies, and more specifically to a multi-channel parallel clock generation system, a clock generation circuit, and a clock generation method. Background Technology

[0002] With the development of technology, electronic devices often require high-capacity DC power supplies. When high-capacity power is required, using a single power supply presents significant challenges in terms of handling the switching stress on the switching transistors and rectifier diodes, as well as heat dissipation, making design and implementation extremely difficult. Compared to traditional single-power supply systems, parallel power supplies offer many advantages, such as achieving high capacity and efficiency, ensuring high reliability, and being configurable as a redundant system as needed. They also enable modularity, expandable capacity, and reduced costs. By using parallel configurations, high-power power supply systems can be built using small-power modules. Since each module only shares a small portion of the total power capacity, implementation is relatively easy, making parallel power supply systems convenient for achieving high capacity. Furthermore, the interleaved operation of multiple parallel power supplies can significantly reduce output current and voltage ripple.

[0003] like Figure 1 The diagram shown is a control block diagram of a traditional interleaved parallel power supply system. Interleaved parallel systems employ centralized control, using a centralized control unit to generate a series of power supplies with the same frequency but a phase difference of [value missing]. The drive signals are used to drive the corresponding converters. This scheme is very effective for cases where a fixed number of converters are connected in parallel, and it is simple to control and easy to implement. However, if the number of converters connected in parallel is not fixed, this scheme is not feasible, and such a situation is common in practical applications. A major advantage of parallel connection is that the number of converters connected in parallel can be adjusted according to the actual load. In addition, even in cases where a fixed number of converters are connected in parallel, if one or more converters fail and need to be taken out of operation, the above method will fail, and the system will not be able to continue to maintain interleaved operation. Furthermore, if the control unit malfunctions, the entire system will completely collapse. Therefore, in some applications requiring high reliability, the traditional scheme will be greatly limited. The difficulty of interleaved parallel connection lies mainly in how to generate corresponding control signals according to the changing number of converters and properly distribute them to the corresponding converters. Summary of the Invention

[0004] In view of the problems existing in the above interleaved parallel control scheme.

[0005] The technical problem solved by this invention is to provide a multi-channel parallel clock generation system, clock generation circuit and clock generation method to realize the control of multi-channel converters in parallel, thereby realizing high frequency parallel connection and reducing output ripple and input peak current.

[0006] To solve the above-mentioned technical problems, the present invention provides a multi-channel parallel clock generation system for use in a power supply system consisting of N converters connected in parallel, where N is an integer greater than or equal to 2. The multi-channel parallel clock generation system includes: a first clock generation circuit and a second clock generation circuit connected in parallel.

[0007] The first clock generation circuit is used to detect the parallel connection count signal, which characterizes the number of converters, and outputs a clock signal and a clock control signal based on the parallel connection count detection signal. The phase of the clock control signal is delayed compared to the clock signal.

[0008] The second clock generation circuit receives the clock control signal and generates a phase delay compared to the clock control signal. Another clock control signal.

[0009] Preferably, the first clock generation circuit includes a parallel number detection circuit, a reference voltage selection circuit, and an interleaved clock generation circuit;

[0010] The parallel number detection circuit is used to detect the parallel number detection signal and output a first indication control signal and a second indication control signal according to the parallel number detection signal;

[0011] The reference voltage selection circuit generates a reference voltage based on the first indication control signal and the second indication control signal;

[0012] The interleaved clock generation circuit generates a clock control signal based on the reference voltage.

[0013] Preferably, the parallel number detection circuit includes: comparator COMP1, comparator COMP2, buffer, power supply, pull-down resistor, constant current source, and switching transistor; the positive input terminals of comparator COMP1 and comparator COMP2 are connected to the parallel number detection signal, the negative input terminal of comparator COMP1 is connected to a first reference voltage signal, and the negative input terminal of comparator COMP2 is connected to a second reference voltage signal, wherein the first reference voltage signal is less than the second reference voltage signal; the power supply is connected to the positive input terminal of comparator COMP1 through a constant current source; the drain of the switching transistor is connected to the positive input terminal of comparator COMP1, the source of the switching transistor is connected to ground through a pull-down resistor, and the gate of the switching transistor is connected to the output terminal of the buffer; the output terminal of comparator COMP1 outputs a first indication control signal, and the output terminal of comparator COMP2 outputs a second indication control signal.

[0014] Preferably, the interleaved clock generation circuit includes: comparator COMP3, comparator COMP4, power supply, capacitor, and switch; wherein, the power supply, capacitor, and switch constitute a capacitor charging and discharging module, which is used to generate a ramp voltage signal; the first positive input terminal of comparator COMP3 is connected to a first input reference voltage, the second positive input terminal of comparator COMP3 is connected to a second input reference voltage, the negative input terminal of comparator COMP3 is connected to the ramp voltage signal, and the output terminal of comparator COMP3 outputs a clock signal; the first positive input terminal of comparator COMP4 is connected to the output terminal of a reference voltage selection circuit, used to receive the reference voltage output by the reference voltage selection circuit, the second positive input terminal of comparator COMP4 is connected to the second input reference voltage, the negative input terminal of comparator COMP4 is connected to the ramp voltage signal, and comparator COMP4 outputs a clock output signal, wherein the first input reference voltage is greater than the second input reference voltage.

[0015] The present invention also provides a clock generation circuit for generating interleaved phases in a power supply system consisting of N converters connected in parallel, where N is an integer greater than or equal to 2. The clock generation circuit includes:

[0016] The parallel number detection circuit is used to detect the parallel number detection signal that represents the number of converters, and output a first indication control signal and a second indication control signal according to the parallel number detection signal;

[0017] The reference voltage selection circuit generates a reference voltage based on the first indication control signal and the second indication control signal.

[0018] An interleaved clock generation circuit generates clock signals and clock control signals of different phases based on a reference voltage, wherein the phase of the clock control signal is delayed relative to the phase of the clock signal.

[0019] Preferably, the phase of the clock control signal is delayed relative to the clock signal.

[0020] The present invention further provides a clock generation method for a power supply system consisting of N converters connected in parallel, where N is an integer greater than or equal to 2. The clock generation method includes:

[0021] Obtain the detection signal representing the number of parallel converters;

[0022] Based on the parallel connection count detection signal, a clock signal and a clock control signal are output, wherein the phase of the clock control signal is delayed compared to the clock signal.

[0023] Receives a clock control signal and outputs a phase that is delayed compared to the clock control signal. Another clock control signal.

[0024] The present invention has the following beneficial effects:

[0025] (1) The circuit implementation of the multi-channel parallel clock generation system / clock generation circuit is simple and easy to control; the phase difference of the interleaved clock is adaptively adjusted according to the actual number of parallel circuits. When the first clock generation circuit is the master circuit and the second clock generation circuit has multiple circuits and is used as a slave circuit, removing any one of the slave circuits will not affect the operation of the master circuit and other slave circuits.

[0026] (2) After the number of converters in parallel in the power supply system is detected by the parallel number detection circuit, the clock generation circuit adaptively adjusts the phase difference of the interleaved clock according to the actual number of parallel connections, so as to realize the series control from the first clock generation circuit to the second clock generation circuit, as well as to realize the parallel high frequency and reduce the output ripple and input peak current; in addition, when multiple converters are connected in parallel, current sharing can be guaranteed by simply connecting the detection pins of each clock generation circuit together. Attached Figure Description

[0027] Figure 1 Traditional interleaved parallel control block diagram;

[0028] Figure 2 Block diagram of the multi-channel parallel clock generation system of the present invention;

[0029] Figure 3 Circuit diagram of the parallel number detection circuit of the present invention;

[0030] Figure 4 Circuit diagram of the reference voltage selection circuit of this invention;

[0031] Figure 5 Circuit diagram of the main circuit interleaved clock generation circuit of this invention;

[0032] Figure 6 The circuit diagram of the first circuit for generating an interleaved clock according to the present invention;

[0033] Figure 7 A schematic diagram of the three interleaved parallel clock phases in this invention. Detailed Implementation

[0034] Please refer to Figure 2 , Figure 2This is a block diagram of the multi-channel parallel clock generation system of the present invention. The multi-channel parallel clock generation system is used in a power supply system consisting of multiple converters connected in parallel. In this embodiment, a three-channel parallel clock generation system (hereinafter referred to as the clock system) is taken as an example. The clock system includes: a first clock generation circuit 1, a second clock generation circuit 2, and a third clock generation circuit 3. The first clock generation circuit 1 is the master clock generation circuit, and the second clock generation circuit 2 and the third clock generation circuit 3 are slave clock generation circuits, respectively. Hereinafter, the first clock generation circuit 1 is defined as the master circuit 1, the second clock generation circuit 2 is defined as the first slave circuit 2, and the third clock generation circuit 3 is defined as the second slave circuit 3. Figure 2 In the diagram, M_S is the master-slave circuit control signal, ISHARE is the parallel circuit number detection signal, CLKI_M is the clock signal output by the master circuit 1, CLKO is the clock control signal output by the master circuit 1, CLKO1 is the clock control signal output by the first slave circuit 2, CLKO2 is the clock control signal output by the second slave circuit 3, CLKI_1 is the clock input signal to the first slave circuit 2, CLKI_2 is the clock input signal to the second slave circuit 3, and VCC is the power supply.

[0035] In clock system applications, the parallel connection count detection signals ISHARE of master circuit 1, first slave circuit 2, and second slave circuit 3 are connected. The parallel connection count detection circuit inside the clock system detects the number of parallel connections. For master circuit 1, it determines the number of parallel converters in the power supply system based on the parallel connection count detection signal ISHARE, and generates a clock control signal CLKO based on the number of parallel converters. The phase difference between the clock control signal CLKO and the master clock signal CLKI_M output by master circuit 1 is [missing information]. The clock control signal CLKO output by the master circuit 1 is used as the clock input signal CLKI_1 input to the first slave circuit 2 (that is, the clock control signal CLKO output by the master circuit 1 and the clock input signal CLKI_1 are the same); the clock control signal CLKO1 output by the first slave circuit 2 is used as the clock input signal CLKI_2 input to the second slave circuit 3 (that is, the clock control signal CLKO1 output by the first slave circuit 2 and the clock input signal CLKI_2 are the same); and so on.

[0036] The number of parallel channels and the corresponding phase differences are shown in Table 1.

[0037] Table 1:

[0038]

[0039] The clock system of the present invention generates different clocks through phase delay and controls multiple converters to work in interleaved parallel, achieving effects such as a 180-degree phase difference for two paths, a 120-degree phase difference for three paths, and a 90-degree phase difference for four paths.

[0040] The circuit compositions of the main circuit 1, the first slave circuit 2, and the second slave circuit 3 in the clock system are basically the same, and each is composed of a parallel number detection circuit, a reference voltage selection circuit, and an interleaved clock generation circuit. Taking the main circuit 1 as an example below, the parallel number detection circuit, the reference voltage selection circuit, and the interleaved clock generation circuit will be specifically described.

[0041] Please refer to Figure 3 , Figure 3 is the circuit diagram of the parallel number detection circuit in the main circuit 1. The parallel number detection circuit includes a comparator COMP1, a comparator COMP2, a buffer buffer, a power supply VCC, a pull-down resistor R0, a constant current source I0, and a switching transistor NM4. The positive input terminals of the comparator COMP1 and the comparator COMP2 are respectively connected to the detection pin of the main circuit 1, and the parallel number detection signal ISHARE is received through the detection pin. The negative input terminal of the comparator COMP1 is connected to the first reference voltage signal VR1, and the negative input terminal of the comparator COMP2 is connected to the second reference voltage signal VR2, where VR1 < VR2; the power supply VCC is connected to the positive input terminal of the comparator COMP1 through the constant current source I0; the drain of the switching transistor NM4 is connected to the positive input terminal of the comparator COMP1, the source of the switching transistor NM4 is connected to the ground through the pull-down resistor R0, the gate of the switching transistor NM4 is connected to the output terminal of the buffer buffer, and the input terminal of the buffer buffer is connected to the master-slave circuit control signal M_S. The output terminal of the comparator COMP1 outputs the first indication control signal PA1, and the output terminal of the comparator COMP2 outputs the second indication control signal PA2. In this embodiment, for the main circuit 1, the master-slave circuit control signal M_S is at a high level; for the first slave circuit 2 and the second slave circuit 3, the master-slave circuit control signal M_S is at a low level.

[0042] The working principle of the parallel number detection circuit is as follows: After the clock system is powered on and starts up, a fixed current I0 passes through the detection pin of the main circuit 1 and the pull-down resistor R0 to the ground. At this time, the main circuit 1 can detect the number of parallel converters according to the voltage V of the detection pin, that is, the parallel number detection signal ISHARE is the voltage V of the detection pin ISHARE . ISHARE .

[0043] When there is only one path of converters, the voltage V of the detection pin ISHARE is as shown in Equation (1);

[0044] V ISHARE = I0 × R0 (1)

[0045] When N converters are connected in parallel, the voltage V of the detection pin ISHARE is as shown in Equation (2);

[0046] V ISHARE = I0 × R0 × N (2)

[0047] Compare the voltages at the non-inverting inputs of comparators COMP1 and COMP2 with the voltage V of the detection pin ISHARE They are the same. When two converters are operating in parallel, V ISHARE < VR1 < VR2, the first indication control signal PA1 output by comparator COMP1 is 0, and the second indication control signal PA2 output by comparator COMP2 is 0; when three converters are operating in parallel, VR1 < V ISHARE < VR2, the first indication control signal PA1 output by comparator COMP1 is 1, and the second indication control signal PA2 output by comparator COMP2 is 0; when four or more converters are operating in parallel, V ISHARE > VR2 > VR1, the first indication control signal PA1 output by comparator COMP1 is 1, and the second indication control signal PA2 output by comparator COMP2 is 1.

[0048] The relationship between the number of parallel connections and the first and second indication control signals is shown in Table 2.

[0049] Table 2:

[0050] Number of parallel converters N PA1 PA2 N＝2 0 0 N＝3 1 0 N≥4 1 1

[0051] Among them, the pull-down resistor R0 is controlled by the master-slave circuit control signal M_S. The M_S of the main circuit 1 is externally connected to the high level VCC, and the switch tube NM4 is turned on, then the pull-down impedance of the main circuit 1 is the resistance value of the resistor R0. The M_S of the first slave circuit 2 and the second slave circuit 3 are externally connected to the low level GND, and the switch tube NM4 is turned off, then the pull-down of the first slave circuit 2 and the second slave circuit 3 is a high impedance. During the power-on startup stage of the clock system, ensure that the master-slave circuits can all work normally before detection. Detect the number of converters connected in parallel in the power supply system through the detection pin, latch and output the first indication control signal PA1 and the second indication control signal PA2. This detection is only performed once during power-on.

[0052] To avoid affecting the normal detection function of the parallel number detection circuit, a transmission gate isolation needs to be added between the detection pin of the main circuit 1 and comparators COMP1 and COMP2; in addition, before the first reference voltage signal VR1 and the second reference voltage signal VR2 are input, an RC filter needs to be added to ensure that the detection circuit has strong anti-interference ability.

[0053] The parallel number detection circuits in the first slave circuit 2 and the second slave circuit 3 are the same as the parallel number detection circuit in the main circuit 1, and will not be described in detail here.

[0054] Please refer to Figure 4 , Figure 4 The circuit diagram of the reference voltage selection circuit of the main circuit 1 is shown. The reference voltage selection circuit includes NOR gate X1, inverter X2, inverter X5, inverter X6, NAND gate X3, NAND gate X4, switch NM1, switch NM2 and switch NM3. Figure 4 In this system, VH1 is the first reference voltage, VH2 is the second reference voltage, and VH3 is the third reference voltage; PA1 is the first indication control signal, and PA2 is the second indication control signal.

[0055] When the first indication control signal PA1 is 0 and the second indication control signal PA2 is 0, the switching transistor NH1 is turned on, and the reference voltage output by the reference voltage selection circuit is VH = VH1; when the first indication control signal PA1 is 1 and the second indication control signal PA2 is 0, the switching transistor NH2 is turned on, and VH = VH2; when the first indication control signal PA1 is 1 and the second indication control signal PA2 is 1, the switching transistor NH3 is turned on, and VH = VH3.

[0056] The reference voltage selection circuits of the first slave circuit 2 and the second slave circuit 3 are the same as those of the reference voltage selection circuit of the main circuit 1, and will not be described in detail here.

[0057] Please refer to Figure 5 , Figure 5 The circuit diagram shows the interleaved clock generation circuit in main circuit 1. This circuit includes comparators COMP3 and COMP4, a power supply VCC, a capacitor C0, and a switch S1. The power supply VCC, capacitor C0, and switch S1 together form capacitor charging / discharging module A. VRAMP is the ramp voltage signal generated by capacitor charging / discharging module A. The capacitor charging current is defined as I1, and the capacitor discharging current is defined as I2.

[0058] Comparator COMP3's first positive input is connected to the first input reference voltage VHH, its second positive input is connected to the second input reference voltage VL, its negative input is connected to the ramp voltage signal VRAMP, and its output is the clock signal CLKI_M. Comparator COMP4's first positive input is connected to the output of the reference voltage selection circuit to receive the reference voltage VH from the circuit. Its second positive input is connected to the second input reference voltage VL, its negative input is connected to the ramp voltage signal VRAMP, and its output is the clock signal CLKO.

[0059] The capacitor charging / discharging module A is used to generate the ramp voltage signal VRAMP. The rise time of the ramp voltage signal VRAMP is related to the capacitor C0, the output voltage VH of the reference voltage selection circuit, the first input reference voltage VHH, and the charging current I1. For the main circuit 1, the capacitor charging / discharging module A and comparator COMP3 generate the main clock signal CLKI_M, and the capacitor charging / discharging module A and comparator COMP4 generate the clock control signal CLKO.

[0060] The rise time of the ramp voltage signal VRAMP is the high-level time T of the master clock signal CLKI_M. ON1 High-level time T ON1 Expressed using equation (3):

[0061]

[0062] The fall time of the ramp voltage signal VRAMP is the low-level time T of the master clock signal CLKI_M. OFF Low level time T OFF Expressed using equation (4):

[0063]

[0064] The high-level time T of the clock control signal CLKO ON2 Expressed using equation (5):

[0065]

[0066] The second input reference voltage VL should be as small as possible, close to 0V, then T ON1 Proportional to VHH, design The phase difference ΔPHASE corresponding to different numbers of parallel modules is shown in equation (6);

[0067]

[0068] Please refer to Figure 6 For the first slave circuit 2, it receives the clock control signal CLKO output from the master circuit 1, and generates the clock control signal CLKO1 for the first slave circuit 2 using the capacitor charging / discharging module A, comparator COMP4, and clock input signal CLKI_1. While ensuring the accuracy of the reference voltage, the second input reference voltage VL is set as small as possible, while VHH is set to a relatively large value. The low-level time T of CLKI generated by the master circuit 1 is... OFF The smaller the value, the better for the accuracy of the phase difference in multi-channel parallel connections.

[0069] The working principle of the interleaved clock generation circuit in the first slave circuit 2 is similar to that of the main circuit 1, and will not be described again.

[0070] Figure 7 The diagram shows the phase of the three interleaved parallel clocks in this embodiment. CLKI_M is the master clock signal output by the master circuit 1, CLKI_1 is the clock input signal input to the first slave circuit 2, and CLKI_2 is the clock input signal input to the second slave circuit 3.

[0071] Three parallel paths, with interleaved phases The clock phases of the first slave circuit 2 and the master circuit 1 are interleaved by 120°, and the clock phases of the second slave circuit 3 and the first slave circuit 2 are interleaved by 120°.

Claims

1. A multi-channel parallel clock generation system for use in a power supply system consisting of N converters connected in parallel, where N is an integer greater than or equal to 2, characterized in that, The multi-channel parallel clock generation system includes: a first clock generation circuit and a second clock generation circuit connected in parallel; The first clock generation circuit includes a parallel number detection circuit, a reference voltage selection circuit, and an interleaved clock generation circuit; the parallel number detection circuit is used to detect the parallel number detection signal and output a first indication control signal and a second indication control signal according to the parallel number detection signal; the reference voltage selection circuit generates a reference voltage according to the first indication control signal and the second indication control signal; the interleaved clock generation circuit generates a clock control signal according to the reference voltage; The first clock generation circuit is used to detect a parallel connection count detection signal characterizing the number of converters, and outputs a clock signal and a clock control signal based on the parallel connection count detection signal, wherein the phase of the clock control signal is delayed compared to the clock signal. The second clock generation circuit receives the clock control signal and generates a phase delay compared to the clock control signal. Another clock control signal.

2. The multi-channel parallel clock generation system according to claim 1, characterized in that, The parallel number detection circuit includes: comparator COMP1, comparator COMP2, buffer, power supply, pull-down resistor, constant current source, and switching transistor; the positive input terminals of comparator COMP1 and comparator COMP2 are connected to the parallel number detection signal, the negative input terminal of comparator COMP1 is connected to a first reference voltage signal, and the negative input terminal of comparator COMP2 is connected to a second reference voltage signal, wherein the first reference voltage signal is less than the second reference voltage signal; the power supply is connected to the positive input terminal of comparator COMP1 through the constant current source; the drain of the switching transistor is connected to the positive input terminal of comparator COMP1, the source of the switching transistor is connected to ground through the pull-down resistor, and the gate of the switching transistor is connected to the output terminal of the buffer; the output terminal of comparator COMP1 outputs the first indication control signal, and the output terminal of comparator COMP2 outputs the second indication control signal.

3. The multi-channel parallel clock generation system according to claim 1, characterized in that, The interleaved clock generation circuit includes: comparator COMP3, comparator COMP4, power supply, capacitor, and switch; wherein, the power supply, the capacitor, and the switch constitute a capacitor charging and discharging module, which is used to generate a ramp voltage signal. The first positive input terminal of comparator COMP3 is connected to a first input reference voltage, the second positive input terminal of comparator COMP3 is connected to a second input reference voltage, the negative input terminal of comparator COMP3 is connected to the ramp voltage signal, and the output terminal of comparator COMP3 outputs the clock signal; the first positive input terminal of comparator COMP4 is connected to the output terminal of the reference voltage selection circuit to receive the reference voltage output by the reference voltage selection circuit, the second positive input terminal of comparator COMP4 is connected to the second input reference voltage, the negative input terminal of comparator COMP4 is connected to the ramp voltage signal, and comparator COMP4 outputs the clock control signal, wherein the first input reference voltage is greater than the second input reference voltage.

4. A clock generation circuit for generating interleaved phases, used in a power supply system consisting of N converters connected in parallel, where N is an integer greater than or equal to 2, characterized in that, The clock generation circuit includes: A parallel number detection circuit is used to detect a parallel number detection signal that characterizes the number of converters, and output a first indication control signal and a second indication control signal according to the parallel number detection signal; A reference voltage selection circuit generates a reference voltage based on the first indication control signal and the second indication control signal; An interleaved clock generation circuit generates clock signals and clock control signals of different phases based on the reference voltage, wherein the phase of the clock control signal is delayed relative to the phase of the clock signal.

5. The clock generation circuit for generating interleaved phases according to claim 4, characterized in that, The phase of the clock control signal is delayed relative to the clock signal.

6. A clock generation method for a power supply system consisting of N converters connected in parallel, wherein N is an integer greater than or equal to 2, the power supply system comprising a multi-channel parallel clock generation system, the multi-channel parallel clock generation system comprising a first clock generation circuit and a second clock generation circuit connected in parallel. The first clock generation circuit includes a parallel number detection circuit, a reference voltage selection circuit, and an interleaved clock generation circuit; The parallel number detection circuit is used to detect the parallel number detection signal, and output a first indication control signal and a second indication control signal according to the parallel number detection signal; The reference voltage selection circuit generates a reference voltage according to the first indication control signal and the second indication control signal; The interleaved clock generation circuit generates a clock control signal based on the reference voltage; characterized in that the clock generation method includes: The first clock generation circuit acquires a parallel connection count detection signal, representing the number of converters; and outputs a clock signal and a clock control signal based on the parallel connection count detection signal, wherein the phase of the clock control signal is delayed compared to the clock signal. The second clock generation circuit receives the clock control signal and outputs a phase delayed compared to the clock control signal. Another clock control signal.

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